1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef LOONGARCH_CPU_H 9 #define LOONGARCH_CPU_H 10 11 #include "qemu/int128.h" 12 #include "exec/cpu-defs.h" 13 #include "exec/cpu-interrupt.h" 14 #include "fpu/softfloat-types.h" 15 #include "hw/registerfields.h" 16 #include "qemu/timer.h" 17 #ifndef CONFIG_USER_ONLY 18 #include "system/memory.h" 19 #endif 20 #include "cpu-csr.h" 21 #include "cpu-qom.h" 22 23 #define IOCSRF_TEMP 0 24 #define IOCSRF_NODECNT 1 25 #define IOCSRF_MSI 2 26 #define IOCSRF_EXTIOI 3 27 #define IOCSRF_CSRIPI 4 28 #define IOCSRF_FREQCSR 5 29 #define IOCSRF_FREQSCALE 6 30 #define IOCSRF_DVFSV1 7 31 #define IOCSRF_GMOD 9 32 #define IOCSRF_VM 11 33 34 #define VERSION_REG 0x0 35 #define FEATURE_REG 0x8 36 #define VENDOR_REG 0x10 37 #define CPUNAME_REG 0x20 38 #define MISC_FUNC_REG 0x420 39 #define IOCSRM_EXTIOI_EN 48 40 #define IOCSRM_EXTIOI_INT_ENCODE 49 41 42 #define IOCSR_MEM_SIZE 0x428 43 44 #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ 45 #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ 46 #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ 47 #define FCSR0_RM 8 /* Round Mode bit num on fcsr0 */ 48 49 FIELD(FCSR0, ENABLES, 0, 5) 50 FIELD(FCSR0, RM, 8, 2) 51 FIELD(FCSR0, FLAGS, 16, 5) 52 FIELD(FCSR0, CAUSE, 24, 5) 53 54 #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE) 55 #define SET_FP_CAUSE(REG, V) \ 56 do { \ 57 (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \ 58 } while (0) 59 #define UPDATE_FP_CAUSE(REG, V) \ 60 do { \ 61 (REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \ 62 } while (0) 63 64 #define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES) 65 #define SET_FP_ENABLES(REG, V) \ 66 do { \ 67 (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \ 68 } while (0) 69 70 #define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS) 71 #define SET_FP_FLAGS(REG, V) \ 72 do { \ 73 (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \ 74 } while (0) 75 76 #define UPDATE_FP_FLAGS(REG, V) \ 77 do { \ 78 (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \ 79 } while (0) 80 81 #define FP_INEXACT 1 82 #define FP_UNDERFLOW 2 83 #define FP_OVERFLOW 4 84 #define FP_DIV0 8 85 #define FP_INVALID 16 86 87 #define EXCODE(code, subcode) ( ((subcode) << 6) | (code) ) 88 #define EXCODE_MCODE(code) ( (code) & 0x3f ) 89 #define EXCODE_SUBCODE(code) ( (code) >> 6 ) 90 91 #define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */ 92 #define EXCCODE_INT EXCODE(0, 0) 93 #define EXCCODE_PIL EXCODE(1, 0) 94 #define EXCCODE_PIS EXCODE(2, 0) 95 #define EXCCODE_PIF EXCODE(3, 0) 96 #define EXCCODE_PME EXCODE(4, 0) 97 #define EXCCODE_PNR EXCODE(5, 0) 98 #define EXCCODE_PNX EXCODE(6, 0) 99 #define EXCCODE_PPI EXCODE(7, 0) 100 #define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */ 101 #define EXCCODE_ADEM EXCODE(8, 1) 102 #define EXCCODE_ALE EXCODE(9, 0) 103 #define EXCCODE_BCE EXCODE(10, 0) 104 #define EXCCODE_SYS EXCODE(11, 0) 105 #define EXCCODE_BRK EXCODE(12, 0) 106 #define EXCCODE_INE EXCODE(13, 0) 107 #define EXCCODE_IPE EXCODE(14, 0) 108 #define EXCCODE_FPD EXCODE(15, 0) 109 #define EXCCODE_SXD EXCODE(16, 0) 110 #define EXCCODE_ASXD EXCODE(17, 0) 111 #define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */ 112 #define EXCCODE_VFPE EXCODE(18, 1) 113 #define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */ 114 #define EXCCODE_WPEM EXCODE(19, 1) 115 #define EXCCODE_BTD EXCODE(20, 0) 116 #define EXCCODE_BTE EXCODE(21, 0) 117 #define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */ 118 119 /* cpucfg[0] bits */ 120 FIELD(CPUCFG0, PRID, 0, 32) 121 122 /* cpucfg[1] bits */ 123 FIELD(CPUCFG1, ARCH, 0, 2) 124 FIELD(CPUCFG1, PGMMU, 2, 1) 125 FIELD(CPUCFG1, IOCSR, 3, 1) 126 FIELD(CPUCFG1, PALEN, 4, 8) 127 FIELD(CPUCFG1, VALEN, 12, 8) 128 FIELD(CPUCFG1, UAL, 20, 1) 129 FIELD(CPUCFG1, RI, 21, 1) 130 FIELD(CPUCFG1, EP, 22, 1) 131 FIELD(CPUCFG1, RPLV, 23, 1) 132 FIELD(CPUCFG1, HP, 24, 1) 133 FIELD(CPUCFG1, IOCSR_BRD, 25, 1) 134 FIELD(CPUCFG1, MSG_INT, 26, 1) 135 136 /* cpucfg[1].arch */ 137 #define CPUCFG1_ARCH_LA32R 0 138 #define CPUCFG1_ARCH_LA32 1 139 #define CPUCFG1_ARCH_LA64 2 140 141 /* cpucfg[2] bits */ 142 FIELD(CPUCFG2, FP, 0, 1) 143 FIELD(CPUCFG2, FP_SP, 1, 1) 144 FIELD(CPUCFG2, FP_DP, 2, 1) 145 FIELD(CPUCFG2, FP_VER, 3, 3) 146 FIELD(CPUCFG2, LSX, 6, 1) 147 FIELD(CPUCFG2, LASX, 7, 1) 148 FIELD(CPUCFG2, COMPLEX, 8, 1) 149 FIELD(CPUCFG2, CRYPTO, 9, 1) 150 FIELD(CPUCFG2, LVZ, 10, 1) 151 FIELD(CPUCFG2, LVZ_VER, 11, 3) 152 FIELD(CPUCFG2, LLFTP, 14, 1) 153 FIELD(CPUCFG2, LLFTP_VER, 15, 3) 154 FIELD(CPUCFG2, LBT_X86, 18, 1) 155 FIELD(CPUCFG2, LBT_ARM, 19, 1) 156 FIELD(CPUCFG2, LBT_MIPS, 20, 1) 157 FIELD(CPUCFG2, LBT_ALL, 18, 3) 158 FIELD(CPUCFG2, LSPW, 21, 1) 159 FIELD(CPUCFG2, LAM, 22, 1) 160 161 /* cpucfg[3] bits */ 162 FIELD(CPUCFG3, CCDMA, 0, 1) 163 FIELD(CPUCFG3, SFB, 1, 1) 164 FIELD(CPUCFG3, UCACC, 2, 1) 165 FIELD(CPUCFG3, LLEXC, 3, 1) 166 FIELD(CPUCFG3, SCDLY, 4, 1) 167 FIELD(CPUCFG3, LLDBAR, 5, 1) 168 FIELD(CPUCFG3, ITLBHMC, 6, 1) 169 FIELD(CPUCFG3, ICHMC, 7, 1) 170 FIELD(CPUCFG3, SPW_LVL, 8, 3) 171 FIELD(CPUCFG3, SPW_HP_HF, 11, 1) 172 FIELD(CPUCFG3, RVA, 12, 1) 173 FIELD(CPUCFG3, RVAMAX, 13, 4) 174 175 /* cpucfg[4] bits */ 176 FIELD(CPUCFG4, CC_FREQ, 0, 32) 177 178 /* cpucfg[5] bits */ 179 FIELD(CPUCFG5, CC_MUL, 0, 16) 180 FIELD(CPUCFG5, CC_DIV, 16, 16) 181 182 /* cpucfg[6] bits */ 183 FIELD(CPUCFG6, PMP, 0, 1) 184 FIELD(CPUCFG6, PMVER, 1, 3) 185 FIELD(CPUCFG6, PMNUM, 4, 4) 186 FIELD(CPUCFG6, PMBITS, 8, 6) 187 FIELD(CPUCFG6, UPM, 14, 1) 188 189 /* cpucfg[16] bits */ 190 FIELD(CPUCFG16, L1_IUPRE, 0, 1) 191 FIELD(CPUCFG16, L1_IUUNIFY, 1, 1) 192 FIELD(CPUCFG16, L1_DPRE, 2, 1) 193 FIELD(CPUCFG16, L2_IUPRE, 3, 1) 194 FIELD(CPUCFG16, L2_IUUNIFY, 4, 1) 195 FIELD(CPUCFG16, L2_IUPRIV, 5, 1) 196 FIELD(CPUCFG16, L2_IUINCL, 6, 1) 197 FIELD(CPUCFG16, L2_DPRE, 7, 1) 198 FIELD(CPUCFG16, L2_DPRIV, 8, 1) 199 FIELD(CPUCFG16, L2_DINCL, 9, 1) 200 FIELD(CPUCFG16, L3_IUPRE, 10, 1) 201 FIELD(CPUCFG16, L3_IUUNIFY, 11, 1) 202 FIELD(CPUCFG16, L3_IUPRIV, 12, 1) 203 FIELD(CPUCFG16, L3_IUINCL, 13, 1) 204 FIELD(CPUCFG16, L3_DPRE, 14, 1) 205 FIELD(CPUCFG16, L3_DPRIV, 15, 1) 206 FIELD(CPUCFG16, L3_DINCL, 16, 1) 207 208 /* cpucfg[17] bits */ 209 FIELD(CPUCFG17, L1IU_WAYS, 0, 16) 210 FIELD(CPUCFG17, L1IU_SETS, 16, 8) 211 FIELD(CPUCFG17, L1IU_SIZE, 24, 7) 212 213 /* cpucfg[18] bits */ 214 FIELD(CPUCFG18, L1D_WAYS, 0, 16) 215 FIELD(CPUCFG18, L1D_SETS, 16, 8) 216 FIELD(CPUCFG18, L1D_SIZE, 24, 7) 217 218 /* cpucfg[19] bits */ 219 FIELD(CPUCFG19, L2IU_WAYS, 0, 16) 220 FIELD(CPUCFG19, L2IU_SETS, 16, 8) 221 FIELD(CPUCFG19, L2IU_SIZE, 24, 7) 222 223 /* cpucfg[20] bits */ 224 FIELD(CPUCFG20, L3IU_WAYS, 0, 16) 225 FIELD(CPUCFG20, L3IU_SETS, 16, 8) 226 FIELD(CPUCFG20, L3IU_SIZE, 24, 7) 227 228 /*CSR_CRMD */ 229 FIELD(CSR_CRMD, PLV, 0, 2) 230 FIELD(CSR_CRMD, IE, 2, 1) 231 FIELD(CSR_CRMD, DA, 3, 1) 232 FIELD(CSR_CRMD, PG, 4, 1) 233 FIELD(CSR_CRMD, DATF, 5, 2) 234 FIELD(CSR_CRMD, DATM, 7, 2) 235 FIELD(CSR_CRMD, WE, 9, 1) 236 237 extern const char * const regnames[32]; 238 extern const char * const fregnames[32]; 239 240 #define N_IRQS 13 241 #define IRQ_TIMER 11 242 #define IRQ_IPI 12 243 244 #define LOONGARCH_STLB 2048 /* 2048 STLB */ 245 #define LOONGARCH_MTLB 64 /* 64 MTLB */ 246 #define LOONGARCH_TLB_MAX (LOONGARCH_STLB + LOONGARCH_MTLB) 247 248 /* 249 * define the ASID PS E VPPN field of TLB 250 */ 251 FIELD(TLB_MISC, E, 0, 1) 252 FIELD(TLB_MISC, ASID, 1, 10) 253 FIELD(TLB_MISC, VPPN, 13, 35) 254 FIELD(TLB_MISC, PS, 48, 6) 255 256 #define LSX_LEN (128) 257 #define LASX_LEN (256) 258 259 typedef union VReg { 260 int8_t B[LASX_LEN / 8]; 261 int16_t H[LASX_LEN / 16]; 262 int32_t W[LASX_LEN / 32]; 263 int64_t D[LASX_LEN / 64]; 264 uint8_t UB[LASX_LEN / 8]; 265 uint16_t UH[LASX_LEN / 16]; 266 uint32_t UW[LASX_LEN / 32]; 267 uint64_t UD[LASX_LEN / 64]; 268 Int128 Q[LASX_LEN / 128]; 269 } VReg; 270 271 typedef union fpr_t fpr_t; 272 union fpr_t { 273 VReg vreg; 274 }; 275 276 #ifdef CONFIG_TCG 277 struct LoongArchTLB { 278 uint64_t tlb_misc; 279 /* Fields corresponding to CSR_TLBELO0/1 */ 280 uint64_t tlb_entry0; 281 uint64_t tlb_entry1; 282 }; 283 typedef struct LoongArchTLB LoongArchTLB; 284 #endif 285 286 enum loongarch_features { 287 LOONGARCH_FEATURE_LSX, 288 LOONGARCH_FEATURE_LASX, 289 LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ 290 LOONGARCH_FEATURE_PMU, 291 LOONGARCH_FEATURE_PV_IPI, 292 LOONGARCH_FEATURE_STEALTIME, 293 }; 294 295 typedef struct LoongArchBT { 296 /* scratch registers */ 297 uint64_t scr0; 298 uint64_t scr1; 299 uint64_t scr2; 300 uint64_t scr3; 301 /* loongarch eflags */ 302 uint32_t eflags; 303 uint32_t ftop; 304 } lbt_t; 305 306 typedef struct CPUArchState { 307 uint64_t gpr[32]; 308 uint64_t pc; 309 310 fpr_t fpr[32]; 311 bool cf[8]; 312 uint32_t fcsr0; 313 lbt_t lbt; 314 315 uint32_t cpucfg[21]; 316 uint32_t pv_features; 317 318 /* LoongArch CSRs */ 319 uint64_t CSR_CRMD; 320 uint64_t CSR_PRMD; 321 uint64_t CSR_EUEN; 322 uint64_t CSR_MISC; 323 uint64_t CSR_ECFG; 324 uint64_t CSR_ESTAT; 325 uint64_t CSR_ERA; 326 uint64_t CSR_BADV; 327 uint64_t CSR_BADI; 328 uint64_t CSR_EENTRY; 329 uint64_t CSR_TLBIDX; 330 uint64_t CSR_TLBEHI; 331 uint64_t CSR_TLBELO0; 332 uint64_t CSR_TLBELO1; 333 uint64_t CSR_ASID; 334 uint64_t CSR_PGDL; 335 uint64_t CSR_PGDH; 336 uint64_t CSR_PGD; 337 uint64_t CSR_PWCL; 338 uint64_t CSR_PWCH; 339 uint64_t CSR_STLBPS; 340 uint64_t CSR_RVACFG; 341 uint64_t CSR_CPUID; 342 uint64_t CSR_PRCFG1; 343 uint64_t CSR_PRCFG2; 344 uint64_t CSR_PRCFG3; 345 uint64_t CSR_SAVE[16]; 346 uint64_t CSR_TID; 347 uint64_t CSR_TCFG; 348 uint64_t CSR_TVAL; 349 uint64_t CSR_CNTC; 350 uint64_t CSR_TICLR; 351 uint64_t CSR_LLBCTL; 352 uint64_t CSR_IMPCTL1; 353 uint64_t CSR_IMPCTL2; 354 uint64_t CSR_TLBRENTRY; 355 uint64_t CSR_TLBRBADV; 356 uint64_t CSR_TLBRERA; 357 uint64_t CSR_TLBRSAVE; 358 uint64_t CSR_TLBRELO0; 359 uint64_t CSR_TLBRELO1; 360 uint64_t CSR_TLBREHI; 361 uint64_t CSR_TLBRPRMD; 362 uint64_t CSR_MERRCTL; 363 uint64_t CSR_MERRINFO1; 364 uint64_t CSR_MERRINFO2; 365 uint64_t CSR_MERRENTRY; 366 uint64_t CSR_MERRERA; 367 uint64_t CSR_MERRSAVE; 368 uint64_t CSR_CTAG; 369 uint64_t CSR_DMW[4]; 370 uint64_t CSR_DBG; 371 uint64_t CSR_DERA; 372 uint64_t CSR_DSAVE; 373 struct { 374 uint64_t guest_addr; 375 } stealtime; 376 377 #ifdef CONFIG_TCG 378 float_status fp_status; 379 uint32_t fcsr0_mask; 380 uint64_t lladdr; /* LL virtual address compared against SC */ 381 uint64_t llval; 382 #endif 383 #ifndef CONFIG_USER_ONLY 384 #ifdef CONFIG_TCG 385 LoongArchTLB tlb[LOONGARCH_TLB_MAX]; 386 #endif 387 388 AddressSpace *address_space_iocsr; 389 bool load_elf; 390 uint64_t elf_address; 391 uint32_t mp_state; 392 393 struct loongarch_boot_info *boot_info; 394 #endif 395 } CPULoongArchState; 396 397 typedef struct LoongArchCPUTopo { 398 int32_t socket_id; /* socket-id of this VCPU */ 399 int32_t core_id; /* core-id of this VCPU */ 400 int32_t thread_id; /* thread-id of this VCPU */ 401 } LoongArchCPUTopo; 402 403 /** 404 * LoongArchCPU: 405 * @env: #CPULoongArchState 406 * 407 * A LoongArch CPU. 408 */ 409 struct ArchCPU { 410 CPUState parent_obj; 411 412 CPULoongArchState env; 413 QEMUTimer timer; 414 uint32_t phy_id; 415 OnOffAuto lbt; 416 OnOffAuto pmu; 417 OnOffAuto lsx; 418 OnOffAuto lasx; 419 OnOffAuto kvm_pv_ipi; 420 OnOffAuto kvm_steal_time; 421 int32_t socket_id; /* socket-id of this CPU */ 422 int32_t core_id; /* core-id of this CPU */ 423 int32_t thread_id; /* thread-id of this CPU */ 424 int32_t node_id; /* NUMA node of this CPU */ 425 426 /* 'compatible' string for this CPU for Linux device trees */ 427 const char *dtb_compatible; 428 /* used by KVM_REG_LOONGARCH_COUNTER ioctl to access guest time counters */ 429 uint64_t kvm_state_counter; 430 VMChangeStateEntry *vmsentry; 431 }; 432 433 /** 434 * LoongArchCPUClass: 435 * @parent_realize: The parent class' realize handler. 436 * @parent_phases: The parent class' reset phase handlers. 437 * 438 * A LoongArch CPU model. 439 */ 440 struct LoongArchCPUClass { 441 CPUClass parent_class; 442 443 DeviceRealize parent_realize; 444 DeviceUnrealize parent_unrealize; 445 ResettablePhases parent_phases; 446 }; 447 448 /* 449 * LoongArch CPUs has 4 privilege levels. 450 * 0 for kernel mode, 3 for user mode. 451 * Define an extra index for DA(direct addressing) mode. 452 */ 453 #define MMU_PLV_KERNEL 0 454 #define MMU_PLV_USER 3 455 #define MMU_KERNEL_IDX MMU_PLV_KERNEL 456 #define MMU_USER_IDX MMU_PLV_USER 457 #define MMU_DA_IDX 4 458 459 static inline bool is_la64(CPULoongArchState *env) 460 { 461 return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64; 462 } 463 464 static inline bool is_va32(CPULoongArchState *env) 465 { 466 /* VA32 if !LA64 or VA32L[1-3] */ 467 bool va32 = !is_la64(env); 468 uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); 469 if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) { 470 va32 = true; 471 } 472 return va32; 473 } 474 475 static inline void set_pc(CPULoongArchState *env, uint64_t value) 476 { 477 if (is_va32(env)) { 478 env->pc = (uint32_t)value; 479 } else { 480 env->pc = value; 481 } 482 } 483 484 /* 485 * LoongArch CPUs hardware flags. 486 */ 487 #define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ 488 #define HW_FLAGS_EUEN_FPE 0x04 489 #define HW_FLAGS_EUEN_SXE 0x08 490 #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ 491 #define HW_FLAGS_VA32 0x20 492 #define HW_FLAGS_EUEN_ASXE 0x40 493 494 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, 495 uint64_t *cs_base, uint32_t *flags) 496 { 497 *pc = env->pc; 498 *cs_base = 0; 499 *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); 500 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; 501 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; 502 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; 503 *flags |= is_va32(env) * HW_FLAGS_VA32; 504 } 505 506 #include "exec/cpu-all.h" 507 508 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU 509 510 void loongarch_cpu_post_init(Object *obj); 511 512 #ifdef CONFIG_KVM 513 void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu); 514 #else 515 static inline void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu) 516 { 517 } 518 #endif 519 520 #endif /* LOONGARCH_CPU_H */ 521