1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef LOONGARCH_CPU_H 9 #define LOONGARCH_CPU_H 10 11 #include "qemu/int128.h" 12 #include "exec/cpu-defs.h" 13 #include "fpu/softfloat-types.h" 14 #include "hw/registerfields.h" 15 #include "qemu/timer.h" 16 #ifndef CONFIG_USER_ONLY 17 #include "exec/memory.h" 18 #endif 19 #include "cpu-csr.h" 20 #include "cpu-qom.h" 21 22 #define IOCSRF_TEMP 0 23 #define IOCSRF_NODECNT 1 24 #define IOCSRF_MSI 2 25 #define IOCSRF_EXTIOI 3 26 #define IOCSRF_CSRIPI 4 27 #define IOCSRF_FREQCSR 5 28 #define IOCSRF_FREQSCALE 6 29 #define IOCSRF_DVFSV1 7 30 #define IOCSRF_GMOD 9 31 #define IOCSRF_VM 11 32 33 #define VERSION_REG 0x0 34 #define FEATURE_REG 0x8 35 #define VENDOR_REG 0x10 36 #define CPUNAME_REG 0x20 37 #define MISC_FUNC_REG 0x420 38 #define IOCSRM_EXTIOI_EN 48 39 #define IOCSRM_EXTIOI_INT_ENCODE 49 40 41 #define IOCSR_MEM_SIZE 0x428 42 43 #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ 44 #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ 45 #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ 46 #define FCSR0_RM 8 /* Round Mode bit num on fcsr0 */ 47 48 FIELD(FCSR0, ENABLES, 0, 5) 49 FIELD(FCSR0, RM, 8, 2) 50 FIELD(FCSR0, FLAGS, 16, 5) 51 FIELD(FCSR0, CAUSE, 24, 5) 52 53 #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE) 54 #define SET_FP_CAUSE(REG, V) \ 55 do { \ 56 (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \ 57 } while (0) 58 #define UPDATE_FP_CAUSE(REG, V) \ 59 do { \ 60 (REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \ 61 } while (0) 62 63 #define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES) 64 #define SET_FP_ENABLES(REG, V) \ 65 do { \ 66 (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \ 67 } while (0) 68 69 #define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS) 70 #define SET_FP_FLAGS(REG, V) \ 71 do { \ 72 (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \ 73 } while (0) 74 75 #define UPDATE_FP_FLAGS(REG, V) \ 76 do { \ 77 (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \ 78 } while (0) 79 80 #define FP_INEXACT 1 81 #define FP_UNDERFLOW 2 82 #define FP_OVERFLOW 4 83 #define FP_DIV0 8 84 #define FP_INVALID 16 85 86 #define EXCODE(code, subcode) ( ((subcode) << 6) | (code) ) 87 #define EXCODE_MCODE(code) ( (code) & 0x3f ) 88 #define EXCODE_SUBCODE(code) ( (code) >> 6 ) 89 90 #define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */ 91 #define EXCCODE_INT EXCODE(0, 0) 92 #define EXCCODE_PIL EXCODE(1, 0) 93 #define EXCCODE_PIS EXCODE(2, 0) 94 #define EXCCODE_PIF EXCODE(3, 0) 95 #define EXCCODE_PME EXCODE(4, 0) 96 #define EXCCODE_PNR EXCODE(5, 0) 97 #define EXCCODE_PNX EXCODE(6, 0) 98 #define EXCCODE_PPI EXCODE(7, 0) 99 #define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */ 100 #define EXCCODE_ADEM EXCODE(8, 1) 101 #define EXCCODE_ALE EXCODE(9, 0) 102 #define EXCCODE_BCE EXCODE(10, 0) 103 #define EXCCODE_SYS EXCODE(11, 0) 104 #define EXCCODE_BRK EXCODE(12, 0) 105 #define EXCCODE_INE EXCODE(13, 0) 106 #define EXCCODE_IPE EXCODE(14, 0) 107 #define EXCCODE_FPD EXCODE(15, 0) 108 #define EXCCODE_SXD EXCODE(16, 0) 109 #define EXCCODE_ASXD EXCODE(17, 0) 110 #define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */ 111 #define EXCCODE_VFPE EXCODE(18, 1) 112 #define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */ 113 #define EXCCODE_WPEM EXCODE(19, 1) 114 #define EXCCODE_BTD EXCODE(20, 0) 115 #define EXCCODE_BTE EXCODE(21, 0) 116 #define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */ 117 118 /* cpucfg[0] bits */ 119 FIELD(CPUCFG0, PRID, 0, 32) 120 121 /* cpucfg[1] bits */ 122 FIELD(CPUCFG1, ARCH, 0, 2) 123 FIELD(CPUCFG1, PGMMU, 2, 1) 124 FIELD(CPUCFG1, IOCSR, 3, 1) 125 FIELD(CPUCFG1, PALEN, 4, 8) 126 FIELD(CPUCFG1, VALEN, 12, 8) 127 FIELD(CPUCFG1, UAL, 20, 1) 128 FIELD(CPUCFG1, RI, 21, 1) 129 FIELD(CPUCFG1, EP, 22, 1) 130 FIELD(CPUCFG1, RPLV, 23, 1) 131 FIELD(CPUCFG1, HP, 24, 1) 132 FIELD(CPUCFG1, IOCSR_BRD, 25, 1) 133 FIELD(CPUCFG1, MSG_INT, 26, 1) 134 135 /* cpucfg[1].arch */ 136 #define CPUCFG1_ARCH_LA32R 0 137 #define CPUCFG1_ARCH_LA32 1 138 #define CPUCFG1_ARCH_LA64 2 139 140 /* cpucfg[2] bits */ 141 FIELD(CPUCFG2, FP, 0, 1) 142 FIELD(CPUCFG2, FP_SP, 1, 1) 143 FIELD(CPUCFG2, FP_DP, 2, 1) 144 FIELD(CPUCFG2, FP_VER, 3, 3) 145 FIELD(CPUCFG2, LSX, 6, 1) 146 FIELD(CPUCFG2, LASX, 7, 1) 147 FIELD(CPUCFG2, COMPLEX, 8, 1) 148 FIELD(CPUCFG2, CRYPTO, 9, 1) 149 FIELD(CPUCFG2, LVZ, 10, 1) 150 FIELD(CPUCFG2, LVZ_VER, 11, 3) 151 FIELD(CPUCFG2, LLFTP, 14, 1) 152 FIELD(CPUCFG2, LLFTP_VER, 15, 3) 153 FIELD(CPUCFG2, LBT_X86, 18, 1) 154 FIELD(CPUCFG2, LBT_ARM, 19, 1) 155 FIELD(CPUCFG2, LBT_MIPS, 20, 1) 156 FIELD(CPUCFG2, LBT_ALL, 18, 3) 157 FIELD(CPUCFG2, LSPW, 21, 1) 158 FIELD(CPUCFG2, LAM, 22, 1) 159 160 /* cpucfg[3] bits */ 161 FIELD(CPUCFG3, CCDMA, 0, 1) 162 FIELD(CPUCFG3, SFB, 1, 1) 163 FIELD(CPUCFG3, UCACC, 2, 1) 164 FIELD(CPUCFG3, LLEXC, 3, 1) 165 FIELD(CPUCFG3, SCDLY, 4, 1) 166 FIELD(CPUCFG3, LLDBAR, 5, 1) 167 FIELD(CPUCFG3, ITLBHMC, 6, 1) 168 FIELD(CPUCFG3, ICHMC, 7, 1) 169 FIELD(CPUCFG3, SPW_LVL, 8, 3) 170 FIELD(CPUCFG3, SPW_HP_HF, 11, 1) 171 FIELD(CPUCFG3, RVA, 12, 1) 172 FIELD(CPUCFG3, RVAMAX, 13, 4) 173 174 /* cpucfg[4] bits */ 175 FIELD(CPUCFG4, CC_FREQ, 0, 32) 176 177 /* cpucfg[5] bits */ 178 FIELD(CPUCFG5, CC_MUL, 0, 16) 179 FIELD(CPUCFG5, CC_DIV, 16, 16) 180 181 /* cpucfg[6] bits */ 182 FIELD(CPUCFG6, PMP, 0, 1) 183 FIELD(CPUCFG6, PMVER, 1, 3) 184 FIELD(CPUCFG6, PMNUM, 4, 4) 185 FIELD(CPUCFG6, PMBITS, 8, 6) 186 FIELD(CPUCFG6, UPM, 14, 1) 187 188 /* cpucfg[16] bits */ 189 FIELD(CPUCFG16, L1_IUPRE, 0, 1) 190 FIELD(CPUCFG16, L1_IUUNIFY, 1, 1) 191 FIELD(CPUCFG16, L1_DPRE, 2, 1) 192 FIELD(CPUCFG16, L2_IUPRE, 3, 1) 193 FIELD(CPUCFG16, L2_IUUNIFY, 4, 1) 194 FIELD(CPUCFG16, L2_IUPRIV, 5, 1) 195 FIELD(CPUCFG16, L2_IUINCL, 6, 1) 196 FIELD(CPUCFG16, L2_DPRE, 7, 1) 197 FIELD(CPUCFG16, L2_DPRIV, 8, 1) 198 FIELD(CPUCFG16, L2_DINCL, 9, 1) 199 FIELD(CPUCFG16, L3_IUPRE, 10, 1) 200 FIELD(CPUCFG16, L3_IUUNIFY, 11, 1) 201 FIELD(CPUCFG16, L3_IUPRIV, 12, 1) 202 FIELD(CPUCFG16, L3_IUINCL, 13, 1) 203 FIELD(CPUCFG16, L3_DPRE, 14, 1) 204 FIELD(CPUCFG16, L3_DPRIV, 15, 1) 205 FIELD(CPUCFG16, L3_DINCL, 16, 1) 206 207 /* cpucfg[17] bits */ 208 FIELD(CPUCFG17, L1IU_WAYS, 0, 16) 209 FIELD(CPUCFG17, L1IU_SETS, 16, 8) 210 FIELD(CPUCFG17, L1IU_SIZE, 24, 7) 211 212 /* cpucfg[18] bits */ 213 FIELD(CPUCFG18, L1D_WAYS, 0, 16) 214 FIELD(CPUCFG18, L1D_SETS, 16, 8) 215 FIELD(CPUCFG18, L1D_SIZE, 24, 7) 216 217 /* cpucfg[19] bits */ 218 FIELD(CPUCFG19, L2IU_WAYS, 0, 16) 219 FIELD(CPUCFG19, L2IU_SETS, 16, 8) 220 FIELD(CPUCFG19, L2IU_SIZE, 24, 7) 221 222 /* cpucfg[20] bits */ 223 FIELD(CPUCFG20, L3IU_WAYS, 0, 16) 224 FIELD(CPUCFG20, L3IU_SETS, 16, 8) 225 FIELD(CPUCFG20, L3IU_SIZE, 24, 7) 226 227 /*CSR_CRMD */ 228 FIELD(CSR_CRMD, PLV, 0, 2) 229 FIELD(CSR_CRMD, IE, 2, 1) 230 FIELD(CSR_CRMD, DA, 3, 1) 231 FIELD(CSR_CRMD, PG, 4, 1) 232 FIELD(CSR_CRMD, DATF, 5, 2) 233 FIELD(CSR_CRMD, DATM, 7, 2) 234 FIELD(CSR_CRMD, WE, 9, 1) 235 236 extern const char * const regnames[32]; 237 extern const char * const fregnames[32]; 238 239 #define N_IRQS 13 240 #define IRQ_TIMER 11 241 #define IRQ_IPI 12 242 243 #define LOONGARCH_STLB 2048 /* 2048 STLB */ 244 #define LOONGARCH_MTLB 64 /* 64 MTLB */ 245 #define LOONGARCH_TLB_MAX (LOONGARCH_STLB + LOONGARCH_MTLB) 246 247 /* 248 * define the ASID PS E VPPN field of TLB 249 */ 250 FIELD(TLB_MISC, E, 0, 1) 251 FIELD(TLB_MISC, ASID, 1, 10) 252 FIELD(TLB_MISC, VPPN, 13, 35) 253 FIELD(TLB_MISC, PS, 48, 6) 254 255 #define LSX_LEN (128) 256 #define LASX_LEN (256) 257 258 typedef union VReg { 259 int8_t B[LASX_LEN / 8]; 260 int16_t H[LASX_LEN / 16]; 261 int32_t W[LASX_LEN / 32]; 262 int64_t D[LASX_LEN / 64]; 263 uint8_t UB[LASX_LEN / 8]; 264 uint16_t UH[LASX_LEN / 16]; 265 uint32_t UW[LASX_LEN / 32]; 266 uint64_t UD[LASX_LEN / 64]; 267 Int128 Q[LASX_LEN / 128]; 268 } VReg; 269 270 typedef union fpr_t fpr_t; 271 union fpr_t { 272 VReg vreg; 273 }; 274 275 #ifdef CONFIG_TCG 276 struct LoongArchTLB { 277 uint64_t tlb_misc; 278 /* Fields corresponding to CSR_TLBELO0/1 */ 279 uint64_t tlb_entry0; 280 uint64_t tlb_entry1; 281 }; 282 typedef struct LoongArchTLB LoongArchTLB; 283 #endif 284 285 enum loongarch_features { 286 LOONGARCH_FEATURE_LSX, 287 LOONGARCH_FEATURE_LASX, 288 LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ 289 LOONGARCH_FEATURE_PMU, 290 LOONGARCH_FEATURE_PV_IPI, 291 LOONGARCH_FEATURE_STEALTIME, 292 }; 293 294 typedef struct LoongArchBT { 295 /* scratch registers */ 296 uint64_t scr0; 297 uint64_t scr1; 298 uint64_t scr2; 299 uint64_t scr3; 300 /* loongarch eflags */ 301 uint32_t eflags; 302 uint32_t ftop; 303 } lbt_t; 304 305 typedef struct CPUArchState { 306 uint64_t gpr[32]; 307 uint64_t pc; 308 309 fpr_t fpr[32]; 310 bool cf[8]; 311 uint32_t fcsr0; 312 lbt_t lbt; 313 314 uint32_t cpucfg[21]; 315 uint32_t pv_features; 316 317 /* LoongArch CSRs */ 318 uint64_t CSR_CRMD; 319 uint64_t CSR_PRMD; 320 uint64_t CSR_EUEN; 321 uint64_t CSR_MISC; 322 uint64_t CSR_ECFG; 323 uint64_t CSR_ESTAT; 324 uint64_t CSR_ERA; 325 uint64_t CSR_BADV; 326 uint64_t CSR_BADI; 327 uint64_t CSR_EENTRY; 328 uint64_t CSR_TLBIDX; 329 uint64_t CSR_TLBEHI; 330 uint64_t CSR_TLBELO0; 331 uint64_t CSR_TLBELO1; 332 uint64_t CSR_ASID; 333 uint64_t CSR_PGDL; 334 uint64_t CSR_PGDH; 335 uint64_t CSR_PGD; 336 uint64_t CSR_PWCL; 337 uint64_t CSR_PWCH; 338 uint64_t CSR_STLBPS; 339 uint64_t CSR_RVACFG; 340 uint64_t CSR_CPUID; 341 uint64_t CSR_PRCFG1; 342 uint64_t CSR_PRCFG2; 343 uint64_t CSR_PRCFG3; 344 uint64_t CSR_SAVE[16]; 345 uint64_t CSR_TID; 346 uint64_t CSR_TCFG; 347 uint64_t CSR_TVAL; 348 uint64_t CSR_CNTC; 349 uint64_t CSR_TICLR; 350 uint64_t CSR_LLBCTL; 351 uint64_t CSR_IMPCTL1; 352 uint64_t CSR_IMPCTL2; 353 uint64_t CSR_TLBRENTRY; 354 uint64_t CSR_TLBRBADV; 355 uint64_t CSR_TLBRERA; 356 uint64_t CSR_TLBRSAVE; 357 uint64_t CSR_TLBRELO0; 358 uint64_t CSR_TLBRELO1; 359 uint64_t CSR_TLBREHI; 360 uint64_t CSR_TLBRPRMD; 361 uint64_t CSR_MERRCTL; 362 uint64_t CSR_MERRINFO1; 363 uint64_t CSR_MERRINFO2; 364 uint64_t CSR_MERRENTRY; 365 uint64_t CSR_MERRERA; 366 uint64_t CSR_MERRSAVE; 367 uint64_t CSR_CTAG; 368 uint64_t CSR_DMW[4]; 369 uint64_t CSR_DBG; 370 uint64_t CSR_DERA; 371 uint64_t CSR_DSAVE; 372 struct { 373 uint64_t guest_addr; 374 } stealtime; 375 376 #ifdef CONFIG_TCG 377 float_status fp_status; 378 uint32_t fcsr0_mask; 379 uint64_t lladdr; /* LL virtual address compared against SC */ 380 uint64_t llval; 381 #endif 382 #ifndef CONFIG_USER_ONLY 383 #ifdef CONFIG_TCG 384 LoongArchTLB tlb[LOONGARCH_TLB_MAX]; 385 #endif 386 387 AddressSpace *address_space_iocsr; 388 bool load_elf; 389 uint64_t elf_address; 390 uint32_t mp_state; 391 392 struct loongarch_boot_info *boot_info; 393 #endif 394 } CPULoongArchState; 395 396 typedef struct LoongArchCPUTopo { 397 int32_t socket_id; /* socket-id of this VCPU */ 398 int32_t core_id; /* core-id of this VCPU */ 399 int32_t thread_id; /* thread-id of this VCPU */ 400 } LoongArchCPUTopo; 401 402 /** 403 * LoongArchCPU: 404 * @env: #CPULoongArchState 405 * 406 * A LoongArch CPU. 407 */ 408 struct ArchCPU { 409 CPUState parent_obj; 410 411 CPULoongArchState env; 412 QEMUTimer timer; 413 uint32_t phy_id; 414 OnOffAuto lbt; 415 OnOffAuto pmu; 416 OnOffAuto lsx; 417 OnOffAuto lasx; 418 OnOffAuto kvm_pv_ipi; 419 OnOffAuto kvm_steal_time; 420 int32_t socket_id; /* socket-id of this CPU */ 421 int32_t core_id; /* core-id of this CPU */ 422 int32_t thread_id; /* thread-id of this CPU */ 423 int32_t node_id; /* NUMA node of this CPU */ 424 425 /* 'compatible' string for this CPU for Linux device trees */ 426 const char *dtb_compatible; 427 /* used by KVM_REG_LOONGARCH_COUNTER ioctl to access guest time counters */ 428 uint64_t kvm_state_counter; 429 }; 430 431 /** 432 * LoongArchCPUClass: 433 * @parent_realize: The parent class' realize handler. 434 * @parent_phases: The parent class' reset phase handlers. 435 * 436 * A LoongArch CPU model. 437 */ 438 struct LoongArchCPUClass { 439 CPUClass parent_class; 440 441 DeviceRealize parent_realize; 442 DeviceUnrealize parent_unrealize; 443 ResettablePhases parent_phases; 444 }; 445 446 /* 447 * LoongArch CPUs has 4 privilege levels. 448 * 0 for kernel mode, 3 for user mode. 449 * Define an extra index for DA(direct addressing) mode. 450 */ 451 #define MMU_PLV_KERNEL 0 452 #define MMU_PLV_USER 3 453 #define MMU_KERNEL_IDX MMU_PLV_KERNEL 454 #define MMU_USER_IDX MMU_PLV_USER 455 #define MMU_DA_IDX 4 456 457 static inline bool is_la64(CPULoongArchState *env) 458 { 459 return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64; 460 } 461 462 static inline bool is_va32(CPULoongArchState *env) 463 { 464 /* VA32 if !LA64 or VA32L[1-3] */ 465 bool va32 = !is_la64(env); 466 uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); 467 if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) { 468 va32 = true; 469 } 470 return va32; 471 } 472 473 static inline void set_pc(CPULoongArchState *env, uint64_t value) 474 { 475 if (is_va32(env)) { 476 env->pc = (uint32_t)value; 477 } else { 478 env->pc = value; 479 } 480 } 481 482 /* 483 * LoongArch CPUs hardware flags. 484 */ 485 #define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ 486 #define HW_FLAGS_EUEN_FPE 0x04 487 #define HW_FLAGS_EUEN_SXE 0x08 488 #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ 489 #define HW_FLAGS_VA32 0x20 490 #define HW_FLAGS_EUEN_ASXE 0x40 491 492 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, 493 uint64_t *cs_base, uint32_t *flags) 494 { 495 *pc = env->pc; 496 *cs_base = 0; 497 *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); 498 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; 499 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; 500 *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; 501 *flags |= is_va32(env) * HW_FLAGS_VA32; 502 } 503 504 #include "exec/cpu-all.h" 505 506 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU 507 508 void loongarch_cpu_post_init(Object *obj); 509 510 #ifdef CONFIG_KVM 511 void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu); 512 #else 513 static inline void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu) 514 { 515 } 516 #endif 517 518 #endif /* LOONGARCH_CPU_H */ 519