1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CSRs 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef LOONGARCH_CPU_CSR_H 9 #define LOONGARCH_CPU_CSR_H 10 11 #include "hw/registerfields.h" 12 13 /* Based on kernel definitions: arch/loongarch/include/asm/loongarch.h */ 14 15 /* Basic CSRs */ 16 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */ 17 18 #define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */ 19 FIELD(CSR_PRMD, PPLV, 0, 2) 20 FIELD(CSR_PRMD, PIE, 2, 1) 21 FIELD(CSR_PRMD, PWE, 3, 1) 22 23 #define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */ 24 FIELD(CSR_EUEN, FPE, 0, 1) 25 FIELD(CSR_EUEN, SXE, 1, 1) 26 FIELD(CSR_EUEN, ASXE, 2, 1) 27 FIELD(CSR_EUEN, BTE, 3, 1) 28 29 #define LOONGARCH_CSR_MISC 0x3 /* Misc config */ 30 FIELD(CSR_MISC, VA32, 0, 4) 31 FIELD(CSR_MISC, DRDTL, 4, 4) 32 FIELD(CSR_MISC, RPCNTL, 8, 4) 33 FIELD(CSR_MISC, ALCL, 12, 4) 34 FIELD(CSR_MISC, DWPL, 16, 3) 35 36 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */ 37 FIELD(CSR_ECFG, LIE, 0, 13) 38 FIELD(CSR_ECFG, VS, 16, 3) 39 40 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ 41 FIELD(CSR_ESTAT, IS, 0, 13) 42 FIELD(CSR_ESTAT, ECODE, 16, 6) 43 FIELD(CSR_ESTAT, ESUBCODE, 22, 9) 44 45 #define LOONGARCH_CSR_ERA 0x6 /* Exception return address */ 46 47 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */ 48 49 #define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */ 50 51 #define LOONGARCH_CSR_EENTRY 0xc /* Exception entry address */ 52 53 /* TLB related CSRs */ 54 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */ 55 FIELD(CSR_TLBIDX, INDEX, 0, 12) 56 FIELD(CSR_TLBIDX, PS, 24, 6) 57 FIELD(CSR_TLBIDX, NE, 31, 1) 58 59 #define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */ 60 FIELD(CSR_TLBEHI, VPPN, 13, 35) 61 62 #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */ 63 #define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */ 64 FIELD(TLBENTRY, V, 0, 1) 65 FIELD(TLBENTRY, D, 1, 1) 66 FIELD(TLBENTRY, PLV, 2, 2) 67 FIELD(TLBENTRY, MAT, 4, 2) 68 FIELD(TLBENTRY, G, 6, 1) 69 FIELD(TLBENTRY_32, PPN, 8, 24) 70 FIELD(TLBENTRY_64, PPN, 12, 36) 71 FIELD(TLBENTRY_64, NR, 61, 1) 72 FIELD(TLBENTRY_64, NX, 62, 1) 73 FIELD(TLBENTRY_64, RPLV, 63, 1) 74 75 #define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */ 76 FIELD(CSR_ASID, ASID, 0, 10) 77 FIELD(CSR_ASID, ASIDBITS, 16, 8) 78 79 /* Page table base address when badv[47] = 0 */ 80 #define LOONGARCH_CSR_PGDL 0x19 81 /* Page table base address when badv[47] = 1 */ 82 #define LOONGARCH_CSR_PGDH 0x1a 83 84 #define LOONGARCH_CSR_PGD 0x1b /* Page table base address */ 85 86 /* Page walk controller's low addr */ 87 #define LOONGARCH_CSR_PWCL 0x1c 88 FIELD(CSR_PWCL, PTBASE, 0, 5) 89 FIELD(CSR_PWCL, PTWIDTH, 5, 5) 90 FIELD(CSR_PWCL, DIR1_BASE, 10, 5) 91 FIELD(CSR_PWCL, DIR1_WIDTH, 15, 5) 92 FIELD(CSR_PWCL, DIR2_BASE, 20, 5) 93 FIELD(CSR_PWCL, DIR2_WIDTH, 25, 5) 94 FIELD(CSR_PWCL, PTEWIDTH, 30, 2) 95 96 /* Page walk controller's high addr */ 97 #define LOONGARCH_CSR_PWCH 0x1d 98 FIELD(CSR_PWCH, DIR3_BASE, 0, 6) 99 FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6) 100 FIELD(CSR_PWCH, DIR4_BASE, 12, 6) 101 FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6) 102 103 #define LOONGARCH_CSR_STLBPS 0x1e /* Stlb page size */ 104 FIELD(CSR_STLBPS, PS, 0, 5) 105 106 #define LOONGARCH_CSR_RVACFG 0x1f /* Reduced virtual address config */ 107 FIELD(CSR_RVACFG, RBITS, 0, 4) 108 109 /* Config CSRs */ 110 #define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */ 111 112 #define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */ 113 FIELD(CSR_PRCFG1, SAVE_NUM, 0, 4) 114 FIELD(CSR_PRCFG1, TIMER_BITS, 4, 8) 115 FIELD(CSR_PRCFG1, VSMAX, 12, 3) 116 117 #define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */ 118 119 #define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */ 120 FIELD(CSR_PRCFG3, TLB_TYPE, 0, 4) 121 FIELD(CSR_PRCFG3, MTLB_ENTRY, 4, 8) 122 FIELD(CSR_PRCFG3, STLB_WAYS, 12, 8) 123 FIELD(CSR_PRCFG3, STLB_SETS, 20, 8) 124 125 /* 126 * Save registers count can read from PRCFG1.SAVE_NUM 127 * The Min count is 1. Max count is 15. 128 */ 129 #define LOONGARCH_CSR_SAVE(N) (0x30 + N) 130 131 /* Timer CSRs */ 132 #define LOONGARCH_CSR_TID 0x40 /* Timer ID */ 133 134 #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */ 135 FIELD(CSR_TCFG, EN, 0, 1) 136 FIELD(CSR_TCFG, PERIODIC, 1, 1) 137 FIELD(CSR_TCFG, INIT_VAL, 2, 46) 138 139 #define LOONGARCH_CSR_TVAL 0x42 /* Timer ticks remain */ 140 141 #define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */ 142 143 #define LOONGARCH_CSR_TICLR 0x44 /* Timer interrupt clear */ 144 145 /* LLBCTL CSRs */ 146 #define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */ 147 FIELD(CSR_LLBCTL, ROLLB, 0, 1) 148 FIELD(CSR_LLBCTL, WCLLB, 1, 1) 149 FIELD(CSR_LLBCTL, KLO, 2, 1) 150 151 /* Implement dependent */ 152 #define LOONGARCH_CSR_IMPCTL1 0x80 /* LoongArch config1 */ 153 154 #define LOONGARCH_CSR_IMPCTL2 0x81 /* LoongArch config2*/ 155 156 /* TLB Refill CSRs */ 157 #define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception address */ 158 #define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */ 159 #define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */ 160 #define LOONGARCH_CSR_TLBRSAVE 0x8b /* KScratch for TLB refill */ 161 FIELD(CSR_TLBRERA, ISTLBR, 0, 1) 162 FIELD(CSR_TLBRERA, PC, 2, 62) 163 #define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */ 164 #define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */ 165 #define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */ 166 FIELD(CSR_TLBREHI, PS, 0, 6) 167 FIELD(CSR_TLBREHI, VPPN, 13, 35) 168 #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */ 169 FIELD(CSR_TLBRPRMD, PPLV, 0, 2) 170 FIELD(CSR_TLBRPRMD, PIE, 2, 1) 171 FIELD(CSR_TLBRPRMD, PWE, 4, 1) 172 173 /* Machine Error CSRs */ 174 #define LOONGARCH_CSR_MERRCTL 0x90 /* ERRCTL */ 175 FIELD(CSR_MERRCTL, ISMERR, 0, 1) 176 #define LOONGARCH_CSR_MERRINFO1 0x91 177 #define LOONGARCH_CSR_MERRINFO2 0x92 178 #define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception base */ 179 #define LOONGARCH_CSR_MERRERA 0x94 /* MError exception PC */ 180 #define LOONGARCH_CSR_MERRSAVE 0x95 /* KScratch for error exception */ 181 182 #define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */ 183 184 /* Direct map windows CSRs*/ 185 #define LOONGARCH_CSR_DMW(N) (0x180 + N) 186 FIELD(CSR_DMW, PLV0, 0, 1) 187 FIELD(CSR_DMW, PLV1, 1, 1) 188 FIELD(CSR_DMW, PLV2, 2, 1) 189 FIELD(CSR_DMW, PLV3, 3, 1) 190 FIELD(CSR_DMW, MAT, 4, 2) 191 FIELD(CSR_DMW_32, PSEG, 25, 3) 192 FIELD(CSR_DMW_32, VSEG, 29, 3) 193 FIELD(CSR_DMW_64, VSEG, 60, 4) 194 195 /* Debug CSRs */ 196 #define LOONGARCH_CSR_DBG 0x500 /* debug config */ 197 FIELD(CSR_DBG, DST, 0, 1) 198 FIELD(CSR_DBG, DREV, 1, 7) 199 FIELD(CSR_DBG, DEI, 8, 1) 200 FIELD(CSR_DBG, DCL, 9, 1) 201 FIELD(CSR_DBG, DFW, 10, 1) 202 FIELD(CSR_DBG, DMW, 11, 1) 203 FIELD(CSR_DBG, ECODE, 16, 6) 204 205 #define LOONGARCH_CSR_DERA 0x501 /* Debug era */ 206 #define LOONGARCH_CSR_DSAVE 0x502 /* Debug save */ 207 208 #endif /* LOONGARCH_CPU_CSR_H */ 209