1 /* 2 * x86 segmentation related helpers: 3 * TSS, interrupts, system calls, jumps and call/task gates, descriptors 4 * 5 * Copyright (c) 2003 Fabrice Bellard 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "qemu/log.h" 24 #include "exec/helper-proto.h" 25 #include "exec/exec-all.h" 26 #include "exec/cpu_ldst.h" 27 #include "exec/log.h" 28 #include "helper-tcg.h" 29 #include "seg_helper.h" 30 31 /* return non zero if error */ 32 static inline int load_segment_ra(CPUX86State *env, uint32_t *e1_ptr, 33 uint32_t *e2_ptr, int selector, 34 uintptr_t retaddr) 35 { 36 SegmentCache *dt; 37 int index; 38 target_ulong ptr; 39 40 if (selector & 0x4) { 41 dt = &env->ldt; 42 } else { 43 dt = &env->gdt; 44 } 45 index = selector & ~7; 46 if ((index + 7) > dt->limit) { 47 return -1; 48 } 49 ptr = dt->base + index; 50 *e1_ptr = cpu_ldl_kernel_ra(env, ptr, retaddr); 51 *e2_ptr = cpu_ldl_kernel_ra(env, ptr + 4, retaddr); 52 return 0; 53 } 54 55 static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr, 56 uint32_t *e2_ptr, int selector) 57 { 58 return load_segment_ra(env, e1_ptr, e2_ptr, selector, 0); 59 } 60 61 static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2) 62 { 63 unsigned int limit; 64 65 limit = (e1 & 0xffff) | (e2 & 0x000f0000); 66 if (e2 & DESC_G_MASK) { 67 limit = (limit << 12) | 0xfff; 68 } 69 return limit; 70 } 71 72 static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2) 73 { 74 return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000); 75 } 76 77 static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, 78 uint32_t e2) 79 { 80 sc->base = get_seg_base(e1, e2); 81 sc->limit = get_seg_limit(e1, e2); 82 sc->flags = e2; 83 } 84 85 /* init the segment cache in vm86 mode. */ 86 static inline void load_seg_vm(CPUX86State *env, int seg, int selector) 87 { 88 selector &= 0xffff; 89 90 cpu_x86_load_seg_cache(env, seg, selector, (selector << 4), 0xffff, 91 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 92 DESC_A_MASK | (3 << DESC_DPL_SHIFT)); 93 } 94 95 static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, 96 uint32_t *esp_ptr, int dpl, 97 uintptr_t retaddr) 98 { 99 X86CPU *cpu = env_archcpu(env); 100 int type, index, shift; 101 102 #if 0 103 { 104 int i; 105 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit); 106 for (i = 0; i < env->tr.limit; i++) { 107 printf("%02x ", env->tr.base[i]); 108 if ((i & 7) == 7) { 109 printf("\n"); 110 } 111 } 112 printf("\n"); 113 } 114 #endif 115 116 if (!(env->tr.flags & DESC_P_MASK)) { 117 cpu_abort(CPU(cpu), "invalid tss"); 118 } 119 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; 120 if ((type & 7) != 1) { 121 cpu_abort(CPU(cpu), "invalid tss type"); 122 } 123 shift = type >> 3; 124 index = (dpl * 4 + 2) << shift; 125 if (index + (4 << shift) - 1 > env->tr.limit) { 126 raise_exception_err_ra(env, EXCP0A_TSS, env->tr.selector & 0xfffc, retaddr); 127 } 128 if (shift == 0) { 129 *esp_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index, retaddr); 130 *ss_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index + 2, retaddr); 131 } else { 132 *esp_ptr = cpu_ldl_kernel_ra(env, env->tr.base + index, retaddr); 133 *ss_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index + 4, retaddr); 134 } 135 } 136 137 static void tss_load_seg(CPUX86State *env, X86Seg seg_reg, int selector, 138 int cpl, uintptr_t retaddr) 139 { 140 uint32_t e1, e2; 141 int rpl, dpl; 142 143 if ((selector & 0xfffc) != 0) { 144 if (load_segment_ra(env, &e1, &e2, selector, retaddr) != 0) { 145 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr); 146 } 147 if (!(e2 & DESC_S_MASK)) { 148 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr); 149 } 150 rpl = selector & 3; 151 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 152 if (seg_reg == R_CS) { 153 if (!(e2 & DESC_CS_MASK)) { 154 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr); 155 } 156 if (dpl != rpl) { 157 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr); 158 } 159 } else if (seg_reg == R_SS) { 160 /* SS must be writable data */ 161 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) { 162 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr); 163 } 164 if (dpl != cpl || dpl != rpl) { 165 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr); 166 } 167 } else { 168 /* not readable code */ 169 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) { 170 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr); 171 } 172 /* if data or non conforming code, checks the rights */ 173 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) { 174 if (dpl < cpl || dpl < rpl) { 175 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr); 176 } 177 } 178 } 179 if (!(e2 & DESC_P_MASK)) { 180 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, retaddr); 181 } 182 cpu_x86_load_seg_cache(env, seg_reg, selector, 183 get_seg_base(e1, e2), 184 get_seg_limit(e1, e2), 185 e2); 186 } else { 187 if (seg_reg == R_SS || seg_reg == R_CS) { 188 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr); 189 } 190 } 191 } 192 193 #define SWITCH_TSS_JMP 0 194 #define SWITCH_TSS_IRET 1 195 #define SWITCH_TSS_CALL 2 196 197 /* XXX: restore CPU state in registers (PowerPC case) */ 198 static void switch_tss_ra(CPUX86State *env, int tss_selector, 199 uint32_t e1, uint32_t e2, int source, 200 uint32_t next_eip, uintptr_t retaddr) 201 { 202 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i; 203 target_ulong tss_base; 204 uint32_t new_regs[8], new_segs[6]; 205 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap; 206 uint32_t old_eflags, eflags_mask; 207 SegmentCache *dt; 208 int index; 209 target_ulong ptr; 210 211 type = (e2 >> DESC_TYPE_SHIFT) & 0xf; 212 LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, 213 source); 214 215 /* if task gate, we read the TSS segment and we load it */ 216 if (type == 5) { 217 if (!(e2 & DESC_P_MASK)) { 218 raise_exception_err_ra(env, EXCP0B_NOSEG, tss_selector & 0xfffc, retaddr); 219 } 220 tss_selector = e1 >> 16; 221 if (tss_selector & 4) { 222 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, retaddr); 223 } 224 if (load_segment_ra(env, &e1, &e2, tss_selector, retaddr) != 0) { 225 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr); 226 } 227 if (e2 & DESC_S_MASK) { 228 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr); 229 } 230 type = (e2 >> DESC_TYPE_SHIFT) & 0xf; 231 if ((type & 7) != 1) { 232 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr); 233 } 234 } 235 236 if (!(e2 & DESC_P_MASK)) { 237 raise_exception_err_ra(env, EXCP0B_NOSEG, tss_selector & 0xfffc, retaddr); 238 } 239 240 if (type & 8) { 241 tss_limit_max = 103; 242 } else { 243 tss_limit_max = 43; 244 } 245 tss_limit = get_seg_limit(e1, e2); 246 tss_base = get_seg_base(e1, e2); 247 if ((tss_selector & 4) != 0 || 248 tss_limit < tss_limit_max) { 249 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, retaddr); 250 } 251 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; 252 if (old_type & 8) { 253 old_tss_limit_max = 103; 254 } else { 255 old_tss_limit_max = 43; 256 } 257 258 /* read all the registers from the new TSS */ 259 if (type & 8) { 260 /* 32 bit */ 261 new_cr3 = cpu_ldl_kernel_ra(env, tss_base + 0x1c, retaddr); 262 new_eip = cpu_ldl_kernel_ra(env, tss_base + 0x20, retaddr); 263 new_eflags = cpu_ldl_kernel_ra(env, tss_base + 0x24, retaddr); 264 for (i = 0; i < 8; i++) { 265 new_regs[i] = cpu_ldl_kernel_ra(env, tss_base + (0x28 + i * 4), 266 retaddr); 267 } 268 for (i = 0; i < 6; i++) { 269 new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x48 + i * 4), 270 retaddr); 271 } 272 new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x60, retaddr); 273 new_trap = cpu_ldl_kernel_ra(env, tss_base + 0x64, retaddr); 274 } else { 275 /* 16 bit */ 276 new_cr3 = 0; 277 new_eip = cpu_lduw_kernel_ra(env, tss_base + 0x0e, retaddr); 278 new_eflags = cpu_lduw_kernel_ra(env, tss_base + 0x10, retaddr); 279 for (i = 0; i < 8; i++) { 280 new_regs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x12 + i * 2), retaddr); 281 } 282 for (i = 0; i < 4; i++) { 283 new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 2), 284 retaddr); 285 } 286 new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x2a, retaddr); 287 new_segs[R_FS] = 0; 288 new_segs[R_GS] = 0; 289 new_trap = 0; 290 } 291 /* XXX: avoid a compiler warning, see 292 http://support.amd.com/us/Processor_TechDocs/24593.pdf 293 chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */ 294 (void)new_trap; 295 296 /* NOTE: we must avoid memory exceptions during the task switch, 297 so we make dummy accesses before */ 298 /* XXX: it can still fail in some cases, so a bigger hack is 299 necessary to valid the TLB after having done the accesses */ 300 301 v1 = cpu_ldub_kernel_ra(env, env->tr.base, retaddr); 302 v2 = cpu_ldub_kernel_ra(env, env->tr.base + old_tss_limit_max, retaddr); 303 cpu_stb_kernel_ra(env, env->tr.base, v1, retaddr); 304 cpu_stb_kernel_ra(env, env->tr.base + old_tss_limit_max, v2, retaddr); 305 306 /* clear busy bit (it is restartable) */ 307 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) { 308 target_ulong ptr; 309 uint32_t e2; 310 311 ptr = env->gdt.base + (env->tr.selector & ~7); 312 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr); 313 e2 &= ~DESC_TSS_BUSY_MASK; 314 cpu_stl_kernel_ra(env, ptr + 4, e2, retaddr); 315 } 316 old_eflags = cpu_compute_eflags(env); 317 if (source == SWITCH_TSS_IRET) { 318 old_eflags &= ~NT_MASK; 319 } 320 321 /* save the current state in the old TSS */ 322 if (old_type & 8) { 323 /* 32 bit */ 324 cpu_stl_kernel_ra(env, env->tr.base + 0x20, next_eip, retaddr); 325 cpu_stl_kernel_ra(env, env->tr.base + 0x24, old_eflags, retaddr); 326 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX], retaddr); 327 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX], retaddr); 328 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX], retaddr); 329 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX], retaddr); 330 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP], retaddr); 331 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP], retaddr); 332 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI], retaddr); 333 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI], retaddr); 334 for (i = 0; i < 6; i++) { 335 cpu_stw_kernel_ra(env, env->tr.base + (0x48 + i * 4), 336 env->segs[i].selector, retaddr); 337 } 338 } else { 339 /* 16 bit */ 340 cpu_stw_kernel_ra(env, env->tr.base + 0x0e, next_eip, retaddr); 341 cpu_stw_kernel_ra(env, env->tr.base + 0x10, old_eflags, retaddr); 342 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX], retaddr); 343 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX], retaddr); 344 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX], retaddr); 345 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX], retaddr); 346 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP], retaddr); 347 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP], retaddr); 348 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI], retaddr); 349 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI], retaddr); 350 for (i = 0; i < 4; i++) { 351 cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 2), 352 env->segs[i].selector, retaddr); 353 } 354 } 355 356 /* now if an exception occurs, it will occurs in the next task 357 context */ 358 359 if (source == SWITCH_TSS_CALL) { 360 cpu_stw_kernel_ra(env, tss_base, env->tr.selector, retaddr); 361 new_eflags |= NT_MASK; 362 } 363 364 /* set busy bit */ 365 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) { 366 target_ulong ptr; 367 uint32_t e2; 368 369 ptr = env->gdt.base + (tss_selector & ~7); 370 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr); 371 e2 |= DESC_TSS_BUSY_MASK; 372 cpu_stl_kernel_ra(env, ptr + 4, e2, retaddr); 373 } 374 375 /* set the new CPU state */ 376 /* from this point, any exception which occurs can give problems */ 377 env->cr[0] |= CR0_TS_MASK; 378 env->hflags |= HF_TS_MASK; 379 env->tr.selector = tss_selector; 380 env->tr.base = tss_base; 381 env->tr.limit = tss_limit; 382 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK; 383 384 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) { 385 cpu_x86_update_cr3(env, new_cr3); 386 } 387 388 /* load all registers without an exception, then reload them with 389 possible exception */ 390 env->eip = new_eip; 391 eflags_mask = TF_MASK | AC_MASK | ID_MASK | 392 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK; 393 if (type & 8) { 394 cpu_load_eflags(env, new_eflags, eflags_mask); 395 for (i = 0; i < 8; i++) { 396 env->regs[i] = new_regs[i]; 397 } 398 } else { 399 cpu_load_eflags(env, new_eflags, eflags_mask & 0xffff); 400 for (i = 0; i < 8; i++) { 401 env->regs[i] = (env->regs[i] & 0xffff0000) | new_regs[i]; 402 } 403 } 404 if (new_eflags & VM_MASK) { 405 for (i = 0; i < 6; i++) { 406 load_seg_vm(env, i, new_segs[i]); 407 } 408 } else { 409 /* first just selectors as the rest may trigger exceptions */ 410 for (i = 0; i < 6; i++) { 411 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0); 412 } 413 } 414 415 env->ldt.selector = new_ldt & ~4; 416 env->ldt.base = 0; 417 env->ldt.limit = 0; 418 env->ldt.flags = 0; 419 420 /* load the LDT */ 421 if (new_ldt & 4) { 422 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr); 423 } 424 425 if ((new_ldt & 0xfffc) != 0) { 426 dt = &env->gdt; 427 index = new_ldt & ~7; 428 if ((index + 7) > dt->limit) { 429 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr); 430 } 431 ptr = dt->base + index; 432 e1 = cpu_ldl_kernel_ra(env, ptr, retaddr); 433 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr); 434 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) { 435 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr); 436 } 437 if (!(e2 & DESC_P_MASK)) { 438 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr); 439 } 440 load_seg_cache_raw_dt(&env->ldt, e1, e2); 441 } 442 443 /* load the segments */ 444 if (!(new_eflags & VM_MASK)) { 445 int cpl = new_segs[R_CS] & 3; 446 tss_load_seg(env, R_CS, new_segs[R_CS], cpl, retaddr); 447 tss_load_seg(env, R_SS, new_segs[R_SS], cpl, retaddr); 448 tss_load_seg(env, R_ES, new_segs[R_ES], cpl, retaddr); 449 tss_load_seg(env, R_DS, new_segs[R_DS], cpl, retaddr); 450 tss_load_seg(env, R_FS, new_segs[R_FS], cpl, retaddr); 451 tss_load_seg(env, R_GS, new_segs[R_GS], cpl, retaddr); 452 } 453 454 /* check that env->eip is in the CS segment limits */ 455 if (new_eip > env->segs[R_CS].limit) { 456 /* XXX: different exception if CALL? */ 457 raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr); 458 } 459 460 #ifndef CONFIG_USER_ONLY 461 /* reset local breakpoints */ 462 if (env->dr[7] & DR7_LOCAL_BP_MASK) { 463 cpu_x86_update_dr7(env, env->dr[7] & ~DR7_LOCAL_BP_MASK); 464 } 465 #endif 466 } 467 468 static void switch_tss(CPUX86State *env, int tss_selector, 469 uint32_t e1, uint32_t e2, int source, 470 uint32_t next_eip) 471 { 472 switch_tss_ra(env, tss_selector, e1, e2, source, next_eip, 0); 473 } 474 475 static inline unsigned int get_sp_mask(unsigned int e2) 476 { 477 #ifdef TARGET_X86_64 478 if (e2 & DESC_L_MASK) { 479 return 0; 480 } else 481 #endif 482 if (e2 & DESC_B_MASK) { 483 return 0xffffffff; 484 } else { 485 return 0xffff; 486 } 487 } 488 489 int exception_has_error_code(int intno) 490 { 491 switch (intno) { 492 case 8: 493 case 10: 494 case 11: 495 case 12: 496 case 13: 497 case 14: 498 case 17: 499 return 1; 500 } 501 return 0; 502 } 503 504 #ifdef TARGET_X86_64 505 #define SET_ESP(val, sp_mask) \ 506 do { \ 507 if ((sp_mask) == 0xffff) { \ 508 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \ 509 ((val) & 0xffff); \ 510 } else if ((sp_mask) == 0xffffffffLL) { \ 511 env->regs[R_ESP] = (uint32_t)(val); \ 512 } else { \ 513 env->regs[R_ESP] = (val); \ 514 } \ 515 } while (0) 516 #else 517 #define SET_ESP(val, sp_mask) \ 518 do { \ 519 env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \ 520 ((val) & (sp_mask)); \ 521 } while (0) 522 #endif 523 524 /* in 64-bit machines, this can overflow. So this segment addition macro 525 * can be used to trim the value to 32-bit whenever needed */ 526 #define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask)))) 527 528 /* XXX: add a is_user flag to have proper security support */ 529 #define PUSHW_RA(ssp, sp, sp_mask, val, ra) \ 530 { \ 531 sp -= 2; \ 532 cpu_stw_kernel_ra(env, (ssp) + (sp & (sp_mask)), (val), ra); \ 533 } 534 535 #define PUSHL_RA(ssp, sp, sp_mask, val, ra) \ 536 { \ 537 sp -= 4; \ 538 cpu_stl_kernel_ra(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val), ra); \ 539 } 540 541 #define POPW_RA(ssp, sp, sp_mask, val, ra) \ 542 { \ 543 val = cpu_lduw_kernel_ra(env, (ssp) + (sp & (sp_mask)), ra); \ 544 sp += 2; \ 545 } 546 547 #define POPL_RA(ssp, sp, sp_mask, val, ra) \ 548 { \ 549 val = (uint32_t)cpu_ldl_kernel_ra(env, SEG_ADDL(ssp, sp, sp_mask), ra); \ 550 sp += 4; \ 551 } 552 553 #define PUSHW(ssp, sp, sp_mask, val) PUSHW_RA(ssp, sp, sp_mask, val, 0) 554 #define PUSHL(ssp, sp, sp_mask, val) PUSHL_RA(ssp, sp, sp_mask, val, 0) 555 #define POPW(ssp, sp, sp_mask, val) POPW_RA(ssp, sp, sp_mask, val, 0) 556 #define POPL(ssp, sp, sp_mask, val) POPL_RA(ssp, sp, sp_mask, val, 0) 557 558 /* protected mode interrupt */ 559 static void do_interrupt_protected(CPUX86State *env, int intno, int is_int, 560 int error_code, unsigned int next_eip, 561 int is_hw) 562 { 563 SegmentCache *dt; 564 target_ulong ptr, ssp; 565 int type, dpl, selector, ss_dpl, cpl; 566 int has_error_code, new_stack, shift; 567 uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0; 568 uint32_t old_eip, sp_mask; 569 int vm86 = env->eflags & VM_MASK; 570 571 has_error_code = 0; 572 if (!is_int && !is_hw) { 573 has_error_code = exception_has_error_code(intno); 574 } 575 if (is_int) { 576 old_eip = next_eip; 577 } else { 578 old_eip = env->eip; 579 } 580 581 dt = &env->idt; 582 if (intno * 8 + 7 > dt->limit) { 583 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); 584 } 585 ptr = dt->base + intno * 8; 586 e1 = cpu_ldl_kernel(env, ptr); 587 e2 = cpu_ldl_kernel(env, ptr + 4); 588 /* check gate type */ 589 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; 590 switch (type) { 591 case 5: /* task gate */ 592 case 6: /* 286 interrupt gate */ 593 case 7: /* 286 trap gate */ 594 case 14: /* 386 interrupt gate */ 595 case 15: /* 386 trap gate */ 596 break; 597 default: 598 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); 599 break; 600 } 601 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 602 cpl = env->hflags & HF_CPL_MASK; 603 /* check privilege if software int */ 604 if (is_int && dpl < cpl) { 605 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); 606 } 607 608 if (type == 5) { 609 /* task gate */ 610 /* must do that check here to return the correct error code */ 611 if (!(e2 & DESC_P_MASK)) { 612 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2); 613 } 614 switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip); 615 if (has_error_code) { 616 int type; 617 uint32_t mask; 618 619 /* push the error code */ 620 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; 621 shift = type >> 3; 622 if (env->segs[R_SS].flags & DESC_B_MASK) { 623 mask = 0xffffffff; 624 } else { 625 mask = 0xffff; 626 } 627 esp = (env->regs[R_ESP] - (2 << shift)) & mask; 628 ssp = env->segs[R_SS].base + esp; 629 if (shift) { 630 cpu_stl_kernel(env, ssp, error_code); 631 } else { 632 cpu_stw_kernel(env, ssp, error_code); 633 } 634 SET_ESP(esp, mask); 635 } 636 return; 637 } 638 639 /* Otherwise, trap or interrupt gate */ 640 641 /* check valid bit */ 642 if (!(e2 & DESC_P_MASK)) { 643 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2); 644 } 645 selector = e1 >> 16; 646 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); 647 if ((selector & 0xfffc) == 0) { 648 raise_exception_err(env, EXCP0D_GPF, 0); 649 } 650 if (load_segment(env, &e1, &e2, selector) != 0) { 651 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); 652 } 653 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) { 654 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); 655 } 656 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 657 if (dpl > cpl) { 658 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); 659 } 660 if (!(e2 & DESC_P_MASK)) { 661 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc); 662 } 663 if (e2 & DESC_C_MASK) { 664 dpl = cpl; 665 } 666 if (dpl < cpl) { 667 /* to inner privilege */ 668 get_ss_esp_from_tss(env, &ss, &esp, dpl, 0); 669 if ((ss & 0xfffc) == 0) { 670 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); 671 } 672 if ((ss & 3) != dpl) { 673 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); 674 } 675 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) { 676 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); 677 } 678 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3; 679 if (ss_dpl != dpl) { 680 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); 681 } 682 if (!(ss_e2 & DESC_S_MASK) || 683 (ss_e2 & DESC_CS_MASK) || 684 !(ss_e2 & DESC_W_MASK)) { 685 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); 686 } 687 if (!(ss_e2 & DESC_P_MASK)) { 688 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); 689 } 690 new_stack = 1; 691 sp_mask = get_sp_mask(ss_e2); 692 ssp = get_seg_base(ss_e1, ss_e2); 693 } else { 694 /* to same privilege */ 695 if (vm86) { 696 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); 697 } 698 new_stack = 0; 699 sp_mask = get_sp_mask(env->segs[R_SS].flags); 700 ssp = env->segs[R_SS].base; 701 esp = env->regs[R_ESP]; 702 } 703 704 shift = type >> 3; 705 706 #if 0 707 /* XXX: check that enough room is available */ 708 push_size = 6 + (new_stack << 2) + (has_error_code << 1); 709 if (vm86) { 710 push_size += 8; 711 } 712 push_size <<= shift; 713 #endif 714 if (shift == 1) { 715 if (new_stack) { 716 if (vm86) { 717 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector); 718 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector); 719 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector); 720 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector); 721 } 722 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector); 723 PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]); 724 } 725 PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env)); 726 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector); 727 PUSHL(ssp, esp, sp_mask, old_eip); 728 if (has_error_code) { 729 PUSHL(ssp, esp, sp_mask, error_code); 730 } 731 } else { 732 if (new_stack) { 733 if (vm86) { 734 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector); 735 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector); 736 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector); 737 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector); 738 } 739 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector); 740 PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]); 741 } 742 PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env)); 743 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector); 744 PUSHW(ssp, esp, sp_mask, old_eip); 745 if (has_error_code) { 746 PUSHW(ssp, esp, sp_mask, error_code); 747 } 748 } 749 750 /* interrupt gate clear IF mask */ 751 if ((type & 1) == 0) { 752 env->eflags &= ~IF_MASK; 753 } 754 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); 755 756 if (new_stack) { 757 if (vm86) { 758 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0); 759 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0); 760 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0); 761 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0); 762 } 763 ss = (ss & ~3) | dpl; 764 cpu_x86_load_seg_cache(env, R_SS, ss, 765 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2); 766 } 767 SET_ESP(esp, sp_mask); 768 769 selector = (selector & ~3) | dpl; 770 cpu_x86_load_seg_cache(env, R_CS, selector, 771 get_seg_base(e1, e2), 772 get_seg_limit(e1, e2), 773 e2); 774 env->eip = offset; 775 } 776 777 #ifdef TARGET_X86_64 778 779 #define PUSHQ_RA(sp, val, ra) \ 780 { \ 781 sp -= 8; \ 782 cpu_stq_kernel_ra(env, sp, (val), ra); \ 783 } 784 785 #define POPQ_RA(sp, val, ra) \ 786 { \ 787 val = cpu_ldq_kernel_ra(env, sp, ra); \ 788 sp += 8; \ 789 } 790 791 #define PUSHQ(sp, val) PUSHQ_RA(sp, val, 0) 792 #define POPQ(sp, val) POPQ_RA(sp, val, 0) 793 794 static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) 795 { 796 X86CPU *cpu = env_archcpu(env); 797 int index; 798 799 #if 0 800 printf("TR: base=" TARGET_FMT_lx " limit=%x\n", 801 env->tr.base, env->tr.limit); 802 #endif 803 804 if (!(env->tr.flags & DESC_P_MASK)) { 805 cpu_abort(CPU(cpu), "invalid tss"); 806 } 807 index = 8 * level + 4; 808 if ((index + 7) > env->tr.limit) { 809 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc); 810 } 811 return cpu_ldq_kernel(env, env->tr.base + index); 812 } 813 814 /* 64 bit interrupt */ 815 static void do_interrupt64(CPUX86State *env, int intno, int is_int, 816 int error_code, target_ulong next_eip, int is_hw) 817 { 818 SegmentCache *dt; 819 target_ulong ptr; 820 int type, dpl, selector, cpl, ist; 821 int has_error_code, new_stack; 822 uint32_t e1, e2, e3, ss; 823 target_ulong old_eip, esp, offset; 824 825 has_error_code = 0; 826 if (!is_int && !is_hw) { 827 has_error_code = exception_has_error_code(intno); 828 } 829 if (is_int) { 830 old_eip = next_eip; 831 } else { 832 old_eip = env->eip; 833 } 834 835 dt = &env->idt; 836 if (intno * 16 + 15 > dt->limit) { 837 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); 838 } 839 ptr = dt->base + intno * 16; 840 e1 = cpu_ldl_kernel(env, ptr); 841 e2 = cpu_ldl_kernel(env, ptr + 4); 842 e3 = cpu_ldl_kernel(env, ptr + 8); 843 /* check gate type */ 844 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; 845 switch (type) { 846 case 14: /* 386 interrupt gate */ 847 case 15: /* 386 trap gate */ 848 break; 849 default: 850 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); 851 break; 852 } 853 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 854 cpl = env->hflags & HF_CPL_MASK; 855 /* check privilege if software int */ 856 if (is_int && dpl < cpl) { 857 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); 858 } 859 /* check valid bit */ 860 if (!(e2 & DESC_P_MASK)) { 861 raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2); 862 } 863 selector = e1 >> 16; 864 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff); 865 ist = e2 & 7; 866 if ((selector & 0xfffc) == 0) { 867 raise_exception_err(env, EXCP0D_GPF, 0); 868 } 869 870 if (load_segment(env, &e1, &e2, selector) != 0) { 871 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); 872 } 873 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) { 874 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); 875 } 876 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 877 if (dpl > cpl) { 878 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); 879 } 880 if (!(e2 & DESC_P_MASK)) { 881 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc); 882 } 883 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) { 884 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); 885 } 886 if (e2 & DESC_C_MASK) { 887 dpl = cpl; 888 } 889 if (dpl < cpl || ist != 0) { 890 /* to inner privilege */ 891 new_stack = 1; 892 esp = get_rsp_from_tss(env, ist != 0 ? ist + 3 : dpl); 893 ss = 0; 894 } else { 895 /* to same privilege */ 896 if (env->eflags & VM_MASK) { 897 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc); 898 } 899 new_stack = 0; 900 esp = env->regs[R_ESP]; 901 } 902 esp &= ~0xfLL; /* align stack */ 903 904 PUSHQ(esp, env->segs[R_SS].selector); 905 PUSHQ(esp, env->regs[R_ESP]); 906 PUSHQ(esp, cpu_compute_eflags(env)); 907 PUSHQ(esp, env->segs[R_CS].selector); 908 PUSHQ(esp, old_eip); 909 if (has_error_code) { 910 PUSHQ(esp, error_code); 911 } 912 913 /* interrupt gate clear IF mask */ 914 if ((type & 1) == 0) { 915 env->eflags &= ~IF_MASK; 916 } 917 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); 918 919 if (new_stack) { 920 ss = 0 | dpl; 921 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, dpl << DESC_DPL_SHIFT); 922 } 923 env->regs[R_ESP] = esp; 924 925 selector = (selector & ~3) | dpl; 926 cpu_x86_load_seg_cache(env, R_CS, selector, 927 get_seg_base(e1, e2), 928 get_seg_limit(e1, e2), 929 e2); 930 env->eip = offset; 931 } 932 933 void helper_sysret(CPUX86State *env, int dflag) 934 { 935 int cpl, selector; 936 937 if (!(env->efer & MSR_EFER_SCE)) { 938 raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC()); 939 } 940 cpl = env->hflags & HF_CPL_MASK; 941 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) { 942 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 943 } 944 selector = (env->star >> 48) & 0xffff; 945 if (env->hflags & HF_LMA_MASK) { 946 cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK 947 | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | 948 NT_MASK); 949 if (dflag == 2) { 950 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3, 951 0, 0xffffffff, 952 DESC_G_MASK | DESC_P_MASK | 953 DESC_S_MASK | (3 << DESC_DPL_SHIFT) | 954 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | 955 DESC_L_MASK); 956 env->eip = env->regs[R_ECX]; 957 } else { 958 cpu_x86_load_seg_cache(env, R_CS, selector | 3, 959 0, 0xffffffff, 960 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 961 DESC_S_MASK | (3 << DESC_DPL_SHIFT) | 962 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); 963 env->eip = (uint32_t)env->regs[R_ECX]; 964 } 965 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3, 966 0, 0xffffffff, 967 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 968 DESC_S_MASK | (3 << DESC_DPL_SHIFT) | 969 DESC_W_MASK | DESC_A_MASK); 970 } else { 971 env->eflags |= IF_MASK; 972 cpu_x86_load_seg_cache(env, R_CS, selector | 3, 973 0, 0xffffffff, 974 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 975 DESC_S_MASK | (3 << DESC_DPL_SHIFT) | 976 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); 977 env->eip = (uint32_t)env->regs[R_ECX]; 978 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3, 979 0, 0xffffffff, 980 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 981 DESC_S_MASK | (3 << DESC_DPL_SHIFT) | 982 DESC_W_MASK | DESC_A_MASK); 983 } 984 } 985 #endif /* TARGET_X86_64 */ 986 987 /* real mode interrupt */ 988 static void do_interrupt_real(CPUX86State *env, int intno, int is_int, 989 int error_code, unsigned int next_eip) 990 { 991 SegmentCache *dt; 992 target_ulong ptr, ssp; 993 int selector; 994 uint32_t offset, esp; 995 uint32_t old_cs, old_eip; 996 997 /* real mode (simpler!) */ 998 dt = &env->idt; 999 if (intno * 4 + 3 > dt->limit) { 1000 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); 1001 } 1002 ptr = dt->base + intno * 4; 1003 offset = cpu_lduw_kernel(env, ptr); 1004 selector = cpu_lduw_kernel(env, ptr + 2); 1005 esp = env->regs[R_ESP]; 1006 ssp = env->segs[R_SS].base; 1007 if (is_int) { 1008 old_eip = next_eip; 1009 } else { 1010 old_eip = env->eip; 1011 } 1012 old_cs = env->segs[R_CS].selector; 1013 /* XXX: use SS segment size? */ 1014 PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env)); 1015 PUSHW(ssp, esp, 0xffff, old_cs); 1016 PUSHW(ssp, esp, 0xffff, old_eip); 1017 1018 /* update processor state */ 1019 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff); 1020 env->eip = offset; 1021 env->segs[R_CS].selector = selector; 1022 env->segs[R_CS].base = (selector << 4); 1023 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK); 1024 } 1025 1026 /* 1027 * Begin execution of an interruption. is_int is TRUE if coming from 1028 * the int instruction. next_eip is the env->eip value AFTER the interrupt 1029 * instruction. It is only relevant if is_int is TRUE. 1030 */ 1031 void do_interrupt_all(X86CPU *cpu, int intno, int is_int, 1032 int error_code, target_ulong next_eip, int is_hw) 1033 { 1034 CPUX86State *env = &cpu->env; 1035 1036 if (qemu_loglevel_mask(CPU_LOG_INT)) { 1037 if ((env->cr[0] & CR0_PE_MASK)) { 1038 static int count; 1039 1040 qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx 1041 " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx, 1042 count, intno, error_code, is_int, 1043 env->hflags & HF_CPL_MASK, 1044 env->segs[R_CS].selector, env->eip, 1045 (int)env->segs[R_CS].base + env->eip, 1046 env->segs[R_SS].selector, env->regs[R_ESP]); 1047 if (intno == 0x0e) { 1048 qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]); 1049 } else { 1050 qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]); 1051 } 1052 qemu_log("\n"); 1053 log_cpu_state(CPU(cpu), CPU_DUMP_CCOP); 1054 #if 0 1055 { 1056 int i; 1057 target_ulong ptr; 1058 1059 qemu_log(" code="); 1060 ptr = env->segs[R_CS].base + env->eip; 1061 for (i = 0; i < 16; i++) { 1062 qemu_log(" %02x", ldub(ptr + i)); 1063 } 1064 qemu_log("\n"); 1065 } 1066 #endif 1067 count++; 1068 } 1069 } 1070 if (env->cr[0] & CR0_PE_MASK) { 1071 #if !defined(CONFIG_USER_ONLY) 1072 if (env->hflags & HF_GUEST_MASK) { 1073 handle_even_inj(env, intno, is_int, error_code, is_hw, 0); 1074 } 1075 #endif 1076 #ifdef TARGET_X86_64 1077 if (env->hflags & HF_LMA_MASK) { 1078 do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw); 1079 } else 1080 #endif 1081 { 1082 do_interrupt_protected(env, intno, is_int, error_code, next_eip, 1083 is_hw); 1084 } 1085 } else { 1086 #if !defined(CONFIG_USER_ONLY) 1087 if (env->hflags & HF_GUEST_MASK) { 1088 handle_even_inj(env, intno, is_int, error_code, is_hw, 1); 1089 } 1090 #endif 1091 do_interrupt_real(env, intno, is_int, error_code, next_eip); 1092 } 1093 1094 #if !defined(CONFIG_USER_ONLY) 1095 if (env->hflags & HF_GUEST_MASK) { 1096 CPUState *cs = CPU(cpu); 1097 uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb + 1098 offsetof(struct vmcb, 1099 control.event_inj)); 1100 1101 x86_stl_phys(cs, 1102 env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 1103 event_inj & ~SVM_EVTINJ_VALID); 1104 } 1105 #endif 1106 } 1107 1108 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) 1109 { 1110 do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); 1111 } 1112 1113 #ifndef CONFIG_USER_ONLY 1114 bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 1115 { 1116 X86CPU *cpu = X86_CPU(cs); 1117 CPUX86State *env = &cpu->env; 1118 int intno; 1119 1120 interrupt_request = x86_cpu_pending_interrupt(cs, interrupt_request); 1121 if (!interrupt_request) { 1122 return false; 1123 } 1124 1125 /* Don't process multiple interrupt requests in a single call. 1126 * This is required to make icount-driven execution deterministic. 1127 */ 1128 switch (interrupt_request) { 1129 case CPU_INTERRUPT_POLL: 1130 cs->interrupt_request &= ~CPU_INTERRUPT_POLL; 1131 apic_poll_irq(cpu->apic_state); 1132 break; 1133 case CPU_INTERRUPT_SIPI: 1134 do_cpu_sipi(cpu); 1135 break; 1136 case CPU_INTERRUPT_SMI: 1137 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); 1138 cs->interrupt_request &= ~CPU_INTERRUPT_SMI; 1139 do_smm_enter(cpu); 1140 break; 1141 case CPU_INTERRUPT_NMI: 1142 cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); 1143 cs->interrupt_request &= ~CPU_INTERRUPT_NMI; 1144 env->hflags2 |= HF2_NMI_MASK; 1145 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); 1146 break; 1147 case CPU_INTERRUPT_MCE: 1148 cs->interrupt_request &= ~CPU_INTERRUPT_MCE; 1149 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); 1150 break; 1151 case CPU_INTERRUPT_HARD: 1152 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0); 1153 cs->interrupt_request &= ~(CPU_INTERRUPT_HARD | 1154 CPU_INTERRUPT_VIRQ); 1155 intno = cpu_get_pic_interrupt(env); 1156 qemu_log_mask(CPU_LOG_TB_IN_ASM, 1157 "Servicing hardware INT=0x%02x\n", intno); 1158 do_interrupt_x86_hardirq(env, intno, 1); 1159 break; 1160 case CPU_INTERRUPT_VIRQ: 1161 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); 1162 intno = x86_ldl_phys(cs, env->vm_vmcb 1163 + offsetof(struct vmcb, control.int_vector)); 1164 qemu_log_mask(CPU_LOG_TB_IN_ASM, 1165 "Servicing virtual hardware INT=0x%02x\n", intno); 1166 do_interrupt_x86_hardirq(env, intno, 1); 1167 cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; 1168 env->int_ctl &= ~V_IRQ_MASK; 1169 break; 1170 } 1171 1172 /* Ensure that no TB jump will be modified as the program flow was changed. */ 1173 return true; 1174 } 1175 #endif /* CONFIG_USER_ONLY */ 1176 1177 void helper_lldt(CPUX86State *env, int selector) 1178 { 1179 SegmentCache *dt; 1180 uint32_t e1, e2; 1181 int index, entry_limit; 1182 target_ulong ptr; 1183 1184 selector &= 0xffff; 1185 if ((selector & 0xfffc) == 0) { 1186 /* XXX: NULL selector case: invalid LDT */ 1187 env->ldt.base = 0; 1188 env->ldt.limit = 0; 1189 } else { 1190 if (selector & 0x4) { 1191 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1192 } 1193 dt = &env->gdt; 1194 index = selector & ~7; 1195 #ifdef TARGET_X86_64 1196 if (env->hflags & HF_LMA_MASK) { 1197 entry_limit = 15; 1198 } else 1199 #endif 1200 { 1201 entry_limit = 7; 1202 } 1203 if ((index + entry_limit) > dt->limit) { 1204 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1205 } 1206 ptr = dt->base + index; 1207 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC()); 1208 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC()); 1209 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) { 1210 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1211 } 1212 if (!(e2 & DESC_P_MASK)) { 1213 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC()); 1214 } 1215 #ifdef TARGET_X86_64 1216 if (env->hflags & HF_LMA_MASK) { 1217 uint32_t e3; 1218 1219 e3 = cpu_ldl_kernel_ra(env, ptr + 8, GETPC()); 1220 load_seg_cache_raw_dt(&env->ldt, e1, e2); 1221 env->ldt.base |= (target_ulong)e3 << 32; 1222 } else 1223 #endif 1224 { 1225 load_seg_cache_raw_dt(&env->ldt, e1, e2); 1226 } 1227 } 1228 env->ldt.selector = selector; 1229 } 1230 1231 void helper_ltr(CPUX86State *env, int selector) 1232 { 1233 SegmentCache *dt; 1234 uint32_t e1, e2; 1235 int index, type, entry_limit; 1236 target_ulong ptr; 1237 1238 selector &= 0xffff; 1239 if ((selector & 0xfffc) == 0) { 1240 /* NULL selector case: invalid TR */ 1241 env->tr.base = 0; 1242 env->tr.limit = 0; 1243 env->tr.flags = 0; 1244 } else { 1245 if (selector & 0x4) { 1246 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1247 } 1248 dt = &env->gdt; 1249 index = selector & ~7; 1250 #ifdef TARGET_X86_64 1251 if (env->hflags & HF_LMA_MASK) { 1252 entry_limit = 15; 1253 } else 1254 #endif 1255 { 1256 entry_limit = 7; 1257 } 1258 if ((index + entry_limit) > dt->limit) { 1259 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1260 } 1261 ptr = dt->base + index; 1262 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC()); 1263 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC()); 1264 type = (e2 >> DESC_TYPE_SHIFT) & 0xf; 1265 if ((e2 & DESC_S_MASK) || 1266 (type != 1 && type != 9)) { 1267 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1268 } 1269 if (!(e2 & DESC_P_MASK)) { 1270 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC()); 1271 } 1272 #ifdef TARGET_X86_64 1273 if (env->hflags & HF_LMA_MASK) { 1274 uint32_t e3, e4; 1275 1276 e3 = cpu_ldl_kernel_ra(env, ptr + 8, GETPC()); 1277 e4 = cpu_ldl_kernel_ra(env, ptr + 12, GETPC()); 1278 if ((e4 >> DESC_TYPE_SHIFT) & 0xf) { 1279 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1280 } 1281 load_seg_cache_raw_dt(&env->tr, e1, e2); 1282 env->tr.base |= (target_ulong)e3 << 32; 1283 } else 1284 #endif 1285 { 1286 load_seg_cache_raw_dt(&env->tr, e1, e2); 1287 } 1288 e2 |= DESC_TSS_BUSY_MASK; 1289 cpu_stl_kernel_ra(env, ptr + 4, e2, GETPC()); 1290 } 1291 env->tr.selector = selector; 1292 } 1293 1294 /* only works if protected mode and not VM86. seg_reg must be != R_CS */ 1295 void helper_load_seg(CPUX86State *env, int seg_reg, int selector) 1296 { 1297 uint32_t e1, e2; 1298 int cpl, dpl, rpl; 1299 SegmentCache *dt; 1300 int index; 1301 target_ulong ptr; 1302 1303 selector &= 0xffff; 1304 cpl = env->hflags & HF_CPL_MASK; 1305 if ((selector & 0xfffc) == 0) { 1306 /* null selector case */ 1307 if (seg_reg == R_SS 1308 #ifdef TARGET_X86_64 1309 && (!(env->hflags & HF_CS64_MASK) || cpl == 3) 1310 #endif 1311 ) { 1312 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 1313 } 1314 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0); 1315 } else { 1316 1317 if (selector & 0x4) { 1318 dt = &env->ldt; 1319 } else { 1320 dt = &env->gdt; 1321 } 1322 index = selector & ~7; 1323 if ((index + 7) > dt->limit) { 1324 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1325 } 1326 ptr = dt->base + index; 1327 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC()); 1328 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC()); 1329 1330 if (!(e2 & DESC_S_MASK)) { 1331 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1332 } 1333 rpl = selector & 3; 1334 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 1335 if (seg_reg == R_SS) { 1336 /* must be writable segment */ 1337 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) { 1338 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1339 } 1340 if (rpl != cpl || dpl != cpl) { 1341 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1342 } 1343 } else { 1344 /* must be readable segment */ 1345 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) { 1346 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1347 } 1348 1349 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) { 1350 /* if not conforming code, test rights */ 1351 if (dpl < cpl || dpl < rpl) { 1352 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1353 } 1354 } 1355 } 1356 1357 if (!(e2 & DESC_P_MASK)) { 1358 if (seg_reg == R_SS) { 1359 raise_exception_err_ra(env, EXCP0C_STACK, selector & 0xfffc, GETPC()); 1360 } else { 1361 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC()); 1362 } 1363 } 1364 1365 /* set the access bit if not already set */ 1366 if (!(e2 & DESC_A_MASK)) { 1367 e2 |= DESC_A_MASK; 1368 cpu_stl_kernel_ra(env, ptr + 4, e2, GETPC()); 1369 } 1370 1371 cpu_x86_load_seg_cache(env, seg_reg, selector, 1372 get_seg_base(e1, e2), 1373 get_seg_limit(e1, e2), 1374 e2); 1375 #if 0 1376 qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n", 1377 selector, (unsigned long)sc->base, sc->limit, sc->flags); 1378 #endif 1379 } 1380 } 1381 1382 /* protected mode jump */ 1383 void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip, 1384 target_ulong next_eip) 1385 { 1386 int gate_cs, type; 1387 uint32_t e1, e2, cpl, dpl, rpl, limit; 1388 1389 if ((new_cs & 0xfffc) == 0) { 1390 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 1391 } 1392 if (load_segment_ra(env, &e1, &e2, new_cs, GETPC()) != 0) { 1393 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1394 } 1395 cpl = env->hflags & HF_CPL_MASK; 1396 if (e2 & DESC_S_MASK) { 1397 if (!(e2 & DESC_CS_MASK)) { 1398 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1399 } 1400 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 1401 if (e2 & DESC_C_MASK) { 1402 /* conforming code segment */ 1403 if (dpl > cpl) { 1404 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1405 } 1406 } else { 1407 /* non conforming code segment */ 1408 rpl = new_cs & 3; 1409 if (rpl > cpl) { 1410 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1411 } 1412 if (dpl != cpl) { 1413 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1414 } 1415 } 1416 if (!(e2 & DESC_P_MASK)) { 1417 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC()); 1418 } 1419 limit = get_seg_limit(e1, e2); 1420 if (new_eip > limit && 1421 (!(env->hflags & HF_LMA_MASK) || !(e2 & DESC_L_MASK))) { 1422 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 1423 } 1424 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl, 1425 get_seg_base(e1, e2), limit, e2); 1426 env->eip = new_eip; 1427 } else { 1428 /* jump to call or task gate */ 1429 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 1430 rpl = new_cs & 3; 1431 cpl = env->hflags & HF_CPL_MASK; 1432 type = (e2 >> DESC_TYPE_SHIFT) & 0xf; 1433 1434 #ifdef TARGET_X86_64 1435 if (env->efer & MSR_EFER_LMA) { 1436 if (type != 12) { 1437 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1438 } 1439 } 1440 #endif 1441 switch (type) { 1442 case 1: /* 286 TSS */ 1443 case 9: /* 386 TSS */ 1444 case 5: /* task gate */ 1445 if (dpl < cpl || dpl < rpl) { 1446 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1447 } 1448 switch_tss_ra(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip, GETPC()); 1449 break; 1450 case 4: /* 286 call gate */ 1451 case 12: /* 386 call gate */ 1452 if ((dpl < cpl) || (dpl < rpl)) { 1453 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1454 } 1455 if (!(e2 & DESC_P_MASK)) { 1456 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC()); 1457 } 1458 gate_cs = e1 >> 16; 1459 new_eip = (e1 & 0xffff); 1460 if (type == 12) { 1461 new_eip |= (e2 & 0xffff0000); 1462 } 1463 1464 #ifdef TARGET_X86_64 1465 if (env->efer & MSR_EFER_LMA) { 1466 /* load the upper 8 bytes of the 64-bit call gate */ 1467 if (load_segment_ra(env, &e1, &e2, new_cs + 8, GETPC())) { 1468 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, 1469 GETPC()); 1470 } 1471 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; 1472 if (type != 0) { 1473 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, 1474 GETPC()); 1475 } 1476 new_eip |= ((target_ulong)e1) << 32; 1477 } 1478 #endif 1479 1480 if (load_segment_ra(env, &e1, &e2, gate_cs, GETPC()) != 0) { 1481 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC()); 1482 } 1483 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 1484 /* must be code segment */ 1485 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) != 1486 (DESC_S_MASK | DESC_CS_MASK))) { 1487 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC()); 1488 } 1489 if (((e2 & DESC_C_MASK) && (dpl > cpl)) || 1490 (!(e2 & DESC_C_MASK) && (dpl != cpl))) { 1491 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC()); 1492 } 1493 #ifdef TARGET_X86_64 1494 if (env->efer & MSR_EFER_LMA) { 1495 if (!(e2 & DESC_L_MASK)) { 1496 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC()); 1497 } 1498 if (e2 & DESC_B_MASK) { 1499 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC()); 1500 } 1501 } 1502 #endif 1503 if (!(e2 & DESC_P_MASK)) { 1504 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC()); 1505 } 1506 limit = get_seg_limit(e1, e2); 1507 if (new_eip > limit && 1508 (!(env->hflags & HF_LMA_MASK) || !(e2 & DESC_L_MASK))) { 1509 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 1510 } 1511 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl, 1512 get_seg_base(e1, e2), limit, e2); 1513 env->eip = new_eip; 1514 break; 1515 default: 1516 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1517 break; 1518 } 1519 } 1520 } 1521 1522 /* real mode call */ 1523 void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1, 1524 int shift, int next_eip) 1525 { 1526 int new_eip; 1527 uint32_t esp, esp_mask; 1528 target_ulong ssp; 1529 1530 new_eip = new_eip1; 1531 esp = env->regs[R_ESP]; 1532 esp_mask = get_sp_mask(env->segs[R_SS].flags); 1533 ssp = env->segs[R_SS].base; 1534 if (shift) { 1535 PUSHL_RA(ssp, esp, esp_mask, env->segs[R_CS].selector, GETPC()); 1536 PUSHL_RA(ssp, esp, esp_mask, next_eip, GETPC()); 1537 } else { 1538 PUSHW_RA(ssp, esp, esp_mask, env->segs[R_CS].selector, GETPC()); 1539 PUSHW_RA(ssp, esp, esp_mask, next_eip, GETPC()); 1540 } 1541 1542 SET_ESP(esp, esp_mask); 1543 env->eip = new_eip; 1544 env->segs[R_CS].selector = new_cs; 1545 env->segs[R_CS].base = (new_cs << 4); 1546 } 1547 1548 /* protected mode call */ 1549 void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, 1550 int shift, target_ulong next_eip) 1551 { 1552 int new_stack, i; 1553 uint32_t e1, e2, cpl, dpl, rpl, selector, param_count; 1554 uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, type, ss_dpl, sp_mask; 1555 uint32_t val, limit, old_sp_mask; 1556 target_ulong ssp, old_ssp, offset, sp; 1557 1558 LOG_PCALL("lcall %04x:" TARGET_FMT_lx " s=%d\n", new_cs, new_eip, shift); 1559 LOG_PCALL_STATE(env_cpu(env)); 1560 if ((new_cs & 0xfffc) == 0) { 1561 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 1562 } 1563 if (load_segment_ra(env, &e1, &e2, new_cs, GETPC()) != 0) { 1564 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1565 } 1566 cpl = env->hflags & HF_CPL_MASK; 1567 LOG_PCALL("desc=%08x:%08x\n", e1, e2); 1568 if (e2 & DESC_S_MASK) { 1569 if (!(e2 & DESC_CS_MASK)) { 1570 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1571 } 1572 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 1573 if (e2 & DESC_C_MASK) { 1574 /* conforming code segment */ 1575 if (dpl > cpl) { 1576 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1577 } 1578 } else { 1579 /* non conforming code segment */ 1580 rpl = new_cs & 3; 1581 if (rpl > cpl) { 1582 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1583 } 1584 if (dpl != cpl) { 1585 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1586 } 1587 } 1588 if (!(e2 & DESC_P_MASK)) { 1589 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC()); 1590 } 1591 1592 #ifdef TARGET_X86_64 1593 /* XXX: check 16/32 bit cases in long mode */ 1594 if (shift == 2) { 1595 target_ulong rsp; 1596 1597 /* 64 bit case */ 1598 rsp = env->regs[R_ESP]; 1599 PUSHQ_RA(rsp, env->segs[R_CS].selector, GETPC()); 1600 PUSHQ_RA(rsp, next_eip, GETPC()); 1601 /* from this point, not restartable */ 1602 env->regs[R_ESP] = rsp; 1603 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl, 1604 get_seg_base(e1, e2), 1605 get_seg_limit(e1, e2), e2); 1606 env->eip = new_eip; 1607 } else 1608 #endif 1609 { 1610 sp = env->regs[R_ESP]; 1611 sp_mask = get_sp_mask(env->segs[R_SS].flags); 1612 ssp = env->segs[R_SS].base; 1613 if (shift) { 1614 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC()); 1615 PUSHL_RA(ssp, sp, sp_mask, next_eip, GETPC()); 1616 } else { 1617 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC()); 1618 PUSHW_RA(ssp, sp, sp_mask, next_eip, GETPC()); 1619 } 1620 1621 limit = get_seg_limit(e1, e2); 1622 if (new_eip > limit) { 1623 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1624 } 1625 /* from this point, not restartable */ 1626 SET_ESP(sp, sp_mask); 1627 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl, 1628 get_seg_base(e1, e2), limit, e2); 1629 env->eip = new_eip; 1630 } 1631 } else { 1632 /* check gate type */ 1633 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; 1634 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 1635 rpl = new_cs & 3; 1636 1637 #ifdef TARGET_X86_64 1638 if (env->efer & MSR_EFER_LMA) { 1639 if (type != 12) { 1640 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1641 } 1642 } 1643 #endif 1644 1645 switch (type) { 1646 case 1: /* available 286 TSS */ 1647 case 9: /* available 386 TSS */ 1648 case 5: /* task gate */ 1649 if (dpl < cpl || dpl < rpl) { 1650 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1651 } 1652 switch_tss_ra(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip, GETPC()); 1653 return; 1654 case 4: /* 286 call gate */ 1655 case 12: /* 386 call gate */ 1656 break; 1657 default: 1658 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1659 break; 1660 } 1661 shift = type >> 3; 1662 1663 if (dpl < cpl || dpl < rpl) { 1664 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC()); 1665 } 1666 /* check valid bit */ 1667 if (!(e2 & DESC_P_MASK)) { 1668 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC()); 1669 } 1670 selector = e1 >> 16; 1671 param_count = e2 & 0x1f; 1672 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); 1673 #ifdef TARGET_X86_64 1674 if (env->efer & MSR_EFER_LMA) { 1675 /* load the upper 8 bytes of the 64-bit call gate */ 1676 if (load_segment_ra(env, &e1, &e2, new_cs + 8, GETPC())) { 1677 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, 1678 GETPC()); 1679 } 1680 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f; 1681 if (type != 0) { 1682 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, 1683 GETPC()); 1684 } 1685 offset |= ((target_ulong)e1) << 32; 1686 } 1687 #endif 1688 if ((selector & 0xfffc) == 0) { 1689 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 1690 } 1691 1692 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) { 1693 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1694 } 1695 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) { 1696 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1697 } 1698 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 1699 if (dpl > cpl) { 1700 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1701 } 1702 #ifdef TARGET_X86_64 1703 if (env->efer & MSR_EFER_LMA) { 1704 if (!(e2 & DESC_L_MASK)) { 1705 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1706 } 1707 if (e2 & DESC_B_MASK) { 1708 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC()); 1709 } 1710 shift++; 1711 } 1712 #endif 1713 if (!(e2 & DESC_P_MASK)) { 1714 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC()); 1715 } 1716 1717 if (!(e2 & DESC_C_MASK) && dpl < cpl) { 1718 /* to inner privilege */ 1719 #ifdef TARGET_X86_64 1720 if (shift == 2) { 1721 sp = get_rsp_from_tss(env, dpl); 1722 ss = dpl; /* SS = NULL selector with RPL = new CPL */ 1723 new_stack = 1; 1724 sp_mask = 0; 1725 ssp = 0; /* SS base is always zero in IA-32e mode */ 1726 LOG_PCALL("new ss:rsp=%04x:%016llx env->regs[R_ESP]=" 1727 TARGET_FMT_lx "\n", ss, sp, env->regs[R_ESP]); 1728 } else 1729 #endif 1730 { 1731 uint32_t sp32; 1732 get_ss_esp_from_tss(env, &ss, &sp32, dpl, GETPC()); 1733 LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" 1734 TARGET_FMT_lx "\n", ss, sp32, param_count, 1735 env->regs[R_ESP]); 1736 sp = sp32; 1737 if ((ss & 0xfffc) == 0) { 1738 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC()); 1739 } 1740 if ((ss & 3) != dpl) { 1741 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC()); 1742 } 1743 if (load_segment_ra(env, &ss_e1, &ss_e2, ss, GETPC()) != 0) { 1744 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC()); 1745 } 1746 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3; 1747 if (ss_dpl != dpl) { 1748 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC()); 1749 } 1750 if (!(ss_e2 & DESC_S_MASK) || 1751 (ss_e2 & DESC_CS_MASK) || 1752 !(ss_e2 & DESC_W_MASK)) { 1753 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC()); 1754 } 1755 if (!(ss_e2 & DESC_P_MASK)) { 1756 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC()); 1757 } 1758 1759 sp_mask = get_sp_mask(ss_e2); 1760 ssp = get_seg_base(ss_e1, ss_e2); 1761 } 1762 1763 /* push_size = ((param_count * 2) + 8) << shift; */ 1764 1765 old_sp_mask = get_sp_mask(env->segs[R_SS].flags); 1766 old_ssp = env->segs[R_SS].base; 1767 #ifdef TARGET_X86_64 1768 if (shift == 2) { 1769 /* XXX: verify if new stack address is canonical */ 1770 PUSHQ_RA(sp, env->segs[R_SS].selector, GETPC()); 1771 PUSHQ_RA(sp, env->regs[R_ESP], GETPC()); 1772 /* parameters aren't supported for 64-bit call gates */ 1773 } else 1774 #endif 1775 if (shift == 1) { 1776 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_SS].selector, GETPC()); 1777 PUSHL_RA(ssp, sp, sp_mask, env->regs[R_ESP], GETPC()); 1778 for (i = param_count - 1; i >= 0; i--) { 1779 val = cpu_ldl_kernel_ra(env, old_ssp + 1780 ((env->regs[R_ESP] + i * 4) & 1781 old_sp_mask), GETPC()); 1782 PUSHL_RA(ssp, sp, sp_mask, val, GETPC()); 1783 } 1784 } else { 1785 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_SS].selector, GETPC()); 1786 PUSHW_RA(ssp, sp, sp_mask, env->regs[R_ESP], GETPC()); 1787 for (i = param_count - 1; i >= 0; i--) { 1788 val = cpu_lduw_kernel_ra(env, old_ssp + 1789 ((env->regs[R_ESP] + i * 2) & 1790 old_sp_mask), GETPC()); 1791 PUSHW_RA(ssp, sp, sp_mask, val, GETPC()); 1792 } 1793 } 1794 new_stack = 1; 1795 } else { 1796 /* to same privilege */ 1797 sp = env->regs[R_ESP]; 1798 sp_mask = get_sp_mask(env->segs[R_SS].flags); 1799 ssp = env->segs[R_SS].base; 1800 /* push_size = (4 << shift); */ 1801 new_stack = 0; 1802 } 1803 1804 #ifdef TARGET_X86_64 1805 if (shift == 2) { 1806 PUSHQ_RA(sp, env->segs[R_CS].selector, GETPC()); 1807 PUSHQ_RA(sp, next_eip, GETPC()); 1808 } else 1809 #endif 1810 if (shift == 1) { 1811 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC()); 1812 PUSHL_RA(ssp, sp, sp_mask, next_eip, GETPC()); 1813 } else { 1814 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC()); 1815 PUSHW_RA(ssp, sp, sp_mask, next_eip, GETPC()); 1816 } 1817 1818 /* from this point, not restartable */ 1819 1820 if (new_stack) { 1821 #ifdef TARGET_X86_64 1822 if (shift == 2) { 1823 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0); 1824 } else 1825 #endif 1826 { 1827 ss = (ss & ~3) | dpl; 1828 cpu_x86_load_seg_cache(env, R_SS, ss, 1829 ssp, 1830 get_seg_limit(ss_e1, ss_e2), 1831 ss_e2); 1832 } 1833 } 1834 1835 selector = (selector & ~3) | dpl; 1836 cpu_x86_load_seg_cache(env, R_CS, selector, 1837 get_seg_base(e1, e2), 1838 get_seg_limit(e1, e2), 1839 e2); 1840 SET_ESP(sp, sp_mask); 1841 env->eip = offset; 1842 } 1843 } 1844 1845 /* real and vm86 mode iret */ 1846 void helper_iret_real(CPUX86State *env, int shift) 1847 { 1848 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask; 1849 target_ulong ssp; 1850 int eflags_mask; 1851 1852 sp_mask = 0xffff; /* XXXX: use SS segment size? */ 1853 sp = env->regs[R_ESP]; 1854 ssp = env->segs[R_SS].base; 1855 if (shift == 1) { 1856 /* 32 bits */ 1857 POPL_RA(ssp, sp, sp_mask, new_eip, GETPC()); 1858 POPL_RA(ssp, sp, sp_mask, new_cs, GETPC()); 1859 new_cs &= 0xffff; 1860 POPL_RA(ssp, sp, sp_mask, new_eflags, GETPC()); 1861 } else { 1862 /* 16 bits */ 1863 POPW_RA(ssp, sp, sp_mask, new_eip, GETPC()); 1864 POPW_RA(ssp, sp, sp_mask, new_cs, GETPC()); 1865 POPW_RA(ssp, sp, sp_mask, new_eflags, GETPC()); 1866 } 1867 env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask); 1868 env->segs[R_CS].selector = new_cs; 1869 env->segs[R_CS].base = (new_cs << 4); 1870 env->eip = new_eip; 1871 if (env->eflags & VM_MASK) { 1872 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | 1873 NT_MASK; 1874 } else { 1875 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | 1876 RF_MASK | NT_MASK; 1877 } 1878 if (shift == 0) { 1879 eflags_mask &= 0xffff; 1880 } 1881 cpu_load_eflags(env, new_eflags, eflags_mask); 1882 env->hflags2 &= ~HF2_NMI_MASK; 1883 } 1884 1885 static inline void validate_seg(CPUX86State *env, X86Seg seg_reg, int cpl) 1886 { 1887 int dpl; 1888 uint32_t e2; 1889 1890 /* XXX: on x86_64, we do not want to nullify FS and GS because 1891 they may still contain a valid base. I would be interested to 1892 know how a real x86_64 CPU behaves */ 1893 if ((seg_reg == R_FS || seg_reg == R_GS) && 1894 (env->segs[seg_reg].selector & 0xfffc) == 0) { 1895 return; 1896 } 1897 1898 e2 = env->segs[seg_reg].flags; 1899 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 1900 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) { 1901 /* data or non conforming code segment */ 1902 if (dpl < cpl) { 1903 cpu_x86_load_seg_cache(env, seg_reg, 0, 1904 env->segs[seg_reg].base, 1905 env->segs[seg_reg].limit, 1906 env->segs[seg_reg].flags & ~DESC_P_MASK); 1907 } 1908 } 1909 } 1910 1911 /* protected mode iret */ 1912 static inline void helper_ret_protected(CPUX86State *env, int shift, 1913 int is_iret, int addend, 1914 uintptr_t retaddr) 1915 { 1916 uint32_t new_cs, new_eflags, new_ss; 1917 uint32_t new_es, new_ds, new_fs, new_gs; 1918 uint32_t e1, e2, ss_e1, ss_e2; 1919 int cpl, dpl, rpl, eflags_mask, iopl; 1920 target_ulong ssp, sp, new_eip, new_esp, sp_mask; 1921 1922 #ifdef TARGET_X86_64 1923 if (shift == 2) { 1924 sp_mask = -1; 1925 } else 1926 #endif 1927 { 1928 sp_mask = get_sp_mask(env->segs[R_SS].flags); 1929 } 1930 sp = env->regs[R_ESP]; 1931 ssp = env->segs[R_SS].base; 1932 new_eflags = 0; /* avoid warning */ 1933 #ifdef TARGET_X86_64 1934 if (shift == 2) { 1935 POPQ_RA(sp, new_eip, retaddr); 1936 POPQ_RA(sp, new_cs, retaddr); 1937 new_cs &= 0xffff; 1938 if (is_iret) { 1939 POPQ_RA(sp, new_eflags, retaddr); 1940 } 1941 } else 1942 #endif 1943 { 1944 if (shift == 1) { 1945 /* 32 bits */ 1946 POPL_RA(ssp, sp, sp_mask, new_eip, retaddr); 1947 POPL_RA(ssp, sp, sp_mask, new_cs, retaddr); 1948 new_cs &= 0xffff; 1949 if (is_iret) { 1950 POPL_RA(ssp, sp, sp_mask, new_eflags, retaddr); 1951 if (new_eflags & VM_MASK) { 1952 goto return_to_vm86; 1953 } 1954 } 1955 } else { 1956 /* 16 bits */ 1957 POPW_RA(ssp, sp, sp_mask, new_eip, retaddr); 1958 POPW_RA(ssp, sp, sp_mask, new_cs, retaddr); 1959 if (is_iret) { 1960 POPW_RA(ssp, sp, sp_mask, new_eflags, retaddr); 1961 } 1962 } 1963 } 1964 LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n", 1965 new_cs, new_eip, shift, addend); 1966 LOG_PCALL_STATE(env_cpu(env)); 1967 if ((new_cs & 0xfffc) == 0) { 1968 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr); 1969 } 1970 if (load_segment_ra(env, &e1, &e2, new_cs, retaddr) != 0) { 1971 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr); 1972 } 1973 if (!(e2 & DESC_S_MASK) || 1974 !(e2 & DESC_CS_MASK)) { 1975 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr); 1976 } 1977 cpl = env->hflags & HF_CPL_MASK; 1978 rpl = new_cs & 3; 1979 if (rpl < cpl) { 1980 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr); 1981 } 1982 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 1983 if (e2 & DESC_C_MASK) { 1984 if (dpl > rpl) { 1985 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr); 1986 } 1987 } else { 1988 if (dpl != rpl) { 1989 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr); 1990 } 1991 } 1992 if (!(e2 & DESC_P_MASK)) { 1993 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, retaddr); 1994 } 1995 1996 sp += addend; 1997 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) || 1998 ((env->hflags & HF_CS64_MASK) && !is_iret))) { 1999 /* return to same privilege level */ 2000 cpu_x86_load_seg_cache(env, R_CS, new_cs, 2001 get_seg_base(e1, e2), 2002 get_seg_limit(e1, e2), 2003 e2); 2004 } else { 2005 /* return to different privilege level */ 2006 #ifdef TARGET_X86_64 2007 if (shift == 2) { 2008 POPQ_RA(sp, new_esp, retaddr); 2009 POPQ_RA(sp, new_ss, retaddr); 2010 new_ss &= 0xffff; 2011 } else 2012 #endif 2013 { 2014 if (shift == 1) { 2015 /* 32 bits */ 2016 POPL_RA(ssp, sp, sp_mask, new_esp, retaddr); 2017 POPL_RA(ssp, sp, sp_mask, new_ss, retaddr); 2018 new_ss &= 0xffff; 2019 } else { 2020 /* 16 bits */ 2021 POPW_RA(ssp, sp, sp_mask, new_esp, retaddr); 2022 POPW_RA(ssp, sp, sp_mask, new_ss, retaddr); 2023 } 2024 } 2025 LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n", 2026 new_ss, new_esp); 2027 if ((new_ss & 0xfffc) == 0) { 2028 #ifdef TARGET_X86_64 2029 /* NULL ss is allowed in long mode if cpl != 3 */ 2030 /* XXX: test CS64? */ 2031 if ((env->hflags & HF_LMA_MASK) && rpl != 3) { 2032 cpu_x86_load_seg_cache(env, R_SS, new_ss, 2033 0, 0xffffffff, 2034 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 2035 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) | 2036 DESC_W_MASK | DESC_A_MASK); 2037 ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */ 2038 } else 2039 #endif 2040 { 2041 raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr); 2042 } 2043 } else { 2044 if ((new_ss & 3) != rpl) { 2045 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr); 2046 } 2047 if (load_segment_ra(env, &ss_e1, &ss_e2, new_ss, retaddr) != 0) { 2048 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr); 2049 } 2050 if (!(ss_e2 & DESC_S_MASK) || 2051 (ss_e2 & DESC_CS_MASK) || 2052 !(ss_e2 & DESC_W_MASK)) { 2053 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr); 2054 } 2055 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3; 2056 if (dpl != rpl) { 2057 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr); 2058 } 2059 if (!(ss_e2 & DESC_P_MASK)) { 2060 raise_exception_err_ra(env, EXCP0B_NOSEG, new_ss & 0xfffc, retaddr); 2061 } 2062 cpu_x86_load_seg_cache(env, R_SS, new_ss, 2063 get_seg_base(ss_e1, ss_e2), 2064 get_seg_limit(ss_e1, ss_e2), 2065 ss_e2); 2066 } 2067 2068 cpu_x86_load_seg_cache(env, R_CS, new_cs, 2069 get_seg_base(e1, e2), 2070 get_seg_limit(e1, e2), 2071 e2); 2072 sp = new_esp; 2073 #ifdef TARGET_X86_64 2074 if (env->hflags & HF_CS64_MASK) { 2075 sp_mask = -1; 2076 } else 2077 #endif 2078 { 2079 sp_mask = get_sp_mask(ss_e2); 2080 } 2081 2082 /* validate data segments */ 2083 validate_seg(env, R_ES, rpl); 2084 validate_seg(env, R_DS, rpl); 2085 validate_seg(env, R_FS, rpl); 2086 validate_seg(env, R_GS, rpl); 2087 2088 sp += addend; 2089 } 2090 SET_ESP(sp, sp_mask); 2091 env->eip = new_eip; 2092 if (is_iret) { 2093 /* NOTE: 'cpl' is the _old_ CPL */ 2094 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK; 2095 if (cpl == 0) { 2096 eflags_mask |= IOPL_MASK; 2097 } 2098 iopl = (env->eflags >> IOPL_SHIFT) & 3; 2099 if (cpl <= iopl) { 2100 eflags_mask |= IF_MASK; 2101 } 2102 if (shift == 0) { 2103 eflags_mask &= 0xffff; 2104 } 2105 cpu_load_eflags(env, new_eflags, eflags_mask); 2106 } 2107 return; 2108 2109 return_to_vm86: 2110 POPL_RA(ssp, sp, sp_mask, new_esp, retaddr); 2111 POPL_RA(ssp, sp, sp_mask, new_ss, retaddr); 2112 POPL_RA(ssp, sp, sp_mask, new_es, retaddr); 2113 POPL_RA(ssp, sp, sp_mask, new_ds, retaddr); 2114 POPL_RA(ssp, sp, sp_mask, new_fs, retaddr); 2115 POPL_RA(ssp, sp, sp_mask, new_gs, retaddr); 2116 2117 /* modify processor state */ 2118 cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK | 2119 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | 2120 VIP_MASK); 2121 load_seg_vm(env, R_CS, new_cs & 0xffff); 2122 load_seg_vm(env, R_SS, new_ss & 0xffff); 2123 load_seg_vm(env, R_ES, new_es & 0xffff); 2124 load_seg_vm(env, R_DS, new_ds & 0xffff); 2125 load_seg_vm(env, R_FS, new_fs & 0xffff); 2126 load_seg_vm(env, R_GS, new_gs & 0xffff); 2127 2128 env->eip = new_eip & 0xffff; 2129 env->regs[R_ESP] = new_esp; 2130 } 2131 2132 void helper_iret_protected(CPUX86State *env, int shift, int next_eip) 2133 { 2134 int tss_selector, type; 2135 uint32_t e1, e2; 2136 2137 /* specific case for TSS */ 2138 if (env->eflags & NT_MASK) { 2139 #ifdef TARGET_X86_64 2140 if (env->hflags & HF_LMA_MASK) { 2141 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 2142 } 2143 #endif 2144 tss_selector = cpu_lduw_kernel_ra(env, env->tr.base + 0, GETPC()); 2145 if (tss_selector & 4) { 2146 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC()); 2147 } 2148 if (load_segment_ra(env, &e1, &e2, tss_selector, GETPC()) != 0) { 2149 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC()); 2150 } 2151 type = (e2 >> DESC_TYPE_SHIFT) & 0x17; 2152 /* NOTE: we check both segment and busy TSS */ 2153 if (type != 3) { 2154 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC()); 2155 } 2156 switch_tss_ra(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip, GETPC()); 2157 } else { 2158 helper_ret_protected(env, shift, 1, 0, GETPC()); 2159 } 2160 env->hflags2 &= ~HF2_NMI_MASK; 2161 } 2162 2163 void helper_lret_protected(CPUX86State *env, int shift, int addend) 2164 { 2165 helper_ret_protected(env, shift, 0, addend, GETPC()); 2166 } 2167 2168 void helper_sysenter(CPUX86State *env) 2169 { 2170 if (env->sysenter_cs == 0) { 2171 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 2172 } 2173 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK); 2174 2175 #ifdef TARGET_X86_64 2176 if (env->hflags & HF_LMA_MASK) { 2177 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc, 2178 0, 0xffffffff, 2179 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 2180 DESC_S_MASK | 2181 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | 2182 DESC_L_MASK); 2183 } else 2184 #endif 2185 { 2186 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc, 2187 0, 0xffffffff, 2188 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 2189 DESC_S_MASK | 2190 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); 2191 } 2192 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc, 2193 0, 0xffffffff, 2194 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 2195 DESC_S_MASK | 2196 DESC_W_MASK | DESC_A_MASK); 2197 env->regs[R_ESP] = env->sysenter_esp; 2198 env->eip = env->sysenter_eip; 2199 } 2200 2201 void helper_sysexit(CPUX86State *env, int dflag) 2202 { 2203 int cpl; 2204 2205 cpl = env->hflags & HF_CPL_MASK; 2206 if (env->sysenter_cs == 0 || cpl != 0) { 2207 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); 2208 } 2209 #ifdef TARGET_X86_64 2210 if (dflag == 2) { 2211 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) | 2212 3, 0, 0xffffffff, 2213 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 2214 DESC_S_MASK | (3 << DESC_DPL_SHIFT) | 2215 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | 2216 DESC_L_MASK); 2217 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) | 2218 3, 0, 0xffffffff, 2219 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 2220 DESC_S_MASK | (3 << DESC_DPL_SHIFT) | 2221 DESC_W_MASK | DESC_A_MASK); 2222 } else 2223 #endif 2224 { 2225 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 2226 3, 0, 0xffffffff, 2227 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 2228 DESC_S_MASK | (3 << DESC_DPL_SHIFT) | 2229 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); 2230 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 2231 3, 0, 0xffffffff, 2232 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | 2233 DESC_S_MASK | (3 << DESC_DPL_SHIFT) | 2234 DESC_W_MASK | DESC_A_MASK); 2235 } 2236 env->regs[R_ESP] = env->regs[R_ECX]; 2237 env->eip = env->regs[R_EDX]; 2238 } 2239 2240 target_ulong helper_lsl(CPUX86State *env, target_ulong selector1) 2241 { 2242 unsigned int limit; 2243 uint32_t e1, e2, eflags, selector; 2244 int rpl, dpl, cpl, type; 2245 2246 selector = selector1 & 0xffff; 2247 eflags = cpu_cc_compute_all(env, CC_OP); 2248 if ((selector & 0xfffc) == 0) { 2249 goto fail; 2250 } 2251 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) { 2252 goto fail; 2253 } 2254 rpl = selector & 3; 2255 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 2256 cpl = env->hflags & HF_CPL_MASK; 2257 if (e2 & DESC_S_MASK) { 2258 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) { 2259 /* conforming */ 2260 } else { 2261 if (dpl < cpl || dpl < rpl) { 2262 goto fail; 2263 } 2264 } 2265 } else { 2266 type = (e2 >> DESC_TYPE_SHIFT) & 0xf; 2267 switch (type) { 2268 case 1: 2269 case 2: 2270 case 3: 2271 case 9: 2272 case 11: 2273 break; 2274 default: 2275 goto fail; 2276 } 2277 if (dpl < cpl || dpl < rpl) { 2278 fail: 2279 CC_SRC = eflags & ~CC_Z; 2280 return 0; 2281 } 2282 } 2283 limit = get_seg_limit(e1, e2); 2284 CC_SRC = eflags | CC_Z; 2285 return limit; 2286 } 2287 2288 target_ulong helper_lar(CPUX86State *env, target_ulong selector1) 2289 { 2290 uint32_t e1, e2, eflags, selector; 2291 int rpl, dpl, cpl, type; 2292 2293 selector = selector1 & 0xffff; 2294 eflags = cpu_cc_compute_all(env, CC_OP); 2295 if ((selector & 0xfffc) == 0) { 2296 goto fail; 2297 } 2298 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) { 2299 goto fail; 2300 } 2301 rpl = selector & 3; 2302 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 2303 cpl = env->hflags & HF_CPL_MASK; 2304 if (e2 & DESC_S_MASK) { 2305 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) { 2306 /* conforming */ 2307 } else { 2308 if (dpl < cpl || dpl < rpl) { 2309 goto fail; 2310 } 2311 } 2312 } else { 2313 type = (e2 >> DESC_TYPE_SHIFT) & 0xf; 2314 switch (type) { 2315 case 1: 2316 case 2: 2317 case 3: 2318 case 4: 2319 case 5: 2320 case 9: 2321 case 11: 2322 case 12: 2323 break; 2324 default: 2325 goto fail; 2326 } 2327 if (dpl < cpl || dpl < rpl) { 2328 fail: 2329 CC_SRC = eflags & ~CC_Z; 2330 return 0; 2331 } 2332 } 2333 CC_SRC = eflags | CC_Z; 2334 return e2 & 0x00f0ff00; 2335 } 2336 2337 void helper_verr(CPUX86State *env, target_ulong selector1) 2338 { 2339 uint32_t e1, e2, eflags, selector; 2340 int rpl, dpl, cpl; 2341 2342 selector = selector1 & 0xffff; 2343 eflags = cpu_cc_compute_all(env, CC_OP); 2344 if ((selector & 0xfffc) == 0) { 2345 goto fail; 2346 } 2347 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) { 2348 goto fail; 2349 } 2350 if (!(e2 & DESC_S_MASK)) { 2351 goto fail; 2352 } 2353 rpl = selector & 3; 2354 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 2355 cpl = env->hflags & HF_CPL_MASK; 2356 if (e2 & DESC_CS_MASK) { 2357 if (!(e2 & DESC_R_MASK)) { 2358 goto fail; 2359 } 2360 if (!(e2 & DESC_C_MASK)) { 2361 if (dpl < cpl || dpl < rpl) { 2362 goto fail; 2363 } 2364 } 2365 } else { 2366 if (dpl < cpl || dpl < rpl) { 2367 fail: 2368 CC_SRC = eflags & ~CC_Z; 2369 return; 2370 } 2371 } 2372 CC_SRC = eflags | CC_Z; 2373 } 2374 2375 void helper_verw(CPUX86State *env, target_ulong selector1) 2376 { 2377 uint32_t e1, e2, eflags, selector; 2378 int rpl, dpl, cpl; 2379 2380 selector = selector1 & 0xffff; 2381 eflags = cpu_cc_compute_all(env, CC_OP); 2382 if ((selector & 0xfffc) == 0) { 2383 goto fail; 2384 } 2385 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) { 2386 goto fail; 2387 } 2388 if (!(e2 & DESC_S_MASK)) { 2389 goto fail; 2390 } 2391 rpl = selector & 3; 2392 dpl = (e2 >> DESC_DPL_SHIFT) & 3; 2393 cpl = env->hflags & HF_CPL_MASK; 2394 if (e2 & DESC_CS_MASK) { 2395 goto fail; 2396 } else { 2397 if (dpl < cpl || dpl < rpl) { 2398 goto fail; 2399 } 2400 if (!(e2 & DESC_W_MASK)) { 2401 fail: 2402 CC_SRC = eflags & ~CC_Z; 2403 return; 2404 } 2405 } 2406 CC_SRC = eflags | CC_Z; 2407 } 2408