1 /* 2 * Decode table flags, mostly based on Intel SDM. 3 * 4 * Copyright (c) 2022 Red Hat, Inc. 5 * 6 * Author: Paolo Bonzini <pbonzini@redhat.com> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 typedef enum X86OpType { 23 X86_TYPE_None, 24 25 X86_TYPE_A, /* Implicit */ 26 X86_TYPE_B, /* VEX.vvvv selects a GPR */ 27 X86_TYPE_C, /* REG in the modrm byte selects a control register */ 28 X86_TYPE_D, /* REG in the modrm byte selects a debug register */ 29 X86_TYPE_E, /* ALU modrm operand */ 30 X86_TYPE_F, /* EFLAGS/RFLAGS */ 31 X86_TYPE_G, /* REG in the modrm byte selects a GPR */ 32 X86_TYPE_H, /* For AVX, VEX.vvvv selects an XMM/YMM register */ 33 X86_TYPE_I, /* Immediate */ 34 X86_TYPE_J, /* Relative offset for a jump */ 35 X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */ 36 X86_TYPE_M, /* modrm byte selects a memory operand */ 37 X86_TYPE_N, /* R/M in the modrm byte selects an MMX register */ 38 X86_TYPE_O, /* Absolute address encoded in the instruction */ 39 X86_TYPE_P, /* reg in the modrm byte selects an MMX register */ 40 X86_TYPE_Q, /* MMX modrm operand */ 41 X86_TYPE_R, /* R/M in the modrm byte selects a register */ 42 X86_TYPE_S, /* reg selects a segment register */ 43 X86_TYPE_U, /* R/M in the modrm byte selects an XMM/YMM register */ 44 X86_TYPE_V, /* reg in the modrm byte selects an XMM/YMM register */ 45 X86_TYPE_W, /* XMM/YMM modrm operand */ 46 X86_TYPE_X, /* string source */ 47 X86_TYPE_Y, /* string destination */ 48 49 /* Custom */ 50 X86_TYPE_EM, /* modrm byte selects an ALU memory operand */ 51 X86_TYPE_WM, /* modrm byte selects an XMM/YMM memory operand */ 52 X86_TYPE_I_unsigned, /* Immediate, zero-extended */ 53 X86_TYPE_2op, /* 2-operand RMW instruction */ 54 X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */ 55 X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */ 56 X86_TYPE_1, 57 X86_TYPE_2, 58 X86_TYPE_3, 59 X86_TYPE_4, 60 X86_TYPE_5, 61 X86_TYPE_6, 62 X86_TYPE_7, 63 X86_TYPE_ES, /* Hard-coded segment registers */ 64 X86_TYPE_CS, 65 X86_TYPE_SS, 66 X86_TYPE_DS, 67 X86_TYPE_FS, 68 X86_TYPE_GS, 69 } X86OpType; 70 71 typedef enum X86OpSize { 72 X86_SIZE_None, 73 74 X86_SIZE_a, /* BOUND operand */ 75 X86_SIZE_b, /* byte */ 76 X86_SIZE_d, /* 32-bit */ 77 X86_SIZE_dq, /* SSE/AVX 128-bit */ 78 X86_SIZE_p, /* Far pointer */ 79 X86_SIZE_pd, /* SSE/AVX packed double precision */ 80 X86_SIZE_pi, /* MMX */ 81 X86_SIZE_ps, /* SSE/AVX packed single precision */ 82 X86_SIZE_q, /* 64-bit */ 83 X86_SIZE_qq, /* AVX 256-bit */ 84 X86_SIZE_s, /* Descriptor */ 85 X86_SIZE_sd, /* SSE/AVX scalar double precision */ 86 X86_SIZE_ss, /* SSE/AVX scalar single precision */ 87 X86_SIZE_si, /* 32-bit GPR */ 88 X86_SIZE_v, /* 16/32/64-bit, based on operand size */ 89 X86_SIZE_w, /* 16-bit */ 90 X86_SIZE_x, /* 128/256-bit, based on operand size */ 91 X86_SIZE_y, /* 32/64-bit, based on operand size */ 92 X86_SIZE_z, /* 16-bit for 16-bit operand size, else 32-bit */ 93 X86_SIZE_z_f64, /* 32-bit for 32-bit operand size or 64-bit mode, else 16-bit */ 94 95 /* Custom */ 96 X86_SIZE_d64, 97 X86_SIZE_f64, 98 X86_SIZE_xh, /* SSE/AVX packed half register */ 99 } X86OpSize; 100 101 typedef enum X86CPUIDFeature { 102 X86_FEAT_None, 103 X86_FEAT_3DNOW, 104 X86_FEAT_ADX, 105 X86_FEAT_AES, 106 X86_FEAT_AVX, 107 X86_FEAT_AVX2, 108 X86_FEAT_BMI1, 109 X86_FEAT_BMI2, 110 X86_FEAT_CMPCCXADD, 111 X86_FEAT_F16C, 112 X86_FEAT_FMA, 113 X86_FEAT_MOVBE, 114 X86_FEAT_PCLMULQDQ, 115 X86_FEAT_SHA_NI, 116 X86_FEAT_SSE, 117 X86_FEAT_SSE2, 118 X86_FEAT_SSE3, 119 X86_FEAT_SSSE3, 120 X86_FEAT_SSE41, 121 X86_FEAT_SSE42, 122 X86_FEAT_SSE4A, 123 } X86CPUIDFeature; 124 125 /* Execution flags */ 126 127 typedef enum X86OpUnit { 128 X86_OP_SKIP, /* not valid or managed by emission function */ 129 X86_OP_SEG, /* segment selector */ 130 X86_OP_CR, /* control register */ 131 X86_OP_DR, /* debug register */ 132 X86_OP_INT, /* loaded into/stored from s->T0/T1 */ 133 X86_OP_IMM, /* immediate */ 134 X86_OP_SSE, /* address in either s->ptrX or s->A0 depending on has_ea */ 135 X86_OP_MMX, /* address in either s->ptrX or s->A0 depending on has_ea */ 136 } X86OpUnit; 137 138 typedef enum X86InsnCheck { 139 /* Illegal or exclusive to 64-bit mode */ 140 X86_CHECK_i64 = 1, 141 X86_CHECK_o64 = 2, 142 143 /* Fault outside protected mode */ 144 X86_CHECK_prot = 4, 145 146 /* Privileged instruction checks */ 147 X86_CHECK_cpl0 = 8, 148 X86_CHECK_vm86_iopl = 16, 149 X86_CHECK_cpl_iopl = 32, 150 X86_CHECK_iopl = X86_CHECK_cpl_iopl | X86_CHECK_vm86_iopl, 151 152 /* Fault if VEX.L=1 */ 153 X86_CHECK_VEX128 = 64, 154 155 /* Fault if VEX.W=1 */ 156 X86_CHECK_W0 = 128, 157 158 /* Fault if VEX.W=0 */ 159 X86_CHECK_W1 = 256, 160 } X86InsnCheck; 161 162 typedef enum X86InsnSpecial { 163 X86_SPECIAL_None, 164 165 /* Accepts LOCK prefix; LOCKed operations do not load or writeback operand 0 */ 166 X86_SPECIAL_HasLock, 167 168 /* Always locked if it has a memory operand (XCHG) */ 169 X86_SPECIAL_Locked, 170 171 /* Do not apply segment base to effective address */ 172 X86_SPECIAL_NoSeg, 173 /* 174 * Rd/Mb or Rd/Mw in the manual: register operand 0 is treated as 32 bits 175 * (and writeback zero-extends it to 64 bits if applicable). PREFIX_DATA 176 * does not trigger 16-bit writeback and, as a side effect, high-byte 177 * registers are never used. 178 */ 179 X86_SPECIAL_Op0_Rd, 180 181 /* 182 * Ry/Mb in the manual (PINSRB). However, the high bits are never used by 183 * the instruction in either the register or memory cases; the *real* effect 184 * of this modifier is that high-byte registers are never used, even without 185 * a REX prefix. Therefore, PINSRW does not need it despite having Ry/Mw. 186 */ 187 X86_SPECIAL_Op2_Ry, 188 189 /* 190 * Register operand 2 is extended to full width, while a memory operand 191 * is doubled in size if VEX.L=1. 192 */ 193 X86_SPECIAL_AVXExtMov, 194 195 /* 196 * MMX instruction exists with no prefix; if there is no prefix, V/H/W/U operands 197 * become P/P/Q/N, and size "x" becomes "q". 198 */ 199 X86_SPECIAL_MMX, 200 201 /* When loaded into s->T0, register operand 1 is zero/sign extended. */ 202 X86_SPECIAL_SExtT0, 203 X86_SPECIAL_ZExtT0, 204 } X86InsnSpecial; 205 206 /* 207 * Special cases for instructions that operate on XMM/YMM registers. Intel 208 * retconned all of them to have VEX exception classes other than 0 and 13, so 209 * all these only matter for instructions that have a VEX exception class. 210 * Based on tables in the "AVX and SSE Instruction Exception Specification" 211 * section of the manual. 212 */ 213 typedef enum X86VEXSpecial { 214 /* Legacy SSE instructions that allow unaligned operands */ 215 X86_VEX_SSEUnaligned, 216 217 /* 218 * Used for instructions that distinguish the XMM operand type with an 219 * instruction prefix; legacy SSE encodings will allow unaligned operands 220 * for scalar operands only (identified by a REP prefix). In this case, 221 * the decoding table uses "x" for the vector operands instead of specifying 222 * pd/ps/sd/ss individually. 223 */ 224 X86_VEX_REPScalar, 225 226 /* 227 * VEX instructions that only support 256-bit operands with AVX2 (Table 2-17 228 * column 3). Columns 2 and 4 (instructions limited to 256- and 127-bit 229 * operands respectively) are implicit in the presence of dq and qq 230 * operands, and thus handled by decode_op_size. 231 */ 232 X86_VEX_AVX2_256, 233 } X86VEXSpecial; 234 235 236 typedef struct X86OpEntry X86OpEntry; 237 typedef struct X86DecodedInsn X86DecodedInsn; 238 239 /* Decode function for multibyte opcodes. */ 240 typedef void (*X86DecodeFunc)(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b); 241 242 /* Code generation function. */ 243 typedef void (*X86GenFunc)(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode); 244 245 struct X86OpEntry { 246 /* Based on the is_decode flags. */ 247 union { 248 X86GenFunc gen; 249 X86DecodeFunc decode; 250 }; 251 /* op0 is always written, op1 and op2 are always read. */ 252 X86OpType op0:8; 253 X86OpSize s0:8; 254 X86OpType op1:8; 255 X86OpSize s1:8; 256 X86OpType op2:8; 257 X86OpSize s2:8; 258 /* Must be I and b respectively if present. */ 259 X86OpType op3:8; 260 X86OpSize s3:8; 261 262 X86InsnSpecial special:8; 263 X86CPUIDFeature cpuid:8; 264 unsigned vex_class:8; 265 X86VEXSpecial vex_special:8; 266 unsigned valid_prefix:16; 267 unsigned check:16; 268 unsigned intercept:8; 269 bool is_decode:1; 270 }; 271 272 typedef struct X86DecodedOp { 273 int8_t n; 274 MemOp ot; /* For b/c/d/p/s/q/v/w/y/z */ 275 X86OpUnit unit; 276 bool has_ea; 277 int offset; /* For MMX and SSE */ 278 279 union { 280 target_ulong imm; 281 /* 282 * This field is used internally by macros OP0_PTR/OP1_PTR/OP2_PTR, 283 * do not access directly! 284 */ 285 TCGv_ptr v_ptr; 286 }; 287 } X86DecodedOp; 288 289 struct X86DecodedInsn { 290 X86OpEntry e; 291 X86DecodedOp op[3]; 292 /* 293 * Rightmost immediate, for convenience since most instructions have 294 * one (and also for 4-operand instructions). 295 */ 296 target_ulong immediate; 297 AddressParts mem; 298 299 TCGv cc_dst, cc_src, cc_src2; 300 TCGv_i32 cc_op_dynamic; 301 int8_t cc_op; 302 303 uint8_t b; 304 }; 305 306