1 /* 2 * Decode table flags, mostly based on Intel SDM. 3 * 4 * Copyright (c) 2022 Red Hat, Inc. 5 * 6 * Author: Paolo Bonzini <pbonzini@redhat.com> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 typedef enum X86OpType { 23 X86_TYPE_None, 24 25 X86_TYPE_A, /* Implicit */ 26 X86_TYPE_B, /* VEX.vvvv selects a GPR */ 27 X86_TYPE_C, /* REG in the modrm byte selects a control register */ 28 X86_TYPE_D, /* REG in the modrm byte selects a debug register */ 29 X86_TYPE_E, /* ALU modrm operand */ 30 X86_TYPE_F, /* EFLAGS/RFLAGS */ 31 X86_TYPE_G, /* REG in the modrm byte selects a GPR */ 32 X86_TYPE_H, /* For AVX, VEX.vvvv selects an XMM/YMM register */ 33 X86_TYPE_I, /* Immediate */ 34 X86_TYPE_J, /* Relative offset for a jump */ 35 X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */ 36 X86_TYPE_M, /* modrm byte selects a memory operand */ 37 X86_TYPE_N, /* R/M in the modrm byte selects an MMX register */ 38 X86_TYPE_O, /* Absolute address encoded in the instruction */ 39 X86_TYPE_P, /* reg in the modrm byte selects an MMX register */ 40 X86_TYPE_Q, /* MMX modrm operand */ 41 X86_TYPE_R, /* R/M in the modrm byte selects a register */ 42 X86_TYPE_S, /* reg selects a segment register */ 43 X86_TYPE_U, /* R/M in the modrm byte selects an XMM/YMM register */ 44 X86_TYPE_V, /* reg in the modrm byte selects an XMM/YMM register */ 45 X86_TYPE_W, /* XMM/YMM modrm operand */ 46 X86_TYPE_X, /* string source */ 47 X86_TYPE_Y, /* string destination */ 48 49 /* Custom */ 50 X86_TYPE_2op, /* 2-operand RMW instruction */ 51 X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */ 52 X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */ 53 X86_TYPE_1, 54 X86_TYPE_2, 55 X86_TYPE_3, 56 X86_TYPE_4, 57 X86_TYPE_5, 58 X86_TYPE_6, 59 X86_TYPE_7, 60 X86_TYPE_ES, /* Hard-coded segment registers */ 61 X86_TYPE_CS, 62 X86_TYPE_SS, 63 X86_TYPE_DS, 64 X86_TYPE_FS, 65 X86_TYPE_GS, 66 } X86OpType; 67 68 typedef enum X86OpSize { 69 X86_SIZE_None, 70 71 X86_SIZE_a, /* BOUND operand */ 72 X86_SIZE_b, /* byte */ 73 X86_SIZE_d, /* 32-bit */ 74 X86_SIZE_dq, /* SSE/AVX 128-bit */ 75 X86_SIZE_p, /* Far pointer */ 76 X86_SIZE_pd, /* SSE/AVX packed double precision */ 77 X86_SIZE_pi, /* MMX */ 78 X86_SIZE_ps, /* SSE/AVX packed single precision */ 79 X86_SIZE_q, /* 64-bit */ 80 X86_SIZE_qq, /* AVX 256-bit */ 81 X86_SIZE_s, /* Descriptor */ 82 X86_SIZE_sd, /* SSE/AVX scalar double precision */ 83 X86_SIZE_ss, /* SSE/AVX scalar single precision */ 84 X86_SIZE_si, /* 32-bit GPR */ 85 X86_SIZE_v, /* 16/32/64-bit, based on operand size */ 86 X86_SIZE_w, /* 16-bit */ 87 X86_SIZE_x, /* 128/256-bit, based on operand size */ 88 X86_SIZE_y, /* 32/64-bit, based on operand size */ 89 X86_SIZE_z, /* 16-bit for 16-bit operand size, else 32-bit */ 90 91 /* Custom */ 92 X86_SIZE_d64, 93 X86_SIZE_f64, 94 } X86OpSize; 95 96 /* Execution flags */ 97 98 typedef enum X86OpUnit { 99 X86_OP_SKIP, /* not valid or managed by emission function */ 100 X86_OP_SEG, /* segment selector */ 101 X86_OP_CR, /* control register */ 102 X86_OP_DR, /* debug register */ 103 X86_OP_INT, /* loaded into/stored from s->T0/T1 */ 104 X86_OP_IMM, /* immediate */ 105 X86_OP_SSE, /* address in either s->ptrX or s->A0 depending on has_ea */ 106 X86_OP_MMX, /* address in either s->ptrX or s->A0 depending on has_ea */ 107 } X86OpUnit; 108 109 typedef enum X86InsnSpecial { 110 X86_SPECIAL_None, 111 112 /* Always locked if it has a memory operand (XCHG) */ 113 X86_SPECIAL_Locked, 114 115 /* Fault outside protected mode */ 116 X86_SPECIAL_ProtMode, 117 118 /* 119 * Register operand 0/2 is zero extended to 32 bits. Rd/Mb or Rd/Mw 120 * in the manual. 121 */ 122 X86_SPECIAL_ZExtOp0, 123 X86_SPECIAL_ZExtOp2, 124 125 /* 126 * MMX instruction exists with no prefix; if there is no prefix, V/H/W/U operands 127 * become P/P/Q/N, and size "x" becomes "q". 128 */ 129 X86_SPECIAL_MMX, 130 131 /* Illegal or exclusive to 64-bit mode */ 132 X86_SPECIAL_i64, 133 X86_SPECIAL_o64, 134 } X86InsnSpecial; 135 136 typedef struct X86OpEntry X86OpEntry; 137 typedef struct X86DecodedInsn X86DecodedInsn; 138 139 /* Decode function for multibyte opcodes. */ 140 typedef void (*X86DecodeFunc)(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b); 141 142 /* Code generation function. */ 143 typedef void (*X86GenFunc)(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode); 144 145 struct X86OpEntry { 146 /* Based on the is_decode flags. */ 147 union { 148 X86GenFunc gen; 149 X86DecodeFunc decode; 150 }; 151 /* op0 is always written, op1 and op2 are always read. */ 152 X86OpType op0:8; 153 X86OpSize s0:8; 154 X86OpType op1:8; 155 X86OpSize s1:8; 156 X86OpType op2:8; 157 X86OpSize s2:8; 158 /* Must be I and b respectively if present. */ 159 X86OpType op3:8; 160 X86OpSize s3:8; 161 162 X86InsnSpecial special:8; 163 bool is_decode:1; 164 }; 165 166 typedef struct X86DecodedOp { 167 int8_t n; 168 MemOp ot; /* For b/c/d/p/s/q/v/w/y/z */ 169 X86OpUnit unit; 170 bool has_ea; 171 } X86DecodedOp; 172 173 struct X86DecodedInsn { 174 X86OpEntry e; 175 X86DecodedOp op[3]; 176 target_ulong immediate; 177 AddressParts mem; 178 179 uint8_t b; 180 }; 181 182