1756e12e7SXiaoyao Li /* SPDX-License-Identifier: GPL-2.0-or-later */ 2756e12e7SXiaoyao Li 3756e12e7SXiaoyao Li #ifndef QEMU_I386_TDX_H 4756e12e7SXiaoyao Li #define QEMU_I386_TDX_H 5756e12e7SXiaoyao Li 61619d0e4SXiaoyao Li #ifndef CONFIG_USER_ONLY 71619d0e4SXiaoyao Li #include CONFIG_DEVICES /* CONFIG_TDX */ 81619d0e4SXiaoyao Li #endif 91619d0e4SXiaoyao Li 10756e12e7SXiaoyao Li #include "confidential-guest.h" 11*98dbfd68SXiaoyao Li #include "cpu.h" 12cb5d65a8SXiaoyao Li #include "hw/i386/tdvf.h" 13756e12e7SXiaoyao Li 14756e12e7SXiaoyao Li #define TYPE_TDX_GUEST "tdx-guest" 15756e12e7SXiaoyao Li #define TDX_GUEST(obj) OBJECT_CHECK(TdxGuest, (obj), TYPE_TDX_GUEST) 16756e12e7SXiaoyao Li 17756e12e7SXiaoyao Li typedef struct TdxGuestClass { 18756e12e7SXiaoyao Li X86ConfidentialGuestClass parent_class; 19756e12e7SXiaoyao Li } TdxGuestClass; 20756e12e7SXiaoyao Li 21d529a2acSXiaoyao Li /* TDX requires bus frequency 25MHz */ 22d529a2acSXiaoyao Li #define TDX_APIC_BUS_CYCLES_NS 40 23d529a2acSXiaoyao Li 24f18672e4SXiaoyao Li enum TdxRamType { 25f18672e4SXiaoyao Li TDX_RAM_UNACCEPTED, 26f18672e4SXiaoyao Li TDX_RAM_ADDED, 27f18672e4SXiaoyao Li }; 28f18672e4SXiaoyao Li 29f18672e4SXiaoyao Li typedef struct TdxRamEntry { 30f18672e4SXiaoyao Li uint64_t address; 31f18672e4SXiaoyao Li uint64_t length; 32f18672e4SXiaoyao Li enum TdxRamType type; 33f18672e4SXiaoyao Li } TdxRamEntry; 34f18672e4SXiaoyao Li 35756e12e7SXiaoyao Li typedef struct TdxGuest { 36756e12e7SXiaoyao Li X86ConfidentialGuest parent_obj; 37756e12e7SXiaoyao Li 38f15898b0SXiaoyao Li QemuMutex lock; 39f15898b0SXiaoyao Li 40f15898b0SXiaoyao Li bool initialized; 41756e12e7SXiaoyao Li uint64_t attributes; /* TD attributes */ 42f15898b0SXiaoyao Li uint64_t xfam; 43d05a0858SIsaku Yamahata char *mrconfigid; /* base64 encoded sha348 digest */ 44d05a0858SIsaku Yamahata char *mrowner; /* base64 encoded sha348 digest */ 45d05a0858SIsaku Yamahata char *mrownerconfig; /* base64 encoded sha348 digest */ 460dd5fe5eSChao Peng 470dd5fe5eSChao Peng MemoryRegion *tdvf_mr; 48cb5d65a8SXiaoyao Li TdxFirmware tdvf; 49f18672e4SXiaoyao Li 50f18672e4SXiaoyao Li uint32_t nr_ram_entries; 51f18672e4SXiaoyao Li TdxRamEntry *ram_entries; 52756e12e7SXiaoyao Li } TdxGuest; 53756e12e7SXiaoyao Li 541619d0e4SXiaoyao Li #ifdef CONFIG_TDX 551619d0e4SXiaoyao Li bool is_tdx_vm(void); 561619d0e4SXiaoyao Li #else 571619d0e4SXiaoyao Li #define is_tdx_vm() 0 581619d0e4SXiaoyao Li #endif /* CONFIG_TDX */ 591619d0e4SXiaoyao Li 60f15898b0SXiaoyao Li int tdx_pre_create_vcpu(CPUState *cpu, Error **errp); 610dd5fe5eSChao Peng void tdx_set_tdvf_region(MemoryRegion *tdvf_mr); 62cb5d65a8SXiaoyao Li int tdx_parse_tdvf(void *flash_ptr, int size); 63*98dbfd68SXiaoyao Li int tdx_handle_report_fatal_error(X86CPU *cpu, struct kvm_run *run); 64f15898b0SXiaoyao Li 65756e12e7SXiaoyao Li #endif /* QEMU_I386_TDX_H */ 66