1 // This software is licensed under the terms of the GNU General Public 2 // License version 2, as published by the Free Software Foundation, and 3 // may be copied, distributed, and modified under those terms. 4 // 5 // This program is distributed in the hope that it will be useful, 6 // but WITHOUT ANY WARRANTY; without even the implied warranty of 7 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 // GNU General Public License for more details. 9 #include "qemu/osdep.h" 10 #include "panic.h" 11 #include "qemu-common.h" 12 #include "qemu/error-report.h" 13 14 #include "sysemu/hvf.h" 15 #include "hvf-i386.h" 16 #include "vmcs.h" 17 #include "vmx.h" 18 #include "x86.h" 19 #include "x86_descr.h" 20 #include "x86_mmu.h" 21 #include "x86_decode.h" 22 #include "x86_emu.h" 23 #include "x86_task.h" 24 #include "x86hvf.h" 25 26 #include <Hypervisor/hv.h> 27 #include <Hypervisor/hv_vmx.h> 28 29 #include "exec/exec-all.h" 30 #include "exec/ioport.h" 31 #include "hw/i386/apic_internal.h" 32 #include "hw/boards.h" 33 #include "qemu/main-loop.h" 34 #include "sysemu/accel.h" 35 #include "sysemu/sysemu.h" 36 #include "target/i386/cpu.h" 37 38 // TODO: taskswitch handling 39 static void save_state_to_tss32(CPUState *cpu, struct x86_tss_segment32 *tss) 40 { 41 X86CPU *x86_cpu = X86_CPU(cpu); 42 CPUX86State *env = &x86_cpu->env; 43 44 /* CR3 and ldt selector are not saved intentionally */ 45 tss->eip = EIP(env); 46 tss->eflags = EFLAGS(env); 47 tss->eax = EAX(env); 48 tss->ecx = ECX(env); 49 tss->edx = EDX(env); 50 tss->ebx = EBX(env); 51 tss->esp = ESP(env); 52 tss->ebp = EBP(env); 53 tss->esi = ESI(env); 54 tss->edi = EDI(env); 55 56 tss->es = vmx_read_segment_selector(cpu, R_ES).sel; 57 tss->cs = vmx_read_segment_selector(cpu, R_CS).sel; 58 tss->ss = vmx_read_segment_selector(cpu, R_SS).sel; 59 tss->ds = vmx_read_segment_selector(cpu, R_DS).sel; 60 tss->fs = vmx_read_segment_selector(cpu, R_FS).sel; 61 tss->gs = vmx_read_segment_selector(cpu, R_GS).sel; 62 } 63 64 static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss) 65 { 66 X86CPU *x86_cpu = X86_CPU(cpu); 67 CPUX86State *env = &x86_cpu->env; 68 69 wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, tss->cr3); 70 71 RIP(env) = tss->eip; 72 EFLAGS(env) = tss->eflags | 2; 73 74 /* General purpose registers */ 75 RAX(env) = tss->eax; 76 RCX(env) = tss->ecx; 77 RDX(env) = tss->edx; 78 RBX(env) = tss->ebx; 79 RSP(env) = tss->esp; 80 RBP(env) = tss->ebp; 81 RSI(env) = tss->esi; 82 RDI(env) = tss->edi; 83 84 vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, R_LDTR); 85 vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, R_ES); 86 vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, R_CS); 87 vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, R_SS); 88 vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, R_DS); 89 vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, R_FS); 90 vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, R_GS); 91 } 92 93 static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segment_selector old_tss_sel, 94 uint64_t old_tss_base, struct x86_segment_descriptor *new_desc) 95 { 96 struct x86_tss_segment32 tss_seg; 97 uint32_t new_tss_base = x86_segment_base(new_desc); 98 uint32_t eip_offset = offsetof(struct x86_tss_segment32, eip); 99 uint32_t ldt_sel_offset = offsetof(struct x86_tss_segment32, ldt); 100 101 vmx_read_mem(cpu, &tss_seg, old_tss_base, sizeof(tss_seg)); 102 save_state_to_tss32(cpu, &tss_seg); 103 104 vmx_write_mem(cpu, old_tss_base + eip_offset, &tss_seg.eip, ldt_sel_offset - eip_offset); 105 vmx_read_mem(cpu, &tss_seg, new_tss_base, sizeof(tss_seg)); 106 107 if (old_tss_sel.sel != 0xffff) { 108 tss_seg.prev_tss = old_tss_sel.sel; 109 110 vmx_write_mem(cpu, new_tss_base, &tss_seg.prev_tss, sizeof(tss_seg.prev_tss)); 111 } 112 load_state_from_tss32(cpu, &tss_seg); 113 return 0; 114 } 115 116 void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type) 117 { 118 uint64_t rip = rreg(cpu->hvf_fd, HV_X86_RIP); 119 if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION && 120 gate_type != VMCS_INTR_T_HWINTR && 121 gate_type != VMCS_INTR_T_NMI)) { 122 int ins_len = rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH); 123 macvm_set_rip(cpu, rip + ins_len); 124 return; 125 } 126 127 load_regs(cpu); 128 129 struct x86_segment_descriptor curr_tss_desc, next_tss_desc; 130 int ret; 131 x68_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, R_TR); 132 uint64_t old_tss_base = vmx_read_segment_base(cpu, R_TR); 133 uint32_t desc_limit; 134 struct x86_call_gate task_gate_desc; 135 struct vmx_segment vmx_seg; 136 137 X86CPU *x86_cpu = X86_CPU(cpu); 138 CPUX86State *env = &x86_cpu->env; 139 140 x86_read_segment_descriptor(cpu, &next_tss_desc, tss_sel); 141 x86_read_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel); 142 143 if (reason == TSR_IDT_GATE && gate_valid) { 144 int dpl; 145 146 ret = x86_read_call_gate(cpu, &task_gate_desc, gate); 147 148 dpl = task_gate_desc.dpl; 149 x68_segment_selector cs = vmx_read_segment_selector(cpu, R_CS); 150 if (tss_sel.rpl > dpl || cs.rpl > dpl) 151 ;//DPRINTF("emulate_gp"); 152 } 153 154 desc_limit = x86_segment_limit(&next_tss_desc); 155 if (!next_tss_desc.p || ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || desc_limit < 0x2b)) { 156 VM_PANIC("emulate_ts"); 157 } 158 159 if (reason == TSR_IRET || reason == TSR_JMP) { 160 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 161 x86_write_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel); 162 } 163 164 if (reason == TSR_IRET) 165 EFLAGS(env) &= ~RFLAGS_NT; 166 167 if (reason != TSR_CALL && reason != TSR_IDT_GATE) 168 old_tss_sel.sel = 0xffff; 169 170 if (reason != TSR_IRET) { 171 next_tss_desc.type |= (1 << 1); /* set busy flag */ 172 x86_write_segment_descriptor(cpu, &next_tss_desc, tss_sel); 173 } 174 175 if (next_tss_desc.type & 8) 176 ret = task_switch_32(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc); 177 else 178 //ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc); 179 VM_PANIC("task_switch_16"); 180 181 macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS); 182 x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg); 183 vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR); 184 185 store_regs(cpu); 186 187 hv_vcpu_invalidate_tlb(cpu->hvf_fd); 188 hv_vcpu_flush(cpu->hvf_fd); 189 } 190