1 /* Copyright 2008 IBM Corporation 2 * 2008 Red Hat, Inc. 3 * Copyright 2011 Intel Corporation 4 * Copyright 2016 Veertu, Inc. 5 * Copyright 2017 The Android Open Source Project 6 * 7 * QEMU Hypervisor.framework support 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of version 2 of the GNU General Public 11 * License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, see <http://www.gnu.org/licenses/>. 20 * 21 * This file contain code under public domain from the hvdos project: 22 * https://github.com/mist64/hvdos 23 * 24 * Parts Copyright (c) 2011 NetApp, Inc. 25 * All rights reserved. 26 * 27 * Redistribution and use in source and binary forms, with or without 28 * modification, are permitted provided that the following conditions 29 * are met: 30 * 1. Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * 2. Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in the 34 * documentation and/or other materials provided with the distribution. 35 * 36 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 37 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 39 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 42 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 44 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 45 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 46 * SUCH DAMAGE. 47 */ 48 49 #include "qemu/osdep.h" 50 #include "qemu/error-report.h" 51 #include "qemu/memalign.h" 52 #include "qapi/error.h" 53 #include "migration/blocker.h" 54 55 #include "sysemu/hvf.h" 56 #include "sysemu/hvf_int.h" 57 #include "sysemu/runstate.h" 58 #include "sysemu/cpus.h" 59 #include "hvf-i386.h" 60 #include "vmcs.h" 61 #include "vmx.h" 62 #include "x86.h" 63 #include "x86_descr.h" 64 #include "x86_mmu.h" 65 #include "x86_decode.h" 66 #include "x86_emu.h" 67 #include "x86_task.h" 68 #include "x86hvf.h" 69 70 #include <Hypervisor/hv.h> 71 #include <Hypervisor/hv_vmx.h> 72 #include <sys/sysctl.h> 73 74 #include "hw/i386/apic_internal.h" 75 #include "qemu/main-loop.h" 76 #include "qemu/accel.h" 77 #include "target/i386/cpu.h" 78 79 static Error *invtsc_mig_blocker; 80 81 void vmx_update_tpr(CPUState *cpu) 82 { 83 /* TODO: need integrate APIC handling */ 84 X86CPU *x86_cpu = X86_CPU(cpu); 85 int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4; 86 int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); 87 88 wreg(cpu->accel->fd, HV_X86_TPR, tpr); 89 if (irr == -1) { 90 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); 91 } else { 92 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : 93 irr >> 4); 94 } 95 } 96 97 static void update_apic_tpr(CPUState *cpu) 98 { 99 X86CPU *x86_cpu = X86_CPU(cpu); 100 int tpr = rreg(cpu->accel->fd, HV_X86_TPR) >> 4; 101 cpu_set_apic_tpr(x86_cpu->apic_state, tpr); 102 } 103 104 #define VECTORING_INFO_VECTOR_MASK 0xff 105 106 void hvf_handle_io(CPUArchState *env, uint16_t port, void *buffer, 107 int direction, int size, int count) 108 { 109 int i; 110 uint8_t *ptr = buffer; 111 112 for (i = 0; i < count; i++) { 113 address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED, 114 ptr, size, 115 direction); 116 ptr += size; 117 } 118 } 119 120 static bool ept_emulation_fault(hvf_slot *slot, uint64_t gpa, uint64_t ept_qual) 121 { 122 int read, write; 123 124 /* EPT fault on an instruction fetch doesn't make sense here */ 125 if (ept_qual & EPT_VIOLATION_INST_FETCH) { 126 return false; 127 } 128 129 /* EPT fault must be a read fault or a write fault */ 130 read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0; 131 write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0; 132 if ((read | write) == 0) { 133 return false; 134 } 135 136 if (write && slot) { 137 if (slot->flags & HVF_SLOT_LOG) { 138 uint64_t dirty_page_start = gpa & ~(TARGET_PAGE_SIZE - 1u); 139 memory_region_set_dirty(slot->region, gpa - slot->start, 1); 140 hv_vm_protect(dirty_page_start, TARGET_PAGE_SIZE, 141 HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC); 142 } 143 } 144 145 /* 146 * The EPT violation must have been caused by accessing a 147 * guest-physical address that is a translation of a guest-linear 148 * address. 149 */ 150 if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 || 151 (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) { 152 return false; 153 } 154 155 if (!slot) { 156 return true; 157 } 158 if (!memory_region_is_ram(slot->region) && 159 !(read && memory_region_is_romd(slot->region))) { 160 return true; 161 } 162 return false; 163 } 164 165 void hvf_arch_vcpu_destroy(CPUState *cpu) 166 { 167 X86CPU *x86_cpu = X86_CPU(cpu); 168 CPUX86State *env = &x86_cpu->env; 169 170 g_free(env->hvf_mmio_buf); 171 } 172 173 static void init_tsc_freq(CPUX86State *env) 174 { 175 size_t length; 176 uint64_t tsc_freq; 177 178 if (env->tsc_khz != 0) { 179 return; 180 } 181 182 length = sizeof(uint64_t); 183 if (sysctlbyname("machdep.tsc.frequency", &tsc_freq, &length, NULL, 0)) { 184 return; 185 } 186 env->tsc_khz = tsc_freq / 1000; /* Hz to KHz */ 187 } 188 189 static void init_apic_bus_freq(CPUX86State *env) 190 { 191 size_t length; 192 uint64_t bus_freq; 193 194 if (env->apic_bus_freq != 0) { 195 return; 196 } 197 198 length = sizeof(uint64_t); 199 if (sysctlbyname("hw.busfrequency", &bus_freq, &length, NULL, 0)) { 200 return; 201 } 202 env->apic_bus_freq = bus_freq; 203 } 204 205 static inline bool tsc_is_known(CPUX86State *env) 206 { 207 return env->tsc_khz != 0; 208 } 209 210 static inline bool apic_bus_freq_is_known(CPUX86State *env) 211 { 212 return env->apic_bus_freq != 0; 213 } 214 215 void hvf_kick_vcpu_thread(CPUState *cpu) 216 { 217 cpus_kick_thread(cpu); 218 } 219 220 int hvf_arch_init(void) 221 { 222 return 0; 223 } 224 225 int hvf_arch_init_vcpu(CPUState *cpu) 226 { 227 X86CPU *x86cpu = X86_CPU(cpu); 228 CPUX86State *env = &x86cpu->env; 229 Error *local_err = NULL; 230 int r; 231 uint64_t reqCap; 232 233 init_emu(); 234 init_decoder(); 235 236 hvf_state->hvf_caps = g_new0(struct hvf_vcpu_caps, 1); 237 env->hvf_mmio_buf = g_new(char, 4096); 238 239 if (x86cpu->vmware_cpuid_freq) { 240 init_tsc_freq(env); 241 init_apic_bus_freq(env); 242 243 if (!tsc_is_known(env) || !apic_bus_freq_is_known(env)) { 244 error_report("vmware-cpuid-freq: feature couldn't be enabled"); 245 } 246 } 247 248 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) && 249 invtsc_mig_blocker == NULL) { 250 error_setg(&invtsc_mig_blocker, 251 "State blocked by non-migratable CPU device (invtsc flag)"); 252 r = migrate_add_blocker(&invtsc_mig_blocker, &local_err); 253 if (r < 0) { 254 error_report_err(local_err); 255 return r; 256 } 257 } 258 259 260 if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, 261 &hvf_state->hvf_caps->vmx_cap_pinbased)) { 262 abort(); 263 } 264 if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, 265 &hvf_state->hvf_caps->vmx_cap_procbased)) { 266 abort(); 267 } 268 if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, 269 &hvf_state->hvf_caps->vmx_cap_procbased2)) { 270 abort(); 271 } 272 if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, 273 &hvf_state->hvf_caps->vmx_cap_entry)) { 274 abort(); 275 } 276 277 /* set VMCS control fields */ 278 wvmcs(cpu->accel->fd, VMCS_PIN_BASED_CTLS, 279 cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, 280 VMCS_PIN_BASED_CTLS_EXTINT | 281 VMCS_PIN_BASED_CTLS_NMI | 282 VMCS_PIN_BASED_CTLS_VNMI)); 283 wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, 284 cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased, 285 VMCS_PRI_PROC_BASED_CTLS_HLT | 286 VMCS_PRI_PROC_BASED_CTLS_MWAIT | 287 VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET | 288 VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) | 289 VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL); 290 291 reqCap = VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES; 292 293 /* Is RDTSCP support in CPUID? If so, enable it in the VMCS. */ 294 if (hvf_get_supported_cpuid(0x80000001, 0, R_EDX) & CPUID_EXT2_RDTSCP) { 295 reqCap |= VMCS_PRI_PROC_BASED2_CTLS_RDTSCP; 296 } 297 298 wvmcs(cpu->accel->fd, VMCS_SEC_PROC_BASED_CTLS, 299 cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, reqCap)); 300 301 wvmcs(cpu->accel->fd, VMCS_ENTRY_CTLS, 302 cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry, 0)); 303 wvmcs(cpu->accel->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ 304 305 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); 306 307 x86cpu = X86_CPU(cpu); 308 x86cpu->env.xsave_buf_len = 4096; 309 x86cpu->env.xsave_buf = qemu_memalign(4096, x86cpu->env.xsave_buf_len); 310 311 /* 312 * The allocated storage must be large enough for all of the 313 * possible XSAVE state components. 314 */ 315 assert(hvf_get_supported_cpuid(0xd, 0, R_ECX) <= x86cpu->env.xsave_buf_len); 316 317 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_STAR, 1); 318 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_LSTAR, 1); 319 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_CSTAR, 1); 320 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FMASK, 1); 321 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FSBASE, 1); 322 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_GSBASE, 1); 323 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_KERNELGSBASE, 1); 324 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_TSC_AUX, 1); 325 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_TSC, 1); 326 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_CS, 1); 327 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_EIP, 1); 328 hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_ESP, 1); 329 330 return 0; 331 } 332 333 static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info) 334 { 335 X86CPU *x86_cpu = X86_CPU(cpu); 336 CPUX86State *env = &x86_cpu->env; 337 338 env->exception_nr = -1; 339 env->exception_pending = 0; 340 env->exception_injected = 0; 341 env->interrupt_injected = -1; 342 env->nmi_injected = false; 343 env->ins_len = 0; 344 env->has_error_code = false; 345 if (idtvec_info & VMCS_IDT_VEC_VALID) { 346 switch (idtvec_info & VMCS_IDT_VEC_TYPE) { 347 case VMCS_IDT_VEC_HWINTR: 348 case VMCS_IDT_VEC_SWINTR: 349 env->interrupt_injected = idtvec_info & VMCS_IDT_VEC_VECNUM; 350 break; 351 case VMCS_IDT_VEC_NMI: 352 env->nmi_injected = true; 353 break; 354 case VMCS_IDT_VEC_HWEXCEPTION: 355 case VMCS_IDT_VEC_SWEXCEPTION: 356 env->exception_nr = idtvec_info & VMCS_IDT_VEC_VECNUM; 357 env->exception_injected = 1; 358 break; 359 case VMCS_IDT_VEC_PRIV_SWEXCEPTION: 360 default: 361 abort(); 362 } 363 if ((idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWEXCEPTION || 364 (idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWINTR) { 365 env->ins_len = ins_len; 366 } 367 if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { 368 env->has_error_code = true; 369 env->error_code = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_ERROR); 370 } 371 } 372 if ((rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) & 373 VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { 374 env->hflags2 |= HF2_NMI_MASK; 375 } else { 376 env->hflags2 &= ~HF2_NMI_MASK; 377 } 378 if (rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) & 379 (VMCS_INTERRUPTIBILITY_STI_BLOCKING | 380 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { 381 env->hflags |= HF_INHIBIT_IRQ_MASK; 382 } else { 383 env->hflags &= ~HF_INHIBIT_IRQ_MASK; 384 } 385 } 386 387 static void hvf_cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 388 uint32_t *eax, uint32_t *ebx, 389 uint32_t *ecx, uint32_t *edx) 390 { 391 /* 392 * A wrapper extends cpu_x86_cpuid with 0x40000000 and 0x40000010 leafs, 393 * leafs 0x40000001-0x4000000F are filled with zeros 394 * Provides vmware-cpuid-freq support to hvf 395 * 396 * Note: leaf 0x40000000 not exposes HVF, 397 * leaving hypervisor signature empty 398 */ 399 400 if (index < 0x40000000 || index > 0x40000010 || 401 !tsc_is_known(env) || !apic_bus_freq_is_known(env)) { 402 403 cpu_x86_cpuid(env, index, count, eax, ebx, ecx, edx); 404 return; 405 } 406 407 switch (index) { 408 case 0x40000000: 409 *eax = 0x40000010; /* Max available cpuid leaf */ 410 *ebx = 0; /* Leave signature empty */ 411 *ecx = 0; 412 *edx = 0; 413 break; 414 case 0x40000010: 415 *eax = env->tsc_khz; 416 *ebx = env->apic_bus_freq / 1000; /* Hz to KHz */ 417 *ecx = 0; 418 *edx = 0; 419 break; 420 default: 421 *eax = 0; 422 *ebx = 0; 423 *ecx = 0; 424 *edx = 0; 425 break; 426 } 427 } 428 429 int hvf_vcpu_exec(CPUState *cpu) 430 { 431 X86CPU *x86_cpu = X86_CPU(cpu); 432 CPUX86State *env = &x86_cpu->env; 433 int ret = 0; 434 uint64_t rip = 0; 435 436 if (hvf_process_events(cpu)) { 437 return EXCP_HLT; 438 } 439 440 do { 441 if (cpu->accel->dirty) { 442 hvf_put_registers(cpu); 443 cpu->accel->dirty = false; 444 } 445 446 if (hvf_inject_interrupts(cpu)) { 447 return EXCP_INTERRUPT; 448 } 449 vmx_update_tpr(cpu); 450 451 bql_unlock(); 452 if (!cpu_is_bsp(X86_CPU(cpu)) && cpu->halted) { 453 bql_lock(); 454 return EXCP_HLT; 455 } 456 457 hv_return_t r = hv_vcpu_run(cpu->accel->fd); 458 assert_hvf_ok(r); 459 460 /* handle VMEXIT */ 461 uint64_t exit_reason = rvmcs(cpu->accel->fd, VMCS_EXIT_REASON); 462 uint64_t exit_qual = rvmcs(cpu->accel->fd, VMCS_EXIT_QUALIFICATION); 463 uint32_t ins_len = (uint32_t)rvmcs(cpu->accel->fd, 464 VMCS_EXIT_INSTRUCTION_LENGTH); 465 466 uint64_t idtvec_info = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_INFO); 467 468 hvf_store_events(cpu, ins_len, idtvec_info); 469 rip = rreg(cpu->accel->fd, HV_X86_RIP); 470 env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS); 471 472 bql_lock(); 473 474 update_apic_tpr(cpu); 475 current_cpu = cpu; 476 477 ret = 0; 478 switch (exit_reason) { 479 case EXIT_REASON_HLT: { 480 macvm_set_rip(cpu, rip + ins_len); 481 if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && 482 (env->eflags & IF_MASK)) 483 && !(cpu->interrupt_request & CPU_INTERRUPT_NMI) && 484 !(idtvec_info & VMCS_IDT_VEC_VALID)) { 485 cpu->halted = 1; 486 ret = EXCP_HLT; 487 break; 488 } 489 ret = EXCP_INTERRUPT; 490 break; 491 } 492 case EXIT_REASON_MWAIT: { 493 ret = EXCP_INTERRUPT; 494 break; 495 } 496 /* Need to check if MMIO or unmapped fault */ 497 case EXIT_REASON_EPT_FAULT: 498 { 499 hvf_slot *slot; 500 uint64_t gpa = rvmcs(cpu->accel->fd, VMCS_GUEST_PHYSICAL_ADDRESS); 501 502 if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) && 503 ((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) { 504 vmx_set_nmi_blocking(cpu); 505 } 506 507 slot = hvf_find_overlap_slot(gpa, 1); 508 /* mmio */ 509 if (ept_emulation_fault(slot, gpa, exit_qual)) { 510 struct x86_decode decode; 511 512 load_regs(cpu); 513 decode_instruction(env, &decode); 514 exec_instruction(env, &decode); 515 store_regs(cpu); 516 break; 517 } 518 break; 519 } 520 case EXIT_REASON_INOUT: 521 { 522 uint32_t in = (exit_qual & 8) != 0; 523 uint32_t size = (exit_qual & 7) + 1; 524 uint32_t string = (exit_qual & 16) != 0; 525 uint32_t port = exit_qual >> 16; 526 /*uint32_t rep = (exit_qual & 0x20) != 0;*/ 527 528 if (!string && in) { 529 uint64_t val = 0; 530 load_regs(cpu); 531 hvf_handle_io(env, port, &val, 0, size, 1); 532 if (size == 1) { 533 AL(env) = val; 534 } else if (size == 2) { 535 AX(env) = val; 536 } else if (size == 4) { 537 RAX(env) = (uint32_t)val; 538 } else { 539 RAX(env) = (uint64_t)val; 540 } 541 env->eip += ins_len; 542 store_regs(cpu); 543 break; 544 } else if (!string && !in) { 545 RAX(env) = rreg(cpu->accel->fd, HV_X86_RAX); 546 hvf_handle_io(env, port, &RAX(env), 1, size, 1); 547 macvm_set_rip(cpu, rip + ins_len); 548 break; 549 } 550 struct x86_decode decode; 551 552 load_regs(cpu); 553 decode_instruction(env, &decode); 554 assert(ins_len == decode.len); 555 exec_instruction(env, &decode); 556 store_regs(cpu); 557 558 break; 559 } 560 case EXIT_REASON_CPUID: { 561 uint32_t rax = (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX); 562 uint32_t rbx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RBX); 563 uint32_t rcx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX); 564 uint32_t rdx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX); 565 566 if (rax == 1) { 567 /* CPUID1.ecx.OSXSAVE needs to know CR4 */ 568 env->cr[4] = rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); 569 } 570 hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); 571 572 wreg(cpu->accel->fd, HV_X86_RAX, rax); 573 wreg(cpu->accel->fd, HV_X86_RBX, rbx); 574 wreg(cpu->accel->fd, HV_X86_RCX, rcx); 575 wreg(cpu->accel->fd, HV_X86_RDX, rdx); 576 577 macvm_set_rip(cpu, rip + ins_len); 578 break; 579 } 580 case EXIT_REASON_XSETBV: { 581 X86CPU *x86_cpu = X86_CPU(cpu); 582 CPUX86State *env = &x86_cpu->env; 583 uint32_t eax = (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX); 584 uint32_t ecx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX); 585 uint32_t edx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX); 586 587 if (ecx) { 588 macvm_set_rip(cpu, rip + ins_len); 589 break; 590 } 591 env->xcr0 = ((uint64_t)edx << 32) | eax; 592 wreg(cpu->accel->fd, HV_X86_XCR0, env->xcr0 | 1); 593 macvm_set_rip(cpu, rip + ins_len); 594 break; 595 } 596 case EXIT_REASON_INTR_WINDOW: 597 vmx_clear_int_window_exiting(cpu); 598 ret = EXCP_INTERRUPT; 599 break; 600 case EXIT_REASON_NMI_WINDOW: 601 vmx_clear_nmi_window_exiting(cpu); 602 ret = EXCP_INTERRUPT; 603 break; 604 case EXIT_REASON_EXT_INTR: 605 /* force exit and allow io handling */ 606 ret = EXCP_INTERRUPT; 607 break; 608 case EXIT_REASON_RDMSR: 609 case EXIT_REASON_WRMSR: 610 { 611 load_regs(cpu); 612 if (exit_reason == EXIT_REASON_RDMSR) { 613 simulate_rdmsr(env); 614 } else { 615 simulate_wrmsr(env); 616 } 617 env->eip += ins_len; 618 store_regs(cpu); 619 break; 620 } 621 case EXIT_REASON_CR_ACCESS: { 622 int cr; 623 int reg; 624 625 load_regs(cpu); 626 cr = exit_qual & 15; 627 reg = (exit_qual >> 8) & 15; 628 629 switch (cr) { 630 case 0x0: { 631 macvm_set_cr0(cpu->accel->fd, RRX(env, reg)); 632 break; 633 } 634 case 4: { 635 macvm_set_cr4(cpu->accel->fd, RRX(env, reg)); 636 break; 637 } 638 case 8: { 639 X86CPU *x86_cpu = X86_CPU(cpu); 640 if (exit_qual & 0x10) { 641 RRX(env, reg) = cpu_get_apic_tpr(x86_cpu->apic_state); 642 } else { 643 int tpr = RRX(env, reg); 644 cpu_set_apic_tpr(x86_cpu->apic_state, tpr); 645 ret = EXCP_INTERRUPT; 646 } 647 break; 648 } 649 default: 650 error_report("Unrecognized CR %d", cr); 651 abort(); 652 } 653 env->eip += ins_len; 654 store_regs(cpu); 655 break; 656 } 657 case EXIT_REASON_APIC_ACCESS: { /* TODO */ 658 struct x86_decode decode; 659 660 load_regs(cpu); 661 decode_instruction(env, &decode); 662 exec_instruction(env, &decode); 663 store_regs(cpu); 664 break; 665 } 666 case EXIT_REASON_TPR: { 667 ret = 1; 668 break; 669 } 670 case EXIT_REASON_TASK_SWITCH: { 671 uint64_t vinfo = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_INFO); 672 x68_segment_selector sel = {.sel = exit_qual & 0xffff}; 673 vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3, 674 vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo 675 & VMCS_INTR_T_MASK); 676 break; 677 } 678 case EXIT_REASON_TRIPLE_FAULT: { 679 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 680 ret = EXCP_INTERRUPT; 681 break; 682 } 683 case EXIT_REASON_RDPMC: 684 wreg(cpu->accel->fd, HV_X86_RAX, 0); 685 wreg(cpu->accel->fd, HV_X86_RDX, 0); 686 macvm_set_rip(cpu, rip + ins_len); 687 break; 688 case VMX_REASON_VMCALL: 689 env->exception_nr = EXCP0D_GPF; 690 env->exception_injected = 1; 691 env->has_error_code = true; 692 env->error_code = 0; 693 break; 694 default: 695 error_report("%llx: unhandled exit %llx", rip, exit_reason); 696 } 697 } while (ret == 0); 698 699 return ret; 700 } 701 702 int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 703 { 704 return -ENOSYS; 705 } 706 707 int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 708 { 709 return -ENOSYS; 710 } 711 712 int hvf_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 713 { 714 return -ENOSYS; 715 } 716 717 int hvf_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 718 { 719 return -ENOSYS; 720 } 721 722 void hvf_arch_remove_all_hw_breakpoints(void) 723 { 724 } 725 726 void hvf_arch_update_guest_debug(CPUState *cpu) 727 { 728 } 729 730 bool hvf_arch_supports_guest_debug(void) 731 { 732 return false; 733 } 734