xref: /qemu/target/i386/helper.c (revision 2c4815590f9ea399bc87f727dd1c883b0d701bb8)
1  /*
2   *  i386 helpers (without register variable usage)
3   *
4   *  Copyright (c) 2003 Fabrice Bellard
5   *
6   * This library is free software; you can redistribute it and/or
7   * modify it under the terms of the GNU Lesser General Public
8   * License as published by the Free Software Foundation; either
9   * version 2.1 of the License, or (at your option) any later version.
10   *
11   * This library is distributed in the hope that it will be useful,
12   * but WITHOUT ANY WARRANTY; without even the implied warranty of
13   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14   * Lesser General Public License for more details.
15   *
16   * You should have received a copy of the GNU Lesser General Public
17   * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18   */
19  
20  #include "qemu/osdep.h"
21  #include "qapi/qapi-events-run-state.h"
22  #include "cpu.h"
23  #include "exec/exec-all.h"
24  #include "exec/translation-block.h"
25  #include "system/runstate.h"
26  #ifndef CONFIG_USER_ONLY
27  #include "system/hw_accel.h"
28  #include "monitor/monitor.h"
29  #include "kvm/kvm_i386.h"
30  #endif
31  #include "qemu/log.h"
32  #ifdef CONFIG_TCG
33  #include "tcg/insn-start-words.h"
34  #endif
35  
36  void cpu_sync_avx_hflag(CPUX86State *env)
37  {
38      if ((env->cr[4] & CR4_OSXSAVE_MASK)
39          && (env->xcr0 & (XSTATE_SSE_MASK | XSTATE_YMM_MASK))
40              == (XSTATE_SSE_MASK | XSTATE_YMM_MASK)) {
41          env->hflags |= HF_AVX_EN_MASK;
42      } else{
43          env->hflags &= ~HF_AVX_EN_MASK;
44      }
45  }
46  
47  void cpu_sync_bndcs_hflags(CPUX86State *env)
48  {
49      uint32_t hflags = env->hflags;
50      uint32_t hflags2 = env->hflags2;
51      uint32_t bndcsr;
52  
53      if ((hflags & HF_CPL_MASK) == 3) {
54          bndcsr = env->bndcs_regs.cfgu;
55      } else {
56          bndcsr = env->msr_bndcfgs;
57      }
58  
59      if ((env->cr[4] & CR4_OSXSAVE_MASK)
60          && (env->xcr0 & XSTATE_BNDCSR_MASK)
61          && (bndcsr & BNDCFG_ENABLE)) {
62          hflags |= HF_MPX_EN_MASK;
63      } else {
64          hflags &= ~HF_MPX_EN_MASK;
65      }
66  
67      if (bndcsr & BNDCFG_BNDPRESERVE) {
68          hflags2 |= HF2_MPX_PR_MASK;
69      } else {
70          hflags2 &= ~HF2_MPX_PR_MASK;
71      }
72  
73      env->hflags = hflags;
74      env->hflags2 = hflags2;
75  }
76  
77  static void cpu_x86_version(CPUX86State *env, int *family, int *model)
78  {
79      int cpuver = env->cpuid_version;
80  
81      if (family == NULL || model == NULL) {
82          return;
83      }
84  
85      *family = (cpuver >> 8) & 0x0f;
86      *model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0x0f);
87  }
88  
89  /* Broadcast MCA signal for processor version 06H_EH and above */
90  int cpu_x86_support_mca_broadcast(CPUX86State *env)
91  {
92      int family = 0;
93      int model = 0;
94  
95      if (IS_AMD_CPU(env)) {
96          return 0;
97      }
98  
99      cpu_x86_version(env, &family, &model);
100      if ((family == 6 && model >= 14) || family > 6) {
101          return 1;
102      }
103  
104      return 0;
105  }
106  
107  /***********************************************************/
108  /* x86 mmu */
109  /* XXX: add PGE support */
110  
111  void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
112  {
113      CPUX86State *env = &cpu->env;
114  
115      a20_state = (a20_state != 0);
116      if (a20_state != ((env->a20_mask >> 20) & 1)) {
117          CPUState *cs = CPU(cpu);
118  
119          qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state);
120          /* if the cpu is currently executing code, we must unlink it and
121             all the potentially executing TB */
122          cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
123  
124          /* when a20 is changed, all the MMU mappings are invalid, so
125             we must flush everything */
126          tlb_flush(cs);
127          env->a20_mask = ~(1 << 20) | (a20_state << 20);
128      }
129  }
130  
131  void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
132  {
133      X86CPU *cpu = env_archcpu(env);
134      int pe_state;
135  
136      qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
137      if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
138          (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
139          tlb_flush(CPU(cpu));
140      }
141  
142  #ifdef TARGET_X86_64
143      if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
144          (env->efer & MSR_EFER_LME)) {
145          /* enter in long mode */
146          /* XXX: generate an exception */
147          if (!(env->cr[4] & CR4_PAE_MASK))
148              return;
149          env->efer |= MSR_EFER_LMA;
150          env->hflags |= HF_LMA_MASK;
151      } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
152                 (env->efer & MSR_EFER_LMA)) {
153          /* exit long mode */
154          env->efer &= ~MSR_EFER_LMA;
155          env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
156          env->eip &= 0xffffffff;
157      }
158  #endif
159      env->cr[0] = new_cr0 | CR0_ET_MASK;
160  
161      /* update PE flag in hidden flags */
162      pe_state = (env->cr[0] & CR0_PE_MASK);
163      env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
164      /* ensure that ADDSEG is always set in real mode */
165      env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
166      /* update FPU flags */
167      env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
168          ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
169  }
170  
171  /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
172     the PDPT */
173  void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
174  {
175      env->cr[3] = new_cr3;
176      if (env->cr[0] & CR0_PG_MASK) {
177          qemu_log_mask(CPU_LOG_MMU,
178                          "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
179          tlb_flush(env_cpu(env));
180      }
181  }
182  
183  void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
184  {
185      uint32_t hflags;
186  
187  #if defined(DEBUG_MMU)
188      printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4);
189  #endif
190      if ((new_cr4 ^ env->cr[4]) &
191          (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
192           CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
193          tlb_flush(env_cpu(env));
194      }
195  
196      /* Clear bits we're going to recompute.  */
197      hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK | HF_UMIP_MASK);
198  
199      /* SSE handling */
200      if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
201          new_cr4 &= ~CR4_OSFXSR_MASK;
202      }
203      if (new_cr4 & CR4_OSFXSR_MASK) {
204          hflags |= HF_OSFXSR_MASK;
205      }
206  
207      if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
208          new_cr4 &= ~CR4_SMAP_MASK;
209      }
210      if (new_cr4 & CR4_SMAP_MASK) {
211          hflags |= HF_SMAP_MASK;
212      }
213      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
214          new_cr4 &= ~CR4_UMIP_MASK;
215      }
216      if (new_cr4 & CR4_UMIP_MASK) {
217          hflags |= HF_UMIP_MASK;
218      }
219  
220      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
221          new_cr4 &= ~CR4_PKE_MASK;
222      }
223      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
224          new_cr4 &= ~CR4_PKS_MASK;
225      }
226  
227      if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) {
228          new_cr4 &= ~CR4_LAM_SUP_MASK;
229      }
230  
231      env->cr[4] = new_cr4;
232      env->hflags = hflags;
233  
234      cpu_sync_bndcs_hflags(env);
235      cpu_sync_avx_hflag(env);
236  }
237  
238  #if !defined(CONFIG_USER_ONLY)
239  hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
240                                           MemTxAttrs *attrs)
241  {
242      X86CPU *cpu = X86_CPU(cs);
243      CPUX86State *env = &cpu->env;
244      target_ulong pde_addr, pte_addr;
245      uint64_t pte;
246      int32_t a20_mask;
247      uint32_t page_offset;
248      int page_size;
249  
250      *attrs = cpu_get_mem_attrs(env);
251  
252      a20_mask = x86_get_a20_mask(env);
253      if (!(env->cr[0] & CR0_PG_MASK)) {
254          pte = addr & a20_mask;
255          page_size = 4096;
256      } else if (env->cr[4] & CR4_PAE_MASK) {
257          target_ulong pdpe_addr;
258          uint64_t pde, pdpe;
259  
260  #ifdef TARGET_X86_64
261          if (env->hflags & HF_LMA_MASK) {
262              bool la57 = env->cr[4] & CR4_LA57_MASK;
263              uint64_t pml5e_addr, pml5e;
264              uint64_t pml4e_addr, pml4e;
265              int32_t sext;
266  
267              /* test virtual address sign extension */
268              sext = la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47;
269              if (sext != 0 && sext != -1) {
270                  return -1;
271              }
272  
273              if (la57) {
274                  pml5e_addr = ((env->cr[3] & ~0xfff) +
275                          (((addr >> 48) & 0x1ff) << 3)) & a20_mask;
276                  pml5e = x86_ldq_phys(cs, pml5e_addr);
277                  if (!(pml5e & PG_PRESENT_MASK)) {
278                      return -1;
279                  }
280              } else {
281                  pml5e = env->cr[3];
282              }
283  
284              pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
285                      (((addr >> 39) & 0x1ff) << 3)) & a20_mask;
286              pml4e = x86_ldq_phys(cs, pml4e_addr);
287              if (!(pml4e & PG_PRESENT_MASK)) {
288                  return -1;
289              }
290              pdpe_addr = ((pml4e & PG_ADDRESS_MASK) +
291                           (((addr >> 30) & 0x1ff) << 3)) & a20_mask;
292              pdpe = x86_ldq_phys(cs, pdpe_addr);
293              if (!(pdpe & PG_PRESENT_MASK)) {
294                  return -1;
295              }
296              if (pdpe & PG_PSE_MASK) {
297                  page_size = 1024 * 1024 * 1024;
298                  pte = pdpe;
299                  goto out;
300              }
301  
302          } else
303  #endif
304          {
305              pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
306                  a20_mask;
307              pdpe = x86_ldq_phys(cs, pdpe_addr);
308              if (!(pdpe & PG_PRESENT_MASK))
309                  return -1;
310          }
311  
312          pde_addr = ((pdpe & PG_ADDRESS_MASK) +
313                      (((addr >> 21) & 0x1ff) << 3)) & a20_mask;
314          pde = x86_ldq_phys(cs, pde_addr);
315          if (!(pde & PG_PRESENT_MASK)) {
316              return -1;
317          }
318          if (pde & PG_PSE_MASK) {
319              /* 2 MB page */
320              page_size = 2048 * 1024;
321              pte = pde;
322          } else {
323              /* 4 KB page */
324              pte_addr = ((pde & PG_ADDRESS_MASK) +
325                          (((addr >> 12) & 0x1ff) << 3)) & a20_mask;
326              page_size = 4096;
327              pte = x86_ldq_phys(cs, pte_addr);
328          }
329          if (!(pte & PG_PRESENT_MASK)) {
330              return -1;
331          }
332      } else {
333          uint32_t pde;
334  
335          /* page directory entry */
336          pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask;
337          pde = x86_ldl_phys(cs, pde_addr);
338          if (!(pde & PG_PRESENT_MASK))
339              return -1;
340          if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
341              pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
342              page_size = 4096 * 1024;
343          } else {
344              /* page directory entry */
345              pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask;
346              pte = x86_ldl_phys(cs, pte_addr);
347              if (!(pte & PG_PRESENT_MASK)) {
348                  return -1;
349              }
350              page_size = 4096;
351          }
352          pte = pte & a20_mask;
353      }
354  
355  #ifdef TARGET_X86_64
356  out:
357  #endif
358      pte &= PG_ADDRESS_MASK & ~(page_size - 1);
359      page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
360      return pte | page_offset;
361  }
362  
363  typedef struct MCEInjectionParams {
364      Monitor *mon;
365      int bank;
366      uint64_t status;
367      uint64_t mcg_status;
368      uint64_t addr;
369      uint64_t misc;
370      int flags;
371  } MCEInjectionParams;
372  
373  static void emit_guest_memory_failure(MemoryFailureAction action, bool ar,
374                                        bool recursive)
375  {
376      MemoryFailureFlags mff = {.action_required = ar, .recursive = recursive};
377  
378      qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_GUEST, action,
379                                     &mff);
380  }
381  
382  static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data data)
383  {
384      MCEInjectionParams *params = data.host_ptr;
385      X86CPU *cpu = X86_CPU(cs);
386      CPUX86State *cenv = &cpu->env;
387      uint64_t *banks = cenv->mce_banks + 4 * params->bank;
388      g_autofree char *msg = NULL;
389      bool need_reset = false;
390      bool recursive;
391      bool ar = !!(params->status & MCI_STATUS_AR);
392  
393      cpu_synchronize_state(cs);
394      recursive = !!(cenv->mcg_status & MCG_STATUS_MCIP);
395  
396      /*
397       * If there is an MCE exception being processed, ignore this SRAO MCE
398       * unless unconditional injection was requested.
399       */
400      if (!(params->flags & MCE_INJECT_UNCOND_AO) && !ar && recursive) {
401          emit_guest_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, ar, recursive);
402          return;
403      }
404  
405      if (params->status & MCI_STATUS_UC) {
406          /*
407           * if MSR_MCG_CTL is not all 1s, the uncorrected error
408           * reporting is disabled
409           */
410          if ((cenv->mcg_cap & MCG_CTL_P) && cenv->mcg_ctl != ~(uint64_t)0) {
411              monitor_printf(params->mon,
412                             "CPU %d: Uncorrected error reporting disabled\n",
413                             cs->cpu_index);
414              return;
415          }
416  
417          /*
418           * if MSR_MCi_CTL is not all 1s, the uncorrected error
419           * reporting is disabled for the bank
420           */
421          if (banks[0] != ~(uint64_t)0) {
422              monitor_printf(params->mon,
423                             "CPU %d: Uncorrected error reporting disabled for"
424                             " bank %d\n",
425                             cs->cpu_index, params->bank);
426              return;
427          }
428  
429          if (!(cenv->cr[4] & CR4_MCE_MASK)) {
430              need_reset = true;
431              msg = g_strdup_printf("CPU %d: MCE capability is not enabled, "
432                                    "raising triple fault", cs->cpu_index);
433          } else if (recursive) {
434              need_reset = true;
435              msg = g_strdup_printf("CPU %d: Previous MCE still in progress, "
436                                    "raising triple fault", cs->cpu_index);
437          }
438  
439          if (need_reset) {
440              emit_guest_memory_failure(MEMORY_FAILURE_ACTION_RESET, ar,
441                                        recursive);
442              monitor_printf(params->mon, "%s", msg);
443              qemu_log_mask(CPU_LOG_RESET, "%s\n", msg);
444              qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
445              return;
446          }
447  
448          if (banks[1] & MCI_STATUS_VAL) {
449              params->status |= MCI_STATUS_OVER;
450          }
451          banks[2] = params->addr;
452          banks[3] = params->misc;
453          cenv->mcg_status = params->mcg_status;
454          banks[1] = params->status;
455          cpu_interrupt(cs, CPU_INTERRUPT_MCE);
456      } else if (!(banks[1] & MCI_STATUS_VAL)
457                 || !(banks[1] & MCI_STATUS_UC)) {
458          if (banks[1] & MCI_STATUS_VAL) {
459              params->status |= MCI_STATUS_OVER;
460          }
461          banks[2] = params->addr;
462          banks[3] = params->misc;
463          banks[1] = params->status;
464      } else {
465          banks[1] |= MCI_STATUS_OVER;
466      }
467  
468      emit_guest_memory_failure(MEMORY_FAILURE_ACTION_INJECT, ar, recursive);
469  }
470  
471  void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
472                          uint64_t status, uint64_t mcg_status, uint64_t addr,
473                          uint64_t misc, int flags)
474  {
475      CPUState *cs = CPU(cpu);
476      CPUX86State *cenv = &cpu->env;
477      MCEInjectionParams params = {
478          .mon = mon,
479          .bank = bank,
480          .status = status,
481          .mcg_status = mcg_status,
482          .addr = addr,
483          .misc = misc,
484          .flags = flags,
485      };
486      unsigned bank_num = cenv->mcg_cap & 0xff;
487  
488      if (!cenv->mcg_cap) {
489          monitor_printf(mon, "MCE injection not supported\n");
490          return;
491      }
492      if (bank >= bank_num) {
493          monitor_printf(mon, "Invalid MCE bank number\n");
494          return;
495      }
496      if (!(status & MCI_STATUS_VAL)) {
497          monitor_printf(mon, "Invalid MCE status code\n");
498          return;
499      }
500      if ((flags & MCE_INJECT_BROADCAST)
501          && !cpu_x86_support_mca_broadcast(cenv)) {
502          monitor_printf(mon, "Guest CPU does not support MCA broadcast\n");
503          return;
504      }
505  
506      run_on_cpu(cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(&params));
507      if (flags & MCE_INJECT_BROADCAST) {
508          CPUState *other_cs;
509  
510          params.bank = 1;
511          params.status = MCI_STATUS_VAL | MCI_STATUS_UC;
512          params.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
513          params.addr = 0;
514          params.misc = 0;
515          CPU_FOREACH(other_cs) {
516              if (other_cs == cs) {
517                  continue;
518              }
519              run_on_cpu(other_cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(&params));
520          }
521      }
522  }
523  
524  static inline target_ulong get_memio_eip(CPUX86State *env)
525  {
526  #ifdef CONFIG_TCG
527      uint64_t data[TARGET_INSN_START_WORDS];
528      CPUState *cs = env_cpu(env);
529  
530      if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) {
531          return env->eip;
532      }
533  
534      /* Per x86_restore_state_to_opc. */
535      if (tcg_cflags_has(cs, CF_PCREL)) {
536          return (env->eip & TARGET_PAGE_MASK) | data[0];
537      } else {
538          return data[0] - env->segs[R_CS].base;
539      }
540  #else
541      qemu_build_not_reached();
542  #endif
543  }
544  
545  void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
546  {
547      X86CPU *cpu = env_archcpu(env);
548      CPUState *cs = env_cpu(env);
549  
550      if (kvm_enabled() || whpx_enabled() || nvmm_enabled()) {
551          env->tpr_access_type = access;
552  
553          cpu_interrupt(cs, CPU_INTERRUPT_TPR);
554      } else if (tcg_enabled()) {
555          target_ulong eip = get_memio_eip(env);
556  
557          apic_handle_tpr_access_report(cpu->apic_state, eip, access);
558      }
559  }
560  #endif /* !CONFIG_USER_ONLY */
561  
562  int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
563                              target_ulong *base, unsigned int *limit,
564                              unsigned int *flags)
565  {
566      CPUState *cs = env_cpu(env);
567      SegmentCache *dt;
568      target_ulong ptr;
569      uint32_t e1, e2;
570      int index;
571  
572      if (selector & 0x4)
573          dt = &env->ldt;
574      else
575          dt = &env->gdt;
576      index = selector & ~7;
577      ptr = dt->base + index;
578      if ((index + 7) > dt->limit
579          || cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
580          || cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
581          return 0;
582  
583      *base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
584      *limit = (e1 & 0xffff) | (e2 & 0x000f0000);
585      if (e2 & DESC_G_MASK)
586          *limit = (*limit << 12) | 0xfff;
587      *flags = e2;
588  
589      return 1;
590  }
591  
592  void do_cpu_init(X86CPU *cpu)
593  {
594  #if !defined(CONFIG_USER_ONLY)
595      CPUState *cs = CPU(cpu);
596      CPUX86State *env = &cpu->env;
597      CPUX86State *save = g_new(CPUX86State, 1);
598      int sipi = cs->interrupt_request & CPU_INTERRUPT_SIPI;
599  
600      *save = *env;
601  
602      cpu_reset(cs);
603      cs->interrupt_request = sipi;
604      memcpy(&env->start_init_save, &save->start_init_save,
605             offsetof(CPUX86State, end_init_save) -
606             offsetof(CPUX86State, start_init_save));
607      g_free(save);
608  
609      if (kvm_enabled()) {
610          kvm_arch_do_init_vcpu(cpu);
611      }
612      apic_init_reset(cpu->apic_state);
613  #endif /* CONFIG_USER_ONLY */
614  }
615  
616  #ifndef CONFIG_USER_ONLY
617  
618  void do_cpu_sipi(X86CPU *cpu)
619  {
620      apic_sipi(cpu->apic_state);
621  }
622  
623  void cpu_load_efer(CPUX86State *env, uint64_t val)
624  {
625      env->efer = val;
626      env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
627      if (env->efer & MSR_EFER_LMA) {
628          env->hflags |= HF_LMA_MASK;
629      }
630      if (env->efer & MSR_EFER_SVME) {
631          env->hflags |= HF_SVME_MASK;
632      }
633  }
634  
635  uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
636  {
637      X86CPU *cpu = X86_CPU(cs);
638      CPUX86State *env = &cpu->env;
639      MemTxAttrs attrs = cpu_get_mem_attrs(env);
640      AddressSpace *as = cpu_addressspace(cs, attrs);
641  
642      return address_space_ldub(as, addr, attrs, NULL);
643  }
644  
645  uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr)
646  {
647      X86CPU *cpu = X86_CPU(cs);
648      CPUX86State *env = &cpu->env;
649      MemTxAttrs attrs = cpu_get_mem_attrs(env);
650      AddressSpace *as = cpu_addressspace(cs, attrs);
651  
652      return address_space_lduw(as, addr, attrs, NULL);
653  }
654  
655  uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr)
656  {
657      X86CPU *cpu = X86_CPU(cs);
658      CPUX86State *env = &cpu->env;
659      MemTxAttrs attrs = cpu_get_mem_attrs(env);
660      AddressSpace *as = cpu_addressspace(cs, attrs);
661  
662      return address_space_ldl(as, addr, attrs, NULL);
663  }
664  
665  uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr)
666  {
667      X86CPU *cpu = X86_CPU(cs);
668      CPUX86State *env = &cpu->env;
669      MemTxAttrs attrs = cpu_get_mem_attrs(env);
670      AddressSpace *as = cpu_addressspace(cs, attrs);
671  
672      return address_space_ldq(as, addr, attrs, NULL);
673  }
674  
675  void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val)
676  {
677      X86CPU *cpu = X86_CPU(cs);
678      CPUX86State *env = &cpu->env;
679      MemTxAttrs attrs = cpu_get_mem_attrs(env);
680      AddressSpace *as = cpu_addressspace(cs, attrs);
681  
682      address_space_stb(as, addr, val, attrs, NULL);
683  }
684  
685  void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val)
686  {
687      X86CPU *cpu = X86_CPU(cs);
688      CPUX86State *env = &cpu->env;
689      MemTxAttrs attrs = cpu_get_mem_attrs(env);
690      AddressSpace *as = cpu_addressspace(cs, attrs);
691  
692      address_space_stl_notdirty(as, addr, val, attrs, NULL);
693  }
694  
695  void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val)
696  {
697      X86CPU *cpu = X86_CPU(cs);
698      CPUX86State *env = &cpu->env;
699      MemTxAttrs attrs = cpu_get_mem_attrs(env);
700      AddressSpace *as = cpu_addressspace(cs, attrs);
701  
702      address_space_stw(as, addr, val, attrs, NULL);
703  }
704  
705  void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val)
706  {
707      X86CPU *cpu = X86_CPU(cs);
708      CPUX86State *env = &cpu->env;
709      MemTxAttrs attrs = cpu_get_mem_attrs(env);
710      AddressSpace *as = cpu_addressspace(cs, attrs);
711  
712      address_space_stl(as, addr, val, attrs, NULL);
713  }
714  
715  void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val)
716  {
717      X86CPU *cpu = X86_CPU(cs);
718      CPUX86State *env = &cpu->env;
719      MemTxAttrs attrs = cpu_get_mem_attrs(env);
720      AddressSpace *as = cpu_addressspace(cs, attrs);
721  
722      address_space_stq(as, addr, val, attrs, NULL);
723  }
724  #endif
725