1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "system/reset.h" 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 51 uint32_t *eax, uint32_t *ebx, 52 uint32_t *ecx, uint32_t *edx); 53 54 /* Helpers for building CPUID[2] descriptors: */ 55 56 struct CPUID2CacheDescriptorInfo { 57 enum CacheType type; 58 int level; 59 int size; 60 int line_size; 61 int associativity; 62 }; 63 64 /* 65 * Known CPUID 2 cache descriptors. 66 * From Intel SDM Volume 2A, CPUID instruction 67 */ 68 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 69 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 70 .associativity = 4, .line_size = 32, }, 71 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 72 .associativity = 4, .line_size = 32, }, 73 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 74 .associativity = 4, .line_size = 64, }, 75 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 76 .associativity = 2, .line_size = 32, }, 77 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 78 .associativity = 4, .line_size = 32, }, 79 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 80 .associativity = 4, .line_size = 64, }, 81 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 82 .associativity = 6, .line_size = 64, }, 83 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 84 .associativity = 2, .line_size = 64, }, 85 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 86 .associativity = 8, .line_size = 64, }, 87 /* lines per sector is not supported cpuid2_cache_descriptor(), 88 * so descriptors 0x22, 0x23 are not included 89 */ 90 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 91 .associativity = 16, .line_size = 64, }, 92 /* lines per sector is not supported cpuid2_cache_descriptor(), 93 * so descriptors 0x25, 0x20 are not included 94 */ 95 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 96 .associativity = 8, .line_size = 64, }, 97 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 98 .associativity = 8, .line_size = 64, }, 99 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 100 .associativity = 4, .line_size = 32, }, 101 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 106 .associativity = 4, .line_size = 32, }, 107 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 108 .associativity = 4, .line_size = 32, }, 109 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 110 .associativity = 4, .line_size = 64, }, 111 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 112 .associativity = 8, .line_size = 64, }, 113 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 116 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 119 .associativity = 16, .line_size = 64, }, 120 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 121 .associativity = 12, .line_size = 64, }, 122 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 123 .associativity = 16, .line_size = 64, }, 124 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 125 .associativity = 24, .line_size = 64, }, 126 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 127 .associativity = 8, .line_size = 64, }, 128 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 129 .associativity = 4, .line_size = 64, }, 130 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 131 .associativity = 4, .line_size = 64, }, 132 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 133 .associativity = 4, .line_size = 64, }, 134 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 135 .associativity = 4, .line_size = 64, }, 136 /* lines per sector is not supported cpuid2_cache_descriptor(), 137 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 138 */ 139 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 140 .associativity = 8, .line_size = 64, }, 141 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 142 .associativity = 2, .line_size = 64, }, 143 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 8, .line_size = 64, }, 145 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 146 .associativity = 8, .line_size = 32, }, 147 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 150 .associativity = 8, .line_size = 32, }, 151 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 152 .associativity = 8, .line_size = 32, }, 153 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 4, .line_size = 64, }, 155 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 156 .associativity = 8, .line_size = 64, }, 157 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 158 .associativity = 4, .line_size = 64, }, 159 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 4, .line_size = 64, }, 161 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 4, .line_size = 64, }, 163 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 164 .associativity = 8, .line_size = 64, }, 165 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 166 .associativity = 8, .line_size = 64, }, 167 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 168 .associativity = 8, .line_size = 64, }, 169 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 170 .associativity = 12, .line_size = 64, }, 171 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 172 .associativity = 12, .line_size = 64, }, 173 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 174 .associativity = 12, .line_size = 64, }, 175 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 176 .associativity = 16, .line_size = 64, }, 177 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 178 .associativity = 16, .line_size = 64, }, 179 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 180 .associativity = 16, .line_size = 64, }, 181 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 182 .associativity = 24, .line_size = 64, }, 183 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 184 .associativity = 24, .line_size = 64, }, 185 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 186 .associativity = 24, .line_size = 64, }, 187 }; 188 189 /* 190 * "CPUID leaf 2 does not report cache descriptor information, 191 * use CPUID leaf 4 to query cache parameters" 192 */ 193 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 194 195 /* 196 * Return a CPUID 2 cache descriptor for a given cache. 197 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 198 */ 199 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 200 { 201 int i; 202 203 assert(cache->size > 0); 204 assert(cache->level > 0); 205 assert(cache->line_size > 0); 206 assert(cache->associativity > 0); 207 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 208 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 209 if (d->level == cache->level && d->type == cache->type && 210 d->size == cache->size && d->line_size == cache->line_size && 211 d->associativity == cache->associativity) { 212 return i; 213 } 214 } 215 216 return CACHE_DESCRIPTOR_UNAVAILABLE; 217 } 218 219 /* CPUID Leaf 4 constants: */ 220 221 /* EAX: */ 222 #define CACHE_TYPE_D 1 223 #define CACHE_TYPE_I 2 224 #define CACHE_TYPE_UNIFIED 3 225 226 #define CACHE_LEVEL(l) (l << 5) 227 228 #define CACHE_SELF_INIT_LEVEL (1 << 8) 229 230 /* EDX: */ 231 #define CACHE_NO_INVD_SHARING (1 << 0) 232 #define CACHE_INCLUSIVE (1 << 1) 233 #define CACHE_COMPLEX_IDX (1 << 2) 234 235 /* Encode CacheType for CPUID[4].EAX */ 236 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 237 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 238 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 239 0 /* Invalid value */) 240 241 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 242 enum CpuTopologyLevel share_level) 243 { 244 uint32_t num_ids = 0; 245 246 switch (share_level) { 247 case CPU_TOPOLOGY_LEVEL_CORE: 248 num_ids = 1 << apicid_core_offset(topo_info); 249 break; 250 case CPU_TOPOLOGY_LEVEL_MODULE: 251 num_ids = 1 << apicid_module_offset(topo_info); 252 break; 253 case CPU_TOPOLOGY_LEVEL_DIE: 254 num_ids = 1 << apicid_die_offset(topo_info); 255 break; 256 case CPU_TOPOLOGY_LEVEL_SOCKET: 257 num_ids = 1 << apicid_pkg_offset(topo_info); 258 break; 259 default: 260 /* 261 * Currently there is no use case for THREAD, so use 262 * assert directly to facilitate debugging. 263 */ 264 g_assert_not_reached(); 265 } 266 267 return num_ids - 1; 268 } 269 270 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 271 { 272 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 273 apicid_core_offset(topo_info)); 274 return num_cores - 1; 275 } 276 277 /* Encode cache info for CPUID[4] */ 278 static void encode_cache_cpuid4(CPUCacheInfo *cache, 279 X86CPUTopoInfo *topo_info, 280 uint32_t *eax, uint32_t *ebx, 281 uint32_t *ecx, uint32_t *edx) 282 { 283 assert(cache->size == cache->line_size * cache->associativity * 284 cache->partitions * cache->sets); 285 286 *eax = CACHE_TYPE(cache->type) | 287 CACHE_LEVEL(cache->level) | 288 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 289 (max_core_ids_in_package(topo_info) << 26) | 290 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 291 292 assert(cache->line_size > 0); 293 assert(cache->partitions > 0); 294 assert(cache->associativity > 0); 295 /* We don't implement fully-associative caches */ 296 assert(cache->associativity < cache->sets); 297 *ebx = (cache->line_size - 1) | 298 ((cache->partitions - 1) << 12) | 299 ((cache->associativity - 1) << 22); 300 301 assert(cache->sets > 0); 302 *ecx = cache->sets - 1; 303 304 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 305 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 306 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 307 } 308 309 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 310 enum CpuTopologyLevel topo_level) 311 { 312 switch (topo_level) { 313 case CPU_TOPOLOGY_LEVEL_THREAD: 314 return 1; 315 case CPU_TOPOLOGY_LEVEL_CORE: 316 return topo_info->threads_per_core; 317 case CPU_TOPOLOGY_LEVEL_MODULE: 318 return x86_threads_per_module(topo_info); 319 case CPU_TOPOLOGY_LEVEL_DIE: 320 return x86_threads_per_die(topo_info); 321 case CPU_TOPOLOGY_LEVEL_SOCKET: 322 return x86_threads_per_pkg(topo_info); 323 default: 324 g_assert_not_reached(); 325 } 326 return 0; 327 } 328 329 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 330 enum CpuTopologyLevel topo_level) 331 { 332 switch (topo_level) { 333 case CPU_TOPOLOGY_LEVEL_THREAD: 334 return 0; 335 case CPU_TOPOLOGY_LEVEL_CORE: 336 return apicid_core_offset(topo_info); 337 case CPU_TOPOLOGY_LEVEL_MODULE: 338 return apicid_module_offset(topo_info); 339 case CPU_TOPOLOGY_LEVEL_DIE: 340 return apicid_die_offset(topo_info); 341 case CPU_TOPOLOGY_LEVEL_SOCKET: 342 return apicid_pkg_offset(topo_info); 343 default: 344 g_assert_not_reached(); 345 } 346 return 0; 347 } 348 349 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 350 { 351 switch (topo_level) { 352 case CPU_TOPOLOGY_LEVEL_INVALID: 353 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 354 case CPU_TOPOLOGY_LEVEL_THREAD: 355 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 356 case CPU_TOPOLOGY_LEVEL_CORE: 357 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 358 case CPU_TOPOLOGY_LEVEL_MODULE: 359 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 360 case CPU_TOPOLOGY_LEVEL_DIE: 361 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 362 default: 363 /* Other types are not supported in QEMU. */ 364 g_assert_not_reached(); 365 } 366 return 0; 367 } 368 369 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 370 X86CPUTopoInfo *topo_info, 371 uint32_t *eax, uint32_t *ebx, 372 uint32_t *ecx, uint32_t *edx) 373 { 374 X86CPU *cpu = env_archcpu(env); 375 unsigned long level, base_level, next_level; 376 uint32_t num_threads_next_level, offset_next_level; 377 378 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 379 380 /* 381 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 382 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 383 */ 384 level = CPU_TOPOLOGY_LEVEL_THREAD; 385 base_level = level; 386 for (int i = 0; i <= count; i++) { 387 level = find_next_bit(env->avail_cpu_topo, 388 CPU_TOPOLOGY_LEVEL_SOCKET, 389 base_level); 390 391 /* 392 * CPUID[0x1f] doesn't explicitly encode the package level, 393 * and it just encodes the invalid level (all fields are 0) 394 * into the last subleaf of 0x1f. 395 */ 396 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 397 level = CPU_TOPOLOGY_LEVEL_INVALID; 398 break; 399 } 400 /* Search the next level. */ 401 base_level = level + 1; 402 } 403 404 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 405 num_threads_next_level = 0; 406 offset_next_level = 0; 407 } else { 408 next_level = find_next_bit(env->avail_cpu_topo, 409 CPU_TOPOLOGY_LEVEL_SOCKET, 410 level + 1); 411 num_threads_next_level = num_threads_by_topo_level(topo_info, 412 next_level); 413 offset_next_level = apicid_offset_by_topo_level(topo_info, 414 next_level); 415 } 416 417 *eax = offset_next_level; 418 /* The count (bits 15-00) doesn't need to be reliable. */ 419 *ebx = num_threads_next_level & 0xffff; 420 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 421 *edx = cpu->apic_id; 422 423 assert(!(*eax & ~0x1f)); 424 } 425 426 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 427 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 428 { 429 assert(cache->size % 1024 == 0); 430 assert(cache->lines_per_tag > 0); 431 assert(cache->associativity > 0); 432 assert(cache->line_size > 0); 433 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 434 (cache->lines_per_tag << 8) | (cache->line_size); 435 } 436 437 #define ASSOC_FULL 0xFF 438 439 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 440 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 441 a == 2 ? 0x2 : \ 442 a == 4 ? 0x4 : \ 443 a == 8 ? 0x6 : \ 444 a == 16 ? 0x8 : \ 445 a == 32 ? 0xA : \ 446 a == 48 ? 0xB : \ 447 a == 64 ? 0xC : \ 448 a == 96 ? 0xD : \ 449 a == 128 ? 0xE : \ 450 a == ASSOC_FULL ? 0xF : \ 451 0 /* invalid value */) 452 453 /* 454 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 455 * @l3 can be NULL. 456 */ 457 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 458 CPUCacheInfo *l3, 459 uint32_t *ecx, uint32_t *edx) 460 { 461 assert(l2->size % 1024 == 0); 462 assert(l2->associativity > 0); 463 assert(l2->lines_per_tag > 0); 464 assert(l2->line_size > 0); 465 *ecx = ((l2->size / 1024) << 16) | 466 (AMD_ENC_ASSOC(l2->associativity) << 12) | 467 (l2->lines_per_tag << 8) | (l2->line_size); 468 469 if (l3) { 470 assert(l3->size % (512 * 1024) == 0); 471 assert(l3->associativity > 0); 472 assert(l3->lines_per_tag > 0); 473 assert(l3->line_size > 0); 474 *edx = ((l3->size / (512 * 1024)) << 18) | 475 (AMD_ENC_ASSOC(l3->associativity) << 12) | 476 (l3->lines_per_tag << 8) | (l3->line_size); 477 } else { 478 *edx = 0; 479 } 480 } 481 482 /* Encode cache info for CPUID[8000001D] */ 483 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 484 X86CPUTopoInfo *topo_info, 485 uint32_t *eax, uint32_t *ebx, 486 uint32_t *ecx, uint32_t *edx) 487 { 488 assert(cache->size == cache->line_size * cache->associativity * 489 cache->partitions * cache->sets); 490 491 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 492 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 493 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 494 495 assert(cache->line_size > 0); 496 assert(cache->partitions > 0); 497 assert(cache->associativity > 0); 498 /* We don't implement fully-associative caches */ 499 assert(cache->associativity < cache->sets); 500 *ebx = (cache->line_size - 1) | 501 ((cache->partitions - 1) << 12) | 502 ((cache->associativity - 1) << 22); 503 504 assert(cache->sets > 0); 505 *ecx = cache->sets - 1; 506 507 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 508 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 509 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 510 } 511 512 /* Encode cache info for CPUID[8000001E] */ 513 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 514 uint32_t *eax, uint32_t *ebx, 515 uint32_t *ecx, uint32_t *edx) 516 { 517 X86CPUTopoIDs topo_ids; 518 519 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 520 521 *eax = cpu->apic_id; 522 523 /* 524 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 525 * Read-only. Reset: 0000_XXXXh. 526 * See Core::X86::Cpuid::ExtApicId. 527 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 528 * Bits Description 529 * 31:16 Reserved. 530 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 531 * The number of threads per core is ThreadsPerCore+1. 532 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 533 * 534 * NOTE: CoreId is already part of apic_id. Just use it. We can 535 * use all the 8 bits to represent the core_id here. 536 */ 537 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 538 539 /* 540 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 541 * Read-only. Reset: 0000_0XXXh. 542 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 543 * Bits Description 544 * 31:11 Reserved. 545 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 546 * ValidValues: 547 * Value Description 548 * 0h 1 node per processor. 549 * 7h-1h Reserved. 550 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 551 * 552 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 553 * But users can create more nodes than the actual hardware can 554 * support. To genaralize we can use all the upper 8 bits for nodes. 555 * NodeId is combination of node and socket_id which is already decoded 556 * in apic_id. Just use it by shifting. 557 */ 558 if (cpu->legacy_multi_node) { 559 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 560 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 561 } else { 562 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 563 } 564 565 *edx = 0; 566 } 567 568 /* 569 * Definitions of the hardcoded cache entries we expose: 570 * These are legacy cache values. If there is a need to change any 571 * of these values please use builtin_x86_defs 572 */ 573 574 /* L1 data cache: */ 575 static CPUCacheInfo legacy_l1d_cache = { 576 .type = DATA_CACHE, 577 .level = 1, 578 .size = 32 * KiB, 579 .self_init = 1, 580 .line_size = 64, 581 .associativity = 8, 582 .sets = 64, 583 .partitions = 1, 584 .no_invd_sharing = true, 585 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 586 }; 587 588 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 589 static CPUCacheInfo legacy_l1d_cache_amd = { 590 .type = DATA_CACHE, 591 .level = 1, 592 .size = 64 * KiB, 593 .self_init = 1, 594 .line_size = 64, 595 .associativity = 2, 596 .sets = 512, 597 .partitions = 1, 598 .lines_per_tag = 1, 599 .no_invd_sharing = true, 600 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 601 }; 602 603 /* L1 instruction cache: */ 604 static CPUCacheInfo legacy_l1i_cache = { 605 .type = INSTRUCTION_CACHE, 606 .level = 1, 607 .size = 32 * KiB, 608 .self_init = 1, 609 .line_size = 64, 610 .associativity = 8, 611 .sets = 64, 612 .partitions = 1, 613 .no_invd_sharing = true, 614 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 615 }; 616 617 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 618 static CPUCacheInfo legacy_l1i_cache_amd = { 619 .type = INSTRUCTION_CACHE, 620 .level = 1, 621 .size = 64 * KiB, 622 .self_init = 1, 623 .line_size = 64, 624 .associativity = 2, 625 .sets = 512, 626 .partitions = 1, 627 .lines_per_tag = 1, 628 .no_invd_sharing = true, 629 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 630 }; 631 632 /* Level 2 unified cache: */ 633 static CPUCacheInfo legacy_l2_cache = { 634 .type = UNIFIED_CACHE, 635 .level = 2, 636 .size = 4 * MiB, 637 .self_init = 1, 638 .line_size = 64, 639 .associativity = 16, 640 .sets = 4096, 641 .partitions = 1, 642 .no_invd_sharing = true, 643 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 644 }; 645 646 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 647 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 648 .type = UNIFIED_CACHE, 649 .level = 2, 650 .size = 2 * MiB, 651 .line_size = 64, 652 .associativity = 8, 653 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 654 }; 655 656 657 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 658 static CPUCacheInfo legacy_l2_cache_amd = { 659 .type = UNIFIED_CACHE, 660 .level = 2, 661 .size = 512 * KiB, 662 .line_size = 64, 663 .lines_per_tag = 1, 664 .associativity = 16, 665 .sets = 512, 666 .partitions = 1, 667 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 668 }; 669 670 /* Level 3 unified cache: */ 671 static CPUCacheInfo legacy_l3_cache = { 672 .type = UNIFIED_CACHE, 673 .level = 3, 674 .size = 16 * MiB, 675 .line_size = 64, 676 .associativity = 16, 677 .sets = 16384, 678 .partitions = 1, 679 .lines_per_tag = 1, 680 .self_init = true, 681 .inclusive = true, 682 .complex_indexing = true, 683 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 684 }; 685 686 /* TLB definitions: */ 687 688 #define L1_DTLB_2M_ASSOC 1 689 #define L1_DTLB_2M_ENTRIES 255 690 #define L1_DTLB_4K_ASSOC 1 691 #define L1_DTLB_4K_ENTRIES 255 692 693 #define L1_ITLB_2M_ASSOC 1 694 #define L1_ITLB_2M_ENTRIES 255 695 #define L1_ITLB_4K_ASSOC 1 696 #define L1_ITLB_4K_ENTRIES 255 697 698 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 699 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 700 #define L2_DTLB_4K_ASSOC 4 701 #define L2_DTLB_4K_ENTRIES 512 702 703 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 704 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 705 #define L2_ITLB_4K_ASSOC 4 706 #define L2_ITLB_4K_ENTRIES 512 707 708 /* CPUID Leaf 0x14 constants: */ 709 #define INTEL_PT_MAX_SUBLEAF 0x1 710 /* 711 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 712 * MSR can be accessed; 713 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 714 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 715 * of Intel PT MSRs across warm reset; 716 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 717 */ 718 #define INTEL_PT_MINIMAL_EBX 0xf 719 /* 720 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 721 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 722 * accessed; 723 * bit[01]: ToPA tables can hold any number of output entries, up to the 724 * maximum allowed by the MaskOrTableOffset field of 725 * IA32_RTIT_OUTPUT_MASK_PTRS; 726 * bit[02]: Support Single-Range Output scheme; 727 */ 728 #define INTEL_PT_MINIMAL_ECX 0x7 729 /* generated packets which contain IP payloads have LIP values */ 730 #define INTEL_PT_IP_LIP (1 << 31) 731 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 732 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 733 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 734 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 735 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 736 737 /* CPUID Leaf 0x1D constants: */ 738 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 739 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 740 #define INTEL_AMX_BYTES_PER_TILE 0x400 741 #define INTEL_AMX_BYTES_PER_ROW 0x40 742 #define INTEL_AMX_TILE_MAX_NAMES 0x8 743 #define INTEL_AMX_TILE_MAX_ROWS 0x10 744 745 /* CPUID Leaf 0x1E constants: */ 746 #define INTEL_AMX_TMUL_MAX_K 0x10 747 #define INTEL_AMX_TMUL_MAX_N 0x40 748 749 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 750 uint32_t vendor2, uint32_t vendor3) 751 { 752 int i; 753 for (i = 0; i < 4; i++) { 754 dst[i] = vendor1 >> (8 * i); 755 dst[i + 4] = vendor2 >> (8 * i); 756 dst[i + 8] = vendor3 >> (8 * i); 757 } 758 dst[CPUID_VENDOR_SZ] = '\0'; 759 } 760 761 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 762 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 763 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 764 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 765 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 766 CPUID_PSE36 | CPUID_FXSR) 767 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 768 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 769 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 770 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 771 CPUID_PAE | CPUID_SEP | CPUID_APIC) 772 773 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 774 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 775 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 776 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 777 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 778 /* partly implemented: 779 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 780 /* missing: 781 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 782 783 /* 784 * Kernel-only features that can be shown to usermode programs even if 785 * they aren't actually supported by TCG, because qemu-user only runs 786 * in CPL=3; remove them if they are ever implemented for system emulation. 787 */ 788 #if defined CONFIG_USER_ONLY 789 #define CPUID_EXT_KERNEL_FEATURES \ 790 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 791 #else 792 #define CPUID_EXT_KERNEL_FEATURES 0 793 #endif 794 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 795 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 796 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 797 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 798 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 799 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 800 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 801 /* missing: 802 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 803 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 804 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 805 CPUID_EXT_TSC_DEADLINE_TIMER 806 */ 807 808 #ifdef TARGET_X86_64 809 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 810 #else 811 #define TCG_EXT2_X86_64_FEATURES 0 812 #endif 813 814 /* 815 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 816 * in usermode or by 32-bit programs. Those are added to supported 817 * TCG features unconditionally in user-mode emulation mode. This may 818 * indeed seem strange or incorrect, but it works because code running 819 * under usermode emulation cannot access them. 820 * 821 * Even for long mode, qemu-i386 is not running "a userspace program on a 822 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 823 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 824 * but again the difference is only visible in kernel mode. 825 */ 826 #if defined CONFIG_LINUX_USER 827 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 828 #elif defined CONFIG_USER_ONLY 829 /* FIXME: Long mode not yet supported for i386 bsd-user */ 830 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 831 #else 832 #define CPUID_EXT2_KERNEL_FEATURES 0 833 #endif 834 835 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 836 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 837 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 838 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 839 CPUID_EXT2_KERNEL_FEATURES) 840 841 #if defined CONFIG_USER_ONLY 842 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 843 #else 844 #define CPUID_EXT3_KERNEL_FEATURES 0 845 #endif 846 847 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 848 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 849 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 850 851 #define TCG_EXT4_FEATURES 0 852 853 #if defined CONFIG_USER_ONLY 854 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 855 #else 856 #define CPUID_SVM_KERNEL_FEATURES 0 857 #endif 858 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 859 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 860 861 #define TCG_KVM_FEATURES 0 862 863 #if defined CONFIG_USER_ONLY 864 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 865 #else 866 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 867 #endif 868 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 869 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 870 CPUID_7_0_EBX_CLFLUSHOPT | \ 871 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 872 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 873 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 874 /* missing: 875 CPUID_7_0_EBX_HLE 876 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 877 878 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 879 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 880 #else 881 #define TCG_7_0_ECX_RDPID 0 882 #endif 883 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 884 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 885 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 886 TCG_7_0_ECX_RDPID) 887 888 #if defined CONFIG_USER_ONLY 889 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 890 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 891 #else 892 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 893 #endif 894 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 895 896 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 897 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 898 #define TCG_7_1_EDX_FEATURES 0 899 #define TCG_7_2_EDX_FEATURES 0 900 #define TCG_APM_FEATURES 0 901 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 902 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 903 /* missing: 904 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 905 #define TCG_14_0_ECX_FEATURES 0 906 #define TCG_SGX_12_0_EAX_FEATURES 0 907 #define TCG_SGX_12_0_EBX_FEATURES 0 908 #define TCG_SGX_12_1_EAX_FEATURES 0 909 #define TCG_24_0_EBX_FEATURES 0 910 911 #if defined CONFIG_USER_ONLY 912 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 913 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 914 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 915 CPUID_8000_0008_EBX_AMD_PSFD) 916 #else 917 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 918 #endif 919 920 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 921 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 922 923 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 924 [FEAT_1_EDX] = { 925 .type = CPUID_FEATURE_WORD, 926 .feat_names = { 927 "fpu", "vme", "de", "pse", 928 "tsc", "msr", "pae", "mce", 929 "cx8", "apic", NULL, "sep", 930 "mtrr", "pge", "mca", "cmov", 931 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 932 NULL, "ds" /* Intel dts */, "acpi", "mmx", 933 "fxsr", "sse", "sse2", "ss", 934 "ht" /* Intel htt */, "tm", "ia64", "pbe", 935 }, 936 .cpuid = {.eax = 1, .reg = R_EDX, }, 937 .tcg_features = TCG_FEATURES, 938 .no_autoenable_flags = CPUID_HT, 939 }, 940 [FEAT_1_ECX] = { 941 .type = CPUID_FEATURE_WORD, 942 .feat_names = { 943 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 944 "ds-cpl", "vmx", "smx", "est", 945 "tm2", "ssse3", "cid", NULL, 946 "fma", "cx16", "xtpr", "pdcm", 947 NULL, "pcid", "dca", "sse4.1", 948 "sse4.2", "x2apic", "movbe", "popcnt", 949 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 950 "avx", "f16c", "rdrand", "hypervisor", 951 }, 952 .cpuid = { .eax = 1, .reg = R_ECX, }, 953 .tcg_features = TCG_EXT_FEATURES, 954 }, 955 /* Feature names that are already defined on feature_name[] but 956 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 957 * names on feat_names below. They are copied automatically 958 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 959 */ 960 [FEAT_8000_0001_EDX] = { 961 .type = CPUID_FEATURE_WORD, 962 .feat_names = { 963 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 964 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 965 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 966 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 967 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 968 "nx", NULL, "mmxext", NULL /* mmx */, 969 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 970 NULL, "lm", "3dnowext", "3dnow", 971 }, 972 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 973 .tcg_features = TCG_EXT2_FEATURES, 974 }, 975 [FEAT_8000_0001_ECX] = { 976 .type = CPUID_FEATURE_WORD, 977 .feat_names = { 978 "lahf-lm", "cmp-legacy", "svm", "extapic", 979 "cr8legacy", "abm", "sse4a", "misalignsse", 980 "3dnowprefetch", "osvw", "ibs", "xop", 981 "skinit", "wdt", NULL, "lwp", 982 "fma4", "tce", NULL, "nodeid-msr", 983 NULL, "tbm", "topoext", "perfctr-core", 984 "perfctr-nb", NULL, NULL, NULL, 985 NULL, NULL, NULL, NULL, 986 }, 987 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 988 .tcg_features = TCG_EXT3_FEATURES, 989 /* 990 * TOPOEXT is always allowed but can't be enabled blindly by 991 * "-cpu host", as it requires consistent cache topology info 992 * to be provided so it doesn't confuse guests. 993 */ 994 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 995 }, 996 [FEAT_C000_0001_EDX] = { 997 .type = CPUID_FEATURE_WORD, 998 .feat_names = { 999 NULL, NULL, "xstore", "xstore-en", 1000 NULL, NULL, "xcrypt", "xcrypt-en", 1001 "ace2", "ace2-en", "phe", "phe-en", 1002 "pmm", "pmm-en", NULL, NULL, 1003 NULL, NULL, NULL, NULL, 1004 NULL, NULL, NULL, NULL, 1005 NULL, NULL, NULL, NULL, 1006 NULL, NULL, NULL, NULL, 1007 }, 1008 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1009 .tcg_features = TCG_EXT4_FEATURES, 1010 }, 1011 [FEAT_KVM] = { 1012 .type = CPUID_FEATURE_WORD, 1013 .feat_names = { 1014 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1015 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1016 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1017 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1018 NULL, NULL, NULL, NULL, 1019 NULL, NULL, NULL, NULL, 1020 "kvmclock-stable-bit", NULL, NULL, NULL, 1021 NULL, NULL, NULL, NULL, 1022 }, 1023 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1024 .tcg_features = TCG_KVM_FEATURES, 1025 }, 1026 [FEAT_KVM_HINTS] = { 1027 .type = CPUID_FEATURE_WORD, 1028 .feat_names = { 1029 "kvm-hint-dedicated", NULL, NULL, NULL, 1030 NULL, NULL, NULL, NULL, 1031 NULL, NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 NULL, NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 NULL, NULL, NULL, NULL, 1036 NULL, NULL, NULL, NULL, 1037 }, 1038 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1039 .tcg_features = TCG_KVM_FEATURES, 1040 /* 1041 * KVM hints aren't auto-enabled by -cpu host, they need to be 1042 * explicitly enabled in the command-line. 1043 */ 1044 .no_autoenable_flags = ~0U, 1045 }, 1046 [FEAT_SVM] = { 1047 .type = CPUID_FEATURE_WORD, 1048 .feat_names = { 1049 "npt", "lbrv", "svm-lock", "nrip-save", 1050 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1051 NULL, NULL, "pause-filter", NULL, 1052 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1053 "vgif", NULL, NULL, NULL, 1054 NULL, NULL, NULL, NULL, 1055 NULL, "vnmi", NULL, NULL, 1056 "svme-addr-chk", NULL, NULL, NULL, 1057 }, 1058 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1059 .tcg_features = TCG_SVM_FEATURES, 1060 }, 1061 [FEAT_7_0_EBX] = { 1062 .type = CPUID_FEATURE_WORD, 1063 .feat_names = { 1064 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1065 "hle", "avx2", "fdp-excptn-only", "smep", 1066 "bmi2", "erms", "invpcid", "rtm", 1067 NULL, "zero-fcs-fds", "mpx", NULL, 1068 "avx512f", "avx512dq", "rdseed", "adx", 1069 "smap", "avx512ifma", "pcommit", "clflushopt", 1070 "clwb", "intel-pt", "avx512pf", "avx512er", 1071 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1072 }, 1073 .cpuid = { 1074 .eax = 7, 1075 .needs_ecx = true, .ecx = 0, 1076 .reg = R_EBX, 1077 }, 1078 .tcg_features = TCG_7_0_EBX_FEATURES, 1079 }, 1080 [FEAT_7_0_ECX] = { 1081 .type = CPUID_FEATURE_WORD, 1082 .feat_names = { 1083 NULL, "avx512vbmi", "umip", "pku", 1084 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1085 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1086 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1087 "la57", NULL, NULL, NULL, 1088 NULL, NULL, "rdpid", NULL, 1089 "bus-lock-detect", "cldemote", NULL, "movdiri", 1090 "movdir64b", NULL, "sgxlc", "pks", 1091 }, 1092 .cpuid = { 1093 .eax = 7, 1094 .needs_ecx = true, .ecx = 0, 1095 .reg = R_ECX, 1096 }, 1097 .tcg_features = TCG_7_0_ECX_FEATURES, 1098 }, 1099 [FEAT_7_0_EDX] = { 1100 .type = CPUID_FEATURE_WORD, 1101 .feat_names = { 1102 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1103 "fsrm", NULL, NULL, NULL, 1104 "avx512-vp2intersect", NULL, "md-clear", NULL, 1105 NULL, NULL, "serialize", NULL, 1106 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1107 NULL, NULL, "amx-bf16", "avx512-fp16", 1108 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1109 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1110 }, 1111 .cpuid = { 1112 .eax = 7, 1113 .needs_ecx = true, .ecx = 0, 1114 .reg = R_EDX, 1115 }, 1116 .tcg_features = TCG_7_0_EDX_FEATURES, 1117 }, 1118 [FEAT_7_1_EAX] = { 1119 .type = CPUID_FEATURE_WORD, 1120 .feat_names = { 1121 "sha512", "sm3", "sm4", NULL, 1122 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1123 NULL, NULL, "fzrm", "fsrs", 1124 "fsrc", NULL, NULL, NULL, 1125 NULL, "fred", "lkgs", "wrmsrns", 1126 NULL, "amx-fp16", NULL, "avx-ifma", 1127 NULL, NULL, "lam", NULL, 1128 NULL, NULL, NULL, NULL, 1129 }, 1130 .cpuid = { 1131 .eax = 7, 1132 .needs_ecx = true, .ecx = 1, 1133 .reg = R_EAX, 1134 }, 1135 .tcg_features = TCG_7_1_EAX_FEATURES, 1136 }, 1137 [FEAT_7_1_EDX] = { 1138 .type = CPUID_FEATURE_WORD, 1139 .feat_names = { 1140 NULL, NULL, NULL, NULL, 1141 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1142 "amx-complex", NULL, "avx-vnni-int16", NULL, 1143 NULL, NULL, "prefetchiti", NULL, 1144 NULL, NULL, NULL, "avx10", 1145 NULL, NULL, NULL, NULL, 1146 NULL, NULL, NULL, NULL, 1147 NULL, NULL, NULL, NULL, 1148 }, 1149 .cpuid = { 1150 .eax = 7, 1151 .needs_ecx = true, .ecx = 1, 1152 .reg = R_EDX, 1153 }, 1154 .tcg_features = TCG_7_1_EDX_FEATURES, 1155 }, 1156 [FEAT_7_2_EDX] = { 1157 .type = CPUID_FEATURE_WORD, 1158 .feat_names = { 1159 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1160 "bhi-ctrl", "mcdt-no", NULL, NULL, 1161 NULL, NULL, NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 NULL, NULL, NULL, NULL, 1164 NULL, NULL, NULL, NULL, 1165 NULL, NULL, NULL, NULL, 1166 NULL, NULL, NULL, NULL, 1167 }, 1168 .cpuid = { 1169 .eax = 7, 1170 .needs_ecx = true, .ecx = 2, 1171 .reg = R_EDX, 1172 }, 1173 .tcg_features = TCG_7_2_EDX_FEATURES, 1174 }, 1175 [FEAT_24_0_EBX] = { 1176 .type = CPUID_FEATURE_WORD, 1177 .feat_names = { 1178 [16] = "avx10-128", 1179 [17] = "avx10-256", 1180 [18] = "avx10-512", 1181 }, 1182 .cpuid = { 1183 .eax = 0x24, 1184 .needs_ecx = true, .ecx = 0, 1185 .reg = R_EBX, 1186 }, 1187 .tcg_features = TCG_24_0_EBX_FEATURES, 1188 }, 1189 [FEAT_8000_0007_EDX] = { 1190 .type = CPUID_FEATURE_WORD, 1191 .feat_names = { 1192 NULL, NULL, NULL, NULL, 1193 NULL, NULL, NULL, NULL, 1194 "invtsc", NULL, NULL, NULL, 1195 NULL, NULL, NULL, NULL, 1196 NULL, NULL, NULL, NULL, 1197 NULL, NULL, NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 NULL, NULL, NULL, NULL, 1200 }, 1201 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1202 .tcg_features = TCG_APM_FEATURES, 1203 .unmigratable_flags = CPUID_APM_INVTSC, 1204 }, 1205 [FEAT_8000_0007_EBX] = { 1206 .type = CPUID_FEATURE_WORD, 1207 .feat_names = { 1208 "overflow-recov", "succor", NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 NULL, NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 NULL, NULL, NULL, NULL, 1216 }, 1217 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1218 .tcg_features = 0, 1219 .unmigratable_flags = 0, 1220 }, 1221 [FEAT_8000_0008_EBX] = { 1222 .type = CPUID_FEATURE_WORD, 1223 .feat_names = { 1224 "clzero", NULL, "xsaveerptr", NULL, 1225 NULL, NULL, NULL, NULL, 1226 NULL, "wbnoinvd", NULL, NULL, 1227 "ibpb", NULL, "ibrs", "amd-stibp", 1228 NULL, "stibp-always-on", NULL, NULL, 1229 NULL, NULL, NULL, NULL, 1230 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1231 "amd-psfd", NULL, NULL, NULL, 1232 }, 1233 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1234 .tcg_features = TCG_8000_0008_EBX, 1235 .unmigratable_flags = 0, 1236 }, 1237 [FEAT_8000_0021_EAX] = { 1238 .type = CPUID_FEATURE_WORD, 1239 .feat_names = { 1240 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1241 NULL, NULL, "null-sel-clr-base", NULL, 1242 "auto-ibrs", NULL, NULL, NULL, 1243 NULL, NULL, NULL, NULL, 1244 NULL, NULL, NULL, NULL, 1245 NULL, NULL, NULL, NULL, 1246 "eraps", NULL, NULL, "sbpb", 1247 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1248 }, 1249 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1250 .tcg_features = 0, 1251 .unmigratable_flags = 0, 1252 }, 1253 [FEAT_8000_0021_EBX] = { 1254 .type = CPUID_FEATURE_WORD, 1255 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1256 .tcg_features = 0, 1257 .unmigratable_flags = 0, 1258 }, 1259 [FEAT_8000_0022_EAX] = { 1260 .type = CPUID_FEATURE_WORD, 1261 .feat_names = { 1262 "perfmon-v2", NULL, NULL, NULL, 1263 NULL, NULL, NULL, NULL, 1264 NULL, NULL, NULL, NULL, 1265 NULL, NULL, NULL, NULL, 1266 NULL, NULL, NULL, NULL, 1267 NULL, NULL, NULL, NULL, 1268 NULL, NULL, NULL, NULL, 1269 NULL, NULL, NULL, NULL, 1270 }, 1271 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1272 .tcg_features = 0, 1273 .unmigratable_flags = 0, 1274 }, 1275 [FEAT_XSAVE] = { 1276 .type = CPUID_FEATURE_WORD, 1277 .feat_names = { 1278 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1279 "xfd", NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 }, 1287 .cpuid = { 1288 .eax = 0xd, 1289 .needs_ecx = true, .ecx = 1, 1290 .reg = R_EAX, 1291 }, 1292 .tcg_features = TCG_XSAVE_FEATURES, 1293 }, 1294 [FEAT_XSAVE_XSS_LO] = { 1295 .type = CPUID_FEATURE_WORD, 1296 .feat_names = { 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 NULL, NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 NULL, NULL, NULL, NULL, 1302 NULL, NULL, NULL, NULL, 1303 NULL, NULL, NULL, NULL, 1304 NULL, NULL, NULL, NULL, 1305 }, 1306 .cpuid = { 1307 .eax = 0xD, 1308 .needs_ecx = true, 1309 .ecx = 1, 1310 .reg = R_ECX, 1311 }, 1312 }, 1313 [FEAT_XSAVE_XSS_HI] = { 1314 .type = CPUID_FEATURE_WORD, 1315 .cpuid = { 1316 .eax = 0xD, 1317 .needs_ecx = true, 1318 .ecx = 1, 1319 .reg = R_EDX 1320 }, 1321 }, 1322 [FEAT_6_EAX] = { 1323 .type = CPUID_FEATURE_WORD, 1324 .feat_names = { 1325 NULL, NULL, "arat", NULL, 1326 NULL, NULL, NULL, NULL, 1327 NULL, NULL, NULL, NULL, 1328 NULL, NULL, NULL, NULL, 1329 NULL, NULL, NULL, NULL, 1330 NULL, NULL, NULL, NULL, 1331 NULL, NULL, NULL, NULL, 1332 NULL, NULL, NULL, NULL, 1333 }, 1334 .cpuid = { .eax = 6, .reg = R_EAX, }, 1335 .tcg_features = TCG_6_EAX_FEATURES, 1336 }, 1337 [FEAT_XSAVE_XCR0_LO] = { 1338 .type = CPUID_FEATURE_WORD, 1339 .cpuid = { 1340 .eax = 0xD, 1341 .needs_ecx = true, .ecx = 0, 1342 .reg = R_EAX, 1343 }, 1344 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1345 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1346 XSTATE_PKRU_MASK, 1347 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1348 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1349 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1350 XSTATE_PKRU_MASK, 1351 }, 1352 [FEAT_XSAVE_XCR0_HI] = { 1353 .type = CPUID_FEATURE_WORD, 1354 .cpuid = { 1355 .eax = 0xD, 1356 .needs_ecx = true, .ecx = 0, 1357 .reg = R_EDX, 1358 }, 1359 .tcg_features = 0U, 1360 }, 1361 /*Below are MSR exposed features*/ 1362 [FEAT_ARCH_CAPABILITIES] = { 1363 .type = MSR_FEATURE_WORD, 1364 .feat_names = { 1365 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1366 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1367 "taa-no", NULL, NULL, NULL, 1368 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1369 NULL, "fb-clear", NULL, NULL, 1370 "bhi-no", NULL, NULL, NULL, 1371 "pbrsb-no", NULL, "gds-no", "rfds-no", 1372 "rfds-clear", NULL, NULL, NULL, 1373 }, 1374 .msr = { 1375 .index = MSR_IA32_ARCH_CAPABILITIES, 1376 }, 1377 /* 1378 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1379 * cannot be read from user mode. Therefore, it has no impact 1380 > on any user-mode operation, and warnings about unsupported 1381 * features do not matter. 1382 */ 1383 .tcg_features = ~0U, 1384 }, 1385 [FEAT_CORE_CAPABILITY] = { 1386 .type = MSR_FEATURE_WORD, 1387 .feat_names = { 1388 NULL, NULL, NULL, NULL, 1389 NULL, "split-lock-detect", NULL, NULL, 1390 NULL, NULL, NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 NULL, NULL, NULL, NULL, 1395 NULL, NULL, NULL, NULL, 1396 }, 1397 .msr = { 1398 .index = MSR_IA32_CORE_CAPABILITY, 1399 }, 1400 }, 1401 [FEAT_PERF_CAPABILITIES] = { 1402 .type = MSR_FEATURE_WORD, 1403 .feat_names = { 1404 NULL, NULL, NULL, NULL, 1405 NULL, NULL, NULL, NULL, 1406 NULL, NULL, NULL, NULL, 1407 NULL, "full-width-write", NULL, NULL, 1408 NULL, NULL, NULL, NULL, 1409 NULL, NULL, NULL, NULL, 1410 NULL, NULL, NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 }, 1413 .msr = { 1414 .index = MSR_IA32_PERF_CAPABILITIES, 1415 }, 1416 }, 1417 1418 [FEAT_VMX_PROCBASED_CTLS] = { 1419 .type = MSR_FEATURE_WORD, 1420 .feat_names = { 1421 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1422 NULL, NULL, NULL, "vmx-hlt-exit", 1423 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1424 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1425 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1426 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1427 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1428 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1429 }, 1430 .msr = { 1431 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1432 } 1433 }, 1434 1435 [FEAT_VMX_SECONDARY_CTLS] = { 1436 .type = MSR_FEATURE_WORD, 1437 .feat_names = { 1438 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1439 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1440 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1441 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1442 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1443 "vmx-xsaves", NULL, NULL, NULL, 1444 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1445 NULL, NULL, NULL, NULL, 1446 }, 1447 .msr = { 1448 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1449 } 1450 }, 1451 1452 [FEAT_VMX_PINBASED_CTLS] = { 1453 .type = MSR_FEATURE_WORD, 1454 .feat_names = { 1455 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1456 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1457 NULL, NULL, NULL, NULL, 1458 NULL, NULL, NULL, NULL, 1459 NULL, NULL, NULL, NULL, 1460 NULL, NULL, NULL, NULL, 1461 NULL, NULL, NULL, NULL, 1462 NULL, NULL, NULL, NULL, 1463 }, 1464 .msr = { 1465 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1466 } 1467 }, 1468 1469 [FEAT_VMX_EXIT_CTLS] = { 1470 .type = MSR_FEATURE_WORD, 1471 /* 1472 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1473 * the LM CPUID bit. 1474 */ 1475 .feat_names = { 1476 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1477 NULL, NULL, NULL, NULL, 1478 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1479 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1480 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1481 "vmx-exit-save-efer", "vmx-exit-load-efer", 1482 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1483 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1484 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1485 }, 1486 .msr = { 1487 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1488 } 1489 }, 1490 1491 [FEAT_VMX_ENTRY_CTLS] = { 1492 .type = MSR_FEATURE_WORD, 1493 .feat_names = { 1494 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1495 NULL, NULL, NULL, NULL, 1496 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1497 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1498 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1499 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1500 NULL, NULL, NULL, NULL, 1501 NULL, NULL, NULL, NULL, 1502 }, 1503 .msr = { 1504 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1505 } 1506 }, 1507 1508 [FEAT_VMX_MISC] = { 1509 .type = MSR_FEATURE_WORD, 1510 .feat_names = { 1511 NULL, NULL, NULL, NULL, 1512 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1513 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1514 NULL, NULL, NULL, NULL, 1515 NULL, NULL, NULL, NULL, 1516 NULL, NULL, NULL, NULL, 1517 NULL, NULL, NULL, NULL, 1518 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1519 }, 1520 .msr = { 1521 .index = MSR_IA32_VMX_MISC, 1522 } 1523 }, 1524 1525 [FEAT_VMX_EPT_VPID_CAPS] = { 1526 .type = MSR_FEATURE_WORD, 1527 .feat_names = { 1528 "vmx-ept-execonly", NULL, NULL, NULL, 1529 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1530 NULL, NULL, NULL, NULL, 1531 NULL, NULL, NULL, NULL, 1532 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1533 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1534 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1535 NULL, NULL, NULL, NULL, 1536 "vmx-invvpid", NULL, NULL, NULL, 1537 NULL, NULL, NULL, NULL, 1538 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1539 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1540 NULL, NULL, NULL, NULL, 1541 NULL, NULL, NULL, NULL, 1542 NULL, NULL, NULL, NULL, 1543 NULL, NULL, NULL, NULL, 1544 NULL, NULL, NULL, NULL, 1545 }, 1546 .msr = { 1547 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1548 } 1549 }, 1550 1551 [FEAT_VMX_BASIC] = { 1552 .type = MSR_FEATURE_WORD, 1553 .feat_names = { 1554 [54] = "vmx-ins-outs", 1555 [55] = "vmx-true-ctls", 1556 [56] = "vmx-any-errcode", 1557 [58] = "vmx-nested-exception", 1558 }, 1559 .msr = { 1560 .index = MSR_IA32_VMX_BASIC, 1561 }, 1562 /* Just to be safe - we don't support setting the MSEG version field. */ 1563 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1564 }, 1565 1566 [FEAT_VMX_VMFUNC] = { 1567 .type = MSR_FEATURE_WORD, 1568 .feat_names = { 1569 [0] = "vmx-eptp-switching", 1570 }, 1571 .msr = { 1572 .index = MSR_IA32_VMX_VMFUNC, 1573 } 1574 }, 1575 1576 [FEAT_14_0_ECX] = { 1577 .type = CPUID_FEATURE_WORD, 1578 .feat_names = { 1579 NULL, NULL, NULL, NULL, 1580 NULL, NULL, NULL, NULL, 1581 NULL, NULL, NULL, NULL, 1582 NULL, NULL, NULL, NULL, 1583 NULL, NULL, NULL, NULL, 1584 NULL, NULL, NULL, NULL, 1585 NULL, NULL, NULL, NULL, 1586 NULL, NULL, NULL, "intel-pt-lip", 1587 }, 1588 .cpuid = { 1589 .eax = 0x14, 1590 .needs_ecx = true, .ecx = 0, 1591 .reg = R_ECX, 1592 }, 1593 .tcg_features = TCG_14_0_ECX_FEATURES, 1594 }, 1595 1596 [FEAT_SGX_12_0_EAX] = { 1597 .type = CPUID_FEATURE_WORD, 1598 .feat_names = { 1599 "sgx1", "sgx2", NULL, NULL, 1600 NULL, NULL, NULL, NULL, 1601 NULL, NULL, NULL, "sgx-edeccssa", 1602 NULL, NULL, NULL, NULL, 1603 NULL, NULL, NULL, NULL, 1604 NULL, NULL, NULL, NULL, 1605 NULL, NULL, NULL, NULL, 1606 NULL, NULL, NULL, NULL, 1607 }, 1608 .cpuid = { 1609 .eax = 0x12, 1610 .needs_ecx = true, .ecx = 0, 1611 .reg = R_EAX, 1612 }, 1613 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1614 }, 1615 1616 [FEAT_SGX_12_0_EBX] = { 1617 .type = CPUID_FEATURE_WORD, 1618 .feat_names = { 1619 "sgx-exinfo" , NULL, NULL, NULL, 1620 NULL, NULL, NULL, NULL, 1621 NULL, NULL, NULL, NULL, 1622 NULL, NULL, NULL, NULL, 1623 NULL, NULL, NULL, NULL, 1624 NULL, NULL, NULL, NULL, 1625 NULL, NULL, NULL, NULL, 1626 NULL, NULL, NULL, NULL, 1627 }, 1628 .cpuid = { 1629 .eax = 0x12, 1630 .needs_ecx = true, .ecx = 0, 1631 .reg = R_EBX, 1632 }, 1633 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1634 }, 1635 1636 [FEAT_SGX_12_1_EAX] = { 1637 .type = CPUID_FEATURE_WORD, 1638 .feat_names = { 1639 NULL, "sgx-debug", "sgx-mode64", NULL, 1640 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1641 NULL, NULL, "sgx-aex-notify", NULL, 1642 NULL, NULL, NULL, NULL, 1643 NULL, NULL, NULL, NULL, 1644 NULL, NULL, NULL, NULL, 1645 NULL, NULL, NULL, NULL, 1646 NULL, NULL, NULL, NULL, 1647 }, 1648 .cpuid = { 1649 .eax = 0x12, 1650 .needs_ecx = true, .ecx = 1, 1651 .reg = R_EAX, 1652 }, 1653 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1654 }, 1655 }; 1656 1657 typedef struct FeatureMask { 1658 FeatureWord index; 1659 uint64_t mask; 1660 } FeatureMask; 1661 1662 typedef struct FeatureDep { 1663 FeatureMask from, to; 1664 } FeatureDep; 1665 1666 static FeatureDep feature_dependencies[] = { 1667 { 1668 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1669 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1670 }, 1671 { 1672 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1673 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1674 }, 1675 { 1676 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1677 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1678 }, 1679 { 1680 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1681 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1682 }, 1683 { 1684 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1685 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1686 }, 1687 { 1688 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1689 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1690 }, 1691 { 1692 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1693 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1694 }, 1695 { 1696 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1697 .to = { FEAT_VMX_MISC, ~0ull }, 1698 }, 1699 { 1700 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1701 .to = { FEAT_VMX_BASIC, ~0ull }, 1702 }, 1703 { 1704 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1705 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1706 }, 1707 { 1708 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1709 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1710 }, 1711 { 1712 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1713 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1714 }, 1715 { 1716 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1717 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1718 }, 1719 { 1720 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1721 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1722 }, 1723 { 1724 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1725 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1726 }, 1727 { 1728 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1729 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1730 }, 1731 { 1732 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1733 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1734 }, 1735 { 1736 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1737 .to = { FEAT_14_0_ECX, ~0ull }, 1738 }, 1739 { 1740 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1741 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1742 }, 1743 { 1744 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1745 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1746 }, 1747 { 1748 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1749 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1750 }, 1751 { 1752 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1753 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1754 }, 1755 { 1756 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1757 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1758 }, 1759 { 1760 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1761 .to = { FEAT_SVM, ~0ull }, 1762 }, 1763 { 1764 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1765 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1766 }, 1767 { 1768 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1769 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1770 }, 1771 { 1772 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1773 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1774 }, 1775 { 1776 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1777 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1778 }, 1779 { 1780 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1781 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1782 }, 1783 { 1784 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1785 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1786 }, 1787 { 1788 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1789 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1790 }, 1791 { 1792 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1793 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1794 }, 1795 { 1796 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1797 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1798 }, 1799 { 1800 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1801 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1802 }, 1803 { 1804 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1805 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1806 }, 1807 { 1808 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1809 .to = { FEAT_24_0_EBX, ~0ull }, 1810 }, 1811 }; 1812 1813 typedef struct X86RegisterInfo32 { 1814 /* Name of register */ 1815 const char *name; 1816 /* QAPI enum value register */ 1817 X86CPURegister32 qapi_enum; 1818 } X86RegisterInfo32; 1819 1820 #define REGISTER(reg) \ 1821 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1822 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1823 REGISTER(EAX), 1824 REGISTER(ECX), 1825 REGISTER(EDX), 1826 REGISTER(EBX), 1827 REGISTER(ESP), 1828 REGISTER(EBP), 1829 REGISTER(ESI), 1830 REGISTER(EDI), 1831 }; 1832 #undef REGISTER 1833 1834 /* CPUID feature bits available in XSS */ 1835 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1836 1837 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1838 [XSTATE_FP_BIT] = { 1839 /* x87 FP state component is always enabled if XSAVE is supported */ 1840 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1841 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1842 }, 1843 [XSTATE_SSE_BIT] = { 1844 /* SSE state component is always enabled if XSAVE is supported */ 1845 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1846 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1847 }, 1848 [XSTATE_YMM_BIT] = 1849 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1850 .size = sizeof(XSaveAVX) }, 1851 [XSTATE_BNDREGS_BIT] = 1852 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1853 .size = sizeof(XSaveBNDREG) }, 1854 [XSTATE_BNDCSR_BIT] = 1855 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1856 .size = sizeof(XSaveBNDCSR) }, 1857 [XSTATE_OPMASK_BIT] = 1858 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1859 .size = sizeof(XSaveOpmask) }, 1860 [XSTATE_ZMM_Hi256_BIT] = 1861 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1862 .size = sizeof(XSaveZMM_Hi256) }, 1863 [XSTATE_Hi16_ZMM_BIT] = 1864 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1865 .size = sizeof(XSaveHi16_ZMM) }, 1866 [XSTATE_PKRU_BIT] = 1867 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1868 .size = sizeof(XSavePKRU) }, 1869 [XSTATE_ARCH_LBR_BIT] = { 1870 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1871 .offset = 0 /*supervisor mode component, offset = 0 */, 1872 .size = sizeof(XSavesArchLBR) }, 1873 [XSTATE_XTILE_CFG_BIT] = { 1874 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1875 .size = sizeof(XSaveXTILECFG), 1876 }, 1877 [XSTATE_XTILE_DATA_BIT] = { 1878 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1879 .size = sizeof(XSaveXTILEDATA) 1880 }, 1881 }; 1882 1883 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1884 { 1885 uint64_t ret = x86_ext_save_areas[0].size; 1886 const ExtSaveArea *esa; 1887 uint32_t offset = 0; 1888 int i; 1889 1890 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1891 esa = &x86_ext_save_areas[i]; 1892 if ((mask >> i) & 1) { 1893 offset = compacted ? ret : esa->offset; 1894 ret = MAX(ret, offset + esa->size); 1895 } 1896 } 1897 return ret; 1898 } 1899 1900 static inline bool accel_uses_host_cpuid(void) 1901 { 1902 return kvm_enabled() || hvf_enabled(); 1903 } 1904 1905 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1906 { 1907 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1908 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1909 } 1910 1911 /* Return name of 32-bit register, from a R_* constant */ 1912 static const char *get_register_name_32(unsigned int reg) 1913 { 1914 if (reg >= CPU_NB_REGS32) { 1915 return NULL; 1916 } 1917 return x86_reg_info_32[reg].name; 1918 } 1919 1920 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1921 { 1922 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1923 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1924 } 1925 1926 /* 1927 * Returns the set of feature flags that are supported and migratable by 1928 * QEMU, for a given FeatureWord. 1929 */ 1930 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1931 { 1932 FeatureWordInfo *wi = &feature_word_info[w]; 1933 CPUX86State *env = &cpu->env; 1934 uint64_t r = 0; 1935 int i; 1936 1937 for (i = 0; i < 64; i++) { 1938 uint64_t f = 1ULL << i; 1939 1940 /* If the feature name is known, it is implicitly considered migratable, 1941 * unless it is explicitly set in unmigratable_flags */ 1942 if ((wi->migratable_flags & f) || 1943 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1944 r |= f; 1945 } 1946 } 1947 1948 /* when tsc-khz is set explicitly, invtsc is migratable */ 1949 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1950 r |= CPUID_APM_INVTSC; 1951 } 1952 1953 return r; 1954 } 1955 1956 void host_cpuid(uint32_t function, uint32_t count, 1957 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1958 { 1959 uint32_t vec[4]; 1960 1961 #ifdef __x86_64__ 1962 asm volatile("cpuid" 1963 : "=a"(vec[0]), "=b"(vec[1]), 1964 "=c"(vec[2]), "=d"(vec[3]) 1965 : "0"(function), "c"(count) : "cc"); 1966 #elif defined(__i386__) 1967 asm volatile("pusha \n\t" 1968 "cpuid \n\t" 1969 "mov %%eax, 0(%2) \n\t" 1970 "mov %%ebx, 4(%2) \n\t" 1971 "mov %%ecx, 8(%2) \n\t" 1972 "mov %%edx, 12(%2) \n\t" 1973 "popa" 1974 : : "a"(function), "c"(count), "S"(vec) 1975 : "memory", "cc"); 1976 #else 1977 abort(); 1978 #endif 1979 1980 if (eax) 1981 *eax = vec[0]; 1982 if (ebx) 1983 *ebx = vec[1]; 1984 if (ecx) 1985 *ecx = vec[2]; 1986 if (edx) 1987 *edx = vec[3]; 1988 } 1989 1990 /* CPU class name definitions: */ 1991 1992 /* Return type name for a given CPU model name 1993 * Caller is responsible for freeing the returned string. 1994 */ 1995 static char *x86_cpu_type_name(const char *model_name) 1996 { 1997 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1998 } 1999 2000 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2001 { 2002 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2003 return object_class_by_name(typename); 2004 } 2005 2006 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2007 { 2008 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2009 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2010 return cpu_model_from_type(class_name); 2011 } 2012 2013 typedef struct X86CPUVersionDefinition { 2014 X86CPUVersion version; 2015 const char *alias; 2016 const char *note; 2017 PropValue *props; 2018 const CPUCaches *const cache_info; 2019 } X86CPUVersionDefinition; 2020 2021 /* Base definition for a CPU model */ 2022 typedef struct X86CPUDefinition { 2023 const char *name; 2024 uint32_t level; 2025 uint32_t xlevel; 2026 /* vendor is zero-terminated, 12 character ASCII string */ 2027 char vendor[CPUID_VENDOR_SZ + 1]; 2028 int family; 2029 int model; 2030 int stepping; 2031 uint8_t avx10_version; 2032 FeatureWordArray features; 2033 const char *model_id; 2034 const CPUCaches *const cache_info; 2035 /* 2036 * Definitions for alternative versions of CPU model. 2037 * List is terminated by item with version == 0. 2038 * If NULL, version 1 will be registered automatically. 2039 */ 2040 const X86CPUVersionDefinition *versions; 2041 const char *deprecation_note; 2042 } X86CPUDefinition; 2043 2044 /* Reference to a specific CPU model version */ 2045 struct X86CPUModel { 2046 /* Base CPU definition */ 2047 const X86CPUDefinition *cpudef; 2048 /* CPU model version */ 2049 X86CPUVersion version; 2050 const char *note; 2051 /* 2052 * If true, this is an alias CPU model. 2053 * This matters only for "-cpu help" and query-cpu-definitions 2054 */ 2055 bool is_alias; 2056 }; 2057 2058 /* Get full model name for CPU version */ 2059 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2060 X86CPUVersion version) 2061 { 2062 assert(version > 0); 2063 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2064 } 2065 2066 static const X86CPUVersionDefinition * 2067 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2068 { 2069 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2070 static const X86CPUVersionDefinition default_version_list[] = { 2071 { 1 }, 2072 { /* end of list */ } 2073 }; 2074 2075 return def->versions ?: default_version_list; 2076 } 2077 2078 static const CPUCaches epyc_cache_info = { 2079 .l1d_cache = &(CPUCacheInfo) { 2080 .type = DATA_CACHE, 2081 .level = 1, 2082 .size = 32 * KiB, 2083 .line_size = 64, 2084 .associativity = 8, 2085 .partitions = 1, 2086 .sets = 64, 2087 .lines_per_tag = 1, 2088 .self_init = 1, 2089 .no_invd_sharing = true, 2090 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2091 }, 2092 .l1i_cache = &(CPUCacheInfo) { 2093 .type = INSTRUCTION_CACHE, 2094 .level = 1, 2095 .size = 64 * KiB, 2096 .line_size = 64, 2097 .associativity = 4, 2098 .partitions = 1, 2099 .sets = 256, 2100 .lines_per_tag = 1, 2101 .self_init = 1, 2102 .no_invd_sharing = true, 2103 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2104 }, 2105 .l2_cache = &(CPUCacheInfo) { 2106 .type = UNIFIED_CACHE, 2107 .level = 2, 2108 .size = 512 * KiB, 2109 .line_size = 64, 2110 .associativity = 8, 2111 .partitions = 1, 2112 .sets = 1024, 2113 .lines_per_tag = 1, 2114 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2115 }, 2116 .l3_cache = &(CPUCacheInfo) { 2117 .type = UNIFIED_CACHE, 2118 .level = 3, 2119 .size = 8 * MiB, 2120 .line_size = 64, 2121 .associativity = 16, 2122 .partitions = 1, 2123 .sets = 8192, 2124 .lines_per_tag = 1, 2125 .self_init = true, 2126 .inclusive = true, 2127 .complex_indexing = true, 2128 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2129 }, 2130 }; 2131 2132 static CPUCaches epyc_v4_cache_info = { 2133 .l1d_cache = &(CPUCacheInfo) { 2134 .type = DATA_CACHE, 2135 .level = 1, 2136 .size = 32 * KiB, 2137 .line_size = 64, 2138 .associativity = 8, 2139 .partitions = 1, 2140 .sets = 64, 2141 .lines_per_tag = 1, 2142 .self_init = 1, 2143 .no_invd_sharing = true, 2144 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2145 }, 2146 .l1i_cache = &(CPUCacheInfo) { 2147 .type = INSTRUCTION_CACHE, 2148 .level = 1, 2149 .size = 64 * KiB, 2150 .line_size = 64, 2151 .associativity = 4, 2152 .partitions = 1, 2153 .sets = 256, 2154 .lines_per_tag = 1, 2155 .self_init = 1, 2156 .no_invd_sharing = true, 2157 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2158 }, 2159 .l2_cache = &(CPUCacheInfo) { 2160 .type = UNIFIED_CACHE, 2161 .level = 2, 2162 .size = 512 * KiB, 2163 .line_size = 64, 2164 .associativity = 8, 2165 .partitions = 1, 2166 .sets = 1024, 2167 .lines_per_tag = 1, 2168 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2169 }, 2170 .l3_cache = &(CPUCacheInfo) { 2171 .type = UNIFIED_CACHE, 2172 .level = 3, 2173 .size = 8 * MiB, 2174 .line_size = 64, 2175 .associativity = 16, 2176 .partitions = 1, 2177 .sets = 8192, 2178 .lines_per_tag = 1, 2179 .self_init = true, 2180 .inclusive = true, 2181 .complex_indexing = false, 2182 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2183 }, 2184 }; 2185 2186 static const CPUCaches epyc_rome_cache_info = { 2187 .l1d_cache = &(CPUCacheInfo) { 2188 .type = DATA_CACHE, 2189 .level = 1, 2190 .size = 32 * KiB, 2191 .line_size = 64, 2192 .associativity = 8, 2193 .partitions = 1, 2194 .sets = 64, 2195 .lines_per_tag = 1, 2196 .self_init = 1, 2197 .no_invd_sharing = true, 2198 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2199 }, 2200 .l1i_cache = &(CPUCacheInfo) { 2201 .type = INSTRUCTION_CACHE, 2202 .level = 1, 2203 .size = 32 * KiB, 2204 .line_size = 64, 2205 .associativity = 8, 2206 .partitions = 1, 2207 .sets = 64, 2208 .lines_per_tag = 1, 2209 .self_init = 1, 2210 .no_invd_sharing = true, 2211 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2212 }, 2213 .l2_cache = &(CPUCacheInfo) { 2214 .type = UNIFIED_CACHE, 2215 .level = 2, 2216 .size = 512 * KiB, 2217 .line_size = 64, 2218 .associativity = 8, 2219 .partitions = 1, 2220 .sets = 1024, 2221 .lines_per_tag = 1, 2222 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2223 }, 2224 .l3_cache = &(CPUCacheInfo) { 2225 .type = UNIFIED_CACHE, 2226 .level = 3, 2227 .size = 16 * MiB, 2228 .line_size = 64, 2229 .associativity = 16, 2230 .partitions = 1, 2231 .sets = 16384, 2232 .lines_per_tag = 1, 2233 .self_init = true, 2234 .inclusive = true, 2235 .complex_indexing = true, 2236 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2237 }, 2238 }; 2239 2240 static const CPUCaches epyc_rome_v3_cache_info = { 2241 .l1d_cache = &(CPUCacheInfo) { 2242 .type = DATA_CACHE, 2243 .level = 1, 2244 .size = 32 * KiB, 2245 .line_size = 64, 2246 .associativity = 8, 2247 .partitions = 1, 2248 .sets = 64, 2249 .lines_per_tag = 1, 2250 .self_init = 1, 2251 .no_invd_sharing = true, 2252 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2253 }, 2254 .l1i_cache = &(CPUCacheInfo) { 2255 .type = INSTRUCTION_CACHE, 2256 .level = 1, 2257 .size = 32 * KiB, 2258 .line_size = 64, 2259 .associativity = 8, 2260 .partitions = 1, 2261 .sets = 64, 2262 .lines_per_tag = 1, 2263 .self_init = 1, 2264 .no_invd_sharing = true, 2265 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2266 }, 2267 .l2_cache = &(CPUCacheInfo) { 2268 .type = UNIFIED_CACHE, 2269 .level = 2, 2270 .size = 512 * KiB, 2271 .line_size = 64, 2272 .associativity = 8, 2273 .partitions = 1, 2274 .sets = 1024, 2275 .lines_per_tag = 1, 2276 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2277 }, 2278 .l3_cache = &(CPUCacheInfo) { 2279 .type = UNIFIED_CACHE, 2280 .level = 3, 2281 .size = 16 * MiB, 2282 .line_size = 64, 2283 .associativity = 16, 2284 .partitions = 1, 2285 .sets = 16384, 2286 .lines_per_tag = 1, 2287 .self_init = true, 2288 .inclusive = true, 2289 .complex_indexing = false, 2290 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2291 }, 2292 }; 2293 2294 static const CPUCaches epyc_milan_cache_info = { 2295 .l1d_cache = &(CPUCacheInfo) { 2296 .type = DATA_CACHE, 2297 .level = 1, 2298 .size = 32 * KiB, 2299 .line_size = 64, 2300 .associativity = 8, 2301 .partitions = 1, 2302 .sets = 64, 2303 .lines_per_tag = 1, 2304 .self_init = 1, 2305 .no_invd_sharing = true, 2306 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2307 }, 2308 .l1i_cache = &(CPUCacheInfo) { 2309 .type = INSTRUCTION_CACHE, 2310 .level = 1, 2311 .size = 32 * KiB, 2312 .line_size = 64, 2313 .associativity = 8, 2314 .partitions = 1, 2315 .sets = 64, 2316 .lines_per_tag = 1, 2317 .self_init = 1, 2318 .no_invd_sharing = true, 2319 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2320 }, 2321 .l2_cache = &(CPUCacheInfo) { 2322 .type = UNIFIED_CACHE, 2323 .level = 2, 2324 .size = 512 * KiB, 2325 .line_size = 64, 2326 .associativity = 8, 2327 .partitions = 1, 2328 .sets = 1024, 2329 .lines_per_tag = 1, 2330 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2331 }, 2332 .l3_cache = &(CPUCacheInfo) { 2333 .type = UNIFIED_CACHE, 2334 .level = 3, 2335 .size = 32 * MiB, 2336 .line_size = 64, 2337 .associativity = 16, 2338 .partitions = 1, 2339 .sets = 32768, 2340 .lines_per_tag = 1, 2341 .self_init = true, 2342 .inclusive = true, 2343 .complex_indexing = true, 2344 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2345 }, 2346 }; 2347 2348 static const CPUCaches epyc_milan_v2_cache_info = { 2349 .l1d_cache = &(CPUCacheInfo) { 2350 .type = DATA_CACHE, 2351 .level = 1, 2352 .size = 32 * KiB, 2353 .line_size = 64, 2354 .associativity = 8, 2355 .partitions = 1, 2356 .sets = 64, 2357 .lines_per_tag = 1, 2358 .self_init = 1, 2359 .no_invd_sharing = true, 2360 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2361 }, 2362 .l1i_cache = &(CPUCacheInfo) { 2363 .type = INSTRUCTION_CACHE, 2364 .level = 1, 2365 .size = 32 * KiB, 2366 .line_size = 64, 2367 .associativity = 8, 2368 .partitions = 1, 2369 .sets = 64, 2370 .lines_per_tag = 1, 2371 .self_init = 1, 2372 .no_invd_sharing = true, 2373 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2374 }, 2375 .l2_cache = &(CPUCacheInfo) { 2376 .type = UNIFIED_CACHE, 2377 .level = 2, 2378 .size = 512 * KiB, 2379 .line_size = 64, 2380 .associativity = 8, 2381 .partitions = 1, 2382 .sets = 1024, 2383 .lines_per_tag = 1, 2384 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2385 }, 2386 .l3_cache = &(CPUCacheInfo) { 2387 .type = UNIFIED_CACHE, 2388 .level = 3, 2389 .size = 32 * MiB, 2390 .line_size = 64, 2391 .associativity = 16, 2392 .partitions = 1, 2393 .sets = 32768, 2394 .lines_per_tag = 1, 2395 .self_init = true, 2396 .inclusive = true, 2397 .complex_indexing = false, 2398 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2399 }, 2400 }; 2401 2402 static const CPUCaches epyc_genoa_cache_info = { 2403 .l1d_cache = &(CPUCacheInfo) { 2404 .type = DATA_CACHE, 2405 .level = 1, 2406 .size = 32 * KiB, 2407 .line_size = 64, 2408 .associativity = 8, 2409 .partitions = 1, 2410 .sets = 64, 2411 .lines_per_tag = 1, 2412 .self_init = 1, 2413 .no_invd_sharing = true, 2414 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2415 }, 2416 .l1i_cache = &(CPUCacheInfo) { 2417 .type = INSTRUCTION_CACHE, 2418 .level = 1, 2419 .size = 32 * KiB, 2420 .line_size = 64, 2421 .associativity = 8, 2422 .partitions = 1, 2423 .sets = 64, 2424 .lines_per_tag = 1, 2425 .self_init = 1, 2426 .no_invd_sharing = true, 2427 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2428 }, 2429 .l2_cache = &(CPUCacheInfo) { 2430 .type = UNIFIED_CACHE, 2431 .level = 2, 2432 .size = 1 * MiB, 2433 .line_size = 64, 2434 .associativity = 8, 2435 .partitions = 1, 2436 .sets = 2048, 2437 .lines_per_tag = 1, 2438 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2439 }, 2440 .l3_cache = &(CPUCacheInfo) { 2441 .type = UNIFIED_CACHE, 2442 .level = 3, 2443 .size = 32 * MiB, 2444 .line_size = 64, 2445 .associativity = 16, 2446 .partitions = 1, 2447 .sets = 32768, 2448 .lines_per_tag = 1, 2449 .self_init = true, 2450 .inclusive = true, 2451 .complex_indexing = false, 2452 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2453 }, 2454 }; 2455 2456 /* The following VMX features are not supported by KVM and are left out in the 2457 * CPU definitions: 2458 * 2459 * Dual-monitor support (all processors) 2460 * Entry to SMM 2461 * Deactivate dual-monitor treatment 2462 * Number of CR3-target values 2463 * Shutdown activity state 2464 * Wait-for-SIPI activity state 2465 * PAUSE-loop exiting (Westmere and newer) 2466 * EPT-violation #VE (Broadwell and newer) 2467 * Inject event with insn length=0 (Skylake and newer) 2468 * Conceal non-root operation from PT 2469 * Conceal VM exits from PT 2470 * Conceal VM entries from PT 2471 * Enable ENCLS exiting 2472 * Mode-based execute control (XS/XU) 2473 * TSC scaling (Skylake Server and newer) 2474 * GPA translation for PT (IceLake and newer) 2475 * User wait and pause 2476 * ENCLV exiting 2477 * Load IA32_RTIT_CTL 2478 * Clear IA32_RTIT_CTL 2479 * Advanced VM-exit information for EPT violations 2480 * Sub-page write permissions 2481 * PT in VMX operation 2482 */ 2483 2484 static const X86CPUDefinition builtin_x86_defs[] = { 2485 { 2486 .name = "qemu64", 2487 .level = 0xd, 2488 .vendor = CPUID_VENDOR_AMD, 2489 .family = 15, 2490 .model = 107, 2491 .stepping = 1, 2492 .features[FEAT_1_EDX] = 2493 PPRO_FEATURES | 2494 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2495 CPUID_PSE36, 2496 .features[FEAT_1_ECX] = 2497 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2498 .features[FEAT_8000_0001_EDX] = 2499 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2500 .features[FEAT_8000_0001_ECX] = 2501 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2502 .xlevel = 0x8000000A, 2503 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2504 }, 2505 { 2506 .name = "phenom", 2507 .level = 5, 2508 .vendor = CPUID_VENDOR_AMD, 2509 .family = 16, 2510 .model = 2, 2511 .stepping = 3, 2512 /* Missing: CPUID_HT */ 2513 .features[FEAT_1_EDX] = 2514 PPRO_FEATURES | 2515 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2516 CPUID_PSE36 | CPUID_VME, 2517 .features[FEAT_1_ECX] = 2518 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2519 CPUID_EXT_POPCNT, 2520 .features[FEAT_8000_0001_EDX] = 2521 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2522 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2523 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2524 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2525 CPUID_EXT3_CR8LEG, 2526 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2527 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2528 .features[FEAT_8000_0001_ECX] = 2529 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2530 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2531 /* Missing: CPUID_SVM_LBRV */ 2532 .features[FEAT_SVM] = 2533 CPUID_SVM_NPT, 2534 .xlevel = 0x8000001A, 2535 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2536 }, 2537 { 2538 .name = "core2duo", 2539 .level = 10, 2540 .vendor = CPUID_VENDOR_INTEL, 2541 .family = 6, 2542 .model = 15, 2543 .stepping = 11, 2544 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2545 .features[FEAT_1_EDX] = 2546 PPRO_FEATURES | 2547 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2548 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2549 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2550 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2551 .features[FEAT_1_ECX] = 2552 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2553 CPUID_EXT_CX16, 2554 .features[FEAT_8000_0001_EDX] = 2555 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2556 .features[FEAT_8000_0001_ECX] = 2557 CPUID_EXT3_LAHF_LM, 2558 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2559 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2560 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2561 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2562 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2563 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2564 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2565 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2566 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2567 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2568 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2569 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2570 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2571 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2572 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2573 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2574 .features[FEAT_VMX_SECONDARY_CTLS] = 2575 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2576 .xlevel = 0x80000008, 2577 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2578 }, 2579 { 2580 .name = "kvm64", 2581 .level = 0xd, 2582 .vendor = CPUID_VENDOR_INTEL, 2583 .family = 15, 2584 .model = 6, 2585 .stepping = 1, 2586 /* Missing: CPUID_HT */ 2587 .features[FEAT_1_EDX] = 2588 PPRO_FEATURES | CPUID_VME | 2589 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2590 CPUID_PSE36, 2591 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2592 .features[FEAT_1_ECX] = 2593 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2594 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2595 .features[FEAT_8000_0001_EDX] = 2596 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2597 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2598 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2599 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2600 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2601 .features[FEAT_8000_0001_ECX] = 2602 0, 2603 /* VMX features from Cedar Mill/Prescott */ 2604 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2605 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2606 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2607 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2608 VMX_PIN_BASED_NMI_EXITING, 2609 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2610 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2611 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2612 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2613 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2614 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2615 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2616 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2617 .xlevel = 0x80000008, 2618 .model_id = "Common KVM processor" 2619 }, 2620 { 2621 .name = "qemu32", 2622 .level = 4, 2623 .vendor = CPUID_VENDOR_INTEL, 2624 .family = 6, 2625 .model = 6, 2626 .stepping = 3, 2627 .features[FEAT_1_EDX] = 2628 PPRO_FEATURES, 2629 .features[FEAT_1_ECX] = 2630 CPUID_EXT_SSE3, 2631 .xlevel = 0x80000004, 2632 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2633 }, 2634 { 2635 .name = "kvm32", 2636 .level = 5, 2637 .vendor = CPUID_VENDOR_INTEL, 2638 .family = 15, 2639 .model = 6, 2640 .stepping = 1, 2641 .features[FEAT_1_EDX] = 2642 PPRO_FEATURES | CPUID_VME | 2643 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2644 .features[FEAT_1_ECX] = 2645 CPUID_EXT_SSE3, 2646 .features[FEAT_8000_0001_ECX] = 2647 0, 2648 /* VMX features from Yonah */ 2649 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2650 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2651 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2652 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2653 VMX_PIN_BASED_NMI_EXITING, 2654 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2655 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2656 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2657 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2658 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2659 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2660 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2661 .xlevel = 0x80000008, 2662 .model_id = "Common 32-bit KVM processor" 2663 }, 2664 { 2665 .name = "coreduo", 2666 .level = 10, 2667 .vendor = CPUID_VENDOR_INTEL, 2668 .family = 6, 2669 .model = 14, 2670 .stepping = 8, 2671 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2672 .features[FEAT_1_EDX] = 2673 PPRO_FEATURES | CPUID_VME | 2674 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2675 CPUID_SS, 2676 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2677 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2678 .features[FEAT_1_ECX] = 2679 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2680 .features[FEAT_8000_0001_EDX] = 2681 CPUID_EXT2_NX, 2682 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2683 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2684 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2685 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2686 VMX_PIN_BASED_NMI_EXITING, 2687 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2688 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2689 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2690 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2691 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2692 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2693 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2694 .xlevel = 0x80000008, 2695 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2696 }, 2697 { 2698 .name = "486", 2699 .level = 1, 2700 .vendor = CPUID_VENDOR_INTEL, 2701 .family = 4, 2702 .model = 8, 2703 .stepping = 0, 2704 .features[FEAT_1_EDX] = 2705 I486_FEATURES, 2706 .xlevel = 0, 2707 .model_id = "", 2708 }, 2709 { 2710 .name = "pentium", 2711 .level = 1, 2712 .vendor = CPUID_VENDOR_INTEL, 2713 .family = 5, 2714 .model = 4, 2715 .stepping = 3, 2716 .features[FEAT_1_EDX] = 2717 PENTIUM_FEATURES, 2718 .xlevel = 0, 2719 .model_id = "", 2720 }, 2721 { 2722 .name = "pentium2", 2723 .level = 2, 2724 .vendor = CPUID_VENDOR_INTEL, 2725 .family = 6, 2726 .model = 5, 2727 .stepping = 2, 2728 .features[FEAT_1_EDX] = 2729 PENTIUM2_FEATURES, 2730 .xlevel = 0, 2731 .model_id = "", 2732 }, 2733 { 2734 .name = "pentium3", 2735 .level = 3, 2736 .vendor = CPUID_VENDOR_INTEL, 2737 .family = 6, 2738 .model = 7, 2739 .stepping = 3, 2740 .features[FEAT_1_EDX] = 2741 PENTIUM3_FEATURES, 2742 .xlevel = 0, 2743 .model_id = "", 2744 }, 2745 { 2746 .name = "athlon", 2747 .level = 2, 2748 .vendor = CPUID_VENDOR_AMD, 2749 .family = 6, 2750 .model = 2, 2751 .stepping = 3, 2752 .features[FEAT_1_EDX] = 2753 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2754 CPUID_MCA, 2755 .features[FEAT_8000_0001_EDX] = 2756 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2757 .xlevel = 0x80000008, 2758 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2759 }, 2760 { 2761 .name = "n270", 2762 .level = 10, 2763 .vendor = CPUID_VENDOR_INTEL, 2764 .family = 6, 2765 .model = 28, 2766 .stepping = 2, 2767 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2768 .features[FEAT_1_EDX] = 2769 PPRO_FEATURES | 2770 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2771 CPUID_ACPI | CPUID_SS, 2772 /* Some CPUs got no CPUID_SEP */ 2773 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2774 * CPUID_EXT_XTPR */ 2775 .features[FEAT_1_ECX] = 2776 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2777 CPUID_EXT_MOVBE, 2778 .features[FEAT_8000_0001_EDX] = 2779 CPUID_EXT2_NX, 2780 .features[FEAT_8000_0001_ECX] = 2781 CPUID_EXT3_LAHF_LM, 2782 .xlevel = 0x80000008, 2783 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2784 }, 2785 { 2786 .name = "Conroe", 2787 .level = 10, 2788 .vendor = CPUID_VENDOR_INTEL, 2789 .family = 6, 2790 .model = 15, 2791 .stepping = 3, 2792 .features[FEAT_1_EDX] = 2793 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2794 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2795 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2796 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2797 CPUID_DE | CPUID_FP87, 2798 .features[FEAT_1_ECX] = 2799 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2800 .features[FEAT_8000_0001_EDX] = 2801 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2802 .features[FEAT_8000_0001_ECX] = 2803 CPUID_EXT3_LAHF_LM, 2804 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2805 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2806 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2807 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2808 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2809 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2810 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2811 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2812 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2813 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2814 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2815 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2816 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2817 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2818 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2819 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2820 .features[FEAT_VMX_SECONDARY_CTLS] = 2821 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2822 .xlevel = 0x80000008, 2823 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2824 }, 2825 { 2826 .name = "Penryn", 2827 .level = 10, 2828 .vendor = CPUID_VENDOR_INTEL, 2829 .family = 6, 2830 .model = 23, 2831 .stepping = 3, 2832 .features[FEAT_1_EDX] = 2833 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2834 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2835 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2836 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2837 CPUID_DE | CPUID_FP87, 2838 .features[FEAT_1_ECX] = 2839 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2840 CPUID_EXT_SSE3, 2841 .features[FEAT_8000_0001_EDX] = 2842 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2843 .features[FEAT_8000_0001_ECX] = 2844 CPUID_EXT3_LAHF_LM, 2845 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2846 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2847 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2848 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2849 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2850 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2851 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2852 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2853 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2854 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2855 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2856 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2857 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2858 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2859 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2860 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2861 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2862 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2863 .features[FEAT_VMX_SECONDARY_CTLS] = 2864 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2865 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2866 .xlevel = 0x80000008, 2867 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2868 }, 2869 { 2870 .name = "Nehalem", 2871 .level = 11, 2872 .vendor = CPUID_VENDOR_INTEL, 2873 .family = 6, 2874 .model = 26, 2875 .stepping = 3, 2876 .features[FEAT_1_EDX] = 2877 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2878 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2879 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2880 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2881 CPUID_DE | CPUID_FP87, 2882 .features[FEAT_1_ECX] = 2883 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2884 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2885 .features[FEAT_8000_0001_EDX] = 2886 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2887 .features[FEAT_8000_0001_ECX] = 2888 CPUID_EXT3_LAHF_LM, 2889 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2890 MSR_VMX_BASIC_TRUE_CTLS, 2891 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2892 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2893 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2894 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2895 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2896 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2897 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2898 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2899 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2900 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2901 .features[FEAT_VMX_EXIT_CTLS] = 2902 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2903 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2904 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2905 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2906 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2907 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2908 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2909 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2910 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2911 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2912 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2913 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2914 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2915 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2916 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2917 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2918 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2919 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2920 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2921 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2922 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2923 .features[FEAT_VMX_SECONDARY_CTLS] = 2924 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2925 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2926 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2927 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2928 VMX_SECONDARY_EXEC_ENABLE_VPID, 2929 .xlevel = 0x80000008, 2930 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2931 .versions = (X86CPUVersionDefinition[]) { 2932 { .version = 1 }, 2933 { 2934 .version = 2, 2935 .alias = "Nehalem-IBRS", 2936 .props = (PropValue[]) { 2937 { "spec-ctrl", "on" }, 2938 { "model-id", 2939 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2940 { /* end of list */ } 2941 } 2942 }, 2943 { /* end of list */ } 2944 } 2945 }, 2946 { 2947 .name = "Westmere", 2948 .level = 11, 2949 .vendor = CPUID_VENDOR_INTEL, 2950 .family = 6, 2951 .model = 44, 2952 .stepping = 1, 2953 .features[FEAT_1_EDX] = 2954 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2955 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2956 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2957 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2958 CPUID_DE | CPUID_FP87, 2959 .features[FEAT_1_ECX] = 2960 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2961 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2962 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2963 .features[FEAT_8000_0001_EDX] = 2964 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2965 .features[FEAT_8000_0001_ECX] = 2966 CPUID_EXT3_LAHF_LM, 2967 .features[FEAT_6_EAX] = 2968 CPUID_6_EAX_ARAT, 2969 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2970 MSR_VMX_BASIC_TRUE_CTLS, 2971 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2972 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2973 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2974 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2975 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2976 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2977 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2978 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2979 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2980 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2981 .features[FEAT_VMX_EXIT_CTLS] = 2982 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2983 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2984 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2985 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2986 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2987 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2988 MSR_VMX_MISC_STORE_LMA, 2989 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2990 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2991 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2992 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2993 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2994 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2995 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2996 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2997 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2998 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2999 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3000 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3001 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3002 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3003 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3004 .features[FEAT_VMX_SECONDARY_CTLS] = 3005 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3006 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3007 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3008 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3009 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3010 .xlevel = 0x80000008, 3011 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3012 .versions = (X86CPUVersionDefinition[]) { 3013 { .version = 1 }, 3014 { 3015 .version = 2, 3016 .alias = "Westmere-IBRS", 3017 .props = (PropValue[]) { 3018 { "spec-ctrl", "on" }, 3019 { "model-id", 3020 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3021 { /* end of list */ } 3022 } 3023 }, 3024 { /* end of list */ } 3025 } 3026 }, 3027 { 3028 .name = "SandyBridge", 3029 .level = 0xd, 3030 .vendor = CPUID_VENDOR_INTEL, 3031 .family = 6, 3032 .model = 42, 3033 .stepping = 1, 3034 .features[FEAT_1_EDX] = 3035 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3036 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3037 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3038 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3039 CPUID_DE | CPUID_FP87, 3040 .features[FEAT_1_ECX] = 3041 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3042 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3043 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3044 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3045 CPUID_EXT_SSE3, 3046 .features[FEAT_8000_0001_EDX] = 3047 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3048 CPUID_EXT2_SYSCALL, 3049 .features[FEAT_8000_0001_ECX] = 3050 CPUID_EXT3_LAHF_LM, 3051 .features[FEAT_XSAVE] = 3052 CPUID_XSAVE_XSAVEOPT, 3053 .features[FEAT_6_EAX] = 3054 CPUID_6_EAX_ARAT, 3055 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3056 MSR_VMX_BASIC_TRUE_CTLS, 3057 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3058 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3059 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3060 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3061 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3062 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3063 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3064 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3065 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3066 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3067 .features[FEAT_VMX_EXIT_CTLS] = 3068 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3069 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3070 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3071 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3072 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3073 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3074 MSR_VMX_MISC_STORE_LMA, 3075 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3076 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3077 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3078 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3079 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3080 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3081 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3082 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3083 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3084 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3085 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3086 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3087 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3088 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3089 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3090 .features[FEAT_VMX_SECONDARY_CTLS] = 3091 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3092 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3093 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3094 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3095 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3096 .xlevel = 0x80000008, 3097 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3098 .versions = (X86CPUVersionDefinition[]) { 3099 { .version = 1 }, 3100 { 3101 .version = 2, 3102 .alias = "SandyBridge-IBRS", 3103 .props = (PropValue[]) { 3104 { "spec-ctrl", "on" }, 3105 { "model-id", 3106 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3107 { /* end of list */ } 3108 } 3109 }, 3110 { /* end of list */ } 3111 } 3112 }, 3113 { 3114 .name = "IvyBridge", 3115 .level = 0xd, 3116 .vendor = CPUID_VENDOR_INTEL, 3117 .family = 6, 3118 .model = 58, 3119 .stepping = 9, 3120 .features[FEAT_1_EDX] = 3121 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3122 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3123 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3124 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3125 CPUID_DE | CPUID_FP87, 3126 .features[FEAT_1_ECX] = 3127 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3128 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3129 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3130 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3131 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3132 .features[FEAT_7_0_EBX] = 3133 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3134 CPUID_7_0_EBX_ERMS, 3135 .features[FEAT_8000_0001_EDX] = 3136 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3137 CPUID_EXT2_SYSCALL, 3138 .features[FEAT_8000_0001_ECX] = 3139 CPUID_EXT3_LAHF_LM, 3140 .features[FEAT_XSAVE] = 3141 CPUID_XSAVE_XSAVEOPT, 3142 .features[FEAT_6_EAX] = 3143 CPUID_6_EAX_ARAT, 3144 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3145 MSR_VMX_BASIC_TRUE_CTLS, 3146 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3147 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3148 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3149 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3150 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3151 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3152 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3153 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3154 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3155 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3156 .features[FEAT_VMX_EXIT_CTLS] = 3157 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3158 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3159 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3160 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3161 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3162 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3163 MSR_VMX_MISC_STORE_LMA, 3164 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3165 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3166 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3167 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3168 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3169 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3170 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3171 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3172 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3173 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3174 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3175 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3176 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3177 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3178 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3179 .features[FEAT_VMX_SECONDARY_CTLS] = 3180 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3181 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3182 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3183 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3184 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3185 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3186 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3187 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3188 .xlevel = 0x80000008, 3189 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3190 .versions = (X86CPUVersionDefinition[]) { 3191 { .version = 1 }, 3192 { 3193 .version = 2, 3194 .alias = "IvyBridge-IBRS", 3195 .props = (PropValue[]) { 3196 { "spec-ctrl", "on" }, 3197 { "model-id", 3198 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3199 { /* end of list */ } 3200 } 3201 }, 3202 { /* end of list */ } 3203 } 3204 }, 3205 { 3206 .name = "Haswell", 3207 .level = 0xd, 3208 .vendor = CPUID_VENDOR_INTEL, 3209 .family = 6, 3210 .model = 60, 3211 .stepping = 4, 3212 .features[FEAT_1_EDX] = 3213 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3214 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3215 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3216 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3217 CPUID_DE | CPUID_FP87, 3218 .features[FEAT_1_ECX] = 3219 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3220 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3221 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3222 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3223 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3224 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3225 .features[FEAT_8000_0001_EDX] = 3226 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3227 CPUID_EXT2_SYSCALL, 3228 .features[FEAT_8000_0001_ECX] = 3229 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3230 .features[FEAT_7_0_EBX] = 3231 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3232 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3233 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3234 CPUID_7_0_EBX_RTM, 3235 .features[FEAT_XSAVE] = 3236 CPUID_XSAVE_XSAVEOPT, 3237 .features[FEAT_6_EAX] = 3238 CPUID_6_EAX_ARAT, 3239 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3240 MSR_VMX_BASIC_TRUE_CTLS, 3241 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3242 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3243 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3244 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3245 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3246 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3247 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3248 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3249 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3250 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3251 .features[FEAT_VMX_EXIT_CTLS] = 3252 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3253 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3254 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3255 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3256 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3257 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3258 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3259 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3260 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3261 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3262 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3263 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3264 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3265 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3266 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3267 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3268 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3269 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3270 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3271 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3272 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3273 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3274 .features[FEAT_VMX_SECONDARY_CTLS] = 3275 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3276 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3277 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3278 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3279 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3280 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3281 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3282 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3283 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3284 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3285 .xlevel = 0x80000008, 3286 .model_id = "Intel Core Processor (Haswell)", 3287 .versions = (X86CPUVersionDefinition[]) { 3288 { .version = 1 }, 3289 { 3290 .version = 2, 3291 .alias = "Haswell-noTSX", 3292 .props = (PropValue[]) { 3293 { "hle", "off" }, 3294 { "rtm", "off" }, 3295 { "stepping", "1" }, 3296 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3297 { /* end of list */ } 3298 }, 3299 }, 3300 { 3301 .version = 3, 3302 .alias = "Haswell-IBRS", 3303 .props = (PropValue[]) { 3304 /* Restore TSX features removed by -v2 above */ 3305 { "hle", "on" }, 3306 { "rtm", "on" }, 3307 /* 3308 * Haswell and Haswell-IBRS had stepping=4 in 3309 * QEMU 4.0 and older 3310 */ 3311 { "stepping", "4" }, 3312 { "spec-ctrl", "on" }, 3313 { "model-id", 3314 "Intel Core Processor (Haswell, IBRS)" }, 3315 { /* end of list */ } 3316 } 3317 }, 3318 { 3319 .version = 4, 3320 .alias = "Haswell-noTSX-IBRS", 3321 .props = (PropValue[]) { 3322 { "hle", "off" }, 3323 { "rtm", "off" }, 3324 /* spec-ctrl was already enabled by -v3 above */ 3325 { "stepping", "1" }, 3326 { "model-id", 3327 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3328 { /* end of list */ } 3329 } 3330 }, 3331 { /* end of list */ } 3332 } 3333 }, 3334 { 3335 .name = "Broadwell", 3336 .level = 0xd, 3337 .vendor = CPUID_VENDOR_INTEL, 3338 .family = 6, 3339 .model = 61, 3340 .stepping = 2, 3341 .features[FEAT_1_EDX] = 3342 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3343 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3344 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3345 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3346 CPUID_DE | CPUID_FP87, 3347 .features[FEAT_1_ECX] = 3348 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3349 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3350 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3351 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3352 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3353 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3354 .features[FEAT_8000_0001_EDX] = 3355 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3356 CPUID_EXT2_SYSCALL, 3357 .features[FEAT_8000_0001_ECX] = 3358 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3359 .features[FEAT_7_0_EBX] = 3360 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3361 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3362 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3363 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3364 CPUID_7_0_EBX_SMAP, 3365 .features[FEAT_XSAVE] = 3366 CPUID_XSAVE_XSAVEOPT, 3367 .features[FEAT_6_EAX] = 3368 CPUID_6_EAX_ARAT, 3369 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3370 MSR_VMX_BASIC_TRUE_CTLS, 3371 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3372 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3373 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3374 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3375 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3376 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3377 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3378 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3379 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3380 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3381 .features[FEAT_VMX_EXIT_CTLS] = 3382 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3383 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3384 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3385 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3386 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3387 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3388 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3389 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3390 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3391 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3392 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3393 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3394 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3395 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3396 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3397 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3398 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3399 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3400 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3401 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3402 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3403 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3404 .features[FEAT_VMX_SECONDARY_CTLS] = 3405 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3406 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3407 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3408 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3409 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3410 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3411 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3412 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3413 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3414 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3415 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3416 .xlevel = 0x80000008, 3417 .model_id = "Intel Core Processor (Broadwell)", 3418 .versions = (X86CPUVersionDefinition[]) { 3419 { .version = 1 }, 3420 { 3421 .version = 2, 3422 .alias = "Broadwell-noTSX", 3423 .props = (PropValue[]) { 3424 { "hle", "off" }, 3425 { "rtm", "off" }, 3426 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3427 { /* end of list */ } 3428 }, 3429 }, 3430 { 3431 .version = 3, 3432 .alias = "Broadwell-IBRS", 3433 .props = (PropValue[]) { 3434 /* Restore TSX features removed by -v2 above */ 3435 { "hle", "on" }, 3436 { "rtm", "on" }, 3437 { "spec-ctrl", "on" }, 3438 { "model-id", 3439 "Intel Core Processor (Broadwell, IBRS)" }, 3440 { /* end of list */ } 3441 } 3442 }, 3443 { 3444 .version = 4, 3445 .alias = "Broadwell-noTSX-IBRS", 3446 .props = (PropValue[]) { 3447 { "hle", "off" }, 3448 { "rtm", "off" }, 3449 /* spec-ctrl was already enabled by -v3 above */ 3450 { "model-id", 3451 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3452 { /* end of list */ } 3453 } 3454 }, 3455 { /* end of list */ } 3456 } 3457 }, 3458 { 3459 .name = "Skylake-Client", 3460 .level = 0xd, 3461 .vendor = CPUID_VENDOR_INTEL, 3462 .family = 6, 3463 .model = 94, 3464 .stepping = 3, 3465 .features[FEAT_1_EDX] = 3466 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3467 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3468 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3469 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3470 CPUID_DE | CPUID_FP87, 3471 .features[FEAT_1_ECX] = 3472 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3473 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3474 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3475 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3476 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3477 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3478 .features[FEAT_8000_0001_EDX] = 3479 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3480 CPUID_EXT2_SYSCALL, 3481 .features[FEAT_8000_0001_ECX] = 3482 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3483 .features[FEAT_7_0_EBX] = 3484 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3485 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3486 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3487 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3488 CPUID_7_0_EBX_SMAP, 3489 /* XSAVES is added in version 4 */ 3490 .features[FEAT_XSAVE] = 3491 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3492 CPUID_XSAVE_XGETBV1, 3493 .features[FEAT_6_EAX] = 3494 CPUID_6_EAX_ARAT, 3495 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3496 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3497 MSR_VMX_BASIC_TRUE_CTLS, 3498 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3499 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3500 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3501 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3502 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3503 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3504 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3505 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3506 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3507 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3508 .features[FEAT_VMX_EXIT_CTLS] = 3509 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3510 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3511 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3512 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3513 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3514 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3515 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3516 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3517 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3518 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3519 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3520 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3521 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3522 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3523 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3524 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3525 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3526 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3527 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3528 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3529 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3530 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3531 .features[FEAT_VMX_SECONDARY_CTLS] = 3532 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3533 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3534 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3535 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3536 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3537 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3538 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3539 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3540 .xlevel = 0x80000008, 3541 .model_id = "Intel Core Processor (Skylake)", 3542 .versions = (X86CPUVersionDefinition[]) { 3543 { .version = 1 }, 3544 { 3545 .version = 2, 3546 .alias = "Skylake-Client-IBRS", 3547 .props = (PropValue[]) { 3548 { "spec-ctrl", "on" }, 3549 { "model-id", 3550 "Intel Core Processor (Skylake, IBRS)" }, 3551 { /* end of list */ } 3552 } 3553 }, 3554 { 3555 .version = 3, 3556 .alias = "Skylake-Client-noTSX-IBRS", 3557 .props = (PropValue[]) { 3558 { "hle", "off" }, 3559 { "rtm", "off" }, 3560 { "model-id", 3561 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3562 { /* end of list */ } 3563 } 3564 }, 3565 { 3566 .version = 4, 3567 .note = "IBRS, XSAVES, no TSX", 3568 .props = (PropValue[]) { 3569 { "xsaves", "on" }, 3570 { "vmx-xsaves", "on" }, 3571 { /* end of list */ } 3572 } 3573 }, 3574 { /* end of list */ } 3575 } 3576 }, 3577 { 3578 .name = "Skylake-Server", 3579 .level = 0xd, 3580 .vendor = CPUID_VENDOR_INTEL, 3581 .family = 6, 3582 .model = 85, 3583 .stepping = 4, 3584 .features[FEAT_1_EDX] = 3585 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3586 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3587 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3588 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3589 CPUID_DE | CPUID_FP87, 3590 .features[FEAT_1_ECX] = 3591 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3592 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3593 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3594 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3595 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3596 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3597 .features[FEAT_8000_0001_EDX] = 3598 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3599 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3600 .features[FEAT_8000_0001_ECX] = 3601 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3602 .features[FEAT_7_0_EBX] = 3603 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3604 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3605 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3606 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3607 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3608 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3609 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3610 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3611 .features[FEAT_7_0_ECX] = 3612 CPUID_7_0_ECX_PKU, 3613 /* XSAVES is added in version 5 */ 3614 .features[FEAT_XSAVE] = 3615 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3616 CPUID_XSAVE_XGETBV1, 3617 .features[FEAT_6_EAX] = 3618 CPUID_6_EAX_ARAT, 3619 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3620 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3621 MSR_VMX_BASIC_TRUE_CTLS, 3622 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3623 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3624 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3625 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3626 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3627 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3628 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3629 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3630 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3631 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3632 .features[FEAT_VMX_EXIT_CTLS] = 3633 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3634 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3635 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3636 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3637 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3638 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3639 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3640 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3641 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3642 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3643 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3644 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3645 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3646 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3647 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3648 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3649 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3650 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3651 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3652 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3653 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3654 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3655 .features[FEAT_VMX_SECONDARY_CTLS] = 3656 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3657 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3658 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3659 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3660 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3661 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3662 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3663 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3664 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3665 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3666 .xlevel = 0x80000008, 3667 .model_id = "Intel Xeon Processor (Skylake)", 3668 .versions = (X86CPUVersionDefinition[]) { 3669 { .version = 1 }, 3670 { 3671 .version = 2, 3672 .alias = "Skylake-Server-IBRS", 3673 .props = (PropValue[]) { 3674 /* clflushopt was not added to Skylake-Server-IBRS */ 3675 /* TODO: add -v3 including clflushopt */ 3676 { "clflushopt", "off" }, 3677 { "spec-ctrl", "on" }, 3678 { "model-id", 3679 "Intel Xeon Processor (Skylake, IBRS)" }, 3680 { /* end of list */ } 3681 } 3682 }, 3683 { 3684 .version = 3, 3685 .alias = "Skylake-Server-noTSX-IBRS", 3686 .props = (PropValue[]) { 3687 { "hle", "off" }, 3688 { "rtm", "off" }, 3689 { "model-id", 3690 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3691 { /* end of list */ } 3692 } 3693 }, 3694 { 3695 .version = 4, 3696 .note = "IBRS, EPT switching, no TSX", 3697 .props = (PropValue[]) { 3698 { "vmx-eptp-switching", "on" }, 3699 { /* end of list */ } 3700 } 3701 }, 3702 { 3703 .version = 5, 3704 .note = "IBRS, XSAVES, EPT switching, no TSX", 3705 .props = (PropValue[]) { 3706 { "xsaves", "on" }, 3707 { "vmx-xsaves", "on" }, 3708 { /* end of list */ } 3709 } 3710 }, 3711 { /* end of list */ } 3712 } 3713 }, 3714 { 3715 .name = "Cascadelake-Server", 3716 .level = 0xd, 3717 .vendor = CPUID_VENDOR_INTEL, 3718 .family = 6, 3719 .model = 85, 3720 .stepping = 6, 3721 .features[FEAT_1_EDX] = 3722 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3723 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3724 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3725 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3726 CPUID_DE | CPUID_FP87, 3727 .features[FEAT_1_ECX] = 3728 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3729 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3730 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3731 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3732 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3733 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3734 .features[FEAT_8000_0001_EDX] = 3735 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3736 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3737 .features[FEAT_8000_0001_ECX] = 3738 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3739 .features[FEAT_7_0_EBX] = 3740 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3741 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3742 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3743 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3744 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3745 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3746 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3747 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3748 .features[FEAT_7_0_ECX] = 3749 CPUID_7_0_ECX_PKU | 3750 CPUID_7_0_ECX_AVX512VNNI, 3751 .features[FEAT_7_0_EDX] = 3752 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3753 /* XSAVES is added in version 5 */ 3754 .features[FEAT_XSAVE] = 3755 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3756 CPUID_XSAVE_XGETBV1, 3757 .features[FEAT_6_EAX] = 3758 CPUID_6_EAX_ARAT, 3759 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3760 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3761 MSR_VMX_BASIC_TRUE_CTLS, 3762 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3763 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3764 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3765 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3766 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3767 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3768 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3769 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3770 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3771 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3772 .features[FEAT_VMX_EXIT_CTLS] = 3773 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3774 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3775 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3776 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3777 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3778 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3779 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3780 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3781 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3782 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3783 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3784 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3785 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3786 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3787 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3788 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3789 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3790 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3791 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3792 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3793 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3794 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3795 .features[FEAT_VMX_SECONDARY_CTLS] = 3796 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3797 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3798 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3799 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3800 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3801 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3802 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3803 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3804 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3805 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3806 .xlevel = 0x80000008, 3807 .model_id = "Intel Xeon Processor (Cascadelake)", 3808 .versions = (X86CPUVersionDefinition[]) { 3809 { .version = 1 }, 3810 { .version = 2, 3811 .note = "ARCH_CAPABILITIES", 3812 .props = (PropValue[]) { 3813 { "arch-capabilities", "on" }, 3814 { "rdctl-no", "on" }, 3815 { "ibrs-all", "on" }, 3816 { "skip-l1dfl-vmentry", "on" }, 3817 { "mds-no", "on" }, 3818 { /* end of list */ } 3819 }, 3820 }, 3821 { .version = 3, 3822 .alias = "Cascadelake-Server-noTSX", 3823 .note = "ARCH_CAPABILITIES, no TSX", 3824 .props = (PropValue[]) { 3825 { "hle", "off" }, 3826 { "rtm", "off" }, 3827 { /* end of list */ } 3828 }, 3829 }, 3830 { .version = 4, 3831 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 3832 .props = (PropValue[]) { 3833 { "vmx-eptp-switching", "on" }, 3834 { /* end of list */ } 3835 }, 3836 }, 3837 { .version = 5, 3838 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3839 .props = (PropValue[]) { 3840 { "xsaves", "on" }, 3841 { "vmx-xsaves", "on" }, 3842 { /* end of list */ } 3843 }, 3844 }, 3845 { /* end of list */ } 3846 } 3847 }, 3848 { 3849 .name = "Cooperlake", 3850 .level = 0xd, 3851 .vendor = CPUID_VENDOR_INTEL, 3852 .family = 6, 3853 .model = 85, 3854 .stepping = 10, 3855 .features[FEAT_1_EDX] = 3856 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3857 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3858 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3859 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3860 CPUID_DE | CPUID_FP87, 3861 .features[FEAT_1_ECX] = 3862 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3863 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3864 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3865 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3866 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3867 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3868 .features[FEAT_8000_0001_EDX] = 3869 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3870 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3871 .features[FEAT_8000_0001_ECX] = 3872 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3873 .features[FEAT_7_0_EBX] = 3874 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3875 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3876 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3877 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3878 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3879 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3880 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3881 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3882 .features[FEAT_7_0_ECX] = 3883 CPUID_7_0_ECX_PKU | 3884 CPUID_7_0_ECX_AVX512VNNI, 3885 .features[FEAT_7_0_EDX] = 3886 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3887 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3888 .features[FEAT_ARCH_CAPABILITIES] = 3889 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3890 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3891 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3892 .features[FEAT_7_1_EAX] = 3893 CPUID_7_1_EAX_AVX512_BF16, 3894 /* XSAVES is added in version 2 */ 3895 .features[FEAT_XSAVE] = 3896 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3897 CPUID_XSAVE_XGETBV1, 3898 .features[FEAT_6_EAX] = 3899 CPUID_6_EAX_ARAT, 3900 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3901 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3902 MSR_VMX_BASIC_TRUE_CTLS, 3903 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3904 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3905 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3906 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3907 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3908 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3909 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3910 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3911 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3912 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3913 .features[FEAT_VMX_EXIT_CTLS] = 3914 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3915 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3916 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3917 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3918 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3919 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3920 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3921 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3922 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3923 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3924 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3925 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3926 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3927 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3928 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3929 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3930 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3931 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3932 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3933 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3934 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3935 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3936 .features[FEAT_VMX_SECONDARY_CTLS] = 3937 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3938 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3939 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3940 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3941 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3942 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3943 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3944 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3945 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3946 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3947 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3948 .xlevel = 0x80000008, 3949 .model_id = "Intel Xeon Processor (Cooperlake)", 3950 .versions = (X86CPUVersionDefinition[]) { 3951 { .version = 1 }, 3952 { .version = 2, 3953 .note = "XSAVES", 3954 .props = (PropValue[]) { 3955 { "xsaves", "on" }, 3956 { "vmx-xsaves", "on" }, 3957 { /* end of list */ } 3958 }, 3959 }, 3960 { /* end of list */ } 3961 } 3962 }, 3963 { 3964 .name = "Icelake-Server", 3965 .level = 0xd, 3966 .vendor = CPUID_VENDOR_INTEL, 3967 .family = 6, 3968 .model = 134, 3969 .stepping = 0, 3970 .features[FEAT_1_EDX] = 3971 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3972 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3973 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3974 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3975 CPUID_DE | CPUID_FP87, 3976 .features[FEAT_1_ECX] = 3977 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3978 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3979 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3980 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3981 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3982 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3983 .features[FEAT_8000_0001_EDX] = 3984 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3985 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3986 .features[FEAT_8000_0001_ECX] = 3987 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3988 .features[FEAT_8000_0008_EBX] = 3989 CPUID_8000_0008_EBX_WBNOINVD, 3990 .features[FEAT_7_0_EBX] = 3991 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3992 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3993 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3994 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3995 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3996 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3997 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3998 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3999 .features[FEAT_7_0_ECX] = 4000 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4001 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4002 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4003 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4004 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4005 .features[FEAT_7_0_EDX] = 4006 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4007 /* XSAVES is added in version 5 */ 4008 .features[FEAT_XSAVE] = 4009 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4010 CPUID_XSAVE_XGETBV1, 4011 .features[FEAT_6_EAX] = 4012 CPUID_6_EAX_ARAT, 4013 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4014 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4015 MSR_VMX_BASIC_TRUE_CTLS, 4016 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4017 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4018 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4019 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4020 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4021 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4022 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4023 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4024 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4025 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4026 .features[FEAT_VMX_EXIT_CTLS] = 4027 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4028 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4029 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4030 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4031 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4032 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4033 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4034 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4035 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4036 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4037 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4038 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4039 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4040 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4041 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4042 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4043 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4044 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4045 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4046 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4047 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4048 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4049 .features[FEAT_VMX_SECONDARY_CTLS] = 4050 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4051 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4052 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4053 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4054 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4055 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4056 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4057 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4058 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4059 .xlevel = 0x80000008, 4060 .model_id = "Intel Xeon Processor (Icelake)", 4061 .versions = (X86CPUVersionDefinition[]) { 4062 { .version = 1 }, 4063 { 4064 .version = 2, 4065 .note = "no TSX", 4066 .alias = "Icelake-Server-noTSX", 4067 .props = (PropValue[]) { 4068 { "hle", "off" }, 4069 { "rtm", "off" }, 4070 { /* end of list */ } 4071 }, 4072 }, 4073 { 4074 .version = 3, 4075 .props = (PropValue[]) { 4076 { "arch-capabilities", "on" }, 4077 { "rdctl-no", "on" }, 4078 { "ibrs-all", "on" }, 4079 { "skip-l1dfl-vmentry", "on" }, 4080 { "mds-no", "on" }, 4081 { "pschange-mc-no", "on" }, 4082 { "taa-no", "on" }, 4083 { /* end of list */ } 4084 }, 4085 }, 4086 { 4087 .version = 4, 4088 .props = (PropValue[]) { 4089 { "sha-ni", "on" }, 4090 { "avx512ifma", "on" }, 4091 { "rdpid", "on" }, 4092 { "fsrm", "on" }, 4093 { "vmx-rdseed-exit", "on" }, 4094 { "vmx-pml", "on" }, 4095 { "vmx-eptp-switching", "on" }, 4096 { "model", "106" }, 4097 { /* end of list */ } 4098 }, 4099 }, 4100 { 4101 .version = 5, 4102 .note = "XSAVES", 4103 .props = (PropValue[]) { 4104 { "xsaves", "on" }, 4105 { "vmx-xsaves", "on" }, 4106 { /* end of list */ } 4107 }, 4108 }, 4109 { 4110 .version = 6, 4111 .note = "5-level EPT", 4112 .props = (PropValue[]) { 4113 { "vmx-page-walk-5", "on" }, 4114 { /* end of list */ } 4115 }, 4116 }, 4117 { 4118 .version = 7, 4119 .note = "TSX, taa-no", 4120 .props = (PropValue[]) { 4121 /* Restore TSX features removed by -v2 above */ 4122 { "hle", "on" }, 4123 { "rtm", "on" }, 4124 { /* end of list */ } 4125 }, 4126 }, 4127 { /* end of list */ } 4128 } 4129 }, 4130 { 4131 .name = "SapphireRapids", 4132 .level = 0x20, 4133 .vendor = CPUID_VENDOR_INTEL, 4134 .family = 6, 4135 .model = 143, 4136 .stepping = 4, 4137 /* 4138 * please keep the ascending order so that we can have a clear view of 4139 * bit position of each feature. 4140 */ 4141 .features[FEAT_1_EDX] = 4142 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4143 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4144 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4145 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4146 CPUID_SSE | CPUID_SSE2, 4147 .features[FEAT_1_ECX] = 4148 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4149 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4150 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4151 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4152 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4153 .features[FEAT_8000_0001_EDX] = 4154 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4155 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4156 .features[FEAT_8000_0001_ECX] = 4157 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4158 .features[FEAT_8000_0008_EBX] = 4159 CPUID_8000_0008_EBX_WBNOINVD, 4160 .features[FEAT_7_0_EBX] = 4161 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4162 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4163 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4164 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4165 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4166 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4167 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4168 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4169 .features[FEAT_7_0_ECX] = 4170 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4171 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4172 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4173 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4174 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4175 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4176 .features[FEAT_7_0_EDX] = 4177 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4178 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4179 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4180 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4181 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4182 .features[FEAT_ARCH_CAPABILITIES] = 4183 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4184 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4185 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4186 .features[FEAT_XSAVE] = 4187 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4188 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4189 .features[FEAT_6_EAX] = 4190 CPUID_6_EAX_ARAT, 4191 .features[FEAT_7_1_EAX] = 4192 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4193 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4194 .features[FEAT_VMX_BASIC] = 4195 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4196 .features[FEAT_VMX_ENTRY_CTLS] = 4197 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4198 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4199 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4200 .features[FEAT_VMX_EPT_VPID_CAPS] = 4201 MSR_VMX_EPT_EXECONLY | 4202 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4203 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4204 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4205 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4206 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4207 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4208 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4209 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4210 .features[FEAT_VMX_EXIT_CTLS] = 4211 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4212 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4213 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4214 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4215 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4216 .features[FEAT_VMX_MISC] = 4217 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4218 MSR_VMX_MISC_VMWRITE_VMEXIT, 4219 .features[FEAT_VMX_PINBASED_CTLS] = 4220 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4221 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4222 VMX_PIN_BASED_POSTED_INTR, 4223 .features[FEAT_VMX_PROCBASED_CTLS] = 4224 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4225 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4226 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4227 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4228 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4229 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4230 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4231 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4232 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4233 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4234 VMX_CPU_BASED_PAUSE_EXITING | 4235 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4236 .features[FEAT_VMX_SECONDARY_CTLS] = 4237 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4238 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4239 VMX_SECONDARY_EXEC_RDTSCP | 4240 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4241 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4242 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4243 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4244 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4245 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4246 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4247 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4248 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4249 VMX_SECONDARY_EXEC_XSAVES, 4250 .features[FEAT_VMX_VMFUNC] = 4251 MSR_VMX_VMFUNC_EPT_SWITCHING, 4252 .xlevel = 0x80000008, 4253 .model_id = "Intel Xeon Processor (SapphireRapids)", 4254 .versions = (X86CPUVersionDefinition[]) { 4255 { .version = 1 }, 4256 { 4257 .version = 2, 4258 .props = (PropValue[]) { 4259 { "sbdr-ssdp-no", "on" }, 4260 { "fbsdp-no", "on" }, 4261 { "psdp-no", "on" }, 4262 { /* end of list */ } 4263 } 4264 }, 4265 { 4266 .version = 3, 4267 .props = (PropValue[]) { 4268 { "ss", "on" }, 4269 { "tsc-adjust", "on" }, 4270 { "cldemote", "on" }, 4271 { "movdiri", "on" }, 4272 { "movdir64b", "on" }, 4273 { /* end of list */ } 4274 } 4275 }, 4276 { /* end of list */ } 4277 } 4278 }, 4279 { 4280 .name = "GraniteRapids", 4281 .level = 0x20, 4282 .vendor = CPUID_VENDOR_INTEL, 4283 .family = 6, 4284 .model = 173, 4285 .stepping = 0, 4286 /* 4287 * please keep the ascending order so that we can have a clear view of 4288 * bit position of each feature. 4289 */ 4290 .features[FEAT_1_EDX] = 4291 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4292 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4293 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4294 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4295 CPUID_SSE | CPUID_SSE2, 4296 .features[FEAT_1_ECX] = 4297 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4298 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4299 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4300 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4301 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4302 .features[FEAT_8000_0001_EDX] = 4303 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4304 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4305 .features[FEAT_8000_0001_ECX] = 4306 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4307 .features[FEAT_8000_0008_EBX] = 4308 CPUID_8000_0008_EBX_WBNOINVD, 4309 .features[FEAT_7_0_EBX] = 4310 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4311 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4312 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4313 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4314 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4315 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4316 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4317 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4318 .features[FEAT_7_0_ECX] = 4319 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4320 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4321 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4322 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4323 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4324 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4325 .features[FEAT_7_0_EDX] = 4326 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4327 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4328 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4329 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4330 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4331 .features[FEAT_ARCH_CAPABILITIES] = 4332 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4333 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4334 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4335 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4336 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4337 .features[FEAT_XSAVE] = 4338 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4339 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4340 .features[FEAT_6_EAX] = 4341 CPUID_6_EAX_ARAT, 4342 .features[FEAT_7_1_EAX] = 4343 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4344 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4345 CPUID_7_1_EAX_AMX_FP16, 4346 .features[FEAT_7_1_EDX] = 4347 CPUID_7_1_EDX_PREFETCHITI, 4348 .features[FEAT_7_2_EDX] = 4349 CPUID_7_2_EDX_MCDT_NO, 4350 .features[FEAT_VMX_BASIC] = 4351 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4352 .features[FEAT_VMX_ENTRY_CTLS] = 4353 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4354 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4355 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4356 .features[FEAT_VMX_EPT_VPID_CAPS] = 4357 MSR_VMX_EPT_EXECONLY | 4358 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4359 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4360 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4361 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4362 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4363 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4364 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4365 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4366 .features[FEAT_VMX_EXIT_CTLS] = 4367 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4368 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4369 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4370 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4371 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4372 .features[FEAT_VMX_MISC] = 4373 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4374 MSR_VMX_MISC_VMWRITE_VMEXIT, 4375 .features[FEAT_VMX_PINBASED_CTLS] = 4376 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4377 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4378 VMX_PIN_BASED_POSTED_INTR, 4379 .features[FEAT_VMX_PROCBASED_CTLS] = 4380 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4381 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4382 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4383 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4384 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4385 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4386 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4387 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4388 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4389 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4390 VMX_CPU_BASED_PAUSE_EXITING | 4391 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4392 .features[FEAT_VMX_SECONDARY_CTLS] = 4393 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4394 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4395 VMX_SECONDARY_EXEC_RDTSCP | 4396 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4397 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4398 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4399 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4400 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4401 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4402 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4403 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4404 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4405 VMX_SECONDARY_EXEC_XSAVES, 4406 .features[FEAT_VMX_VMFUNC] = 4407 MSR_VMX_VMFUNC_EPT_SWITCHING, 4408 .xlevel = 0x80000008, 4409 .model_id = "Intel Xeon Processor (GraniteRapids)", 4410 .versions = (X86CPUVersionDefinition[]) { 4411 { .version = 1 }, 4412 { 4413 .version = 2, 4414 .props = (PropValue[]) { 4415 { "ss", "on" }, 4416 { "tsc-adjust", "on" }, 4417 { "cldemote", "on" }, 4418 { "movdiri", "on" }, 4419 { "movdir64b", "on" }, 4420 { "avx10", "on" }, 4421 { "avx10-128", "on" }, 4422 { "avx10-256", "on" }, 4423 { "avx10-512", "on" }, 4424 { "avx10-version", "1" }, 4425 { "stepping", "1" }, 4426 { /* end of list */ } 4427 } 4428 }, 4429 { /* end of list */ }, 4430 }, 4431 }, 4432 { 4433 .name = "SierraForest", 4434 .level = 0x23, 4435 .vendor = CPUID_VENDOR_INTEL, 4436 .family = 6, 4437 .model = 175, 4438 .stepping = 0, 4439 /* 4440 * please keep the ascending order so that we can have a clear view of 4441 * bit position of each feature. 4442 */ 4443 .features[FEAT_1_EDX] = 4444 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4445 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4446 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4447 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4448 CPUID_SSE | CPUID_SSE2, 4449 .features[FEAT_1_ECX] = 4450 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4451 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4452 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4453 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4454 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4455 .features[FEAT_8000_0001_EDX] = 4456 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4457 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4458 .features[FEAT_8000_0001_ECX] = 4459 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4460 .features[FEAT_8000_0008_EBX] = 4461 CPUID_8000_0008_EBX_WBNOINVD, 4462 .features[FEAT_7_0_EBX] = 4463 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4464 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4465 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4466 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4467 CPUID_7_0_EBX_SHA_NI, 4468 .features[FEAT_7_0_ECX] = 4469 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4470 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4471 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4472 .features[FEAT_7_0_EDX] = 4473 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4474 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4475 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4476 .features[FEAT_ARCH_CAPABILITIES] = 4477 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4478 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4479 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4480 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4481 MSR_ARCH_CAP_PBRSB_NO, 4482 .features[FEAT_XSAVE] = 4483 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4484 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4485 .features[FEAT_6_EAX] = 4486 CPUID_6_EAX_ARAT, 4487 .features[FEAT_7_1_EAX] = 4488 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4489 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4490 .features[FEAT_7_1_EDX] = 4491 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4492 .features[FEAT_7_2_EDX] = 4493 CPUID_7_2_EDX_MCDT_NO, 4494 .features[FEAT_VMX_BASIC] = 4495 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4496 .features[FEAT_VMX_ENTRY_CTLS] = 4497 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4498 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4499 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4500 .features[FEAT_VMX_EPT_VPID_CAPS] = 4501 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4502 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4503 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4504 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4505 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4506 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4507 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4508 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4509 .features[FEAT_VMX_EXIT_CTLS] = 4510 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4511 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4512 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4513 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4514 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4515 .features[FEAT_VMX_MISC] = 4516 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4517 MSR_VMX_MISC_VMWRITE_VMEXIT, 4518 .features[FEAT_VMX_PINBASED_CTLS] = 4519 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4520 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4521 VMX_PIN_BASED_POSTED_INTR, 4522 .features[FEAT_VMX_PROCBASED_CTLS] = 4523 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4524 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4525 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4526 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4527 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4528 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4529 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4530 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4531 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4532 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4533 VMX_CPU_BASED_PAUSE_EXITING | 4534 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4535 .features[FEAT_VMX_SECONDARY_CTLS] = 4536 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4537 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4538 VMX_SECONDARY_EXEC_RDTSCP | 4539 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4540 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4541 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4542 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4543 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4544 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4545 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4546 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4547 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4548 VMX_SECONDARY_EXEC_XSAVES, 4549 .features[FEAT_VMX_VMFUNC] = 4550 MSR_VMX_VMFUNC_EPT_SWITCHING, 4551 .xlevel = 0x80000008, 4552 .model_id = "Intel Xeon Processor (SierraForest)", 4553 .versions = (X86CPUVersionDefinition[]) { 4554 { .version = 1 }, 4555 { 4556 .version = 2, 4557 .props = (PropValue[]) { 4558 { "ss", "on" }, 4559 { "tsc-adjust", "on" }, 4560 { "cldemote", "on" }, 4561 { "movdiri", "on" }, 4562 { "movdir64b", "on" }, 4563 { "gds-no", "on" }, 4564 { "rfds-no", "on" }, 4565 { "lam", "on" }, 4566 { "intel-psfd", "on"}, 4567 { "ipred-ctrl", "on"}, 4568 { "rrsba-ctrl", "on"}, 4569 { "bhi-ctrl", "on"}, 4570 { "stepping", "3" }, 4571 { /* end of list */ } 4572 } 4573 }, 4574 { /* end of list */ }, 4575 }, 4576 }, 4577 { 4578 .name = "ClearwaterForest", 4579 .level = 0x23, 4580 .xlevel = 0x80000008, 4581 .vendor = CPUID_VENDOR_INTEL, 4582 .family = 6, 4583 .model = 221, 4584 .stepping = 0, 4585 /* 4586 * please keep the ascending order so that we can have a clear view of 4587 * bit position of each feature. 4588 */ 4589 .features[FEAT_1_EDX] = 4590 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4591 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4592 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4593 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4594 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 4595 .features[FEAT_1_ECX] = 4596 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4597 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4598 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4599 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4600 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4601 .features[FEAT_8000_0001_EDX] = 4602 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4603 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4604 .features[FEAT_8000_0001_ECX] = 4605 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4606 .features[FEAT_8000_0008_EBX] = 4607 CPUID_8000_0008_EBX_WBNOINVD, 4608 .features[FEAT_7_0_EBX] = 4609 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 4610 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4611 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4612 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4613 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4614 CPUID_7_0_EBX_SHA_NI, 4615 .features[FEAT_7_0_ECX] = 4616 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4617 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4618 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 4619 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 4620 CPUID_7_0_ECX_MOVDIR64B, 4621 .features[FEAT_7_0_EDX] = 4622 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4623 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4624 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4625 .features[FEAT_ARCH_CAPABILITIES] = 4626 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4627 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4628 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4629 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4630 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 4631 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 4632 .features[FEAT_XSAVE] = 4633 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4634 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4635 .features[FEAT_6_EAX] = 4636 CPUID_6_EAX_ARAT, 4637 .features[FEAT_7_1_EAX] = 4638 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 4639 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4640 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 4641 CPUID_7_1_EAX_LAM, 4642 .features[FEAT_7_1_EDX] = 4643 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 4644 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 4645 .features[FEAT_7_2_EDX] = 4646 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 4647 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 4648 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 4649 .features[FEAT_VMX_BASIC] = 4650 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4651 .features[FEAT_VMX_ENTRY_CTLS] = 4652 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4653 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4654 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4655 .features[FEAT_VMX_EPT_VPID_CAPS] = 4656 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4657 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4658 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4659 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4660 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4661 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4662 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4663 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4664 .features[FEAT_VMX_EXIT_CTLS] = 4665 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4666 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4667 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4668 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4669 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4670 .features[FEAT_VMX_MISC] = 4671 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4672 MSR_VMX_MISC_VMWRITE_VMEXIT, 4673 .features[FEAT_VMX_PINBASED_CTLS] = 4674 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4675 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4676 VMX_PIN_BASED_POSTED_INTR, 4677 .features[FEAT_VMX_PROCBASED_CTLS] = 4678 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4679 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4680 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4681 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4682 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4683 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4684 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4685 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4686 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4687 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4688 VMX_CPU_BASED_PAUSE_EXITING | 4689 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4690 .features[FEAT_VMX_SECONDARY_CTLS] = 4691 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4692 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4693 VMX_SECONDARY_EXEC_RDTSCP | 4694 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4695 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4696 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4697 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4698 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4699 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4700 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4701 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4702 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4703 VMX_SECONDARY_EXEC_XSAVES, 4704 .features[FEAT_VMX_VMFUNC] = 4705 MSR_VMX_VMFUNC_EPT_SWITCHING, 4706 .model_id = "Intel Xeon Processor (ClearwaterForest)", 4707 .versions = (X86CPUVersionDefinition[]) { 4708 { .version = 1 }, 4709 { /* end of list */ }, 4710 }, 4711 }, 4712 { 4713 .name = "Denverton", 4714 .level = 21, 4715 .vendor = CPUID_VENDOR_INTEL, 4716 .family = 6, 4717 .model = 95, 4718 .stepping = 1, 4719 .features[FEAT_1_EDX] = 4720 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4721 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4722 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4723 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4724 CPUID_SSE | CPUID_SSE2, 4725 .features[FEAT_1_ECX] = 4726 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4727 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4728 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4729 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4730 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4731 .features[FEAT_8000_0001_EDX] = 4732 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4733 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4734 .features[FEAT_8000_0001_ECX] = 4735 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4736 .features[FEAT_7_0_EBX] = 4737 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4738 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4739 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4740 .features[FEAT_7_0_EDX] = 4741 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4742 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4743 /* XSAVES is added in version 3 */ 4744 .features[FEAT_XSAVE] = 4745 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4746 .features[FEAT_6_EAX] = 4747 CPUID_6_EAX_ARAT, 4748 .features[FEAT_ARCH_CAPABILITIES] = 4749 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4750 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4751 MSR_VMX_BASIC_TRUE_CTLS, 4752 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4753 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4754 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4755 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4756 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4757 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4758 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4759 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4760 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4761 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4762 .features[FEAT_VMX_EXIT_CTLS] = 4763 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4764 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4765 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4766 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4767 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4768 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4769 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4770 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4771 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4772 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4773 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4774 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4775 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4776 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4777 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4778 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4779 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4780 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4781 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4782 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4783 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4784 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4785 .features[FEAT_VMX_SECONDARY_CTLS] = 4786 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4787 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4788 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4789 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4790 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4791 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4792 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4793 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4794 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4795 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4796 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4797 .xlevel = 0x80000008, 4798 .model_id = "Intel Atom Processor (Denverton)", 4799 .versions = (X86CPUVersionDefinition[]) { 4800 { .version = 1 }, 4801 { 4802 .version = 2, 4803 .note = "no MPX, no MONITOR", 4804 .props = (PropValue[]) { 4805 { "monitor", "off" }, 4806 { "mpx", "off" }, 4807 { /* end of list */ }, 4808 }, 4809 }, 4810 { 4811 .version = 3, 4812 .note = "XSAVES, no MPX, no MONITOR", 4813 .props = (PropValue[]) { 4814 { "xsaves", "on" }, 4815 { "vmx-xsaves", "on" }, 4816 { /* end of list */ }, 4817 }, 4818 }, 4819 { /* end of list */ }, 4820 }, 4821 }, 4822 { 4823 .name = "Snowridge", 4824 .level = 27, 4825 .vendor = CPUID_VENDOR_INTEL, 4826 .family = 6, 4827 .model = 134, 4828 .stepping = 1, 4829 .features[FEAT_1_EDX] = 4830 /* missing: CPUID_PN CPUID_IA64 */ 4831 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4832 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4833 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4834 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4835 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4836 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4837 CPUID_MMX | 4838 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4839 .features[FEAT_1_ECX] = 4840 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4841 CPUID_EXT_SSSE3 | 4842 CPUID_EXT_CX16 | 4843 CPUID_EXT_SSE41 | 4844 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4845 CPUID_EXT_POPCNT | 4846 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4847 CPUID_EXT_RDRAND, 4848 .features[FEAT_8000_0001_EDX] = 4849 CPUID_EXT2_SYSCALL | 4850 CPUID_EXT2_NX | 4851 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4852 CPUID_EXT2_LM, 4853 .features[FEAT_8000_0001_ECX] = 4854 CPUID_EXT3_LAHF_LM | 4855 CPUID_EXT3_3DNOWPREFETCH, 4856 .features[FEAT_7_0_EBX] = 4857 CPUID_7_0_EBX_FSGSBASE | 4858 CPUID_7_0_EBX_SMEP | 4859 CPUID_7_0_EBX_ERMS | 4860 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4861 CPUID_7_0_EBX_RDSEED | 4862 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4863 CPUID_7_0_EBX_CLWB | 4864 CPUID_7_0_EBX_SHA_NI, 4865 .features[FEAT_7_0_ECX] = 4866 CPUID_7_0_ECX_UMIP | 4867 /* missing bit 5 */ 4868 CPUID_7_0_ECX_GFNI | 4869 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4870 CPUID_7_0_ECX_MOVDIR64B, 4871 .features[FEAT_7_0_EDX] = 4872 CPUID_7_0_EDX_SPEC_CTRL | 4873 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4874 CPUID_7_0_EDX_CORE_CAPABILITY, 4875 .features[FEAT_CORE_CAPABILITY] = 4876 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4877 /* XSAVES is added in version 3 */ 4878 .features[FEAT_XSAVE] = 4879 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4880 CPUID_XSAVE_XGETBV1, 4881 .features[FEAT_6_EAX] = 4882 CPUID_6_EAX_ARAT, 4883 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4884 MSR_VMX_BASIC_TRUE_CTLS, 4885 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4886 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4887 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4888 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4889 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4890 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4891 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4892 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4893 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4894 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4895 .features[FEAT_VMX_EXIT_CTLS] = 4896 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4897 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4898 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4899 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4900 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4901 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4902 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4903 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4904 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4905 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4906 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4907 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4908 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4909 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4910 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4911 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4912 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4913 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4914 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4915 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4916 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4917 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4918 .features[FEAT_VMX_SECONDARY_CTLS] = 4919 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4920 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4921 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4922 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4923 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4924 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4925 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4926 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4927 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4928 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4929 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4930 .xlevel = 0x80000008, 4931 .model_id = "Intel Atom Processor (SnowRidge)", 4932 .versions = (X86CPUVersionDefinition[]) { 4933 { .version = 1 }, 4934 { 4935 .version = 2, 4936 .props = (PropValue[]) { 4937 { "mpx", "off" }, 4938 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4939 { /* end of list */ }, 4940 }, 4941 }, 4942 { 4943 .version = 3, 4944 .note = "XSAVES, no MPX", 4945 .props = (PropValue[]) { 4946 { "xsaves", "on" }, 4947 { "vmx-xsaves", "on" }, 4948 { /* end of list */ }, 4949 }, 4950 }, 4951 { 4952 .version = 4, 4953 .note = "no split lock detect, no core-capability", 4954 .props = (PropValue[]) { 4955 { "split-lock-detect", "off" }, 4956 { "core-capability", "off" }, 4957 { /* end of list */ }, 4958 }, 4959 }, 4960 { /* end of list */ }, 4961 }, 4962 }, 4963 { 4964 .name = "KnightsMill", 4965 .level = 0xd, 4966 .vendor = CPUID_VENDOR_INTEL, 4967 .family = 6, 4968 .model = 133, 4969 .stepping = 0, 4970 .features[FEAT_1_EDX] = 4971 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4972 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4973 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4974 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4975 CPUID_PSE | CPUID_DE | CPUID_FP87, 4976 .features[FEAT_1_ECX] = 4977 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4978 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4979 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4980 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4981 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4982 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4983 .features[FEAT_8000_0001_EDX] = 4984 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4985 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4986 .features[FEAT_8000_0001_ECX] = 4987 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4988 .features[FEAT_7_0_EBX] = 4989 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4990 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4991 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4992 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4993 CPUID_7_0_EBX_AVX512ER, 4994 .features[FEAT_7_0_ECX] = 4995 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4996 .features[FEAT_7_0_EDX] = 4997 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4998 .features[FEAT_XSAVE] = 4999 CPUID_XSAVE_XSAVEOPT, 5000 .features[FEAT_6_EAX] = 5001 CPUID_6_EAX_ARAT, 5002 .xlevel = 0x80000008, 5003 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5004 }, 5005 { 5006 .name = "Opteron_G1", 5007 .level = 5, 5008 .vendor = CPUID_VENDOR_AMD, 5009 .family = 15, 5010 .model = 6, 5011 .stepping = 1, 5012 .features[FEAT_1_EDX] = 5013 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5014 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5015 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5016 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5017 CPUID_DE | CPUID_FP87, 5018 .features[FEAT_1_ECX] = 5019 CPUID_EXT_SSE3, 5020 .features[FEAT_8000_0001_EDX] = 5021 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5022 .xlevel = 0x80000008, 5023 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5024 }, 5025 { 5026 .name = "Opteron_G2", 5027 .level = 5, 5028 .vendor = CPUID_VENDOR_AMD, 5029 .family = 15, 5030 .model = 6, 5031 .stepping = 1, 5032 .features[FEAT_1_EDX] = 5033 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5034 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5035 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5036 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5037 CPUID_DE | CPUID_FP87, 5038 .features[FEAT_1_ECX] = 5039 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5040 .features[FEAT_8000_0001_EDX] = 5041 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5042 .features[FEAT_8000_0001_ECX] = 5043 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5044 .xlevel = 0x80000008, 5045 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5046 }, 5047 { 5048 .name = "Opteron_G3", 5049 .level = 5, 5050 .vendor = CPUID_VENDOR_AMD, 5051 .family = 16, 5052 .model = 2, 5053 .stepping = 3, 5054 .features[FEAT_1_EDX] = 5055 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5056 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5057 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5058 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5059 CPUID_DE | CPUID_FP87, 5060 .features[FEAT_1_ECX] = 5061 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5062 CPUID_EXT_SSE3, 5063 .features[FEAT_8000_0001_EDX] = 5064 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5065 CPUID_EXT2_RDTSCP, 5066 .features[FEAT_8000_0001_ECX] = 5067 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5068 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5069 .xlevel = 0x80000008, 5070 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5071 }, 5072 { 5073 .name = "Opteron_G4", 5074 .level = 0xd, 5075 .vendor = CPUID_VENDOR_AMD, 5076 .family = 21, 5077 .model = 1, 5078 .stepping = 2, 5079 .features[FEAT_1_EDX] = 5080 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5081 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5082 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5083 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5084 CPUID_DE | CPUID_FP87, 5085 .features[FEAT_1_ECX] = 5086 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5087 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5088 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5089 CPUID_EXT_SSE3, 5090 .features[FEAT_8000_0001_EDX] = 5091 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5092 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5093 .features[FEAT_8000_0001_ECX] = 5094 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5095 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5096 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5097 CPUID_EXT3_LAHF_LM, 5098 .features[FEAT_SVM] = 5099 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5100 /* no xsaveopt! */ 5101 .xlevel = 0x8000001A, 5102 .model_id = "AMD Opteron 62xx class CPU", 5103 }, 5104 { 5105 .name = "Opteron_G5", 5106 .level = 0xd, 5107 .vendor = CPUID_VENDOR_AMD, 5108 .family = 21, 5109 .model = 2, 5110 .stepping = 0, 5111 .features[FEAT_1_EDX] = 5112 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5113 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5114 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5115 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5116 CPUID_DE | CPUID_FP87, 5117 .features[FEAT_1_ECX] = 5118 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5119 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5120 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5121 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5122 .features[FEAT_8000_0001_EDX] = 5123 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5124 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5125 .features[FEAT_8000_0001_ECX] = 5126 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5127 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5128 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5129 CPUID_EXT3_LAHF_LM, 5130 .features[FEAT_SVM] = 5131 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5132 /* no xsaveopt! */ 5133 .xlevel = 0x8000001A, 5134 .model_id = "AMD Opteron 63xx class CPU", 5135 }, 5136 { 5137 .name = "EPYC", 5138 .level = 0xd, 5139 .vendor = CPUID_VENDOR_AMD, 5140 .family = 23, 5141 .model = 1, 5142 .stepping = 2, 5143 .features[FEAT_1_EDX] = 5144 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5145 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5146 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5147 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5148 CPUID_VME | CPUID_FP87, 5149 .features[FEAT_1_ECX] = 5150 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5151 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5152 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5153 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5154 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5155 .features[FEAT_8000_0001_EDX] = 5156 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5157 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5158 CPUID_EXT2_SYSCALL, 5159 .features[FEAT_8000_0001_ECX] = 5160 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5161 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5162 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5163 CPUID_EXT3_TOPOEXT, 5164 .features[FEAT_7_0_EBX] = 5165 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5166 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5167 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5168 CPUID_7_0_EBX_SHA_NI, 5169 .features[FEAT_XSAVE] = 5170 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5171 CPUID_XSAVE_XGETBV1, 5172 .features[FEAT_6_EAX] = 5173 CPUID_6_EAX_ARAT, 5174 .features[FEAT_SVM] = 5175 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5176 .xlevel = 0x8000001E, 5177 .model_id = "AMD EPYC Processor", 5178 .cache_info = &epyc_cache_info, 5179 .versions = (X86CPUVersionDefinition[]) { 5180 { .version = 1 }, 5181 { 5182 .version = 2, 5183 .alias = "EPYC-IBPB", 5184 .props = (PropValue[]) { 5185 { "ibpb", "on" }, 5186 { "model-id", 5187 "AMD EPYC Processor (with IBPB)" }, 5188 { /* end of list */ } 5189 } 5190 }, 5191 { 5192 .version = 3, 5193 .props = (PropValue[]) { 5194 { "ibpb", "on" }, 5195 { "perfctr-core", "on" }, 5196 { "clzero", "on" }, 5197 { "xsaveerptr", "on" }, 5198 { "xsaves", "on" }, 5199 { "model-id", 5200 "AMD EPYC Processor" }, 5201 { /* end of list */ } 5202 } 5203 }, 5204 { 5205 .version = 4, 5206 .props = (PropValue[]) { 5207 { "model-id", 5208 "AMD EPYC-v4 Processor" }, 5209 { /* end of list */ } 5210 }, 5211 .cache_info = &epyc_v4_cache_info 5212 }, 5213 { /* end of list */ } 5214 } 5215 }, 5216 { 5217 .name = "Dhyana", 5218 .level = 0xd, 5219 .vendor = CPUID_VENDOR_HYGON, 5220 .family = 24, 5221 .model = 0, 5222 .stepping = 1, 5223 .features[FEAT_1_EDX] = 5224 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5225 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5226 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5227 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5228 CPUID_VME | CPUID_FP87, 5229 .features[FEAT_1_ECX] = 5230 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5231 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5232 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5233 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5234 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5235 .features[FEAT_8000_0001_EDX] = 5236 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5237 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5238 CPUID_EXT2_SYSCALL, 5239 .features[FEAT_8000_0001_ECX] = 5240 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5241 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5242 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5243 CPUID_EXT3_TOPOEXT, 5244 .features[FEAT_8000_0008_EBX] = 5245 CPUID_8000_0008_EBX_IBPB, 5246 .features[FEAT_7_0_EBX] = 5247 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5248 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5249 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5250 /* XSAVES is added in version 2 */ 5251 .features[FEAT_XSAVE] = 5252 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5253 CPUID_XSAVE_XGETBV1, 5254 .features[FEAT_6_EAX] = 5255 CPUID_6_EAX_ARAT, 5256 .features[FEAT_SVM] = 5257 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5258 .xlevel = 0x8000001E, 5259 .model_id = "Hygon Dhyana Processor", 5260 .cache_info = &epyc_cache_info, 5261 .versions = (X86CPUVersionDefinition[]) { 5262 { .version = 1 }, 5263 { .version = 2, 5264 .note = "XSAVES", 5265 .props = (PropValue[]) { 5266 { "xsaves", "on" }, 5267 { /* end of list */ } 5268 }, 5269 }, 5270 { /* end of list */ } 5271 } 5272 }, 5273 { 5274 .name = "EPYC-Rome", 5275 .level = 0xd, 5276 .vendor = CPUID_VENDOR_AMD, 5277 .family = 23, 5278 .model = 49, 5279 .stepping = 0, 5280 .features[FEAT_1_EDX] = 5281 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5282 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5283 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5284 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5285 CPUID_VME | CPUID_FP87, 5286 .features[FEAT_1_ECX] = 5287 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5288 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5289 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5290 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5291 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5292 .features[FEAT_8000_0001_EDX] = 5293 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5294 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5295 CPUID_EXT2_SYSCALL, 5296 .features[FEAT_8000_0001_ECX] = 5297 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5298 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5299 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5300 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5301 .features[FEAT_8000_0008_EBX] = 5302 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5303 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5304 CPUID_8000_0008_EBX_STIBP, 5305 .features[FEAT_7_0_EBX] = 5306 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5307 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5308 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5309 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5310 .features[FEAT_7_0_ECX] = 5311 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5312 .features[FEAT_XSAVE] = 5313 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5314 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5315 .features[FEAT_6_EAX] = 5316 CPUID_6_EAX_ARAT, 5317 .features[FEAT_SVM] = 5318 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5319 .xlevel = 0x8000001E, 5320 .model_id = "AMD EPYC-Rome Processor", 5321 .cache_info = &epyc_rome_cache_info, 5322 .versions = (X86CPUVersionDefinition[]) { 5323 { .version = 1 }, 5324 { 5325 .version = 2, 5326 .props = (PropValue[]) { 5327 { "ibrs", "on" }, 5328 { "amd-ssbd", "on" }, 5329 { /* end of list */ } 5330 } 5331 }, 5332 { 5333 .version = 3, 5334 .props = (PropValue[]) { 5335 { "model-id", 5336 "AMD EPYC-Rome-v3 Processor" }, 5337 { /* end of list */ } 5338 }, 5339 .cache_info = &epyc_rome_v3_cache_info 5340 }, 5341 { 5342 .version = 4, 5343 .props = (PropValue[]) { 5344 /* Erratum 1386 */ 5345 { "model-id", 5346 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5347 { "xsaves", "off" }, 5348 { /* end of list */ } 5349 }, 5350 }, 5351 { /* end of list */ } 5352 } 5353 }, 5354 { 5355 .name = "EPYC-Milan", 5356 .level = 0xd, 5357 .vendor = CPUID_VENDOR_AMD, 5358 .family = 25, 5359 .model = 1, 5360 .stepping = 1, 5361 .features[FEAT_1_EDX] = 5362 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5363 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5364 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5365 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5366 CPUID_VME | CPUID_FP87, 5367 .features[FEAT_1_ECX] = 5368 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5369 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5370 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5371 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5372 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5373 CPUID_EXT_PCID, 5374 .features[FEAT_8000_0001_EDX] = 5375 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5376 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5377 CPUID_EXT2_SYSCALL, 5378 .features[FEAT_8000_0001_ECX] = 5379 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5380 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5381 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5382 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5383 .features[FEAT_8000_0008_EBX] = 5384 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5385 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5386 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5387 CPUID_8000_0008_EBX_AMD_SSBD, 5388 .features[FEAT_7_0_EBX] = 5389 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5390 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5391 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5392 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5393 CPUID_7_0_EBX_INVPCID, 5394 .features[FEAT_7_0_ECX] = 5395 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5396 .features[FEAT_7_0_EDX] = 5397 CPUID_7_0_EDX_FSRM, 5398 .features[FEAT_XSAVE] = 5399 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5400 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5401 .features[FEAT_6_EAX] = 5402 CPUID_6_EAX_ARAT, 5403 .features[FEAT_SVM] = 5404 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5405 .xlevel = 0x8000001E, 5406 .model_id = "AMD EPYC-Milan Processor", 5407 .cache_info = &epyc_milan_cache_info, 5408 .versions = (X86CPUVersionDefinition[]) { 5409 { .version = 1 }, 5410 { 5411 .version = 2, 5412 .props = (PropValue[]) { 5413 { "model-id", 5414 "AMD EPYC-Milan-v2 Processor" }, 5415 { "vaes", "on" }, 5416 { "vpclmulqdq", "on" }, 5417 { "stibp-always-on", "on" }, 5418 { "amd-psfd", "on" }, 5419 { "no-nested-data-bp", "on" }, 5420 { "lfence-always-serializing", "on" }, 5421 { "null-sel-clr-base", "on" }, 5422 { /* end of list */ } 5423 }, 5424 .cache_info = &epyc_milan_v2_cache_info 5425 }, 5426 { /* end of list */ } 5427 } 5428 }, 5429 { 5430 .name = "EPYC-Genoa", 5431 .level = 0xd, 5432 .vendor = CPUID_VENDOR_AMD, 5433 .family = 25, 5434 .model = 17, 5435 .stepping = 0, 5436 .features[FEAT_1_EDX] = 5437 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5438 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5439 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5440 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5441 CPUID_VME | CPUID_FP87, 5442 .features[FEAT_1_ECX] = 5443 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5444 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5445 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5446 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5447 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5448 CPUID_EXT_SSE3, 5449 .features[FEAT_8000_0001_EDX] = 5450 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5451 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5452 CPUID_EXT2_SYSCALL, 5453 .features[FEAT_8000_0001_ECX] = 5454 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5455 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5456 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5457 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5458 .features[FEAT_8000_0008_EBX] = 5459 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5460 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5461 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5462 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5463 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5464 .features[FEAT_8000_0021_EAX] = 5465 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5466 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5467 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5468 CPUID_8000_0021_EAX_AUTO_IBRS, 5469 .features[FEAT_7_0_EBX] = 5470 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5471 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5472 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5473 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5474 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5475 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5476 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5477 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5478 .features[FEAT_7_0_ECX] = 5479 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5480 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5481 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5482 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5483 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5484 CPUID_7_0_ECX_RDPID, 5485 .features[FEAT_7_0_EDX] = 5486 CPUID_7_0_EDX_FSRM, 5487 .features[FEAT_7_1_EAX] = 5488 CPUID_7_1_EAX_AVX512_BF16, 5489 .features[FEAT_XSAVE] = 5490 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5491 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5492 .features[FEAT_6_EAX] = 5493 CPUID_6_EAX_ARAT, 5494 .features[FEAT_SVM] = 5495 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5496 CPUID_SVM_SVME_ADDR_CHK, 5497 .xlevel = 0x80000022, 5498 .model_id = "AMD EPYC-Genoa Processor", 5499 .cache_info = &epyc_genoa_cache_info, 5500 }, 5501 { 5502 .name = "YongFeng", 5503 .level = 0x1F, 5504 .vendor = CPUID_VENDOR_ZHAOXIN1, 5505 .family = 7, 5506 .model = 11, 5507 .stepping = 3, 5508 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 5509 .features[FEAT_1_EDX] = 5510 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5511 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5512 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5513 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5514 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 5515 /* 5516 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 5517 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 5518 */ 5519 .features[FEAT_1_ECX] = 5520 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5521 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 5522 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 5523 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 5524 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5525 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5526 .features[FEAT_7_0_EBX] = 5527 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 5528 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 5529 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 5530 CPUID_7_0_EBX_FSGSBASE, 5531 /* missing: CPUID_7_0_ECX_OSPKE */ 5532 .features[FEAT_7_0_ECX] = 5533 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 5534 .features[FEAT_7_0_EDX] = 5535 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 5536 .features[FEAT_8000_0001_EDX] = 5537 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5538 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5539 .features[FEAT_8000_0001_ECX] = 5540 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 5541 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 5542 /* 5543 * TODO: When the Linux kernel introduces other existing definitions 5544 * for this leaf, remember to update the definitions here. 5545 */ 5546 .features[FEAT_C000_0001_EDX] = 5547 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 5548 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 5549 CPUID_C000_0001_EDX_ACE2 | 5550 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 5551 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 5552 .features[FEAT_XSAVE] = 5553 CPUID_XSAVE_XSAVEOPT, 5554 .features[FEAT_ARCH_CAPABILITIES] = 5555 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 5556 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 5557 MSR_ARCH_CAP_SSB_NO, 5558 .features[FEAT_VMX_PROCBASED_CTLS] = 5559 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 5560 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 5561 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 5562 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 5563 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 5564 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 5565 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 5566 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5567 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 5568 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5569 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5570 /* 5571 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 5572 * VMX_SECONDARY_EXEC_TSC_SCALING 5573 */ 5574 .features[FEAT_VMX_SECONDARY_CTLS] = 5575 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5576 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5577 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 5578 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5579 VMX_SECONDARY_EXEC_WBINVD_EXITING | 5580 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5581 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5582 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5583 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5584 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5585 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 5586 VMX_SECONDARY_EXEC_SHADOW_VMCS | 5587 VMX_SECONDARY_EXEC_ENABLE_PML, 5588 .features[FEAT_VMX_PINBASED_CTLS] = 5589 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5590 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5591 VMX_PIN_BASED_POSTED_INTR, 5592 .features[FEAT_VMX_EXIT_CTLS] = 5593 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 5594 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5595 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5596 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5597 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5598 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 5599 .features[FEAT_VMX_ENTRY_CTLS] = 5600 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5601 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5602 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5603 /* 5604 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 5605 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 5606 */ 5607 .features[FEAT_VMX_MISC] = 5608 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5609 MSR_VMX_MISC_VMWRITE_VMEXIT, 5610 /* missing: MSR_VMX_EPT_UC */ 5611 .features[FEAT_VMX_EPT_VPID_CAPS] = 5612 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5613 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5614 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5615 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5616 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 5617 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5618 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5619 .features[FEAT_VMX_BASIC] = 5620 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5621 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5622 .xlevel = 0x80000008, 5623 .model_id = "Zhaoxin YongFeng Processor", 5624 }, 5625 }; 5626 5627 /* 5628 * We resolve CPU model aliases using -v1 when using "-machine 5629 * none", but this is just for compatibility while libvirt isn't 5630 * adapted to resolve CPU model versions before creating VMs. 5631 * See "Runnability guarantee of CPU models" at 5632 * docs/about/deprecated.rst. 5633 */ 5634 X86CPUVersion default_cpu_version = 1; 5635 5636 void x86_cpu_set_default_version(X86CPUVersion version) 5637 { 5638 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5639 assert(version != CPU_VERSION_AUTO); 5640 default_cpu_version = version; 5641 } 5642 5643 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5644 { 5645 int v = 0; 5646 const X86CPUVersionDefinition *vdef = 5647 x86_cpu_def_get_versions(model->cpudef); 5648 while (vdef->version) { 5649 v = vdef->version; 5650 vdef++; 5651 } 5652 return v; 5653 } 5654 5655 /* Return the actual version being used for a specific CPU model */ 5656 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5657 { 5658 X86CPUVersion v = model->version; 5659 if (v == CPU_VERSION_AUTO) { 5660 v = default_cpu_version; 5661 } 5662 if (v == CPU_VERSION_LATEST) { 5663 return x86_cpu_model_last_version(model); 5664 } 5665 return v; 5666 } 5667 5668 static const Property max_x86_cpu_properties[] = { 5669 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5670 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5671 }; 5672 5673 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5674 { 5675 Object *obj = OBJECT(dev); 5676 5677 if (!object_property_get_int(obj, "family", &error_abort)) { 5678 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5679 object_property_set_int(obj, "family", 15, &error_abort); 5680 object_property_set_int(obj, "model", 107, &error_abort); 5681 object_property_set_int(obj, "stepping", 1, &error_abort); 5682 } else { 5683 object_property_set_int(obj, "family", 6, &error_abort); 5684 object_property_set_int(obj, "model", 6, &error_abort); 5685 object_property_set_int(obj, "stepping", 3, &error_abort); 5686 } 5687 } 5688 5689 x86_cpu_realizefn(dev, errp); 5690 } 5691 5692 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5693 { 5694 DeviceClass *dc = DEVICE_CLASS(oc); 5695 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5696 5697 xcc->ordering = 9; 5698 5699 xcc->model_description = 5700 "Enables all features supported by the accelerator in the current host"; 5701 5702 device_class_set_props(dc, max_x86_cpu_properties); 5703 dc->realize = max_x86_cpu_realize; 5704 } 5705 5706 static void max_x86_cpu_initfn(Object *obj) 5707 { 5708 X86CPU *cpu = X86_CPU(obj); 5709 5710 /* We can't fill the features array here because we don't know yet if 5711 * "migratable" is true or false. 5712 */ 5713 cpu->max_features = true; 5714 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5715 5716 /* 5717 * these defaults are used for TCG and all other accelerators 5718 * besides KVM and HVF, which overwrite these values 5719 */ 5720 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5721 &error_abort); 5722 object_property_set_str(OBJECT(cpu), "model-id", 5723 "QEMU TCG CPU version " QEMU_HW_VERSION, 5724 &error_abort); 5725 } 5726 5727 static const TypeInfo max_x86_cpu_type_info = { 5728 .name = X86_CPU_TYPE_NAME("max"), 5729 .parent = TYPE_X86_CPU, 5730 .instance_init = max_x86_cpu_initfn, 5731 .class_init = max_x86_cpu_class_init, 5732 }; 5733 5734 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5735 { 5736 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5737 5738 switch (f->type) { 5739 case CPUID_FEATURE_WORD: 5740 { 5741 const char *reg = get_register_name_32(f->cpuid.reg); 5742 assert(reg); 5743 return g_strdup_printf("CPUID.%02XH:%s", 5744 f->cpuid.eax, reg); 5745 } 5746 case MSR_FEATURE_WORD: 5747 return g_strdup_printf("MSR(%02XH)", 5748 f->msr.index); 5749 } 5750 5751 return NULL; 5752 } 5753 5754 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5755 { 5756 FeatureWord w; 5757 5758 for (w = 0; w < FEATURE_WORDS; w++) { 5759 if (cpu->filtered_features[w]) { 5760 return true; 5761 } 5762 } 5763 5764 return false; 5765 } 5766 5767 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5768 const char *verbose_prefix) 5769 { 5770 CPUX86State *env = &cpu->env; 5771 FeatureWordInfo *f = &feature_word_info[w]; 5772 int i; 5773 5774 if (!cpu->force_features) { 5775 env->features[w] &= ~mask; 5776 } 5777 cpu->filtered_features[w] |= mask; 5778 5779 if (!verbose_prefix) { 5780 return; 5781 } 5782 5783 for (i = 0; i < 64; ++i) { 5784 if ((1ULL << i) & mask) { 5785 g_autofree char *feat_word_str = feature_word_description(f, i); 5786 warn_report("%s: %s%s%s [bit %d]", 5787 verbose_prefix, 5788 feat_word_str, 5789 f->feat_names[i] ? "." : "", 5790 f->feat_names[i] ? f->feat_names[i] : "", i); 5791 } 5792 } 5793 } 5794 5795 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5796 const char *name, void *opaque, 5797 Error **errp) 5798 { 5799 X86CPU *cpu = X86_CPU(obj); 5800 CPUX86State *env = &cpu->env; 5801 uint64_t value; 5802 5803 value = (env->cpuid_version >> 8) & 0xf; 5804 if (value == 0xf) { 5805 value += (env->cpuid_version >> 20) & 0xff; 5806 } 5807 visit_type_uint64(v, name, &value, errp); 5808 } 5809 5810 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5811 const char *name, void *opaque, 5812 Error **errp) 5813 { 5814 X86CPU *cpu = X86_CPU(obj); 5815 CPUX86State *env = &cpu->env; 5816 const uint64_t max = 0xff + 0xf; 5817 uint64_t value; 5818 5819 if (!visit_type_uint64(v, name, &value, errp)) { 5820 return; 5821 } 5822 if (value > max) { 5823 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5824 name ? name : "null", max); 5825 return; 5826 } 5827 5828 env->cpuid_version &= ~0xff00f00; 5829 if (value > 0x0f) { 5830 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5831 } else { 5832 env->cpuid_version |= value << 8; 5833 } 5834 } 5835 5836 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5837 const char *name, void *opaque, 5838 Error **errp) 5839 { 5840 X86CPU *cpu = X86_CPU(obj); 5841 CPUX86State *env = &cpu->env; 5842 uint64_t value; 5843 5844 value = (env->cpuid_version >> 4) & 0xf; 5845 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5846 visit_type_uint64(v, name, &value, errp); 5847 } 5848 5849 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5850 const char *name, void *opaque, 5851 Error **errp) 5852 { 5853 X86CPU *cpu = X86_CPU(obj); 5854 CPUX86State *env = &cpu->env; 5855 const uint64_t max = 0xff; 5856 uint64_t value; 5857 5858 if (!visit_type_uint64(v, name, &value, errp)) { 5859 return; 5860 } 5861 if (value > max) { 5862 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5863 name ? name : "null", max); 5864 return; 5865 } 5866 5867 env->cpuid_version &= ~0xf00f0; 5868 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5869 } 5870 5871 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5872 const char *name, void *opaque, 5873 Error **errp) 5874 { 5875 X86CPU *cpu = X86_CPU(obj); 5876 CPUX86State *env = &cpu->env; 5877 uint64_t value; 5878 5879 value = env->cpuid_version & 0xf; 5880 visit_type_uint64(v, name, &value, errp); 5881 } 5882 5883 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5884 const char *name, void *opaque, 5885 Error **errp) 5886 { 5887 X86CPU *cpu = X86_CPU(obj); 5888 CPUX86State *env = &cpu->env; 5889 const uint64_t max = 0xf; 5890 uint64_t value; 5891 5892 if (!visit_type_uint64(v, name, &value, errp)) { 5893 return; 5894 } 5895 if (value > max) { 5896 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5897 name ? name : "null", max); 5898 return; 5899 } 5900 5901 env->cpuid_version &= ~0xf; 5902 env->cpuid_version |= value & 0xf; 5903 } 5904 5905 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5906 { 5907 X86CPU *cpu = X86_CPU(obj); 5908 CPUX86State *env = &cpu->env; 5909 char *value; 5910 5911 value = g_malloc(CPUID_VENDOR_SZ + 1); 5912 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5913 env->cpuid_vendor3); 5914 return value; 5915 } 5916 5917 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5918 Error **errp) 5919 { 5920 X86CPU *cpu = X86_CPU(obj); 5921 CPUX86State *env = &cpu->env; 5922 int i; 5923 5924 if (strlen(value) != CPUID_VENDOR_SZ) { 5925 error_setg(errp, "value of property 'vendor' must consist of" 5926 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5927 return; 5928 } 5929 5930 env->cpuid_vendor1 = 0; 5931 env->cpuid_vendor2 = 0; 5932 env->cpuid_vendor3 = 0; 5933 for (i = 0; i < 4; i++) { 5934 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5935 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5936 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5937 } 5938 } 5939 5940 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5941 { 5942 X86CPU *cpu = X86_CPU(obj); 5943 CPUX86State *env = &cpu->env; 5944 char *value; 5945 int i; 5946 5947 value = g_malloc(48 + 1); 5948 for (i = 0; i < 48; i++) { 5949 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5950 } 5951 value[48] = '\0'; 5952 return value; 5953 } 5954 5955 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5956 Error **errp) 5957 { 5958 X86CPU *cpu = X86_CPU(obj); 5959 CPUX86State *env = &cpu->env; 5960 int c, len, i; 5961 5962 if (model_id == NULL) { 5963 model_id = ""; 5964 } 5965 len = strlen(model_id); 5966 memset(env->cpuid_model, 0, 48); 5967 for (i = 0; i < 48; i++) { 5968 if (i >= len) { 5969 c = '\0'; 5970 } else { 5971 c = (uint8_t)model_id[i]; 5972 } 5973 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5974 } 5975 } 5976 5977 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5978 void *opaque, Error **errp) 5979 { 5980 X86CPU *cpu = X86_CPU(obj); 5981 int64_t value; 5982 5983 value = cpu->env.tsc_khz * 1000; 5984 visit_type_int(v, name, &value, errp); 5985 } 5986 5987 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5988 void *opaque, Error **errp) 5989 { 5990 X86CPU *cpu = X86_CPU(obj); 5991 const int64_t max = INT64_MAX; 5992 int64_t value; 5993 5994 if (!visit_type_int(v, name, &value, errp)) { 5995 return; 5996 } 5997 if (value < 0 || value > max) { 5998 error_setg(errp, "parameter '%s' can be at most %" PRId64, 5999 name ? name : "null", max); 6000 return; 6001 } 6002 6003 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 6004 } 6005 6006 /* Generic getter for "feature-words" and "filtered-features" properties */ 6007 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 6008 const char *name, void *opaque, 6009 Error **errp) 6010 { 6011 uint64_t *array = (uint64_t *)opaque; 6012 FeatureWord w; 6013 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 6014 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 6015 X86CPUFeatureWordInfoList *list = NULL; 6016 6017 for (w = 0; w < FEATURE_WORDS; w++) { 6018 FeatureWordInfo *wi = &feature_word_info[w]; 6019 /* 6020 * We didn't have MSR features when "feature-words" was 6021 * introduced. Therefore skipped other type entries. 6022 */ 6023 if (wi->type != CPUID_FEATURE_WORD) { 6024 continue; 6025 } 6026 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 6027 qwi->cpuid_input_eax = wi->cpuid.eax; 6028 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 6029 qwi->cpuid_input_ecx = wi->cpuid.ecx; 6030 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 6031 qwi->features = array[w]; 6032 6033 /* List will be in reverse order, but order shouldn't matter */ 6034 list_entries[w].next = list; 6035 list_entries[w].value = &word_infos[w]; 6036 list = &list_entries[w]; 6037 } 6038 6039 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 6040 } 6041 6042 /* Convert all '_' in a feature string option name to '-', to make feature 6043 * name conform to QOM property naming rule, which uses '-' instead of '_'. 6044 */ 6045 static inline void feat2prop(char *s) 6046 { 6047 while ((s = strchr(s, '_'))) { 6048 *s = '-'; 6049 } 6050 } 6051 6052 /* Return the feature property name for a feature flag bit */ 6053 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 6054 { 6055 const char *name; 6056 /* XSAVE components are automatically enabled by other features, 6057 * so return the original feature name instead 6058 */ 6059 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 6060 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 6061 6062 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 6063 x86_ext_save_areas[comp].bits) { 6064 w = x86_ext_save_areas[comp].feature; 6065 bitnr = ctz32(x86_ext_save_areas[comp].bits); 6066 } 6067 } 6068 6069 assert(bitnr < 64); 6070 assert(w < FEATURE_WORDS); 6071 name = feature_word_info[w].feat_names[bitnr]; 6072 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 6073 return name; 6074 } 6075 6076 /* Compatibility hack to maintain legacy +-feat semantic, 6077 * where +-feat overwrites any feature set by 6078 * feat=on|feat even if the later is parsed after +-feat 6079 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 6080 */ 6081 static GList *plus_features, *minus_features; 6082 6083 static gint compare_string(gconstpointer a, gconstpointer b) 6084 { 6085 return g_strcmp0(a, b); 6086 } 6087 6088 /* Parse "+feature,-feature,feature=foo" CPU feature string 6089 */ 6090 static void x86_cpu_parse_featurestr(const char *typename, char *features, 6091 Error **errp) 6092 { 6093 char *featurestr; /* Single 'key=value" string being parsed */ 6094 static bool cpu_globals_initialized; 6095 bool ambiguous = false; 6096 6097 if (cpu_globals_initialized) { 6098 return; 6099 } 6100 cpu_globals_initialized = true; 6101 6102 if (!features) { 6103 return; 6104 } 6105 6106 for (featurestr = strtok(features, ","); 6107 featurestr; 6108 featurestr = strtok(NULL, ",")) { 6109 const char *name; 6110 const char *val = NULL; 6111 char *eq = NULL; 6112 char num[32]; 6113 GlobalProperty *prop; 6114 6115 /* Compatibility syntax: */ 6116 if (featurestr[0] == '+') { 6117 plus_features = g_list_append(plus_features, 6118 g_strdup(featurestr + 1)); 6119 continue; 6120 } else if (featurestr[0] == '-') { 6121 minus_features = g_list_append(minus_features, 6122 g_strdup(featurestr + 1)); 6123 continue; 6124 } 6125 6126 eq = strchr(featurestr, '='); 6127 if (eq) { 6128 *eq++ = 0; 6129 val = eq; 6130 } else { 6131 val = "on"; 6132 } 6133 6134 feat2prop(featurestr); 6135 name = featurestr; 6136 6137 if (g_list_find_custom(plus_features, name, compare_string)) { 6138 warn_report("Ambiguous CPU model string. " 6139 "Don't mix both \"+%s\" and \"%s=%s\"", 6140 name, name, val); 6141 ambiguous = true; 6142 } 6143 if (g_list_find_custom(minus_features, name, compare_string)) { 6144 warn_report("Ambiguous CPU model string. " 6145 "Don't mix both \"-%s\" and \"%s=%s\"", 6146 name, name, val); 6147 ambiguous = true; 6148 } 6149 6150 /* Special case: */ 6151 if (!strcmp(name, "tsc-freq")) { 6152 int ret; 6153 uint64_t tsc_freq; 6154 6155 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 6156 if (ret < 0 || tsc_freq > INT64_MAX) { 6157 error_setg(errp, "bad numerical value %s", val); 6158 return; 6159 } 6160 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 6161 val = num; 6162 name = "tsc-frequency"; 6163 } 6164 6165 prop = g_new0(typeof(*prop), 1); 6166 prop->driver = typename; 6167 prop->property = g_strdup(name); 6168 prop->value = g_strdup(val); 6169 qdev_prop_register_global(prop); 6170 } 6171 6172 if (ambiguous) { 6173 warn_report("Compatibility of ambiguous CPU model " 6174 "strings won't be kept on future QEMU versions"); 6175 } 6176 } 6177 6178 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 6179 6180 /* Build a list with the name of all features on a feature word array */ 6181 static void x86_cpu_list_feature_names(FeatureWordArray features, 6182 strList **list) 6183 { 6184 strList **tail = list; 6185 FeatureWord w; 6186 6187 for (w = 0; w < FEATURE_WORDS; w++) { 6188 uint64_t filtered = features[w]; 6189 int i; 6190 for (i = 0; i < 64; i++) { 6191 if (filtered & (1ULL << i)) { 6192 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 6193 } 6194 } 6195 } 6196 } 6197 6198 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 6199 const char *name, void *opaque, 6200 Error **errp) 6201 { 6202 X86CPU *xc = X86_CPU(obj); 6203 strList *result = NULL; 6204 6205 x86_cpu_list_feature_names(xc->filtered_features, &result); 6206 visit_type_strList(v, "unavailable-features", &result, errp); 6207 } 6208 6209 /* Print all cpuid feature names in featureset 6210 */ 6211 static void listflags(GList *features) 6212 { 6213 size_t len = 0; 6214 GList *tmp; 6215 6216 for (tmp = features; tmp; tmp = tmp->next) { 6217 const char *name = tmp->data; 6218 if ((len + strlen(name) + 1) >= 75) { 6219 qemu_printf("\n"); 6220 len = 0; 6221 } 6222 qemu_printf("%s%s", len == 0 ? " " : " ", name); 6223 len += strlen(name) + 1; 6224 } 6225 qemu_printf("\n"); 6226 } 6227 6228 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 6229 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 6230 { 6231 ObjectClass *class_a = (ObjectClass *)a; 6232 ObjectClass *class_b = (ObjectClass *)b; 6233 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 6234 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 6235 int ret; 6236 6237 if (cc_a->ordering != cc_b->ordering) { 6238 ret = cc_a->ordering - cc_b->ordering; 6239 } else { 6240 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 6241 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 6242 ret = strcmp(name_a, name_b); 6243 } 6244 return ret; 6245 } 6246 6247 static GSList *get_sorted_cpu_model_list(void) 6248 { 6249 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 6250 list = g_slist_sort(list, x86_cpu_list_compare); 6251 return list; 6252 } 6253 6254 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 6255 { 6256 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 6257 char *r = object_property_get_str(obj, "model-id", &error_abort); 6258 object_unref(obj); 6259 return r; 6260 } 6261 6262 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 6263 { 6264 X86CPUVersion version; 6265 6266 if (!cc->model || !cc->model->is_alias) { 6267 return NULL; 6268 } 6269 version = x86_cpu_model_resolve_version(cc->model); 6270 if (version <= 0) { 6271 return NULL; 6272 } 6273 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 6274 } 6275 6276 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 6277 { 6278 ObjectClass *oc = data; 6279 X86CPUClass *cc = X86_CPU_CLASS(oc); 6280 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6281 g_autofree char *desc = g_strdup(cc->model_description); 6282 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6283 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6284 6285 if (!desc && alias_of) { 6286 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6287 desc = g_strdup("(alias configured by machine type)"); 6288 } else { 6289 desc = g_strdup_printf("(alias of %s)", alias_of); 6290 } 6291 } 6292 if (!desc && cc->model && cc->model->note) { 6293 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6294 } 6295 if (!desc) { 6296 desc = g_strdup(model_id); 6297 } 6298 6299 if (cc->model && cc->model->cpudef->deprecation_note) { 6300 g_autofree char *olddesc = desc; 6301 desc = g_strdup_printf("%s (deprecated)", olddesc); 6302 } 6303 6304 qemu_printf(" %-20s %s\n", name, desc); 6305 } 6306 6307 /* list available CPU models and flags */ 6308 void x86_cpu_list(void) 6309 { 6310 int i, j; 6311 GSList *list; 6312 GList *names = NULL; 6313 6314 qemu_printf("Available CPUs:\n"); 6315 list = get_sorted_cpu_model_list(); 6316 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6317 g_slist_free(list); 6318 6319 names = NULL; 6320 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6321 FeatureWordInfo *fw = &feature_word_info[i]; 6322 for (j = 0; j < 64; j++) { 6323 if (fw->feat_names[j]) { 6324 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6325 } 6326 } 6327 } 6328 6329 names = g_list_sort(names, (GCompareFunc)strcmp); 6330 6331 qemu_printf("\nRecognized CPUID flags:\n"); 6332 listflags(names); 6333 qemu_printf("\n"); 6334 g_list_free(names); 6335 } 6336 6337 #ifndef CONFIG_USER_ONLY 6338 6339 /* Check for missing features that may prevent the CPU class from 6340 * running using the current machine and accelerator. 6341 */ 6342 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6343 strList **list) 6344 { 6345 strList **tail = list; 6346 X86CPU *xc; 6347 Error *err = NULL; 6348 6349 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6350 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6351 return; 6352 } 6353 6354 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6355 6356 x86_cpu_expand_features(xc, &err); 6357 if (err) { 6358 /* Errors at x86_cpu_expand_features should never happen, 6359 * but in case it does, just report the model as not 6360 * runnable at all using the "type" property. 6361 */ 6362 QAPI_LIST_APPEND(tail, g_strdup("type")); 6363 error_free(err); 6364 } 6365 6366 x86_cpu_filter_features(xc, false); 6367 6368 x86_cpu_list_feature_names(xc->filtered_features, tail); 6369 6370 object_unref(OBJECT(xc)); 6371 } 6372 6373 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6374 { 6375 ObjectClass *oc = data; 6376 X86CPUClass *cc = X86_CPU_CLASS(oc); 6377 CpuDefinitionInfoList **cpu_list = user_data; 6378 CpuDefinitionInfo *info; 6379 6380 info = g_malloc0(sizeof(*info)); 6381 info->name = x86_cpu_class_get_model_name(cc); 6382 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6383 info->has_unavailable_features = true; 6384 info->q_typename = g_strdup(object_class_get_name(oc)); 6385 info->migration_safe = cc->migration_safe; 6386 info->has_migration_safe = true; 6387 info->q_static = cc->static_model; 6388 if (cc->model && cc->model->cpudef->deprecation_note) { 6389 info->deprecated = true; 6390 } else { 6391 info->deprecated = false; 6392 } 6393 /* 6394 * Old machine types won't report aliases, so that alias translation 6395 * doesn't break compatibility with previous QEMU versions. 6396 */ 6397 if (default_cpu_version != CPU_VERSION_LEGACY) { 6398 info->alias_of = x86_cpu_class_get_alias_of(cc); 6399 } 6400 6401 QAPI_LIST_PREPEND(*cpu_list, info); 6402 } 6403 6404 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6405 { 6406 CpuDefinitionInfoList *cpu_list = NULL; 6407 GSList *list = get_sorted_cpu_model_list(); 6408 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6409 g_slist_free(list); 6410 return cpu_list; 6411 } 6412 6413 #endif /* !CONFIG_USER_ONLY */ 6414 6415 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6416 { 6417 FeatureWordInfo *wi = &feature_word_info[w]; 6418 uint64_t r = 0; 6419 uint64_t unavail = 0; 6420 6421 if (kvm_enabled()) { 6422 switch (wi->type) { 6423 case CPUID_FEATURE_WORD: 6424 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6425 wi->cpuid.ecx, 6426 wi->cpuid.reg); 6427 break; 6428 case MSR_FEATURE_WORD: 6429 r = kvm_arch_get_supported_msr_feature(kvm_state, 6430 wi->msr.index); 6431 break; 6432 } 6433 } else if (hvf_enabled()) { 6434 if (wi->type != CPUID_FEATURE_WORD) { 6435 return 0; 6436 } 6437 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6438 wi->cpuid.ecx, 6439 wi->cpuid.reg); 6440 } else if (tcg_enabled()) { 6441 r = wi->tcg_features; 6442 } else { 6443 return ~0; 6444 } 6445 6446 switch (w) { 6447 #ifndef TARGET_X86_64 6448 case FEAT_8000_0001_EDX: 6449 /* 6450 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6451 * way for userspace to get out of its 32-bit jail, we can leave 6452 * the LM bit set. 6453 */ 6454 unavail = tcg_enabled() 6455 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6456 : CPUID_EXT2_LM; 6457 break; 6458 #endif 6459 6460 case FEAT_8000_0007_EBX: 6461 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6462 /* Disable AMD machine check architecture for Intel CPU. */ 6463 unavail = ~0; 6464 } 6465 break; 6466 6467 case FEAT_7_0_EBX: 6468 #ifndef CONFIG_USER_ONLY 6469 if (!check_sgx_support()) { 6470 unavail = CPUID_7_0_EBX_SGX; 6471 } 6472 #endif 6473 break; 6474 case FEAT_7_0_ECX: 6475 #ifndef CONFIG_USER_ONLY 6476 if (!check_sgx_support()) { 6477 unavail = CPUID_7_0_ECX_SGX_LC; 6478 } 6479 #endif 6480 break; 6481 6482 default: 6483 break; 6484 } 6485 6486 r &= ~unavail; 6487 if (cpu && cpu->migratable) { 6488 r &= x86_cpu_get_migratable_flags(cpu, w); 6489 } 6490 return r; 6491 } 6492 6493 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6494 uint32_t *eax, uint32_t *ebx, 6495 uint32_t *ecx, uint32_t *edx) 6496 { 6497 if (kvm_enabled()) { 6498 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6499 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6500 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6501 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6502 } else if (hvf_enabled()) { 6503 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6504 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6505 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6506 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6507 } else { 6508 *eax = 0; 6509 *ebx = 0; 6510 *ecx = 0; 6511 *edx = 0; 6512 } 6513 } 6514 6515 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6516 uint32_t *eax, uint32_t *ebx, 6517 uint32_t *ecx, uint32_t *edx) 6518 { 6519 uint32_t level, unused; 6520 6521 /* Only return valid host leaves. */ 6522 switch (func) { 6523 case 2: 6524 case 4: 6525 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6526 break; 6527 case 0x80000005: 6528 case 0x80000006: 6529 case 0x8000001d: 6530 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6531 break; 6532 default: 6533 return; 6534 } 6535 6536 if (func > level) { 6537 *eax = 0; 6538 *ebx = 0; 6539 *ecx = 0; 6540 *edx = 0; 6541 } else { 6542 host_cpuid(func, index, eax, ebx, ecx, edx); 6543 } 6544 } 6545 6546 /* 6547 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6548 */ 6549 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6550 { 6551 PropValue *pv; 6552 for (pv = props; pv->prop; pv++) { 6553 if (!pv->value) { 6554 continue; 6555 } 6556 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6557 &error_abort); 6558 } 6559 } 6560 6561 /* 6562 * Apply properties for the CPU model version specified in model. 6563 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6564 */ 6565 6566 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6567 { 6568 const X86CPUVersionDefinition *vdef; 6569 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6570 6571 if (version == CPU_VERSION_LEGACY) { 6572 return; 6573 } 6574 6575 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6576 PropValue *p; 6577 6578 for (p = vdef->props; p && p->prop; p++) { 6579 object_property_parse(OBJECT(cpu), p->prop, p->value, 6580 &error_abort); 6581 } 6582 6583 if (vdef->version == version) { 6584 break; 6585 } 6586 } 6587 6588 /* 6589 * If we reached the end of the list, version number was invalid 6590 */ 6591 assert(vdef->version == version); 6592 } 6593 6594 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6595 X86CPUModel *model) 6596 { 6597 const X86CPUVersionDefinition *vdef; 6598 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6599 const CPUCaches *cache_info = model->cpudef->cache_info; 6600 6601 if (version == CPU_VERSION_LEGACY) { 6602 return cache_info; 6603 } 6604 6605 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6606 if (vdef->cache_info) { 6607 cache_info = vdef->cache_info; 6608 } 6609 6610 if (vdef->version == version) { 6611 break; 6612 } 6613 } 6614 6615 assert(vdef->version == version); 6616 return cache_info; 6617 } 6618 6619 /* 6620 * Load data from X86CPUDefinition into a X86CPU object. 6621 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6622 */ 6623 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6624 { 6625 const X86CPUDefinition *def = model->cpudef; 6626 CPUX86State *env = &cpu->env; 6627 FeatureWord w; 6628 6629 /*NOTE: any property set by this function should be returned by 6630 * x86_cpu_static_props(), so static expansion of 6631 * query-cpu-model-expansion is always complete. 6632 */ 6633 6634 /* CPU models only set _minimum_ values for level/xlevel: */ 6635 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6636 &error_abort); 6637 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6638 &error_abort); 6639 6640 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6641 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6642 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6643 &error_abort); 6644 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6645 &error_abort); 6646 for (w = 0; w < FEATURE_WORDS; w++) { 6647 env->features[w] = def->features[w]; 6648 } 6649 6650 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6651 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6652 6653 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6654 6655 /* sysenter isn't supported in compatibility mode on AMD, 6656 * syscall isn't supported in compatibility mode on Intel. 6657 * Normally we advertise the actual CPU vendor, but you can 6658 * override this using the 'vendor' property if you want to use 6659 * KVM's sysenter/syscall emulation in compatibility mode and 6660 * when doing cross vendor migration 6661 */ 6662 6663 /* 6664 * vendor property is set here but then overloaded with the 6665 * host cpu vendor for KVM and HVF. 6666 */ 6667 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6668 6669 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 6670 &error_abort); 6671 6672 x86_cpu_apply_version_props(cpu, model); 6673 6674 /* 6675 * Properties in versioned CPU model are not user specified features. 6676 * We can simply clear env->user_features here since it will be filled later 6677 * in x86_cpu_expand_features() based on plus_features and minus_features. 6678 */ 6679 memset(&env->user_features, 0, sizeof(env->user_features)); 6680 } 6681 6682 static const gchar *x86_gdb_arch_name(CPUState *cs) 6683 { 6684 #ifdef TARGET_X86_64 6685 return "i386:x86-64"; 6686 #else 6687 return "i386"; 6688 #endif 6689 } 6690 6691 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6692 { 6693 X86CPUModel *model = data; 6694 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6695 CPUClass *cc = CPU_CLASS(oc); 6696 6697 xcc->model = model; 6698 xcc->migration_safe = true; 6699 cc->deprecation_note = model->cpudef->deprecation_note; 6700 } 6701 6702 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6703 { 6704 g_autofree char *typename = x86_cpu_type_name(name); 6705 TypeInfo ti = { 6706 .name = typename, 6707 .parent = TYPE_X86_CPU, 6708 .class_init = x86_cpu_cpudef_class_init, 6709 .class_data = model, 6710 }; 6711 6712 type_register_static(&ti); 6713 } 6714 6715 6716 /* 6717 * register builtin_x86_defs; 6718 * "max", "base" and subclasses ("host") are not registered here. 6719 * See x86_cpu_register_types for all model registrations. 6720 */ 6721 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6722 { 6723 X86CPUModel *m; 6724 const X86CPUVersionDefinition *vdef; 6725 6726 /* AMD aliases are handled at runtime based on CPUID vendor, so 6727 * they shouldn't be set on the CPU model table. 6728 */ 6729 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6730 /* catch mistakes instead of silently truncating model_id when too long */ 6731 assert(def->model_id && strlen(def->model_id) <= 48); 6732 6733 /* Unversioned model: */ 6734 m = g_new0(X86CPUModel, 1); 6735 m->cpudef = def; 6736 m->version = CPU_VERSION_AUTO; 6737 m->is_alias = true; 6738 x86_register_cpu_model_type(def->name, m); 6739 6740 /* Versioned models: */ 6741 6742 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6743 g_autofree char *name = 6744 x86_cpu_versioned_model_name(def, vdef->version); 6745 6746 m = g_new0(X86CPUModel, 1); 6747 m->cpudef = def; 6748 m->version = vdef->version; 6749 m->note = vdef->note; 6750 x86_register_cpu_model_type(name, m); 6751 6752 if (vdef->alias) { 6753 X86CPUModel *am = g_new0(X86CPUModel, 1); 6754 am->cpudef = def; 6755 am->version = vdef->version; 6756 am->is_alias = true; 6757 x86_register_cpu_model_type(vdef->alias, am); 6758 } 6759 } 6760 6761 } 6762 6763 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6764 { 6765 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6766 return 57; /* 57 bits virtual */ 6767 } else { 6768 return 48; /* 48 bits virtual */ 6769 } 6770 } 6771 6772 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6773 uint32_t *eax, uint32_t *ebx, 6774 uint32_t *ecx, uint32_t *edx) 6775 { 6776 X86CPU *cpu = env_archcpu(env); 6777 CPUState *cs = env_cpu(env); 6778 uint32_t limit; 6779 uint32_t signature[3]; 6780 X86CPUTopoInfo *topo_info = &env->topo_info; 6781 uint32_t threads_per_pkg; 6782 6783 threads_per_pkg = x86_threads_per_pkg(topo_info); 6784 6785 /* Calculate & apply limits for different index ranges */ 6786 if (index >= 0xC0000000) { 6787 limit = env->cpuid_xlevel2; 6788 } else if (index >= 0x80000000) { 6789 limit = env->cpuid_xlevel; 6790 } else if (index >= 0x40000000) { 6791 limit = 0x40000001; 6792 } else { 6793 limit = env->cpuid_level; 6794 } 6795 6796 if (index > limit) { 6797 /* Intel documentation states that invalid EAX input will 6798 * return the same information as EAX=cpuid_level 6799 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6800 */ 6801 index = env->cpuid_level; 6802 } 6803 6804 switch(index) { 6805 case 0: 6806 *eax = env->cpuid_level; 6807 *ebx = env->cpuid_vendor1; 6808 *edx = env->cpuid_vendor2; 6809 *ecx = env->cpuid_vendor3; 6810 break; 6811 case 1: 6812 *eax = env->cpuid_version; 6813 *ebx = (cpu->apic_id << 24) | 6814 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6815 *ecx = env->features[FEAT_1_ECX]; 6816 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6817 *ecx |= CPUID_EXT_OSXSAVE; 6818 } 6819 *edx = env->features[FEAT_1_EDX]; 6820 if (threads_per_pkg > 1) { 6821 *ebx |= threads_per_pkg << 16; 6822 } 6823 if (!cpu->enable_pmu) { 6824 *ecx &= ~CPUID_EXT_PDCM; 6825 } 6826 break; 6827 case 2: 6828 /* cache info: needed for Pentium Pro compatibility */ 6829 if (cpu->cache_info_passthrough) { 6830 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6831 break; 6832 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6833 *eax = *ebx = *ecx = *edx = 0; 6834 break; 6835 } 6836 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6837 *ebx = 0; 6838 if (!cpu->enable_l3_cache) { 6839 *ecx = 0; 6840 } else { 6841 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6842 } 6843 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6844 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6845 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6846 break; 6847 case 4: 6848 /* cache info: needed for Core compatibility */ 6849 if (cpu->cache_info_passthrough) { 6850 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6851 /* 6852 * QEMU has its own number of cores/logical cpus, 6853 * set 24..14, 31..26 bit to configured values 6854 */ 6855 if (*eax & 31) { 6856 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6857 6858 *eax &= ~0xFC000000; 6859 *eax |= max_core_ids_in_package(topo_info) << 26; 6860 if (host_vcpus_per_cache > threads_per_pkg) { 6861 *eax &= ~0x3FFC000; 6862 6863 /* Share the cache at package level. */ 6864 *eax |= max_thread_ids_for_cache(topo_info, 6865 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 6866 } 6867 } 6868 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6869 *eax = *ebx = *ecx = *edx = 0; 6870 } else { 6871 *eax = 0; 6872 6873 switch (count) { 6874 case 0: /* L1 dcache info */ 6875 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6876 topo_info, 6877 eax, ebx, ecx, edx); 6878 if (!cpu->l1_cache_per_core) { 6879 *eax &= ~MAKE_64BIT_MASK(14, 12); 6880 } 6881 break; 6882 case 1: /* L1 icache info */ 6883 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6884 topo_info, 6885 eax, ebx, ecx, edx); 6886 if (!cpu->l1_cache_per_core) { 6887 *eax &= ~MAKE_64BIT_MASK(14, 12); 6888 } 6889 break; 6890 case 2: /* L2 cache info */ 6891 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6892 topo_info, 6893 eax, ebx, ecx, edx); 6894 break; 6895 case 3: /* L3 cache info */ 6896 if (cpu->enable_l3_cache) { 6897 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6898 topo_info, 6899 eax, ebx, ecx, edx); 6900 break; 6901 } 6902 /* fall through */ 6903 default: /* end of info */ 6904 *eax = *ebx = *ecx = *edx = 0; 6905 break; 6906 } 6907 } 6908 break; 6909 case 5: 6910 /* MONITOR/MWAIT Leaf */ 6911 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6912 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6913 *ecx = cpu->mwait.ecx; /* flags */ 6914 *edx = cpu->mwait.edx; /* mwait substates */ 6915 break; 6916 case 6: 6917 /* Thermal and Power Leaf */ 6918 *eax = env->features[FEAT_6_EAX]; 6919 *ebx = 0; 6920 *ecx = 0; 6921 *edx = 0; 6922 break; 6923 case 7: 6924 /* Structured Extended Feature Flags Enumeration Leaf */ 6925 if (count == 0) { 6926 /* Maximum ECX value for sub-leaves */ 6927 *eax = env->cpuid_level_func7; 6928 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6929 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6930 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6931 *ecx |= CPUID_7_0_ECX_OSPKE; 6932 } 6933 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6934 } else if (count == 1) { 6935 *eax = env->features[FEAT_7_1_EAX]; 6936 *edx = env->features[FEAT_7_1_EDX]; 6937 *ebx = 0; 6938 *ecx = 0; 6939 } else if (count == 2) { 6940 *edx = env->features[FEAT_7_2_EDX]; 6941 *eax = 0; 6942 *ebx = 0; 6943 *ecx = 0; 6944 } else { 6945 *eax = 0; 6946 *ebx = 0; 6947 *ecx = 0; 6948 *edx = 0; 6949 } 6950 break; 6951 case 9: 6952 /* Direct Cache Access Information Leaf */ 6953 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6954 *ebx = 0; 6955 *ecx = 0; 6956 *edx = 0; 6957 break; 6958 case 0xA: 6959 /* Architectural Performance Monitoring Leaf */ 6960 if (cpu->enable_pmu) { 6961 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6962 } else { 6963 *eax = 0; 6964 *ebx = 0; 6965 *ecx = 0; 6966 *edx = 0; 6967 } 6968 break; 6969 case 0xB: 6970 /* Extended Topology Enumeration Leaf */ 6971 if (!cpu->enable_cpuid_0xb) { 6972 *eax = *ebx = *ecx = *edx = 0; 6973 break; 6974 } 6975 6976 *ecx = count & 0xff; 6977 *edx = cpu->apic_id; 6978 6979 switch (count) { 6980 case 0: 6981 *eax = apicid_core_offset(topo_info); 6982 *ebx = topo_info->threads_per_core; 6983 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6984 break; 6985 case 1: 6986 *eax = apicid_pkg_offset(topo_info); 6987 *ebx = threads_per_pkg; 6988 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6989 break; 6990 default: 6991 *eax = 0; 6992 *ebx = 0; 6993 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6994 } 6995 6996 assert(!(*eax & ~0x1f)); 6997 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6998 break; 6999 case 0x1C: 7000 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7001 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 7002 *edx = 0; 7003 } 7004 break; 7005 case 0x1F: 7006 /* V2 Extended Topology Enumeration Leaf */ 7007 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 7008 *eax = *ebx = *ecx = *edx = 0; 7009 break; 7010 } 7011 7012 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 7013 break; 7014 case 0xD: { 7015 /* Processor Extended State */ 7016 *eax = 0; 7017 *ebx = 0; 7018 *ecx = 0; 7019 *edx = 0; 7020 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7021 break; 7022 } 7023 7024 if (count == 0) { 7025 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 7026 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 7027 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 7028 /* 7029 * The initial value of xcr0 and ebx == 0, On host without kvm 7030 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 7031 * even through guest update xcr0, this will crash some legacy guest 7032 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 7033 */ 7034 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 7035 } else if (count == 1) { 7036 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 7037 x86_cpu_xsave_xss_components(cpu); 7038 7039 *eax = env->features[FEAT_XSAVE]; 7040 *ebx = xsave_area_size(xstate, true); 7041 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 7042 *edx = env->features[FEAT_XSAVE_XSS_HI]; 7043 if (kvm_enabled() && cpu->enable_pmu && 7044 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 7045 (*eax & CPUID_XSAVE_XSAVES)) { 7046 *ecx |= XSTATE_ARCH_LBR_MASK; 7047 } else { 7048 *ecx &= ~XSTATE_ARCH_LBR_MASK; 7049 } 7050 } else if (count == 0xf && cpu->enable_pmu 7051 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7052 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 7053 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 7054 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 7055 7056 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 7057 *eax = esa->size; 7058 *ebx = esa->offset; 7059 *ecx = esa->ecx & 7060 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 7061 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 7062 *eax = esa->size; 7063 *ebx = 0; 7064 *ecx = 1; 7065 } 7066 } 7067 break; 7068 } 7069 case 0x12: 7070 #ifndef CONFIG_USER_ONLY 7071 if (!kvm_enabled() || 7072 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 7073 *eax = *ebx = *ecx = *edx = 0; 7074 break; 7075 } 7076 7077 /* 7078 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 7079 * the EPC properties, e.g. confidentiality and integrity, from the 7080 * host's first EPC section, i.e. assume there is one EPC section or 7081 * that all EPC sections have the same security properties. 7082 */ 7083 if (count > 1) { 7084 uint64_t epc_addr, epc_size; 7085 7086 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 7087 *eax = *ebx = *ecx = *edx = 0; 7088 break; 7089 } 7090 host_cpuid(index, 2, eax, ebx, ecx, edx); 7091 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 7092 *ebx = (uint32_t)(epc_addr >> 32); 7093 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 7094 *edx = (uint32_t)(epc_size >> 32); 7095 break; 7096 } 7097 7098 /* 7099 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 7100 * and KVM, i.e. QEMU cannot emulate features to override what KVM 7101 * supports. Features can be further restricted by userspace, but not 7102 * made more permissive. 7103 */ 7104 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 7105 7106 if (count == 0) { 7107 *eax &= env->features[FEAT_SGX_12_0_EAX]; 7108 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 7109 } else { 7110 *eax &= env->features[FEAT_SGX_12_1_EAX]; 7111 *ebx &= 0; /* ebx reserve */ 7112 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 7113 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 7114 7115 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 7116 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 7117 7118 /* Access to PROVISIONKEY requires additional credentials. */ 7119 if ((*eax & (1U << 4)) && 7120 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 7121 *eax &= ~(1U << 4); 7122 } 7123 } 7124 #endif 7125 break; 7126 case 0x14: { 7127 /* Intel Processor Trace Enumeration */ 7128 *eax = 0; 7129 *ebx = 0; 7130 *ecx = 0; 7131 *edx = 0; 7132 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 7133 !kvm_enabled()) { 7134 break; 7135 } 7136 7137 /* 7138 * If these are changed, they should stay in sync with 7139 * x86_cpu_filter_features(). 7140 */ 7141 if (count == 0) { 7142 *eax = INTEL_PT_MAX_SUBLEAF; 7143 *ebx = INTEL_PT_MINIMAL_EBX; 7144 *ecx = INTEL_PT_MINIMAL_ECX; 7145 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 7146 *ecx |= CPUID_14_0_ECX_LIP; 7147 } 7148 } else if (count == 1) { 7149 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 7150 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 7151 } 7152 break; 7153 } 7154 case 0x1D: { 7155 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 7156 *eax = 0; 7157 *ebx = 0; 7158 *ecx = 0; 7159 *edx = 0; 7160 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7161 break; 7162 } 7163 7164 if (count == 0) { 7165 /* Highest numbered palette subleaf */ 7166 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 7167 } else if (count == 1) { 7168 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 7169 (INTEL_AMX_BYTES_PER_TILE << 16); 7170 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 7171 *ecx = INTEL_AMX_TILE_MAX_ROWS; 7172 } 7173 break; 7174 } 7175 case 0x1E: { 7176 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 7177 *eax = 0; 7178 *ebx = 0; 7179 *ecx = 0; 7180 *edx = 0; 7181 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7182 break; 7183 } 7184 7185 if (count == 0) { 7186 /* Highest numbered palette subleaf */ 7187 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 7188 } 7189 break; 7190 } 7191 case 0x24: { 7192 *eax = 0; 7193 *ebx = 0; 7194 *ecx = 0; 7195 *edx = 0; 7196 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 7197 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 7198 } 7199 break; 7200 } 7201 case 0x40000000: 7202 /* 7203 * CPUID code in kvm_arch_init_vcpu() ignores stuff 7204 * set here, but we restrict to TCG none the less. 7205 */ 7206 if (tcg_enabled() && cpu->expose_tcg) { 7207 memcpy(signature, "TCGTCGTCGTCG", 12); 7208 *eax = 0x40000001; 7209 *ebx = signature[0]; 7210 *ecx = signature[1]; 7211 *edx = signature[2]; 7212 } else { 7213 *eax = 0; 7214 *ebx = 0; 7215 *ecx = 0; 7216 *edx = 0; 7217 } 7218 break; 7219 case 0x40000001: 7220 *eax = 0; 7221 *ebx = 0; 7222 *ecx = 0; 7223 *edx = 0; 7224 break; 7225 case 0x80000000: 7226 *eax = env->cpuid_xlevel; 7227 *ebx = env->cpuid_vendor1; 7228 *edx = env->cpuid_vendor2; 7229 *ecx = env->cpuid_vendor3; 7230 break; 7231 case 0x80000001: 7232 *eax = env->cpuid_version; 7233 *ebx = 0; 7234 *ecx = env->features[FEAT_8000_0001_ECX]; 7235 *edx = env->features[FEAT_8000_0001_EDX]; 7236 7237 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 7238 !(env->hflags & HF_LMA_MASK)) { 7239 *edx &= ~CPUID_EXT2_SYSCALL; 7240 } 7241 break; 7242 case 0x80000002: 7243 case 0x80000003: 7244 case 0x80000004: 7245 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 7246 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 7247 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 7248 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 7249 break; 7250 case 0x80000005: 7251 /* cache info (L1 cache) */ 7252 if (cpu->cache_info_passthrough) { 7253 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7254 break; 7255 } 7256 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 7257 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 7258 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 7259 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7260 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7261 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7262 break; 7263 case 0x80000006: 7264 /* cache info (L2 cache) */ 7265 if (cpu->cache_info_passthrough) { 7266 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7267 break; 7268 } 7269 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7270 (L2_DTLB_2M_ENTRIES << 16) | 7271 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7272 (L2_ITLB_2M_ENTRIES); 7273 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7274 (L2_DTLB_4K_ENTRIES << 16) | 7275 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7276 (L2_ITLB_4K_ENTRIES); 7277 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7278 cpu->enable_l3_cache ? 7279 env->cache_info_amd.l3_cache : NULL, 7280 ecx, edx); 7281 break; 7282 case 0x80000007: 7283 *eax = 0; 7284 *ebx = env->features[FEAT_8000_0007_EBX]; 7285 *ecx = 0; 7286 *edx = env->features[FEAT_8000_0007_EDX]; 7287 break; 7288 case 0x80000008: 7289 /* virtual & phys address size in low 2 bytes. */ 7290 *eax = cpu->phys_bits; 7291 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7292 /* 64 bit processor */ 7293 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7294 *eax |= (cpu->guest_phys_bits << 16); 7295 } 7296 *ebx = env->features[FEAT_8000_0008_EBX]; 7297 if (threads_per_pkg > 1) { 7298 /* 7299 * Bits 15:12 is "The number of bits in the initial 7300 * Core::X86::Apic::ApicId[ApicId] value that indicate 7301 * thread ID within a package". 7302 * Bits 7:0 is "The number of threads in the package is NC+1" 7303 */ 7304 *ecx = (apicid_pkg_offset(topo_info) << 12) | 7305 (threads_per_pkg - 1); 7306 } else { 7307 *ecx = 0; 7308 } 7309 *edx = 0; 7310 break; 7311 case 0x8000000A: 7312 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7313 *eax = 0x00000001; /* SVM Revision */ 7314 *ebx = 0x00000010; /* nr of ASIDs */ 7315 *ecx = 0; 7316 *edx = env->features[FEAT_SVM]; /* optional features */ 7317 } else { 7318 *eax = 0; 7319 *ebx = 0; 7320 *ecx = 0; 7321 *edx = 0; 7322 } 7323 break; 7324 case 0x8000001D: 7325 *eax = 0; 7326 if (cpu->cache_info_passthrough) { 7327 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7328 break; 7329 } 7330 switch (count) { 7331 case 0: /* L1 dcache info */ 7332 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7333 topo_info, eax, ebx, ecx, edx); 7334 break; 7335 case 1: /* L1 icache info */ 7336 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7337 topo_info, eax, ebx, ecx, edx); 7338 break; 7339 case 2: /* L2 cache info */ 7340 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7341 topo_info, eax, ebx, ecx, edx); 7342 break; 7343 case 3: /* L3 cache info */ 7344 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7345 topo_info, eax, ebx, ecx, edx); 7346 break; 7347 default: /* end of info */ 7348 *eax = *ebx = *ecx = *edx = 0; 7349 break; 7350 } 7351 if (cpu->amd_topoext_features_only) { 7352 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7353 } 7354 break; 7355 case 0x8000001E: 7356 if (cpu->core_id <= 255) { 7357 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 7358 } else { 7359 *eax = 0; 7360 *ebx = 0; 7361 *ecx = 0; 7362 *edx = 0; 7363 } 7364 break; 7365 case 0x80000022: 7366 *eax = *ebx = *ecx = *edx = 0; 7367 /* AMD Extended Performance Monitoring and Debug */ 7368 if (kvm_enabled() && cpu->enable_pmu && 7369 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7370 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7371 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7372 R_EBX) & 0xf; 7373 } 7374 break; 7375 case 0xC0000000: 7376 *eax = env->cpuid_xlevel2; 7377 *ebx = 0; 7378 *ecx = 0; 7379 *edx = 0; 7380 break; 7381 case 0xC0000001: 7382 /* Support for VIA CPU's CPUID instruction */ 7383 *eax = env->cpuid_version; 7384 *ebx = 0; 7385 *ecx = 0; 7386 *edx = env->features[FEAT_C000_0001_EDX]; 7387 break; 7388 case 0xC0000002: 7389 case 0xC0000003: 7390 case 0xC0000004: 7391 /* Reserved for the future, and now filled with zero */ 7392 *eax = 0; 7393 *ebx = 0; 7394 *ecx = 0; 7395 *edx = 0; 7396 break; 7397 case 0x8000001F: 7398 *eax = *ebx = *ecx = *edx = 0; 7399 if (sev_enabled()) { 7400 *eax = 0x2; 7401 *eax |= sev_es_enabled() ? 0x8 : 0; 7402 *eax |= sev_snp_enabled() ? 0x10 : 0; 7403 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7404 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7405 } 7406 break; 7407 case 0x80000021: 7408 *eax = *ebx = *ecx = *edx = 0; 7409 *eax = env->features[FEAT_8000_0021_EAX]; 7410 *ebx = env->features[FEAT_8000_0021_EBX]; 7411 break; 7412 default: 7413 /* reserved values: zero */ 7414 *eax = 0; 7415 *ebx = 0; 7416 *ecx = 0; 7417 *edx = 0; 7418 break; 7419 } 7420 } 7421 7422 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7423 { 7424 #ifndef CONFIG_USER_ONLY 7425 /* Those default values are defined in Skylake HW */ 7426 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7427 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7428 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7429 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7430 #endif 7431 } 7432 7433 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7434 { 7435 if (!esa->size) { 7436 return false; 7437 } 7438 7439 if (env->features[esa->feature] & esa->bits) { 7440 return true; 7441 } 7442 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7443 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7444 return true; 7445 } 7446 7447 return false; 7448 } 7449 7450 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7451 { 7452 CPUState *cs = CPU(obj); 7453 X86CPU *cpu = X86_CPU(cs); 7454 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7455 CPUX86State *env = &cpu->env; 7456 target_ulong cr4; 7457 uint64_t xcr0; 7458 int i; 7459 7460 if (xcc->parent_phases.hold) { 7461 xcc->parent_phases.hold(obj, type); 7462 } 7463 7464 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7465 7466 if (tcg_enabled()) { 7467 cpu_init_fp_statuses(env); 7468 } 7469 7470 env->old_exception = -1; 7471 7472 /* init to reset state */ 7473 env->int_ctl = 0; 7474 env->hflags2 |= HF2_GIF_MASK; 7475 env->hflags2 |= HF2_VGIF_MASK; 7476 env->hflags &= ~HF_GUEST_MASK; 7477 7478 cpu_x86_update_cr0(env, 0x60000010); 7479 env->a20_mask = ~0x0; 7480 env->smbase = 0x30000; 7481 env->msr_smi_count = 0; 7482 7483 env->idt.limit = 0xffff; 7484 env->gdt.limit = 0xffff; 7485 env->ldt.limit = 0xffff; 7486 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7487 env->tr.limit = 0xffff; 7488 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7489 7490 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7491 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7492 DESC_R_MASK | DESC_A_MASK); 7493 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7494 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7495 DESC_A_MASK); 7496 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7497 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7498 DESC_A_MASK); 7499 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7500 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7501 DESC_A_MASK); 7502 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7503 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7504 DESC_A_MASK); 7505 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7506 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7507 DESC_A_MASK); 7508 7509 env->eip = 0xfff0; 7510 env->regs[R_EDX] = env->cpuid_version; 7511 7512 env->eflags = 0x2; 7513 7514 /* FPU init */ 7515 for (i = 0; i < 8; i++) { 7516 env->fptags[i] = 1; 7517 } 7518 cpu_set_fpuc(env, 0x37f); 7519 7520 env->mxcsr = 0x1f80; 7521 /* All units are in INIT state. */ 7522 env->xstate_bv = 0; 7523 7524 env->pat = 0x0007040600070406ULL; 7525 7526 if (kvm_enabled()) { 7527 /* 7528 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7529 * a new CPU, use 1 instead to force a reset. 7530 */ 7531 if (env->tsc != 0) { 7532 env->tsc = 1; 7533 } 7534 } else { 7535 env->tsc = 0; 7536 } 7537 7538 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7539 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7540 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7541 } 7542 7543 memset(env->dr, 0, sizeof(env->dr)); 7544 env->dr[6] = DR6_FIXED_1; 7545 env->dr[7] = DR7_FIXED_1; 7546 cpu_breakpoint_remove_all(cs, BP_CPU); 7547 cpu_watchpoint_remove_all(cs, BP_CPU); 7548 7549 cr4 = 0; 7550 xcr0 = XSTATE_FP_MASK; 7551 7552 #ifdef CONFIG_USER_ONLY 7553 /* Enable all the features for user-mode. */ 7554 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7555 xcr0 |= XSTATE_SSE_MASK; 7556 } 7557 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7558 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7559 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7560 continue; 7561 } 7562 if (cpuid_has_xsave_feature(env, esa)) { 7563 xcr0 |= 1ull << i; 7564 } 7565 } 7566 7567 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7568 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7569 } 7570 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7571 cr4 |= CR4_FSGSBASE_MASK; 7572 } 7573 #endif 7574 7575 env->xcr0 = xcr0; 7576 cpu_x86_update_cr4(env, cr4); 7577 7578 /* 7579 * SDM 11.11.5 requires: 7580 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7581 * - IA32_MTRR_PHYSMASKn.V = 0 7582 * All other bits are undefined. For simplification, zero it all. 7583 */ 7584 env->mtrr_deftype = 0; 7585 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7586 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7587 7588 env->interrupt_injected = -1; 7589 env->exception_nr = -1; 7590 env->exception_pending = 0; 7591 env->exception_injected = 0; 7592 env->exception_has_payload = false; 7593 env->exception_payload = 0; 7594 env->nmi_injected = false; 7595 env->triple_fault_pending = false; 7596 #if !defined(CONFIG_USER_ONLY) 7597 /* We hard-wire the BSP to the first CPU. */ 7598 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7599 7600 cs->halted = !cpu_is_bsp(cpu); 7601 7602 if (kvm_enabled()) { 7603 kvm_arch_reset_vcpu(cpu); 7604 } 7605 7606 x86_cpu_set_sgxlepubkeyhash(env); 7607 7608 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7609 7610 #endif 7611 } 7612 7613 void x86_cpu_after_reset(X86CPU *cpu) 7614 { 7615 #ifndef CONFIG_USER_ONLY 7616 if (kvm_enabled()) { 7617 kvm_arch_after_reset_vcpu(cpu); 7618 } 7619 7620 if (cpu->apic_state) { 7621 device_cold_reset(cpu->apic_state); 7622 } 7623 #endif 7624 } 7625 7626 static void mce_init(X86CPU *cpu) 7627 { 7628 CPUX86State *cenv = &cpu->env; 7629 unsigned int bank; 7630 7631 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7632 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7633 (CPUID_MCE | CPUID_MCA)) { 7634 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7635 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7636 cenv->mcg_ctl = ~(uint64_t)0; 7637 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7638 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7639 } 7640 } 7641 } 7642 7643 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7644 { 7645 if (*min < value) { 7646 *min = value; 7647 } 7648 } 7649 7650 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7651 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7652 { 7653 CPUX86State *env = &cpu->env; 7654 FeatureWordInfo *fi = &feature_word_info[w]; 7655 uint32_t eax = fi->cpuid.eax; 7656 uint32_t region = eax & 0xF0000000; 7657 7658 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7659 if (!env->features[w]) { 7660 return; 7661 } 7662 7663 switch (region) { 7664 case 0x00000000: 7665 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7666 break; 7667 case 0x80000000: 7668 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7669 break; 7670 case 0xC0000000: 7671 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7672 break; 7673 } 7674 7675 if (eax == 7) { 7676 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7677 fi->cpuid.ecx); 7678 } 7679 } 7680 7681 /* Calculate XSAVE components based on the configured CPU feature flags */ 7682 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7683 { 7684 CPUX86State *env = &cpu->env; 7685 int i; 7686 uint64_t mask; 7687 static bool request_perm; 7688 7689 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7690 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7691 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7692 env->features[FEAT_XSAVE_XSS_LO] = 0; 7693 env->features[FEAT_XSAVE_XSS_HI] = 0; 7694 return; 7695 } 7696 7697 mask = 0; 7698 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7699 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7700 if (cpuid_has_xsave_feature(env, esa)) { 7701 mask |= (1ULL << i); 7702 } 7703 } 7704 7705 /* Only request permission for first vcpu */ 7706 if (kvm_enabled() && !request_perm) { 7707 kvm_request_xsave_components(cpu, mask); 7708 request_perm = true; 7709 } 7710 7711 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7712 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7713 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7714 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7715 } 7716 7717 /***** Steps involved on loading and filtering CPUID data 7718 * 7719 * When initializing and realizing a CPU object, the steps 7720 * involved in setting up CPUID data are: 7721 * 7722 * 1) Loading CPU model definition (X86CPUDefinition). This is 7723 * implemented by x86_cpu_load_model() and should be completely 7724 * transparent, as it is done automatically by instance_init. 7725 * No code should need to look at X86CPUDefinition structs 7726 * outside instance_init. 7727 * 7728 * 2) CPU expansion. This is done by realize before CPUID 7729 * filtering, and will make sure host/accelerator data is 7730 * loaded for CPU models that depend on host capabilities 7731 * (e.g. "host"). Done by x86_cpu_expand_features(). 7732 * 7733 * 3) CPUID filtering. This initializes extra data related to 7734 * CPUID, and checks if the host supports all capabilities 7735 * required by the CPU. Runnability of a CPU model is 7736 * determined at this step. Done by x86_cpu_filter_features(). 7737 * 7738 * Some operations don't require all steps to be performed. 7739 * More precisely: 7740 * 7741 * - CPU instance creation (instance_init) will run only CPU 7742 * model loading. CPU expansion can't run at instance_init-time 7743 * because host/accelerator data may be not available yet. 7744 * - CPU realization will perform both CPU model expansion and CPUID 7745 * filtering, and return an error in case one of them fails. 7746 * - query-cpu-definitions needs to run all 3 steps. It needs 7747 * to run CPUID filtering, as the 'unavailable-features' 7748 * field is set based on the filtering results. 7749 * - The query-cpu-model-expansion QMP command only needs to run 7750 * CPU model loading and CPU expansion. It should not filter 7751 * any CPUID data based on host capabilities. 7752 */ 7753 7754 /* Expand CPU configuration data, based on configured features 7755 * and host/accelerator capabilities when appropriate. 7756 */ 7757 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7758 { 7759 CPUX86State *env = &cpu->env; 7760 FeatureWord w; 7761 int i; 7762 GList *l; 7763 7764 for (l = plus_features; l; l = l->next) { 7765 const char *prop = l->data; 7766 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7767 return; 7768 } 7769 } 7770 7771 for (l = minus_features; l; l = l->next) { 7772 const char *prop = l->data; 7773 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7774 return; 7775 } 7776 } 7777 7778 /*TODO: Now cpu->max_features doesn't overwrite features 7779 * set using QOM properties, and we can convert 7780 * plus_features & minus_features to global properties 7781 * inside x86_cpu_parse_featurestr() too. 7782 */ 7783 if (cpu->max_features) { 7784 for (w = 0; w < FEATURE_WORDS; w++) { 7785 /* Override only features that weren't set explicitly 7786 * by the user. 7787 */ 7788 env->features[w] |= 7789 x86_cpu_get_supported_feature_word(cpu, w) & 7790 ~env->user_features[w] & 7791 ~feature_word_info[w].no_autoenable_flags; 7792 } 7793 7794 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 7795 uint32_t eax, ebx, ecx, edx; 7796 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 7797 env->avx10_version = ebx & 0xff; 7798 } 7799 } 7800 7801 if (x86_threads_per_pkg(&env->topo_info) > 1) { 7802 env->features[FEAT_1_EDX] |= CPUID_HT; 7803 7804 /* 7805 * The Linux kernel checks for the CMPLegacy bit and 7806 * discards multiple thread information if it is set. 7807 * So don't set it here for Intel (and other processors 7808 * following Intel's behavior) to make Linux guests happy. 7809 */ 7810 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 7811 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 7812 } 7813 } 7814 7815 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7816 FeatureDep *d = &feature_dependencies[i]; 7817 if (!(env->features[d->from.index] & d->from.mask)) { 7818 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7819 7820 /* Not an error unless the dependent feature was added explicitly. */ 7821 mark_unavailable_features(cpu, d->to.index, 7822 unavailable_features & env->user_features[d->to.index], 7823 "This feature depends on other features that were not requested"); 7824 7825 env->features[d->to.index] &= ~unavailable_features; 7826 } 7827 } 7828 7829 if (!kvm_enabled() || !cpu->expose_kvm) { 7830 env->features[FEAT_KVM] = 0; 7831 } 7832 7833 x86_cpu_enable_xsave_components(cpu); 7834 7835 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7836 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7837 if (cpu->full_cpuid_auto_level) { 7838 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7839 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7840 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7841 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7842 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7843 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7844 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7845 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7846 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7847 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7848 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7849 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7850 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7851 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7852 7853 /* Intel Processor Trace requires CPUID[0x14] */ 7854 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7855 if (cpu->intel_pt_auto_level) { 7856 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7857 } else if (cpu->env.cpuid_min_level < 0x14) { 7858 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7859 CPUID_7_0_EBX_INTEL_PT, 7860 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7861 } 7862 } 7863 7864 /* 7865 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7866 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7867 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7868 * cpu->vendor_cpuid_only has been unset for compatibility with older 7869 * machine types. 7870 */ 7871 if (x86_has_extended_topo(env->avail_cpu_topo) && 7872 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7873 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7874 } 7875 7876 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 7877 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7878 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 7879 } 7880 7881 /* SVM requires CPUID[0x8000000A] */ 7882 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7883 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7884 } 7885 7886 /* SEV requires CPUID[0x8000001F] */ 7887 if (sev_enabled()) { 7888 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7889 } 7890 7891 if (env->features[FEAT_8000_0021_EAX]) { 7892 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7893 } 7894 7895 /* SGX requires CPUID[0x12] for EPC enumeration */ 7896 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7897 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7898 } 7899 } 7900 7901 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7902 if (env->cpuid_level_func7 == UINT32_MAX) { 7903 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7904 } 7905 if (env->cpuid_level == UINT32_MAX) { 7906 env->cpuid_level = env->cpuid_min_level; 7907 } 7908 if (env->cpuid_xlevel == UINT32_MAX) { 7909 env->cpuid_xlevel = env->cpuid_min_xlevel; 7910 } 7911 if (env->cpuid_xlevel2 == UINT32_MAX) { 7912 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7913 } 7914 7915 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7916 return; 7917 } 7918 } 7919 7920 /* 7921 * Finishes initialization of CPUID data, filters CPU feature 7922 * words based on host availability of each feature. 7923 * 7924 * Returns: true if any flag is not supported by the host, false otherwise. 7925 */ 7926 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7927 { 7928 CPUX86State *env = &cpu->env; 7929 FeatureWord w; 7930 const char *prefix = NULL; 7931 bool have_filtered_features; 7932 7933 uint32_t eax_0, ebx_0, ecx_0, edx_0; 7934 uint32_t eax_1, ebx_1, ecx_1, edx_1; 7935 7936 if (verbose) { 7937 prefix = accel_uses_host_cpuid() 7938 ? "host doesn't support requested feature" 7939 : "TCG doesn't support requested feature"; 7940 } 7941 7942 for (w = 0; w < FEATURE_WORDS; w++) { 7943 uint64_t host_feat = 7944 x86_cpu_get_supported_feature_word(NULL, w); 7945 uint64_t requested_features = env->features[w]; 7946 uint64_t unavailable_features = requested_features & ~host_feat; 7947 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7948 } 7949 7950 /* 7951 * Check that KVM actually allows the processor tracing features that 7952 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7953 */ 7954 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7955 kvm_enabled()) { 7956 x86_cpu_get_supported_cpuid(0x14, 0, 7957 &eax_0, &ebx_0, &ecx_0, &edx_0); 7958 x86_cpu_get_supported_cpuid(0x14, 1, 7959 &eax_1, &ebx_1, &ecx_1, &edx_1); 7960 7961 if (!eax_0 || 7962 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7963 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7964 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7965 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7966 INTEL_PT_ADDR_RANGES_NUM) || 7967 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7968 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7969 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7970 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7971 /* 7972 * Processor Trace capabilities aren't configurable, so if the 7973 * host can't emulate the capabilities we report on 7974 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7975 */ 7976 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7977 } 7978 } 7979 7980 have_filtered_features = x86_cpu_have_filtered_features(cpu); 7981 7982 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7983 x86_cpu_get_supported_cpuid(0x24, 0, 7984 &eax_0, &ebx_0, &ecx_0, &edx_0); 7985 uint8_t version = ebx_0 & 0xff; 7986 7987 if (version < env->avx10_version) { 7988 if (prefix) { 7989 warn_report("%s: avx10.%d. Adjust to avx10.%d", 7990 prefix, env->avx10_version, version); 7991 } 7992 env->avx10_version = version; 7993 have_filtered_features = true; 7994 } 7995 } else if (env->avx10_version) { 7996 if (prefix) { 7997 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 7998 } 7999 have_filtered_features = true; 8000 } 8001 8002 return have_filtered_features; 8003 } 8004 8005 static void x86_cpu_hyperv_realize(X86CPU *cpu) 8006 { 8007 size_t len; 8008 8009 /* Hyper-V vendor id */ 8010 if (!cpu->hyperv_vendor) { 8011 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 8012 &error_abort); 8013 } 8014 len = strlen(cpu->hyperv_vendor); 8015 if (len > 12) { 8016 warn_report("hv-vendor-id truncated to 12 characters"); 8017 len = 12; 8018 } 8019 memset(cpu->hyperv_vendor_id, 0, 12); 8020 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 8021 8022 /* 'Hv#1' interface identification*/ 8023 cpu->hyperv_interface_id[0] = 0x31237648; 8024 cpu->hyperv_interface_id[1] = 0; 8025 cpu->hyperv_interface_id[2] = 0; 8026 cpu->hyperv_interface_id[3] = 0; 8027 8028 /* Hypervisor implementation limits */ 8029 cpu->hyperv_limits[0] = 64; 8030 cpu->hyperv_limits[1] = 0; 8031 cpu->hyperv_limits[2] = 0; 8032 } 8033 8034 #ifndef CONFIG_USER_ONLY 8035 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 8036 Error **errp) 8037 { 8038 CPUX86State *env = &cpu->env; 8039 CpuTopologyLevel level; 8040 8041 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 8042 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8043 env->cache_info_cpuid4.l1d_cache->share_level = level; 8044 env->cache_info_amd.l1d_cache->share_level = level; 8045 } else { 8046 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8047 env->cache_info_cpuid4.l1d_cache->share_level); 8048 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8049 env->cache_info_amd.l1d_cache->share_level); 8050 } 8051 8052 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 8053 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8054 env->cache_info_cpuid4.l1i_cache->share_level = level; 8055 env->cache_info_amd.l1i_cache->share_level = level; 8056 } else { 8057 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8058 env->cache_info_cpuid4.l1i_cache->share_level); 8059 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8060 env->cache_info_amd.l1i_cache->share_level); 8061 } 8062 8063 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 8064 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8065 env->cache_info_cpuid4.l2_cache->share_level = level; 8066 env->cache_info_amd.l2_cache->share_level = level; 8067 } else { 8068 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8069 env->cache_info_cpuid4.l2_cache->share_level); 8070 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8071 env->cache_info_amd.l2_cache->share_level); 8072 } 8073 8074 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 8075 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8076 env->cache_info_cpuid4.l3_cache->share_level = level; 8077 env->cache_info_amd.l3_cache->share_level = level; 8078 } else { 8079 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8080 env->cache_info_cpuid4.l3_cache->share_level); 8081 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8082 env->cache_info_amd.l3_cache->share_level); 8083 } 8084 8085 if (!machine_check_smp_cache(ms, errp)) { 8086 return false; 8087 } 8088 return true; 8089 } 8090 #endif 8091 8092 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 8093 { 8094 CPUState *cs = CPU(dev); 8095 X86CPU *cpu = X86_CPU(dev); 8096 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8097 CPUX86State *env = &cpu->env; 8098 Error *local_err = NULL; 8099 unsigned requested_lbr_fmt; 8100 8101 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 8102 /* Use pc-relative instructions in system-mode */ 8103 tcg_cflags_set(cs, CF_PCREL); 8104 #endif 8105 8106 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 8107 error_setg(errp, "apic-id property was not initialized properly"); 8108 return; 8109 } 8110 8111 /* 8112 * Process Hyper-V enlightenments. 8113 * Note: this currently has to happen before the expansion of CPU features. 8114 */ 8115 x86_cpu_hyperv_realize(cpu); 8116 8117 x86_cpu_expand_features(cpu, &local_err); 8118 if (local_err) { 8119 goto out; 8120 } 8121 8122 /* 8123 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 8124 * with user-provided setting. 8125 */ 8126 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 8127 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 8128 error_setg(errp, "invalid lbr-fmt"); 8129 return; 8130 } 8131 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 8132 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 8133 } 8134 8135 /* 8136 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 8137 * 3)vPMU LBR format matches that of host setting. 8138 */ 8139 requested_lbr_fmt = 8140 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 8141 if (requested_lbr_fmt && kvm_enabled()) { 8142 uint64_t host_perf_cap = 8143 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 8144 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 8145 8146 if (!cpu->enable_pmu) { 8147 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 8148 return; 8149 } 8150 if (requested_lbr_fmt != host_lbr_fmt) { 8151 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 8152 "the host value (0x%x).", 8153 requested_lbr_fmt, host_lbr_fmt); 8154 return; 8155 } 8156 } 8157 8158 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 8159 if (cpu->enforce_cpuid) { 8160 error_setg(&local_err, 8161 accel_uses_host_cpuid() ? 8162 "Host doesn't support requested features" : 8163 "TCG doesn't support requested features"); 8164 goto out; 8165 } 8166 } 8167 8168 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 8169 * CPUID[1].EDX. 8170 */ 8171 if (IS_AMD_CPU(env)) { 8172 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 8173 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 8174 & CPUID_EXT2_AMD_ALIASES); 8175 } 8176 8177 x86_cpu_set_sgxlepubkeyhash(env); 8178 8179 /* 8180 * note: the call to the framework needs to happen after feature expansion, 8181 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 8182 * These may be set by the accel-specific code, 8183 * and the results are subsequently checked / assumed in this function. 8184 */ 8185 cpu_exec_realizefn(cs, &local_err); 8186 if (local_err != NULL) { 8187 error_propagate(errp, local_err); 8188 return; 8189 } 8190 8191 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 8192 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8193 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 8194 goto out; 8195 } 8196 8197 if (cpu->guest_phys_bits == -1) { 8198 /* 8199 * If it was not set by the user, or by the accelerator via 8200 * cpu_exec_realizefn, clear. 8201 */ 8202 cpu->guest_phys_bits = 0; 8203 } 8204 8205 if (cpu->ucode_rev == 0) { 8206 /* 8207 * The default is the same as KVM's. Note that this check 8208 * needs to happen after the evenual setting of ucode_rev in 8209 * accel-specific code in cpu_exec_realizefn. 8210 */ 8211 if (IS_AMD_CPU(env)) { 8212 cpu->ucode_rev = 0x01000065; 8213 } else { 8214 cpu->ucode_rev = 0x100000000ULL; 8215 } 8216 } 8217 8218 /* 8219 * mwait extended info: needed for Core compatibility 8220 * We always wake on interrupt even if host does not have the capability. 8221 * 8222 * requires the accel-specific code in cpu_exec_realizefn to 8223 * have already acquired the CPUID data into cpu->mwait. 8224 */ 8225 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 8226 8227 /* 8228 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 8229 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8230 * based on inputs (sockets,cores,threads), it is still better to give 8231 * users a warning. 8232 */ 8233 if (IS_AMD_CPU(env) && 8234 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8235 env->topo_info.threads_per_core > 1) { 8236 warn_report_once("This family of AMD CPU doesn't support " 8237 "hyperthreading(%d). Please configure -smp " 8238 "options properly or try enabling topoext " 8239 "feature.", env->topo_info.threads_per_core); 8240 } 8241 8242 /* For 64bit systems think about the number of physical bits to present. 8243 * ideally this should be the same as the host; anything other than matching 8244 * the host can cause incorrect guest behaviour. 8245 * QEMU used to pick the magic value of 40 bits that corresponds to 8246 * consumer AMD devices but nothing else. 8247 * 8248 * Note that this code assumes features expansion has already been done 8249 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 8250 * phys_bits adjustments to match the host have been already done in 8251 * accel-specific code in cpu_exec_realizefn. 8252 */ 8253 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8254 if (cpu->phys_bits && 8255 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 8256 cpu->phys_bits < 32)) { 8257 error_setg(errp, "phys-bits should be between 32 and %u " 8258 " (but is %u)", 8259 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 8260 return; 8261 } 8262 /* 8263 * 0 means it was not explicitly set by the user (or by machine 8264 * compat_props or by the host code in host-cpu.c). 8265 * In this case, the default is the value used by TCG (40). 8266 */ 8267 if (cpu->phys_bits == 0) { 8268 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 8269 } 8270 if (cpu->guest_phys_bits && 8271 (cpu->guest_phys_bits > cpu->phys_bits || 8272 cpu->guest_phys_bits < 32)) { 8273 error_setg(errp, "guest-phys-bits should be between 32 and %u " 8274 " (but is %u)", 8275 cpu->phys_bits, cpu->guest_phys_bits); 8276 return; 8277 } 8278 } else { 8279 /* For 32 bit systems don't use the user set value, but keep 8280 * phys_bits consistent with what we tell the guest. 8281 */ 8282 if (cpu->phys_bits != 0) { 8283 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 8284 return; 8285 } 8286 if (cpu->guest_phys_bits != 0) { 8287 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 8288 return; 8289 } 8290 8291 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 8292 cpu->phys_bits = 36; 8293 } else { 8294 cpu->phys_bits = 32; 8295 } 8296 } 8297 8298 /* Cache information initialization */ 8299 if (!cpu->legacy_cache) { 8300 const CPUCaches *cache_info = 8301 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 8302 8303 if (!xcc->model || !cache_info) { 8304 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8305 error_setg(errp, 8306 "CPU model '%s' doesn't support legacy-cache=off", name); 8307 return; 8308 } 8309 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 8310 *cache_info; 8311 } else { 8312 /* Build legacy cache information */ 8313 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 8314 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 8315 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 8316 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 8317 8318 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 8319 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 8320 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 8321 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 8322 8323 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 8324 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 8325 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 8326 env->cache_info_amd.l3_cache = &legacy_l3_cache; 8327 } 8328 8329 #ifndef CONFIG_USER_ONLY 8330 MachineState *ms = MACHINE(qdev_get_machine()); 8331 MachineClass *mc = MACHINE_GET_CLASS(ms); 8332 8333 if (mc->smp_props.has_caches) { 8334 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 8335 return; 8336 } 8337 } 8338 8339 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 8340 8341 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 8342 x86_cpu_apic_create(cpu, &local_err); 8343 if (local_err != NULL) { 8344 goto out; 8345 } 8346 } 8347 #endif 8348 8349 mce_init(cpu); 8350 8351 x86_cpu_gdb_init(cs); 8352 qemu_init_vcpu(cs); 8353 8354 #ifndef CONFIG_USER_ONLY 8355 x86_cpu_apic_realize(cpu, &local_err); 8356 if (local_err != NULL) { 8357 goto out; 8358 } 8359 #endif /* !CONFIG_USER_ONLY */ 8360 cpu_reset(cs); 8361 8362 xcc->parent_realize(dev, &local_err); 8363 8364 out: 8365 if (local_err != NULL) { 8366 error_propagate(errp, local_err); 8367 return; 8368 } 8369 } 8370 8371 static void x86_cpu_unrealizefn(DeviceState *dev) 8372 { 8373 X86CPU *cpu = X86_CPU(dev); 8374 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8375 8376 #ifndef CONFIG_USER_ONLY 8377 cpu_remove_sync(CPU(dev)); 8378 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8379 #endif 8380 8381 if (cpu->apic_state) { 8382 object_unparent(OBJECT(cpu->apic_state)); 8383 cpu->apic_state = NULL; 8384 } 8385 8386 xcc->parent_unrealize(dev); 8387 } 8388 8389 typedef struct BitProperty { 8390 FeatureWord w; 8391 uint64_t mask; 8392 } BitProperty; 8393 8394 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8395 void *opaque, Error **errp) 8396 { 8397 X86CPU *cpu = X86_CPU(obj); 8398 BitProperty *fp = opaque; 8399 uint64_t f = cpu->env.features[fp->w]; 8400 bool value = (f & fp->mask) == fp->mask; 8401 visit_type_bool(v, name, &value, errp); 8402 } 8403 8404 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8405 void *opaque, Error **errp) 8406 { 8407 DeviceState *dev = DEVICE(obj); 8408 X86CPU *cpu = X86_CPU(obj); 8409 BitProperty *fp = opaque; 8410 bool value; 8411 8412 if (dev->realized) { 8413 qdev_prop_set_after_realize(dev, name, errp); 8414 return; 8415 } 8416 8417 if (!visit_type_bool(v, name, &value, errp)) { 8418 return; 8419 } 8420 8421 if (value) { 8422 cpu->env.features[fp->w] |= fp->mask; 8423 } else { 8424 cpu->env.features[fp->w] &= ~fp->mask; 8425 } 8426 cpu->env.user_features[fp->w] |= fp->mask; 8427 } 8428 8429 /* Register a boolean property to get/set a single bit in a uint32_t field. 8430 * 8431 * The same property name can be registered multiple times to make it affect 8432 * multiple bits in the same FeatureWord. In that case, the getter will return 8433 * true only if all bits are set. 8434 */ 8435 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8436 const char *prop_name, 8437 FeatureWord w, 8438 int bitnr) 8439 { 8440 ObjectClass *oc = OBJECT_CLASS(xcc); 8441 BitProperty *fp; 8442 ObjectProperty *op; 8443 uint64_t mask = (1ULL << bitnr); 8444 8445 op = object_class_property_find(oc, prop_name); 8446 if (op) { 8447 fp = op->opaque; 8448 assert(fp->w == w); 8449 fp->mask |= mask; 8450 } else { 8451 fp = g_new0(BitProperty, 1); 8452 fp->w = w; 8453 fp->mask = mask; 8454 object_class_property_add(oc, prop_name, "bool", 8455 x86_cpu_get_bit_prop, 8456 x86_cpu_set_bit_prop, 8457 NULL, fp); 8458 } 8459 } 8460 8461 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8462 FeatureWord w, 8463 int bitnr) 8464 { 8465 FeatureWordInfo *fi = &feature_word_info[w]; 8466 const char *name = fi->feat_names[bitnr]; 8467 8468 if (!name) { 8469 return; 8470 } 8471 8472 /* Property names should use "-" instead of "_". 8473 * Old names containing underscores are registered as aliases 8474 * using object_property_add_alias() 8475 */ 8476 assert(!strchr(name, '_')); 8477 /* aliases don't use "|" delimiters anymore, they are registered 8478 * manually using object_property_add_alias() */ 8479 assert(!strchr(name, '|')); 8480 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8481 } 8482 8483 static void x86_cpu_post_initfn(Object *obj) 8484 { 8485 static bool first = true; 8486 uint64_t supported_xcr0; 8487 int i; 8488 8489 if (first) { 8490 first = false; 8491 8492 supported_xcr0 = 8493 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 8494 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 8495 8496 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 8497 ExtSaveArea *esa = &x86_ext_save_areas[i]; 8498 8499 if (!(supported_xcr0 & (1 << i))) { 8500 esa->size = 0; 8501 } 8502 } 8503 } 8504 8505 accel_cpu_instance_init(CPU(obj)); 8506 } 8507 8508 static void x86_cpu_init_default_topo(X86CPU *cpu) 8509 { 8510 CPUX86State *env = &cpu->env; 8511 8512 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 8513 8514 /* thread, core and socket levels are set by default. */ 8515 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 8516 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 8517 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 8518 } 8519 8520 static void x86_cpu_initfn(Object *obj) 8521 { 8522 X86CPU *cpu = X86_CPU(obj); 8523 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8524 CPUX86State *env = &cpu->env; 8525 8526 x86_cpu_init_default_topo(cpu); 8527 8528 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8529 x86_cpu_get_feature_words, 8530 NULL, NULL, (void *)env->features); 8531 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8532 x86_cpu_get_feature_words, 8533 NULL, NULL, (void *)cpu->filtered_features); 8534 8535 object_property_add_alias(obj, "sse3", obj, "pni"); 8536 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8537 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8538 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8539 object_property_add_alias(obj, "xd", obj, "nx"); 8540 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8541 object_property_add_alias(obj, "i64", obj, "lm"); 8542 8543 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8544 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8545 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8546 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8547 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8548 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8549 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8550 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8551 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8552 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8553 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8554 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8555 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8556 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8557 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8558 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8559 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8560 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8561 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8562 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8563 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8564 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8565 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8566 8567 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8568 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8569 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8570 8571 if (xcc->model) { 8572 x86_cpu_load_model(cpu, xcc->model); 8573 } 8574 } 8575 8576 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8577 { 8578 X86CPU *cpu = X86_CPU(cs); 8579 8580 return cpu->apic_id; 8581 } 8582 8583 #if !defined(CONFIG_USER_ONLY) 8584 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8585 { 8586 X86CPU *cpu = X86_CPU(cs); 8587 8588 return cpu->env.cr[0] & CR0_PG_MASK; 8589 } 8590 #endif /* !CONFIG_USER_ONLY */ 8591 8592 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8593 { 8594 X86CPU *cpu = X86_CPU(cs); 8595 8596 cpu->env.eip = value; 8597 } 8598 8599 static vaddr x86_cpu_get_pc(CPUState *cs) 8600 { 8601 X86CPU *cpu = X86_CPU(cs); 8602 8603 /* Match cpu_get_tb_cpu_state. */ 8604 return cpu->env.eip + cpu->env.segs[R_CS].base; 8605 } 8606 8607 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8608 { 8609 X86CPU *cpu = X86_CPU(cs); 8610 CPUX86State *env = &cpu->env; 8611 8612 #if !defined(CONFIG_USER_ONLY) 8613 if (interrupt_request & CPU_INTERRUPT_POLL) { 8614 return CPU_INTERRUPT_POLL; 8615 } 8616 #endif 8617 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8618 return CPU_INTERRUPT_SIPI; 8619 } 8620 8621 if (env->hflags2 & HF2_GIF_MASK) { 8622 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8623 !(env->hflags & HF_SMM_MASK)) { 8624 return CPU_INTERRUPT_SMI; 8625 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8626 !(env->hflags2 & HF2_NMI_MASK)) { 8627 return CPU_INTERRUPT_NMI; 8628 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8629 return CPU_INTERRUPT_MCE; 8630 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8631 (((env->hflags2 & HF2_VINTR_MASK) && 8632 (env->hflags2 & HF2_HIF_MASK)) || 8633 (!(env->hflags2 & HF2_VINTR_MASK) && 8634 (env->eflags & IF_MASK && 8635 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8636 return CPU_INTERRUPT_HARD; 8637 #if !defined(CONFIG_USER_ONLY) 8638 } else if (env->hflags2 & HF2_VGIF_MASK) { 8639 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8640 (env->eflags & IF_MASK) && 8641 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8642 return CPU_INTERRUPT_VIRQ; 8643 } 8644 #endif 8645 } 8646 } 8647 8648 return 0; 8649 } 8650 8651 static bool x86_cpu_has_work(CPUState *cs) 8652 { 8653 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8654 } 8655 8656 int x86_mmu_index_pl(CPUX86State *env, unsigned pl) 8657 { 8658 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8659 int mmu_index_base = 8660 pl == 3 ? MMU_USER64_IDX : 8661 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8662 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8663 8664 return mmu_index_base + mmu_index_32; 8665 } 8666 8667 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8668 { 8669 CPUX86State *env = cpu_env(cs); 8670 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); 8671 } 8672 8673 static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) 8674 { 8675 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; 8676 int mmu_index_base = 8677 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8678 (pl < 3 && (env->eflags & AC_MASK) 8679 ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); 8680 8681 return mmu_index_base + mmu_index_32; 8682 } 8683 8684 int cpu_mmu_index_kernel(CPUX86State *env) 8685 { 8686 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); 8687 } 8688 8689 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8690 { 8691 X86CPU *cpu = X86_CPU(cs); 8692 CPUX86State *env = &cpu->env; 8693 8694 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8695 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8696 : bfd_mach_i386_i8086); 8697 8698 info->cap_arch = CS_ARCH_X86; 8699 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8700 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8701 : CS_MODE_16); 8702 info->cap_insn_unit = 1; 8703 info->cap_insn_split = 8; 8704 } 8705 8706 void x86_update_hflags(CPUX86State *env) 8707 { 8708 uint32_t hflags; 8709 #define HFLAG_COPY_MASK \ 8710 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8711 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8712 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8713 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8714 8715 hflags = env->hflags & HFLAG_COPY_MASK; 8716 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8717 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8718 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8719 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8720 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8721 8722 if (env->cr[4] & CR4_OSFXSR_MASK) { 8723 hflags |= HF_OSFXSR_MASK; 8724 } 8725 8726 if (env->efer & MSR_EFER_LMA) { 8727 hflags |= HF_LMA_MASK; 8728 } 8729 8730 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8731 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8732 } else { 8733 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8734 (DESC_B_SHIFT - HF_CS32_SHIFT); 8735 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8736 (DESC_B_SHIFT - HF_SS32_SHIFT); 8737 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8738 !(hflags & HF_CS32_MASK)) { 8739 hflags |= HF_ADDSEG_MASK; 8740 } else { 8741 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8742 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8743 } 8744 } 8745 env->hflags = hflags; 8746 } 8747 8748 static const Property x86_cpu_properties[] = { 8749 #ifdef CONFIG_USER_ONLY 8750 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8751 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8752 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8753 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8754 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8755 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8756 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8757 #else 8758 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8759 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8760 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8761 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8762 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8763 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8764 #endif 8765 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8766 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8767 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8768 8769 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8770 HYPERV_SPINLOCK_NEVER_NOTIFY), 8771 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8772 HYPERV_FEAT_RELAXED, 0), 8773 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8774 HYPERV_FEAT_VAPIC, 0), 8775 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8776 HYPERV_FEAT_TIME, 0), 8777 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8778 HYPERV_FEAT_CRASH, 0), 8779 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8780 HYPERV_FEAT_RESET, 0), 8781 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8782 HYPERV_FEAT_VPINDEX, 0), 8783 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8784 HYPERV_FEAT_RUNTIME, 0), 8785 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8786 HYPERV_FEAT_SYNIC, 0), 8787 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8788 HYPERV_FEAT_STIMER, 0), 8789 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8790 HYPERV_FEAT_FREQUENCIES, 0), 8791 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8792 HYPERV_FEAT_REENLIGHTENMENT, 0), 8793 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8794 HYPERV_FEAT_TLBFLUSH, 0), 8795 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8796 HYPERV_FEAT_EVMCS, 0), 8797 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8798 HYPERV_FEAT_IPI, 0), 8799 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8800 HYPERV_FEAT_STIMER_DIRECT, 0), 8801 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8802 HYPERV_FEAT_AVIC, 0), 8803 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8804 HYPERV_FEAT_MSR_BITMAP, 0), 8805 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8806 HYPERV_FEAT_XMM_INPUT, 0), 8807 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8808 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8809 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8810 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8811 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8812 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8813 #ifdef CONFIG_SYNDBG 8814 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8815 HYPERV_FEAT_SYNDBG, 0), 8816 #endif 8817 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8818 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8819 8820 /* WS2008R2 identify by default */ 8821 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8822 0x3839), 8823 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8824 0x000A), 8825 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8826 0x0000), 8827 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8828 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8829 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8830 8831 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8832 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8833 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8834 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8835 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8836 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8837 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8838 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8839 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8840 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8841 UINT32_MAX), 8842 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8843 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8844 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8845 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8846 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8847 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8848 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 8849 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8850 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8851 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8852 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8853 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8854 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8855 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8856 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8857 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8858 false), 8859 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8860 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8861 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8862 true), 8863 /* 8864 * lecacy_cache defaults to true unless the CPU model provides its 8865 * own cache information (see x86_cpu_load_def()). 8866 */ 8867 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8868 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8869 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8870 8871 /* 8872 * From "Requirements for Implementing the Microsoft 8873 * Hypervisor Interface": 8874 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8875 * 8876 * "Starting with Windows Server 2012 and Windows 8, if 8877 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8878 * the hypervisor imposes no specific limit to the number of VPs. 8879 * In this case, Windows Server 2012 guest VMs may use more than 8880 * 64 VPs, up to the maximum supported number of processors applicable 8881 * to the specific Windows version being used." 8882 */ 8883 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8884 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8885 false), 8886 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8887 true), 8888 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8889 }; 8890 8891 #ifndef CONFIG_USER_ONLY 8892 #include "hw/core/sysemu-cpu-ops.h" 8893 8894 static const struct SysemuCPUOps i386_sysemu_ops = { 8895 .get_memory_mapping = x86_cpu_get_memory_mapping, 8896 .get_paging_enabled = x86_cpu_get_paging_enabled, 8897 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8898 .asidx_from_attrs = x86_asidx_from_attrs, 8899 .get_crash_info = x86_cpu_get_crash_info, 8900 .write_elf32_note = x86_cpu_write_elf32_note, 8901 .write_elf64_note = x86_cpu_write_elf64_note, 8902 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8903 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8904 .legacy_vmsd = &vmstate_x86_cpu, 8905 }; 8906 #endif 8907 8908 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8909 { 8910 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8911 CPUClass *cc = CPU_CLASS(oc); 8912 DeviceClass *dc = DEVICE_CLASS(oc); 8913 ResettableClass *rc = RESETTABLE_CLASS(oc); 8914 FeatureWord w; 8915 8916 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8917 &xcc->parent_realize); 8918 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8919 &xcc->parent_unrealize); 8920 device_class_set_props(dc, x86_cpu_properties); 8921 8922 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8923 &xcc->parent_phases); 8924 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8925 8926 cc->class_by_name = x86_cpu_class_by_name; 8927 cc->parse_features = x86_cpu_parse_featurestr; 8928 cc->has_work = x86_cpu_has_work; 8929 cc->mmu_index = x86_cpu_mmu_index; 8930 cc->dump_state = x86_cpu_dump_state; 8931 cc->set_pc = x86_cpu_set_pc; 8932 cc->get_pc = x86_cpu_get_pc; 8933 cc->gdb_read_register = x86_cpu_gdb_read_register; 8934 cc->gdb_write_register = x86_cpu_gdb_write_register; 8935 cc->get_arch_id = x86_cpu_get_arch_id; 8936 8937 #ifndef CONFIG_USER_ONLY 8938 cc->sysemu_ops = &i386_sysemu_ops; 8939 #endif /* !CONFIG_USER_ONLY */ 8940 8941 cc->gdb_arch_name = x86_gdb_arch_name; 8942 #ifdef TARGET_X86_64 8943 cc->gdb_core_xml_file = "i386-64bit.xml"; 8944 #else 8945 cc->gdb_core_xml_file = "i386-32bit.xml"; 8946 #endif 8947 cc->disas_set_info = x86_disas_set_info; 8948 8949 dc->user_creatable = true; 8950 8951 object_class_property_add(oc, "family", "int", 8952 x86_cpuid_version_get_family, 8953 x86_cpuid_version_set_family, NULL, NULL); 8954 object_class_property_add(oc, "model", "int", 8955 x86_cpuid_version_get_model, 8956 x86_cpuid_version_set_model, NULL, NULL); 8957 object_class_property_add(oc, "stepping", "int", 8958 x86_cpuid_version_get_stepping, 8959 x86_cpuid_version_set_stepping, NULL, NULL); 8960 object_class_property_add_str(oc, "vendor", 8961 x86_cpuid_get_vendor, 8962 x86_cpuid_set_vendor); 8963 object_class_property_add_str(oc, "model-id", 8964 x86_cpuid_get_model_id, 8965 x86_cpuid_set_model_id); 8966 object_class_property_add(oc, "tsc-frequency", "int", 8967 x86_cpuid_get_tsc_freq, 8968 x86_cpuid_set_tsc_freq, NULL, NULL); 8969 /* 8970 * The "unavailable-features" property has the same semantics as 8971 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8972 * QMP command: they list the features that would have prevented the 8973 * CPU from running if the "enforce" flag was set. 8974 */ 8975 object_class_property_add(oc, "unavailable-features", "strList", 8976 x86_cpu_get_unavailable_features, 8977 NULL, NULL, NULL); 8978 8979 #if !defined(CONFIG_USER_ONLY) 8980 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8981 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8982 #endif 8983 8984 for (w = 0; w < FEATURE_WORDS; w++) { 8985 int bitnr; 8986 for (bitnr = 0; bitnr < 64; bitnr++) { 8987 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8988 } 8989 } 8990 } 8991 8992 static const TypeInfo x86_cpu_type_info = { 8993 .name = TYPE_X86_CPU, 8994 .parent = TYPE_CPU, 8995 .instance_size = sizeof(X86CPU), 8996 .instance_align = __alignof(X86CPU), 8997 .instance_init = x86_cpu_initfn, 8998 .instance_post_init = x86_cpu_post_initfn, 8999 9000 .abstract = true, 9001 .class_size = sizeof(X86CPUClass), 9002 .class_init = x86_cpu_common_class_init, 9003 }; 9004 9005 /* "base" CPU model, used by query-cpu-model-expansion */ 9006 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 9007 { 9008 X86CPUClass *xcc = X86_CPU_CLASS(oc); 9009 9010 xcc->static_model = true; 9011 xcc->migration_safe = true; 9012 xcc->model_description = "base CPU model type with no features enabled"; 9013 xcc->ordering = 8; 9014 } 9015 9016 static const TypeInfo x86_base_cpu_type_info = { 9017 .name = X86_CPU_TYPE_NAME("base"), 9018 .parent = TYPE_X86_CPU, 9019 .class_init = x86_cpu_base_class_init, 9020 }; 9021 9022 static void x86_cpu_register_types(void) 9023 { 9024 int i; 9025 9026 type_register_static(&x86_cpu_type_info); 9027 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 9028 x86_register_cpudef_types(&builtin_x86_defs[i]); 9029 } 9030 type_register_static(&max_x86_cpu_type_info); 9031 type_register_static(&x86_base_cpu_type_info); 9032 } 9033 9034 type_init(x86_cpu_register_types) 9035