1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #include "exec/watchpoint.h" 39 #ifndef CONFIG_USER_ONLY 40 #include "system/reset.h" 41 #include "qapi/qapi-commands-machine-target.h" 42 #include "system/address-spaces.h" 43 #include "hw/boards.h" 44 #include "hw/i386/sgx-epc.h" 45 #endif 46 #include "tcg/tcg-cpu.h" 47 48 #include "disas/capstone.h" 49 #include "cpu-internal.h" 50 51 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 52 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 53 uint32_t *eax, uint32_t *ebx, 54 uint32_t *ecx, uint32_t *edx); 55 56 /* Helpers for building CPUID[2] descriptors: */ 57 58 struct CPUID2CacheDescriptorInfo { 59 enum CacheType type; 60 int level; 61 int size; 62 int line_size; 63 int associativity; 64 }; 65 66 /* 67 * Known CPUID 2 cache descriptors. 68 * From Intel SDM Volume 2A, CPUID instruction 69 */ 70 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 71 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 72 .associativity = 4, .line_size = 32, }, 73 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 76 .associativity = 4, .line_size = 64, }, 77 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 78 .associativity = 2, .line_size = 32, }, 79 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 80 .associativity = 4, .line_size = 32, }, 81 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 82 .associativity = 4, .line_size = 64, }, 83 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 84 .associativity = 6, .line_size = 64, }, 85 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 86 .associativity = 2, .line_size = 64, }, 87 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 88 .associativity = 8, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x22, 0x23 are not included 91 */ 92 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 93 .associativity = 16, .line_size = 64, }, 94 /* lines per sector is not supported cpuid2_cache_descriptor(), 95 * so descriptors 0x25, 0x20 are not included 96 */ 97 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 98 .associativity = 8, .line_size = 64, }, 99 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 100 .associativity = 8, .line_size = 64, }, 101 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 106 .associativity = 4, .line_size = 32, }, 107 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 108 .associativity = 4, .line_size = 32, }, 109 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 110 .associativity = 4, .line_size = 32, }, 111 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 112 .associativity = 4, .line_size = 64, }, 113 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 114 .associativity = 8, .line_size = 64, }, 115 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 116 .associativity = 12, .line_size = 64, }, 117 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 118 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 119 .associativity = 12, .line_size = 64, }, 120 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 121 .associativity = 16, .line_size = 64, }, 122 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 123 .associativity = 12, .line_size = 64, }, 124 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 125 .associativity = 16, .line_size = 64, }, 126 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 127 .associativity = 24, .line_size = 64, }, 128 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 129 .associativity = 8, .line_size = 64, }, 130 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 131 .associativity = 4, .line_size = 64, }, 132 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 133 .associativity = 4, .line_size = 64, }, 134 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 135 .associativity = 4, .line_size = 64, }, 136 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 137 .associativity = 4, .line_size = 64, }, 138 /* lines per sector is not supported cpuid2_cache_descriptor(), 139 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 140 */ 141 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 142 .associativity = 8, .line_size = 64, }, 143 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 2, .line_size = 64, }, 145 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 146 .associativity = 8, .line_size = 64, }, 147 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 150 .associativity = 8, .line_size = 32, }, 151 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 152 .associativity = 8, .line_size = 32, }, 153 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 154 .associativity = 8, .line_size = 32, }, 155 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 156 .associativity = 4, .line_size = 64, }, 157 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 158 .associativity = 8, .line_size = 64, }, 159 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 160 .associativity = 4, .line_size = 64, }, 161 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 162 .associativity = 4, .line_size = 64, }, 163 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 164 .associativity = 4, .line_size = 64, }, 165 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 166 .associativity = 8, .line_size = 64, }, 167 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 168 .associativity = 8, .line_size = 64, }, 169 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 170 .associativity = 8, .line_size = 64, }, 171 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 172 .associativity = 12, .line_size = 64, }, 173 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 174 .associativity = 12, .line_size = 64, }, 175 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 176 .associativity = 12, .line_size = 64, }, 177 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 178 .associativity = 16, .line_size = 64, }, 179 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 180 .associativity = 16, .line_size = 64, }, 181 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 182 .associativity = 16, .line_size = 64, }, 183 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 184 .associativity = 24, .line_size = 64, }, 185 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 186 .associativity = 24, .line_size = 64, }, 187 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 188 .associativity = 24, .line_size = 64, }, 189 }; 190 191 /* 192 * "CPUID leaf 2 does not report cache descriptor information, 193 * use CPUID leaf 4 to query cache parameters" 194 */ 195 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 196 197 /* 198 * Return a CPUID 2 cache descriptor for a given cache. 199 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 200 */ 201 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 202 { 203 int i; 204 205 assert(cache->size > 0); 206 assert(cache->level > 0); 207 assert(cache->line_size > 0); 208 assert(cache->associativity > 0); 209 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 210 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 211 if (d->level == cache->level && d->type == cache->type && 212 d->size == cache->size && d->line_size == cache->line_size && 213 d->associativity == cache->associativity) { 214 return i; 215 } 216 } 217 218 return CACHE_DESCRIPTOR_UNAVAILABLE; 219 } 220 221 /* CPUID Leaf 4 constants: */ 222 223 /* EAX: */ 224 #define CACHE_TYPE_D 1 225 #define CACHE_TYPE_I 2 226 #define CACHE_TYPE_UNIFIED 3 227 228 #define CACHE_LEVEL(l) (l << 5) 229 230 #define CACHE_SELF_INIT_LEVEL (1 << 8) 231 232 /* EDX: */ 233 #define CACHE_NO_INVD_SHARING (1 << 0) 234 #define CACHE_INCLUSIVE (1 << 1) 235 #define CACHE_COMPLEX_IDX (1 << 2) 236 237 /* Encode CacheType for CPUID[4].EAX */ 238 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 239 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 240 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 241 0 /* Invalid value */) 242 243 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 244 enum CpuTopologyLevel share_level) 245 { 246 uint32_t num_ids = 0; 247 248 switch (share_level) { 249 case CPU_TOPOLOGY_LEVEL_CORE: 250 num_ids = 1 << apicid_core_offset(topo_info); 251 break; 252 case CPU_TOPOLOGY_LEVEL_MODULE: 253 num_ids = 1 << apicid_module_offset(topo_info); 254 break; 255 case CPU_TOPOLOGY_LEVEL_DIE: 256 num_ids = 1 << apicid_die_offset(topo_info); 257 break; 258 case CPU_TOPOLOGY_LEVEL_SOCKET: 259 num_ids = 1 << apicid_pkg_offset(topo_info); 260 break; 261 default: 262 /* 263 * Currently there is no use case for THREAD, so use 264 * assert directly to facilitate debugging. 265 */ 266 g_assert_not_reached(); 267 } 268 269 return num_ids - 1; 270 } 271 272 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 273 { 274 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 275 apicid_core_offset(topo_info)); 276 return num_cores - 1; 277 } 278 279 /* Encode cache info for CPUID[4] */ 280 static void encode_cache_cpuid4(CPUCacheInfo *cache, 281 X86CPUTopoInfo *topo_info, 282 uint32_t *eax, uint32_t *ebx, 283 uint32_t *ecx, uint32_t *edx) 284 { 285 assert(cache->size == cache->line_size * cache->associativity * 286 cache->partitions * cache->sets); 287 288 *eax = CACHE_TYPE(cache->type) | 289 CACHE_LEVEL(cache->level) | 290 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 291 (max_core_ids_in_package(topo_info) << 26) | 292 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 293 294 assert(cache->line_size > 0); 295 assert(cache->partitions > 0); 296 assert(cache->associativity > 0); 297 /* We don't implement fully-associative caches */ 298 assert(cache->associativity < cache->sets); 299 *ebx = (cache->line_size - 1) | 300 ((cache->partitions - 1) << 12) | 301 ((cache->associativity - 1) << 22); 302 303 assert(cache->sets > 0); 304 *ecx = cache->sets - 1; 305 306 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 307 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 308 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 309 } 310 311 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 312 enum CpuTopologyLevel topo_level) 313 { 314 switch (topo_level) { 315 case CPU_TOPOLOGY_LEVEL_THREAD: 316 return 1; 317 case CPU_TOPOLOGY_LEVEL_CORE: 318 return topo_info->threads_per_core; 319 case CPU_TOPOLOGY_LEVEL_MODULE: 320 return x86_threads_per_module(topo_info); 321 case CPU_TOPOLOGY_LEVEL_DIE: 322 return x86_threads_per_die(topo_info); 323 case CPU_TOPOLOGY_LEVEL_SOCKET: 324 return x86_threads_per_pkg(topo_info); 325 default: 326 g_assert_not_reached(); 327 } 328 return 0; 329 } 330 331 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 332 enum CpuTopologyLevel topo_level) 333 { 334 switch (topo_level) { 335 case CPU_TOPOLOGY_LEVEL_THREAD: 336 return 0; 337 case CPU_TOPOLOGY_LEVEL_CORE: 338 return apicid_core_offset(topo_info); 339 case CPU_TOPOLOGY_LEVEL_MODULE: 340 return apicid_module_offset(topo_info); 341 case CPU_TOPOLOGY_LEVEL_DIE: 342 return apicid_die_offset(topo_info); 343 case CPU_TOPOLOGY_LEVEL_SOCKET: 344 return apicid_pkg_offset(topo_info); 345 default: 346 g_assert_not_reached(); 347 } 348 return 0; 349 } 350 351 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 352 { 353 switch (topo_level) { 354 case CPU_TOPOLOGY_LEVEL_INVALID: 355 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 356 case CPU_TOPOLOGY_LEVEL_THREAD: 357 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 358 case CPU_TOPOLOGY_LEVEL_CORE: 359 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 360 case CPU_TOPOLOGY_LEVEL_MODULE: 361 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 362 case CPU_TOPOLOGY_LEVEL_DIE: 363 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 364 default: 365 /* Other types are not supported in QEMU. */ 366 g_assert_not_reached(); 367 } 368 return 0; 369 } 370 371 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 372 X86CPUTopoInfo *topo_info, 373 uint32_t *eax, uint32_t *ebx, 374 uint32_t *ecx, uint32_t *edx) 375 { 376 X86CPU *cpu = env_archcpu(env); 377 unsigned long level, base_level, next_level; 378 uint32_t num_threads_next_level, offset_next_level; 379 380 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 381 382 /* 383 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 384 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 385 */ 386 level = CPU_TOPOLOGY_LEVEL_THREAD; 387 base_level = level; 388 for (int i = 0; i <= count; i++) { 389 level = find_next_bit(env->avail_cpu_topo, 390 CPU_TOPOLOGY_LEVEL_SOCKET, 391 base_level); 392 393 /* 394 * CPUID[0x1f] doesn't explicitly encode the package level, 395 * and it just encodes the invalid level (all fields are 0) 396 * into the last subleaf of 0x1f. 397 */ 398 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 399 level = CPU_TOPOLOGY_LEVEL_INVALID; 400 break; 401 } 402 /* Search the next level. */ 403 base_level = level + 1; 404 } 405 406 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 407 num_threads_next_level = 0; 408 offset_next_level = 0; 409 } else { 410 next_level = find_next_bit(env->avail_cpu_topo, 411 CPU_TOPOLOGY_LEVEL_SOCKET, 412 level + 1); 413 num_threads_next_level = num_threads_by_topo_level(topo_info, 414 next_level); 415 offset_next_level = apicid_offset_by_topo_level(topo_info, 416 next_level); 417 } 418 419 *eax = offset_next_level; 420 /* The count (bits 15-00) doesn't need to be reliable. */ 421 *ebx = num_threads_next_level & 0xffff; 422 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 423 *edx = cpu->apic_id; 424 425 assert(!(*eax & ~0x1f)); 426 } 427 428 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 429 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 430 { 431 assert(cache->size % 1024 == 0); 432 assert(cache->lines_per_tag > 0); 433 assert(cache->associativity > 0); 434 assert(cache->line_size > 0); 435 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 436 (cache->lines_per_tag << 8) | (cache->line_size); 437 } 438 439 #define ASSOC_FULL 0xFF 440 441 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 442 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 443 a == 2 ? 0x2 : \ 444 a == 4 ? 0x4 : \ 445 a == 8 ? 0x6 : \ 446 a == 16 ? 0x8 : \ 447 a == 32 ? 0xA : \ 448 a == 48 ? 0xB : \ 449 a == 64 ? 0xC : \ 450 a == 96 ? 0xD : \ 451 a == 128 ? 0xE : \ 452 a == ASSOC_FULL ? 0xF : \ 453 0 /* invalid value */) 454 455 /* 456 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 457 * @l3 can be NULL. 458 */ 459 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 460 CPUCacheInfo *l3, 461 uint32_t *ecx, uint32_t *edx) 462 { 463 assert(l2->size % 1024 == 0); 464 assert(l2->associativity > 0); 465 assert(l2->lines_per_tag > 0); 466 assert(l2->line_size > 0); 467 *ecx = ((l2->size / 1024) << 16) | 468 (AMD_ENC_ASSOC(l2->associativity) << 12) | 469 (l2->lines_per_tag << 8) | (l2->line_size); 470 471 if (l3) { 472 assert(l3->size % (512 * 1024) == 0); 473 assert(l3->associativity > 0); 474 assert(l3->lines_per_tag > 0); 475 assert(l3->line_size > 0); 476 *edx = ((l3->size / (512 * 1024)) << 18) | 477 (AMD_ENC_ASSOC(l3->associativity) << 12) | 478 (l3->lines_per_tag << 8) | (l3->line_size); 479 } else { 480 *edx = 0; 481 } 482 } 483 484 /* Encode cache info for CPUID[8000001D] */ 485 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 486 X86CPUTopoInfo *topo_info, 487 uint32_t *eax, uint32_t *ebx, 488 uint32_t *ecx, uint32_t *edx) 489 { 490 assert(cache->size == cache->line_size * cache->associativity * 491 cache->partitions * cache->sets); 492 493 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 494 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 495 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 496 497 assert(cache->line_size > 0); 498 assert(cache->partitions > 0); 499 assert(cache->associativity > 0); 500 /* We don't implement fully-associative caches */ 501 assert(cache->associativity < cache->sets); 502 *ebx = (cache->line_size - 1) | 503 ((cache->partitions - 1) << 12) | 504 ((cache->associativity - 1) << 22); 505 506 assert(cache->sets > 0); 507 *ecx = cache->sets - 1; 508 509 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 510 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 511 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 512 } 513 514 /* Encode cache info for CPUID[8000001E] */ 515 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 516 uint32_t *eax, uint32_t *ebx, 517 uint32_t *ecx, uint32_t *edx) 518 { 519 X86CPUTopoIDs topo_ids; 520 521 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 522 523 *eax = cpu->apic_id; 524 525 /* 526 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 527 * Read-only. Reset: 0000_XXXXh. 528 * See Core::X86::Cpuid::ExtApicId. 529 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 530 * Bits Description 531 * 31:16 Reserved. 532 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 533 * The number of threads per core is ThreadsPerCore+1. 534 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 535 * 536 * NOTE: CoreId is already part of apic_id. Just use it. We can 537 * use all the 8 bits to represent the core_id here. 538 */ 539 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 540 541 /* 542 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 543 * Read-only. Reset: 0000_0XXXh. 544 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 545 * Bits Description 546 * 31:11 Reserved. 547 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 548 * ValidValues: 549 * Value Description 550 * 0h 1 node per processor. 551 * 7h-1h Reserved. 552 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 553 * 554 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 555 * But users can create more nodes than the actual hardware can 556 * support. To genaralize we can use all the upper 8 bits for nodes. 557 * NodeId is combination of node and socket_id which is already decoded 558 * in apic_id. Just use it by shifting. 559 */ 560 if (cpu->legacy_multi_node) { 561 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 562 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 563 } else { 564 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 565 } 566 567 *edx = 0; 568 } 569 570 /* 571 * Definitions of the hardcoded cache entries we expose: 572 * These are legacy cache values. If there is a need to change any 573 * of these values please use builtin_x86_defs 574 */ 575 576 /* L1 data cache: */ 577 static CPUCacheInfo legacy_l1d_cache = { 578 .type = DATA_CACHE, 579 .level = 1, 580 .size = 32 * KiB, 581 .self_init = 1, 582 .line_size = 64, 583 .associativity = 8, 584 .sets = 64, 585 .partitions = 1, 586 .no_invd_sharing = true, 587 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 588 }; 589 590 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 591 static CPUCacheInfo legacy_l1d_cache_amd = { 592 .type = DATA_CACHE, 593 .level = 1, 594 .size = 64 * KiB, 595 .self_init = 1, 596 .line_size = 64, 597 .associativity = 2, 598 .sets = 512, 599 .partitions = 1, 600 .lines_per_tag = 1, 601 .no_invd_sharing = true, 602 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 603 }; 604 605 /* L1 instruction cache: */ 606 static CPUCacheInfo legacy_l1i_cache = { 607 .type = INSTRUCTION_CACHE, 608 .level = 1, 609 .size = 32 * KiB, 610 .self_init = 1, 611 .line_size = 64, 612 .associativity = 8, 613 .sets = 64, 614 .partitions = 1, 615 .no_invd_sharing = true, 616 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 617 }; 618 619 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 620 static CPUCacheInfo legacy_l1i_cache_amd = { 621 .type = INSTRUCTION_CACHE, 622 .level = 1, 623 .size = 64 * KiB, 624 .self_init = 1, 625 .line_size = 64, 626 .associativity = 2, 627 .sets = 512, 628 .partitions = 1, 629 .lines_per_tag = 1, 630 .no_invd_sharing = true, 631 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 632 }; 633 634 /* Level 2 unified cache: */ 635 static CPUCacheInfo legacy_l2_cache = { 636 .type = UNIFIED_CACHE, 637 .level = 2, 638 .size = 4 * MiB, 639 .self_init = 1, 640 .line_size = 64, 641 .associativity = 16, 642 .sets = 4096, 643 .partitions = 1, 644 .no_invd_sharing = true, 645 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 646 }; 647 648 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 649 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 650 .type = UNIFIED_CACHE, 651 .level = 2, 652 .size = 2 * MiB, 653 .line_size = 64, 654 .associativity = 8, 655 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 656 }; 657 658 659 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 660 static CPUCacheInfo legacy_l2_cache_amd = { 661 .type = UNIFIED_CACHE, 662 .level = 2, 663 .size = 512 * KiB, 664 .line_size = 64, 665 .lines_per_tag = 1, 666 .associativity = 16, 667 .sets = 512, 668 .partitions = 1, 669 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 670 }; 671 672 /* Level 3 unified cache: */ 673 static CPUCacheInfo legacy_l3_cache = { 674 .type = UNIFIED_CACHE, 675 .level = 3, 676 .size = 16 * MiB, 677 .line_size = 64, 678 .associativity = 16, 679 .sets = 16384, 680 .partitions = 1, 681 .lines_per_tag = 1, 682 .self_init = true, 683 .inclusive = true, 684 .complex_indexing = true, 685 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 686 }; 687 688 /* TLB definitions: */ 689 690 #define L1_DTLB_2M_ASSOC 1 691 #define L1_DTLB_2M_ENTRIES 255 692 #define L1_DTLB_4K_ASSOC 1 693 #define L1_DTLB_4K_ENTRIES 255 694 695 #define L1_ITLB_2M_ASSOC 1 696 #define L1_ITLB_2M_ENTRIES 255 697 #define L1_ITLB_4K_ASSOC 1 698 #define L1_ITLB_4K_ENTRIES 255 699 700 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 701 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 702 #define L2_DTLB_4K_ASSOC 4 703 #define L2_DTLB_4K_ENTRIES 512 704 705 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 706 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 707 #define L2_ITLB_4K_ASSOC 4 708 #define L2_ITLB_4K_ENTRIES 512 709 710 /* CPUID Leaf 0x14 constants: */ 711 #define INTEL_PT_MAX_SUBLEAF 0x1 712 /* 713 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 714 * MSR can be accessed; 715 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 716 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 717 * of Intel PT MSRs across warm reset; 718 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 719 */ 720 #define INTEL_PT_MINIMAL_EBX 0xf 721 /* 722 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 723 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 724 * accessed; 725 * bit[01]: ToPA tables can hold any number of output entries, up to the 726 * maximum allowed by the MaskOrTableOffset field of 727 * IA32_RTIT_OUTPUT_MASK_PTRS; 728 * bit[02]: Support Single-Range Output scheme; 729 */ 730 #define INTEL_PT_MINIMAL_ECX 0x7 731 /* generated packets which contain IP payloads have LIP values */ 732 #define INTEL_PT_IP_LIP (1 << 31) 733 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 734 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 735 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 736 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 737 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 738 739 /* CPUID Leaf 0x1D constants: */ 740 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 741 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 742 #define INTEL_AMX_BYTES_PER_TILE 0x400 743 #define INTEL_AMX_BYTES_PER_ROW 0x40 744 #define INTEL_AMX_TILE_MAX_NAMES 0x8 745 #define INTEL_AMX_TILE_MAX_ROWS 0x10 746 747 /* CPUID Leaf 0x1E constants: */ 748 #define INTEL_AMX_TMUL_MAX_K 0x10 749 #define INTEL_AMX_TMUL_MAX_N 0x40 750 751 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 752 uint32_t vendor2, uint32_t vendor3) 753 { 754 int i; 755 for (i = 0; i < 4; i++) { 756 dst[i] = vendor1 >> (8 * i); 757 dst[i + 4] = vendor2 >> (8 * i); 758 dst[i + 8] = vendor3 >> (8 * i); 759 } 760 dst[CPUID_VENDOR_SZ] = '\0'; 761 } 762 763 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 764 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 765 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 766 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 767 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 768 CPUID_PSE36 | CPUID_FXSR) 769 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 770 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 771 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 772 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 773 CPUID_PAE | CPUID_SEP | CPUID_APIC) 774 775 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 776 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 777 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 778 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 779 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 780 /* partly implemented: 781 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 782 /* missing: 783 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 784 785 /* 786 * Kernel-only features that can be shown to usermode programs even if 787 * they aren't actually supported by TCG, because qemu-user only runs 788 * in CPL=3; remove them if they are ever implemented for system emulation. 789 */ 790 #if defined CONFIG_USER_ONLY 791 #define CPUID_EXT_KERNEL_FEATURES \ 792 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 793 #else 794 #define CPUID_EXT_KERNEL_FEATURES 0 795 #endif 796 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 797 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 798 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 799 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 800 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 801 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 802 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 803 /* missing: 804 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 805 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 806 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 807 CPUID_EXT_TSC_DEADLINE_TIMER 808 */ 809 810 #ifdef TARGET_X86_64 811 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 812 #else 813 #define TCG_EXT2_X86_64_FEATURES 0 814 #endif 815 816 /* 817 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 818 * in usermode or by 32-bit programs. Those are added to supported 819 * TCG features unconditionally in user-mode emulation mode. This may 820 * indeed seem strange or incorrect, but it works because code running 821 * under usermode emulation cannot access them. 822 * 823 * Even for long mode, qemu-i386 is not running "a userspace program on a 824 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 825 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 826 * but again the difference is only visible in kernel mode. 827 */ 828 #if defined CONFIG_LINUX_USER 829 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 830 #elif defined CONFIG_USER_ONLY 831 /* FIXME: Long mode not yet supported for i386 bsd-user */ 832 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 833 #else 834 #define CPUID_EXT2_KERNEL_FEATURES 0 835 #endif 836 837 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 838 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 839 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 840 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 841 CPUID_EXT2_KERNEL_FEATURES) 842 843 #if defined CONFIG_USER_ONLY 844 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 845 #else 846 #define CPUID_EXT3_KERNEL_FEATURES 0 847 #endif 848 849 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 850 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 851 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 852 853 #define TCG_EXT4_FEATURES 0 854 855 #if defined CONFIG_USER_ONLY 856 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 857 #else 858 #define CPUID_SVM_KERNEL_FEATURES 0 859 #endif 860 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 861 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 862 863 #define TCG_KVM_FEATURES 0 864 865 #if defined CONFIG_USER_ONLY 866 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 867 #else 868 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 869 #endif 870 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 871 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 872 CPUID_7_0_EBX_CLFLUSHOPT | \ 873 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 874 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 875 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 876 /* missing: 877 CPUID_7_0_EBX_HLE 878 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 879 880 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 881 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 882 #else 883 #define TCG_7_0_ECX_RDPID 0 884 #endif 885 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 886 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 887 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 888 TCG_7_0_ECX_RDPID) 889 890 #if defined CONFIG_USER_ONLY 891 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 892 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 893 #else 894 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 895 #endif 896 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 897 898 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 899 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 900 #define TCG_7_1_EDX_FEATURES 0 901 #define TCG_7_2_EDX_FEATURES 0 902 #define TCG_APM_FEATURES 0 903 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 904 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 905 /* missing: 906 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 907 #define TCG_14_0_ECX_FEATURES 0 908 #define TCG_SGX_12_0_EAX_FEATURES 0 909 #define TCG_SGX_12_0_EBX_FEATURES 0 910 #define TCG_SGX_12_1_EAX_FEATURES 0 911 #define TCG_24_0_EBX_FEATURES 0 912 913 #if defined CONFIG_USER_ONLY 914 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 915 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 916 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 917 CPUID_8000_0008_EBX_AMD_PSFD) 918 #else 919 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 920 #endif 921 922 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 923 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 924 925 #if defined CONFIG_USER_ONLY 926 #define CPUID_8000_0021_EAX_KERNEL_FEATURES CPUID_8000_0021_EAX_AUTO_IBRS 927 #else 928 #define CPUID_8000_0021_EAX_KERNEL_FEATURES 0 929 #endif 930 931 #define TCG_8000_0021_EAX_FEATURES ( \ 932 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | \ 933 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | \ 934 CPUID_8000_0021_EAX_KERNEL_FEATURES) 935 936 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 937 [FEAT_1_EDX] = { 938 .type = CPUID_FEATURE_WORD, 939 .feat_names = { 940 "fpu", "vme", "de", "pse", 941 "tsc", "msr", "pae", "mce", 942 "cx8", "apic", NULL, "sep", 943 "mtrr", "pge", "mca", "cmov", 944 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 945 NULL, "ds" /* Intel dts */, "acpi", "mmx", 946 "fxsr", "sse", "sse2", "ss", 947 "ht" /* Intel htt */, "tm", "ia64", "pbe", 948 }, 949 .cpuid = {.eax = 1, .reg = R_EDX, }, 950 .tcg_features = TCG_FEATURES, 951 .no_autoenable_flags = CPUID_HT, 952 }, 953 [FEAT_1_ECX] = { 954 .type = CPUID_FEATURE_WORD, 955 .feat_names = { 956 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 957 "ds-cpl", "vmx", "smx", "est", 958 "tm2", "ssse3", "cid", NULL, 959 "fma", "cx16", "xtpr", "pdcm", 960 NULL, "pcid", "dca", "sse4.1", 961 "sse4.2", "x2apic", "movbe", "popcnt", 962 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 963 "avx", "f16c", "rdrand", "hypervisor", 964 }, 965 .cpuid = { .eax = 1, .reg = R_ECX, }, 966 .tcg_features = TCG_EXT_FEATURES, 967 }, 968 /* Feature names that are already defined on feature_name[] but 969 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 970 * names on feat_names below. They are copied automatically 971 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 972 */ 973 [FEAT_8000_0001_EDX] = { 974 .type = CPUID_FEATURE_WORD, 975 .feat_names = { 976 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 977 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 978 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 979 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 980 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 981 "nx", NULL, "mmxext", NULL /* mmx */, 982 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 983 NULL, "lm", "3dnowext", "3dnow", 984 }, 985 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 986 .tcg_features = TCG_EXT2_FEATURES, 987 }, 988 [FEAT_8000_0001_ECX] = { 989 .type = CPUID_FEATURE_WORD, 990 .feat_names = { 991 "lahf-lm", "cmp-legacy", "svm", "extapic", 992 "cr8legacy", "abm", "sse4a", "misalignsse", 993 "3dnowprefetch", "osvw", "ibs", "xop", 994 "skinit", "wdt", NULL, "lwp", 995 "fma4", "tce", NULL, "nodeid-msr", 996 NULL, "tbm", "topoext", "perfctr-core", 997 "perfctr-nb", NULL, NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 }, 1000 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 1001 .tcg_features = TCG_EXT3_FEATURES, 1002 /* 1003 * TOPOEXT is always allowed but can't be enabled blindly by 1004 * "-cpu host", as it requires consistent cache topology info 1005 * to be provided so it doesn't confuse guests. 1006 */ 1007 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 1008 }, 1009 [FEAT_C000_0001_EDX] = { 1010 .type = CPUID_FEATURE_WORD, 1011 .feat_names = { 1012 NULL, NULL, "xstore", "xstore-en", 1013 NULL, NULL, "xcrypt", "xcrypt-en", 1014 "ace2", "ace2-en", "phe", "phe-en", 1015 "pmm", "pmm-en", NULL, NULL, 1016 NULL, NULL, NULL, NULL, 1017 NULL, NULL, NULL, NULL, 1018 NULL, NULL, NULL, NULL, 1019 NULL, NULL, NULL, NULL, 1020 }, 1021 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1022 .tcg_features = TCG_EXT4_FEATURES, 1023 }, 1024 [FEAT_KVM] = { 1025 .type = CPUID_FEATURE_WORD, 1026 .feat_names = { 1027 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1028 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1029 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1030 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1031 NULL, NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 "kvmclock-stable-bit", NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 }, 1036 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1037 .tcg_features = TCG_KVM_FEATURES, 1038 }, 1039 [FEAT_KVM_HINTS] = { 1040 .type = CPUID_FEATURE_WORD, 1041 .feat_names = { 1042 "kvm-hint-dedicated", NULL, NULL, NULL, 1043 NULL, NULL, NULL, NULL, 1044 NULL, NULL, NULL, NULL, 1045 NULL, NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 }, 1051 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1052 .tcg_features = TCG_KVM_FEATURES, 1053 /* 1054 * KVM hints aren't auto-enabled by -cpu host, they need to be 1055 * explicitly enabled in the command-line. 1056 */ 1057 .no_autoenable_flags = ~0U, 1058 }, 1059 [FEAT_SVM] = { 1060 .type = CPUID_FEATURE_WORD, 1061 .feat_names = { 1062 "npt", "lbrv", "svm-lock", "nrip-save", 1063 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1064 NULL, NULL, "pause-filter", NULL, 1065 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1066 "vgif", NULL, NULL, NULL, 1067 NULL, NULL, NULL, NULL, 1068 NULL, "vnmi", NULL, NULL, 1069 "svme-addr-chk", NULL, NULL, NULL, 1070 }, 1071 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1072 .tcg_features = TCG_SVM_FEATURES, 1073 }, 1074 [FEAT_7_0_EBX] = { 1075 .type = CPUID_FEATURE_WORD, 1076 .feat_names = { 1077 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1078 "hle", "avx2", "fdp-excptn-only", "smep", 1079 "bmi2", "erms", "invpcid", "rtm", 1080 NULL, "zero-fcs-fds", "mpx", NULL, 1081 "avx512f", "avx512dq", "rdseed", "adx", 1082 "smap", "avx512ifma", "pcommit", "clflushopt", 1083 "clwb", "intel-pt", "avx512pf", "avx512er", 1084 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1085 }, 1086 .cpuid = { 1087 .eax = 7, 1088 .needs_ecx = true, .ecx = 0, 1089 .reg = R_EBX, 1090 }, 1091 .tcg_features = TCG_7_0_EBX_FEATURES, 1092 }, 1093 [FEAT_7_0_ECX] = { 1094 .type = CPUID_FEATURE_WORD, 1095 .feat_names = { 1096 NULL, "avx512vbmi", "umip", "pku", 1097 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1098 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1099 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1100 "la57", NULL, NULL, NULL, 1101 NULL, NULL, "rdpid", NULL, 1102 "bus-lock-detect", "cldemote", NULL, "movdiri", 1103 "movdir64b", NULL, "sgxlc", "pks", 1104 }, 1105 .cpuid = { 1106 .eax = 7, 1107 .needs_ecx = true, .ecx = 0, 1108 .reg = R_ECX, 1109 }, 1110 .tcg_features = TCG_7_0_ECX_FEATURES, 1111 }, 1112 [FEAT_7_0_EDX] = { 1113 .type = CPUID_FEATURE_WORD, 1114 .feat_names = { 1115 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1116 "fsrm", NULL, NULL, NULL, 1117 "avx512-vp2intersect", NULL, "md-clear", NULL, 1118 NULL, NULL, "serialize", NULL, 1119 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1120 NULL, NULL, "amx-bf16", "avx512-fp16", 1121 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1122 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1123 }, 1124 .cpuid = { 1125 .eax = 7, 1126 .needs_ecx = true, .ecx = 0, 1127 .reg = R_EDX, 1128 }, 1129 .tcg_features = TCG_7_0_EDX_FEATURES, 1130 }, 1131 [FEAT_7_1_EAX] = { 1132 .type = CPUID_FEATURE_WORD, 1133 .feat_names = { 1134 "sha512", "sm3", "sm4", NULL, 1135 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1136 NULL, NULL, "fzrm", "fsrs", 1137 "fsrc", NULL, NULL, NULL, 1138 NULL, "fred", "lkgs", "wrmsrns", 1139 NULL, "amx-fp16", NULL, "avx-ifma", 1140 NULL, NULL, "lam", NULL, 1141 NULL, NULL, NULL, NULL, 1142 }, 1143 .cpuid = { 1144 .eax = 7, 1145 .needs_ecx = true, .ecx = 1, 1146 .reg = R_EAX, 1147 }, 1148 .tcg_features = TCG_7_1_EAX_FEATURES, 1149 }, 1150 [FEAT_7_1_EDX] = { 1151 .type = CPUID_FEATURE_WORD, 1152 .feat_names = { 1153 NULL, NULL, NULL, NULL, 1154 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1155 "amx-complex", NULL, "avx-vnni-int16", NULL, 1156 NULL, NULL, "prefetchiti", NULL, 1157 NULL, NULL, NULL, "avx10", 1158 NULL, NULL, NULL, NULL, 1159 NULL, NULL, NULL, NULL, 1160 NULL, NULL, NULL, NULL, 1161 }, 1162 .cpuid = { 1163 .eax = 7, 1164 .needs_ecx = true, .ecx = 1, 1165 .reg = R_EDX, 1166 }, 1167 .tcg_features = TCG_7_1_EDX_FEATURES, 1168 }, 1169 [FEAT_7_2_EDX] = { 1170 .type = CPUID_FEATURE_WORD, 1171 .feat_names = { 1172 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1173 "bhi-ctrl", "mcdt-no", NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 NULL, NULL, NULL, NULL, 1180 }, 1181 .cpuid = { 1182 .eax = 7, 1183 .needs_ecx = true, .ecx = 2, 1184 .reg = R_EDX, 1185 }, 1186 .tcg_features = TCG_7_2_EDX_FEATURES, 1187 }, 1188 [FEAT_24_0_EBX] = { 1189 .type = CPUID_FEATURE_WORD, 1190 .feat_names = { 1191 [16] = "avx10-128", 1192 [17] = "avx10-256", 1193 [18] = "avx10-512", 1194 }, 1195 .cpuid = { 1196 .eax = 0x24, 1197 .needs_ecx = true, .ecx = 0, 1198 .reg = R_EBX, 1199 }, 1200 .tcg_features = TCG_24_0_EBX_FEATURES, 1201 }, 1202 [FEAT_8000_0007_EDX] = { 1203 .type = CPUID_FEATURE_WORD, 1204 .feat_names = { 1205 NULL, NULL, NULL, NULL, 1206 NULL, NULL, NULL, NULL, 1207 "invtsc", NULL, NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 NULL, NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 }, 1214 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1215 .tcg_features = TCG_APM_FEATURES, 1216 .unmigratable_flags = CPUID_APM_INVTSC, 1217 }, 1218 [FEAT_8000_0007_EBX] = { 1219 .type = CPUID_FEATURE_WORD, 1220 .feat_names = { 1221 "overflow-recov", "succor", NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, NULL, NULL, NULL, 1224 NULL, NULL, NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 NULL, NULL, NULL, NULL, 1227 NULL, NULL, NULL, NULL, 1228 NULL, NULL, NULL, NULL, 1229 }, 1230 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1231 .tcg_features = 0, 1232 .unmigratable_flags = 0, 1233 }, 1234 [FEAT_8000_0008_EBX] = { 1235 .type = CPUID_FEATURE_WORD, 1236 .feat_names = { 1237 "clzero", NULL, "xsaveerptr", NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, "wbnoinvd", NULL, NULL, 1240 "ibpb", NULL, "ibrs", "amd-stibp", 1241 NULL, "stibp-always-on", NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1244 "amd-psfd", NULL, NULL, NULL, 1245 }, 1246 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1247 .tcg_features = TCG_8000_0008_EBX, 1248 .unmigratable_flags = 0, 1249 }, 1250 [FEAT_8000_0021_EAX] = { 1251 .type = CPUID_FEATURE_WORD, 1252 .feat_names = { 1253 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1254 NULL, NULL, "null-sel-clr-base", NULL, 1255 "auto-ibrs", NULL, NULL, NULL, 1256 NULL, NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 "eraps", NULL, NULL, "sbpb", 1260 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1261 }, 1262 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1263 .tcg_features = TCG_8000_0021_EAX_FEATURES, 1264 .unmigratable_flags = 0, 1265 }, 1266 [FEAT_8000_0021_EBX] = { 1267 .type = CPUID_FEATURE_WORD, 1268 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1269 .tcg_features = 0, 1270 .unmigratable_flags = 0, 1271 }, 1272 [FEAT_8000_0022_EAX] = { 1273 .type = CPUID_FEATURE_WORD, 1274 .feat_names = { 1275 "perfmon-v2", NULL, NULL, NULL, 1276 NULL, NULL, NULL, NULL, 1277 NULL, NULL, NULL, NULL, 1278 NULL, NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 }, 1284 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1285 .tcg_features = 0, 1286 .unmigratable_flags = 0, 1287 }, 1288 [FEAT_XSAVE] = { 1289 .type = CPUID_FEATURE_WORD, 1290 .feat_names = { 1291 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1292 "xfd", NULL, NULL, NULL, 1293 NULL, NULL, NULL, NULL, 1294 NULL, NULL, NULL, NULL, 1295 NULL, NULL, NULL, NULL, 1296 NULL, NULL, NULL, NULL, 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 }, 1300 .cpuid = { 1301 .eax = 0xd, 1302 .needs_ecx = true, .ecx = 1, 1303 .reg = R_EAX, 1304 }, 1305 .tcg_features = TCG_XSAVE_FEATURES, 1306 }, 1307 [FEAT_XSAVE_XSS_LO] = { 1308 .type = CPUID_FEATURE_WORD, 1309 .feat_names = { 1310 NULL, NULL, NULL, NULL, 1311 NULL, NULL, NULL, NULL, 1312 NULL, NULL, NULL, NULL, 1313 NULL, NULL, NULL, NULL, 1314 NULL, NULL, NULL, NULL, 1315 NULL, NULL, NULL, NULL, 1316 NULL, NULL, NULL, NULL, 1317 NULL, NULL, NULL, NULL, 1318 }, 1319 .cpuid = { 1320 .eax = 0xD, 1321 .needs_ecx = true, 1322 .ecx = 1, 1323 .reg = R_ECX, 1324 }, 1325 }, 1326 [FEAT_XSAVE_XSS_HI] = { 1327 .type = CPUID_FEATURE_WORD, 1328 .cpuid = { 1329 .eax = 0xD, 1330 .needs_ecx = true, 1331 .ecx = 1, 1332 .reg = R_EDX 1333 }, 1334 }, 1335 [FEAT_6_EAX] = { 1336 .type = CPUID_FEATURE_WORD, 1337 .feat_names = { 1338 NULL, NULL, "arat", NULL, 1339 NULL, NULL, NULL, NULL, 1340 NULL, NULL, NULL, NULL, 1341 NULL, NULL, NULL, NULL, 1342 NULL, NULL, NULL, NULL, 1343 NULL, NULL, NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 }, 1347 .cpuid = { .eax = 6, .reg = R_EAX, }, 1348 .tcg_features = TCG_6_EAX_FEATURES, 1349 }, 1350 [FEAT_XSAVE_XCR0_LO] = { 1351 .type = CPUID_FEATURE_WORD, 1352 .cpuid = { 1353 .eax = 0xD, 1354 .needs_ecx = true, .ecx = 0, 1355 .reg = R_EAX, 1356 }, 1357 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1358 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1359 XSTATE_PKRU_MASK, 1360 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1361 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1362 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1363 XSTATE_PKRU_MASK, 1364 }, 1365 [FEAT_XSAVE_XCR0_HI] = { 1366 .type = CPUID_FEATURE_WORD, 1367 .cpuid = { 1368 .eax = 0xD, 1369 .needs_ecx = true, .ecx = 0, 1370 .reg = R_EDX, 1371 }, 1372 .tcg_features = 0U, 1373 }, 1374 /*Below are MSR exposed features*/ 1375 [FEAT_ARCH_CAPABILITIES] = { 1376 .type = MSR_FEATURE_WORD, 1377 .feat_names = { 1378 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1379 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1380 "taa-no", NULL, NULL, NULL, 1381 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1382 NULL, "fb-clear", NULL, NULL, 1383 "bhi-no", NULL, NULL, NULL, 1384 "pbrsb-no", NULL, "gds-no", "rfds-no", 1385 "rfds-clear", NULL, NULL, NULL, 1386 NULL, NULL, NULL, NULL, 1387 NULL, NULL, NULL, NULL, 1388 NULL, NULL, NULL, NULL, 1389 NULL, NULL, NULL, NULL, 1390 NULL, NULL, NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, "its-no", NULL, 1394 }, 1395 .msr = { 1396 .index = MSR_IA32_ARCH_CAPABILITIES, 1397 }, 1398 /* 1399 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1400 * cannot be read from user mode. Therefore, it has no impact 1401 > on any user-mode operation, and warnings about unsupported 1402 * features do not matter. 1403 */ 1404 .tcg_features = ~0U, 1405 }, 1406 [FEAT_CORE_CAPABILITY] = { 1407 .type = MSR_FEATURE_WORD, 1408 .feat_names = { 1409 NULL, NULL, NULL, NULL, 1410 NULL, "split-lock-detect", NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 NULL, NULL, NULL, NULL, 1417 }, 1418 .msr = { 1419 .index = MSR_IA32_CORE_CAPABILITY, 1420 }, 1421 }, 1422 [FEAT_PERF_CAPABILITIES] = { 1423 .type = MSR_FEATURE_WORD, 1424 .feat_names = { 1425 NULL, NULL, NULL, NULL, 1426 NULL, NULL, NULL, NULL, 1427 NULL, NULL, NULL, NULL, 1428 NULL, "full-width-write", NULL, NULL, 1429 NULL, NULL, NULL, NULL, 1430 NULL, NULL, NULL, NULL, 1431 NULL, NULL, NULL, NULL, 1432 NULL, NULL, NULL, NULL, 1433 }, 1434 .msr = { 1435 .index = MSR_IA32_PERF_CAPABILITIES, 1436 }, 1437 }, 1438 1439 [FEAT_VMX_PROCBASED_CTLS] = { 1440 .type = MSR_FEATURE_WORD, 1441 .feat_names = { 1442 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1443 NULL, NULL, NULL, "vmx-hlt-exit", 1444 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1445 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1446 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1447 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1448 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1449 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1450 }, 1451 .msr = { 1452 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1453 } 1454 }, 1455 1456 [FEAT_VMX_SECONDARY_CTLS] = { 1457 .type = MSR_FEATURE_WORD, 1458 .feat_names = { 1459 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1460 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1461 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1462 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1463 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1464 "vmx-xsaves", NULL, NULL, NULL, 1465 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1466 NULL, NULL, NULL, NULL, 1467 }, 1468 .msr = { 1469 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1470 } 1471 }, 1472 1473 [FEAT_VMX_PINBASED_CTLS] = { 1474 .type = MSR_FEATURE_WORD, 1475 .feat_names = { 1476 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1477 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1478 NULL, NULL, NULL, NULL, 1479 NULL, NULL, NULL, NULL, 1480 NULL, NULL, NULL, NULL, 1481 NULL, NULL, NULL, NULL, 1482 NULL, NULL, NULL, NULL, 1483 NULL, NULL, NULL, NULL, 1484 }, 1485 .msr = { 1486 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1487 } 1488 }, 1489 1490 [FEAT_VMX_EXIT_CTLS] = { 1491 .type = MSR_FEATURE_WORD, 1492 /* 1493 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1494 * the LM CPUID bit. 1495 */ 1496 .feat_names = { 1497 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1498 NULL, NULL, NULL, NULL, 1499 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1500 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1501 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1502 "vmx-exit-save-efer", "vmx-exit-load-efer", 1503 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1504 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1505 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1506 }, 1507 .msr = { 1508 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1509 } 1510 }, 1511 1512 [FEAT_VMX_ENTRY_CTLS] = { 1513 .type = MSR_FEATURE_WORD, 1514 .feat_names = { 1515 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1516 NULL, NULL, NULL, NULL, 1517 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1518 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1519 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1520 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1521 NULL, NULL, NULL, NULL, 1522 NULL, NULL, NULL, NULL, 1523 }, 1524 .msr = { 1525 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1526 } 1527 }, 1528 1529 [FEAT_VMX_MISC] = { 1530 .type = MSR_FEATURE_WORD, 1531 .feat_names = { 1532 NULL, NULL, NULL, NULL, 1533 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1534 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1535 NULL, NULL, NULL, NULL, 1536 NULL, NULL, NULL, NULL, 1537 NULL, NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1540 }, 1541 .msr = { 1542 .index = MSR_IA32_VMX_MISC, 1543 } 1544 }, 1545 1546 [FEAT_VMX_EPT_VPID_CAPS] = { 1547 .type = MSR_FEATURE_WORD, 1548 .feat_names = { 1549 "vmx-ept-execonly", NULL, NULL, NULL, 1550 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1551 NULL, NULL, NULL, NULL, 1552 NULL, NULL, NULL, NULL, 1553 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1554 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1555 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1556 NULL, NULL, NULL, NULL, 1557 "vmx-invvpid", NULL, NULL, NULL, 1558 NULL, NULL, NULL, NULL, 1559 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1560 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1561 NULL, NULL, NULL, NULL, 1562 NULL, NULL, NULL, NULL, 1563 NULL, NULL, NULL, NULL, 1564 NULL, NULL, NULL, NULL, 1565 NULL, NULL, NULL, NULL, 1566 }, 1567 .msr = { 1568 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1569 } 1570 }, 1571 1572 [FEAT_VMX_BASIC] = { 1573 .type = MSR_FEATURE_WORD, 1574 .feat_names = { 1575 [54] = "vmx-ins-outs", 1576 [55] = "vmx-true-ctls", 1577 [56] = "vmx-any-errcode", 1578 [58] = "vmx-nested-exception", 1579 }, 1580 .msr = { 1581 .index = MSR_IA32_VMX_BASIC, 1582 }, 1583 /* Just to be safe - we don't support setting the MSEG version field. */ 1584 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1585 }, 1586 1587 [FEAT_VMX_VMFUNC] = { 1588 .type = MSR_FEATURE_WORD, 1589 .feat_names = { 1590 [0] = "vmx-eptp-switching", 1591 }, 1592 .msr = { 1593 .index = MSR_IA32_VMX_VMFUNC, 1594 } 1595 }, 1596 1597 [FEAT_14_0_ECX] = { 1598 .type = CPUID_FEATURE_WORD, 1599 .feat_names = { 1600 NULL, NULL, NULL, NULL, 1601 NULL, NULL, NULL, NULL, 1602 NULL, NULL, NULL, NULL, 1603 NULL, NULL, NULL, NULL, 1604 NULL, NULL, NULL, NULL, 1605 NULL, NULL, NULL, NULL, 1606 NULL, NULL, NULL, NULL, 1607 NULL, NULL, NULL, "intel-pt-lip", 1608 }, 1609 .cpuid = { 1610 .eax = 0x14, 1611 .needs_ecx = true, .ecx = 0, 1612 .reg = R_ECX, 1613 }, 1614 .tcg_features = TCG_14_0_ECX_FEATURES, 1615 }, 1616 1617 [FEAT_SGX_12_0_EAX] = { 1618 .type = CPUID_FEATURE_WORD, 1619 .feat_names = { 1620 "sgx1", "sgx2", NULL, NULL, 1621 NULL, NULL, NULL, NULL, 1622 NULL, NULL, NULL, "sgx-edeccssa", 1623 NULL, NULL, NULL, NULL, 1624 NULL, NULL, NULL, NULL, 1625 NULL, NULL, NULL, NULL, 1626 NULL, NULL, NULL, NULL, 1627 NULL, NULL, NULL, NULL, 1628 }, 1629 .cpuid = { 1630 .eax = 0x12, 1631 .needs_ecx = true, .ecx = 0, 1632 .reg = R_EAX, 1633 }, 1634 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1635 }, 1636 1637 [FEAT_SGX_12_0_EBX] = { 1638 .type = CPUID_FEATURE_WORD, 1639 .feat_names = { 1640 "sgx-exinfo" , NULL, NULL, NULL, 1641 NULL, NULL, NULL, NULL, 1642 NULL, NULL, NULL, NULL, 1643 NULL, NULL, NULL, NULL, 1644 NULL, NULL, NULL, NULL, 1645 NULL, NULL, NULL, NULL, 1646 NULL, NULL, NULL, NULL, 1647 NULL, NULL, NULL, NULL, 1648 }, 1649 .cpuid = { 1650 .eax = 0x12, 1651 .needs_ecx = true, .ecx = 0, 1652 .reg = R_EBX, 1653 }, 1654 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1655 }, 1656 1657 [FEAT_SGX_12_1_EAX] = { 1658 .type = CPUID_FEATURE_WORD, 1659 .feat_names = { 1660 NULL, "sgx-debug", "sgx-mode64", NULL, 1661 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1662 NULL, NULL, "sgx-aex-notify", NULL, 1663 NULL, NULL, NULL, NULL, 1664 NULL, NULL, NULL, NULL, 1665 NULL, NULL, NULL, NULL, 1666 NULL, NULL, NULL, NULL, 1667 NULL, NULL, NULL, NULL, 1668 }, 1669 .cpuid = { 1670 .eax = 0x12, 1671 .needs_ecx = true, .ecx = 1, 1672 .reg = R_EAX, 1673 }, 1674 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1675 }, 1676 }; 1677 1678 typedef struct FeatureMask { 1679 FeatureWord index; 1680 uint64_t mask; 1681 } FeatureMask; 1682 1683 typedef struct FeatureDep { 1684 FeatureMask from, to; 1685 } FeatureDep; 1686 1687 static FeatureDep feature_dependencies[] = { 1688 { 1689 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1690 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1691 }, 1692 { 1693 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1694 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1695 }, 1696 { 1697 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1698 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1699 }, 1700 { 1701 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1702 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1703 }, 1704 { 1705 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1706 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1707 }, 1708 { 1709 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1710 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1711 }, 1712 { 1713 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1714 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1715 }, 1716 { 1717 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1718 .to = { FEAT_VMX_MISC, ~0ull }, 1719 }, 1720 { 1721 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1722 .to = { FEAT_VMX_BASIC, ~0ull }, 1723 }, 1724 { 1725 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1726 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1727 }, 1728 { 1729 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1730 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1731 }, 1732 { 1733 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1734 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1735 }, 1736 { 1737 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1738 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1739 }, 1740 { 1741 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1742 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1743 }, 1744 { 1745 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1746 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1747 }, 1748 { 1749 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1750 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1751 }, 1752 { 1753 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1754 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1755 }, 1756 { 1757 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1758 .to = { FEAT_14_0_ECX, ~0ull }, 1759 }, 1760 { 1761 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1762 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1763 }, 1764 { 1765 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1766 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1767 }, 1768 { 1769 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1770 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1771 }, 1772 { 1773 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1774 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1775 }, 1776 { 1777 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1778 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1779 }, 1780 { 1781 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1782 .to = { FEAT_SVM, ~0ull }, 1783 }, 1784 { 1785 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1786 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1787 }, 1788 { 1789 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1790 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1791 }, 1792 { 1793 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1794 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1795 }, 1796 { 1797 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1798 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1799 }, 1800 { 1801 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1802 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1803 }, 1804 { 1805 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1806 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1807 }, 1808 { 1809 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1810 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1811 }, 1812 { 1813 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1814 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1815 }, 1816 { 1817 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1818 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1819 }, 1820 { 1821 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1822 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1823 }, 1824 { 1825 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1826 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1827 }, 1828 { 1829 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1830 .to = { FEAT_24_0_EBX, ~0ull }, 1831 }, 1832 }; 1833 1834 typedef struct X86RegisterInfo32 { 1835 /* Name of register */ 1836 const char *name; 1837 /* QAPI enum value register */ 1838 X86CPURegister32 qapi_enum; 1839 } X86RegisterInfo32; 1840 1841 #define REGISTER(reg) \ 1842 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1843 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1844 REGISTER(EAX), 1845 REGISTER(ECX), 1846 REGISTER(EDX), 1847 REGISTER(EBX), 1848 REGISTER(ESP), 1849 REGISTER(EBP), 1850 REGISTER(ESI), 1851 REGISTER(EDI), 1852 }; 1853 #undef REGISTER 1854 1855 /* CPUID feature bits available in XSS */ 1856 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1857 1858 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1859 [XSTATE_FP_BIT] = { 1860 /* x87 FP state component is always enabled if XSAVE is supported */ 1861 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1862 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1863 }, 1864 [XSTATE_SSE_BIT] = { 1865 /* SSE state component is always enabled if XSAVE is supported */ 1866 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1867 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1868 }, 1869 [XSTATE_YMM_BIT] = 1870 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1871 .size = sizeof(XSaveAVX) }, 1872 [XSTATE_BNDREGS_BIT] = 1873 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1874 .size = sizeof(XSaveBNDREG) }, 1875 [XSTATE_BNDCSR_BIT] = 1876 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1877 .size = sizeof(XSaveBNDCSR) }, 1878 [XSTATE_OPMASK_BIT] = 1879 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1880 .size = sizeof(XSaveOpmask) }, 1881 [XSTATE_ZMM_Hi256_BIT] = 1882 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1883 .size = sizeof(XSaveZMM_Hi256) }, 1884 [XSTATE_Hi16_ZMM_BIT] = 1885 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1886 .size = sizeof(XSaveHi16_ZMM) }, 1887 [XSTATE_PKRU_BIT] = 1888 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1889 .size = sizeof(XSavePKRU) }, 1890 [XSTATE_ARCH_LBR_BIT] = { 1891 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1892 .offset = 0 /*supervisor mode component, offset = 0 */, 1893 .size = sizeof(XSavesArchLBR) }, 1894 [XSTATE_XTILE_CFG_BIT] = { 1895 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1896 .size = sizeof(XSaveXTILECFG), 1897 }, 1898 [XSTATE_XTILE_DATA_BIT] = { 1899 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1900 .size = sizeof(XSaveXTILEDATA) 1901 }, 1902 }; 1903 1904 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1905 { 1906 uint64_t ret = x86_ext_save_areas[0].size; 1907 const ExtSaveArea *esa; 1908 uint32_t offset = 0; 1909 int i; 1910 1911 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1912 esa = &x86_ext_save_areas[i]; 1913 if ((mask >> i) & 1) { 1914 offset = compacted ? ret : esa->offset; 1915 ret = MAX(ret, offset + esa->size); 1916 } 1917 } 1918 return ret; 1919 } 1920 1921 static inline bool accel_uses_host_cpuid(void) 1922 { 1923 return kvm_enabled() || hvf_enabled(); 1924 } 1925 1926 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1927 { 1928 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1929 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1930 } 1931 1932 /* Return name of 32-bit register, from a R_* constant */ 1933 static const char *get_register_name_32(unsigned int reg) 1934 { 1935 if (reg >= CPU_NB_REGS32) { 1936 return NULL; 1937 } 1938 return x86_reg_info_32[reg].name; 1939 } 1940 1941 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1942 { 1943 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1944 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1945 } 1946 1947 /* 1948 * Returns the set of feature flags that are supported and migratable by 1949 * QEMU, for a given FeatureWord. 1950 */ 1951 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1952 { 1953 FeatureWordInfo *wi = &feature_word_info[w]; 1954 CPUX86State *env = &cpu->env; 1955 uint64_t r = 0; 1956 int i; 1957 1958 for (i = 0; i < 64; i++) { 1959 uint64_t f = 1ULL << i; 1960 1961 /* If the feature name is known, it is implicitly considered migratable, 1962 * unless it is explicitly set in unmigratable_flags */ 1963 if ((wi->migratable_flags & f) || 1964 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1965 r |= f; 1966 } 1967 } 1968 1969 /* when tsc-khz is set explicitly, invtsc is migratable */ 1970 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1971 r |= CPUID_APM_INVTSC; 1972 } 1973 1974 return r; 1975 } 1976 1977 void host_cpuid(uint32_t function, uint32_t count, 1978 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1979 { 1980 uint32_t vec[4]; 1981 1982 #ifdef __x86_64__ 1983 asm volatile("cpuid" 1984 : "=a"(vec[0]), "=b"(vec[1]), 1985 "=c"(vec[2]), "=d"(vec[3]) 1986 : "0"(function), "c"(count) : "cc"); 1987 #elif defined(__i386__) 1988 asm volatile("pusha \n\t" 1989 "cpuid \n\t" 1990 "mov %%eax, 0(%2) \n\t" 1991 "mov %%ebx, 4(%2) \n\t" 1992 "mov %%ecx, 8(%2) \n\t" 1993 "mov %%edx, 12(%2) \n\t" 1994 "popa" 1995 : : "a"(function), "c"(count), "S"(vec) 1996 : "memory", "cc"); 1997 #else 1998 abort(); 1999 #endif 2000 2001 if (eax) 2002 *eax = vec[0]; 2003 if (ebx) 2004 *ebx = vec[1]; 2005 if (ecx) 2006 *ecx = vec[2]; 2007 if (edx) 2008 *edx = vec[3]; 2009 } 2010 2011 /* CPU class name definitions: */ 2012 2013 /* Return type name for a given CPU model name 2014 * Caller is responsible for freeing the returned string. 2015 */ 2016 static char *x86_cpu_type_name(const char *model_name) 2017 { 2018 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 2019 } 2020 2021 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2022 { 2023 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2024 return object_class_by_name(typename); 2025 } 2026 2027 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2028 { 2029 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2030 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2031 return cpu_model_from_type(class_name); 2032 } 2033 2034 typedef struct X86CPUVersionDefinition { 2035 X86CPUVersion version; 2036 const char *alias; 2037 const char *note; 2038 PropValue *props; 2039 const CPUCaches *const cache_info; 2040 } X86CPUVersionDefinition; 2041 2042 /* Base definition for a CPU model */ 2043 typedef struct X86CPUDefinition { 2044 const char *name; 2045 uint32_t level; 2046 uint32_t xlevel; 2047 /* vendor is zero-terminated, 12 character ASCII string */ 2048 char vendor[CPUID_VENDOR_SZ + 1]; 2049 int family; 2050 int model; 2051 int stepping; 2052 uint8_t avx10_version; 2053 FeatureWordArray features; 2054 const char *model_id; 2055 const CPUCaches *const cache_info; 2056 /* 2057 * Definitions for alternative versions of CPU model. 2058 * List is terminated by item with version == 0. 2059 * If NULL, version 1 will be registered automatically. 2060 */ 2061 const X86CPUVersionDefinition *versions; 2062 const char *deprecation_note; 2063 } X86CPUDefinition; 2064 2065 /* Reference to a specific CPU model version */ 2066 struct X86CPUModel { 2067 /* Base CPU definition */ 2068 const X86CPUDefinition *cpudef; 2069 /* CPU model version */ 2070 X86CPUVersion version; 2071 const char *note; 2072 /* 2073 * If true, this is an alias CPU model. 2074 * This matters only for "-cpu help" and query-cpu-definitions 2075 */ 2076 bool is_alias; 2077 }; 2078 2079 /* Get full model name for CPU version */ 2080 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2081 X86CPUVersion version) 2082 { 2083 assert(version > 0); 2084 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2085 } 2086 2087 static const X86CPUVersionDefinition * 2088 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2089 { 2090 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2091 static const X86CPUVersionDefinition default_version_list[] = { 2092 { 1 }, 2093 { /* end of list */ } 2094 }; 2095 2096 return def->versions ?: default_version_list; 2097 } 2098 2099 static const CPUCaches epyc_cache_info = { 2100 .l1d_cache = &(CPUCacheInfo) { 2101 .type = DATA_CACHE, 2102 .level = 1, 2103 .size = 32 * KiB, 2104 .line_size = 64, 2105 .associativity = 8, 2106 .partitions = 1, 2107 .sets = 64, 2108 .lines_per_tag = 1, 2109 .self_init = 1, 2110 .no_invd_sharing = true, 2111 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2112 }, 2113 .l1i_cache = &(CPUCacheInfo) { 2114 .type = INSTRUCTION_CACHE, 2115 .level = 1, 2116 .size = 64 * KiB, 2117 .line_size = 64, 2118 .associativity = 4, 2119 .partitions = 1, 2120 .sets = 256, 2121 .lines_per_tag = 1, 2122 .self_init = 1, 2123 .no_invd_sharing = true, 2124 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2125 }, 2126 .l2_cache = &(CPUCacheInfo) { 2127 .type = UNIFIED_CACHE, 2128 .level = 2, 2129 .size = 512 * KiB, 2130 .line_size = 64, 2131 .associativity = 8, 2132 .partitions = 1, 2133 .sets = 1024, 2134 .lines_per_tag = 1, 2135 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2136 }, 2137 .l3_cache = &(CPUCacheInfo) { 2138 .type = UNIFIED_CACHE, 2139 .level = 3, 2140 .size = 8 * MiB, 2141 .line_size = 64, 2142 .associativity = 16, 2143 .partitions = 1, 2144 .sets = 8192, 2145 .lines_per_tag = 1, 2146 .self_init = true, 2147 .inclusive = true, 2148 .complex_indexing = true, 2149 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2150 }, 2151 }; 2152 2153 static CPUCaches epyc_v4_cache_info = { 2154 .l1d_cache = &(CPUCacheInfo) { 2155 .type = DATA_CACHE, 2156 .level = 1, 2157 .size = 32 * KiB, 2158 .line_size = 64, 2159 .associativity = 8, 2160 .partitions = 1, 2161 .sets = 64, 2162 .lines_per_tag = 1, 2163 .self_init = 1, 2164 .no_invd_sharing = true, 2165 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2166 }, 2167 .l1i_cache = &(CPUCacheInfo) { 2168 .type = INSTRUCTION_CACHE, 2169 .level = 1, 2170 .size = 64 * KiB, 2171 .line_size = 64, 2172 .associativity = 4, 2173 .partitions = 1, 2174 .sets = 256, 2175 .lines_per_tag = 1, 2176 .self_init = 1, 2177 .no_invd_sharing = true, 2178 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2179 }, 2180 .l2_cache = &(CPUCacheInfo) { 2181 .type = UNIFIED_CACHE, 2182 .level = 2, 2183 .size = 512 * KiB, 2184 .line_size = 64, 2185 .associativity = 8, 2186 .partitions = 1, 2187 .sets = 1024, 2188 .lines_per_tag = 1, 2189 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2190 }, 2191 .l3_cache = &(CPUCacheInfo) { 2192 .type = UNIFIED_CACHE, 2193 .level = 3, 2194 .size = 8 * MiB, 2195 .line_size = 64, 2196 .associativity = 16, 2197 .partitions = 1, 2198 .sets = 8192, 2199 .lines_per_tag = 1, 2200 .self_init = true, 2201 .inclusive = true, 2202 .complex_indexing = false, 2203 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2204 }, 2205 }; 2206 2207 static const CPUCaches epyc_rome_cache_info = { 2208 .l1d_cache = &(CPUCacheInfo) { 2209 .type = DATA_CACHE, 2210 .level = 1, 2211 .size = 32 * KiB, 2212 .line_size = 64, 2213 .associativity = 8, 2214 .partitions = 1, 2215 .sets = 64, 2216 .lines_per_tag = 1, 2217 .self_init = 1, 2218 .no_invd_sharing = true, 2219 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2220 }, 2221 .l1i_cache = &(CPUCacheInfo) { 2222 .type = INSTRUCTION_CACHE, 2223 .level = 1, 2224 .size = 32 * KiB, 2225 .line_size = 64, 2226 .associativity = 8, 2227 .partitions = 1, 2228 .sets = 64, 2229 .lines_per_tag = 1, 2230 .self_init = 1, 2231 .no_invd_sharing = true, 2232 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2233 }, 2234 .l2_cache = &(CPUCacheInfo) { 2235 .type = UNIFIED_CACHE, 2236 .level = 2, 2237 .size = 512 * KiB, 2238 .line_size = 64, 2239 .associativity = 8, 2240 .partitions = 1, 2241 .sets = 1024, 2242 .lines_per_tag = 1, 2243 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2244 }, 2245 .l3_cache = &(CPUCacheInfo) { 2246 .type = UNIFIED_CACHE, 2247 .level = 3, 2248 .size = 16 * MiB, 2249 .line_size = 64, 2250 .associativity = 16, 2251 .partitions = 1, 2252 .sets = 16384, 2253 .lines_per_tag = 1, 2254 .self_init = true, 2255 .inclusive = true, 2256 .complex_indexing = true, 2257 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2258 }, 2259 }; 2260 2261 static const CPUCaches epyc_rome_v3_cache_info = { 2262 .l1d_cache = &(CPUCacheInfo) { 2263 .type = DATA_CACHE, 2264 .level = 1, 2265 .size = 32 * KiB, 2266 .line_size = 64, 2267 .associativity = 8, 2268 .partitions = 1, 2269 .sets = 64, 2270 .lines_per_tag = 1, 2271 .self_init = 1, 2272 .no_invd_sharing = true, 2273 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2274 }, 2275 .l1i_cache = &(CPUCacheInfo) { 2276 .type = INSTRUCTION_CACHE, 2277 .level = 1, 2278 .size = 32 * KiB, 2279 .line_size = 64, 2280 .associativity = 8, 2281 .partitions = 1, 2282 .sets = 64, 2283 .lines_per_tag = 1, 2284 .self_init = 1, 2285 .no_invd_sharing = true, 2286 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2287 }, 2288 .l2_cache = &(CPUCacheInfo) { 2289 .type = UNIFIED_CACHE, 2290 .level = 2, 2291 .size = 512 * KiB, 2292 .line_size = 64, 2293 .associativity = 8, 2294 .partitions = 1, 2295 .sets = 1024, 2296 .lines_per_tag = 1, 2297 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2298 }, 2299 .l3_cache = &(CPUCacheInfo) { 2300 .type = UNIFIED_CACHE, 2301 .level = 3, 2302 .size = 16 * MiB, 2303 .line_size = 64, 2304 .associativity = 16, 2305 .partitions = 1, 2306 .sets = 16384, 2307 .lines_per_tag = 1, 2308 .self_init = true, 2309 .inclusive = true, 2310 .complex_indexing = false, 2311 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2312 }, 2313 }; 2314 2315 static const CPUCaches epyc_milan_cache_info = { 2316 .l1d_cache = &(CPUCacheInfo) { 2317 .type = DATA_CACHE, 2318 .level = 1, 2319 .size = 32 * KiB, 2320 .line_size = 64, 2321 .associativity = 8, 2322 .partitions = 1, 2323 .sets = 64, 2324 .lines_per_tag = 1, 2325 .self_init = 1, 2326 .no_invd_sharing = true, 2327 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2328 }, 2329 .l1i_cache = &(CPUCacheInfo) { 2330 .type = INSTRUCTION_CACHE, 2331 .level = 1, 2332 .size = 32 * KiB, 2333 .line_size = 64, 2334 .associativity = 8, 2335 .partitions = 1, 2336 .sets = 64, 2337 .lines_per_tag = 1, 2338 .self_init = 1, 2339 .no_invd_sharing = true, 2340 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2341 }, 2342 .l2_cache = &(CPUCacheInfo) { 2343 .type = UNIFIED_CACHE, 2344 .level = 2, 2345 .size = 512 * KiB, 2346 .line_size = 64, 2347 .associativity = 8, 2348 .partitions = 1, 2349 .sets = 1024, 2350 .lines_per_tag = 1, 2351 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2352 }, 2353 .l3_cache = &(CPUCacheInfo) { 2354 .type = UNIFIED_CACHE, 2355 .level = 3, 2356 .size = 32 * MiB, 2357 .line_size = 64, 2358 .associativity = 16, 2359 .partitions = 1, 2360 .sets = 32768, 2361 .lines_per_tag = 1, 2362 .self_init = true, 2363 .inclusive = true, 2364 .complex_indexing = true, 2365 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2366 }, 2367 }; 2368 2369 static const CPUCaches epyc_milan_v2_cache_info = { 2370 .l1d_cache = &(CPUCacheInfo) { 2371 .type = DATA_CACHE, 2372 .level = 1, 2373 .size = 32 * KiB, 2374 .line_size = 64, 2375 .associativity = 8, 2376 .partitions = 1, 2377 .sets = 64, 2378 .lines_per_tag = 1, 2379 .self_init = 1, 2380 .no_invd_sharing = true, 2381 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2382 }, 2383 .l1i_cache = &(CPUCacheInfo) { 2384 .type = INSTRUCTION_CACHE, 2385 .level = 1, 2386 .size = 32 * KiB, 2387 .line_size = 64, 2388 .associativity = 8, 2389 .partitions = 1, 2390 .sets = 64, 2391 .lines_per_tag = 1, 2392 .self_init = 1, 2393 .no_invd_sharing = true, 2394 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2395 }, 2396 .l2_cache = &(CPUCacheInfo) { 2397 .type = UNIFIED_CACHE, 2398 .level = 2, 2399 .size = 512 * KiB, 2400 .line_size = 64, 2401 .associativity = 8, 2402 .partitions = 1, 2403 .sets = 1024, 2404 .lines_per_tag = 1, 2405 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2406 }, 2407 .l3_cache = &(CPUCacheInfo) { 2408 .type = UNIFIED_CACHE, 2409 .level = 3, 2410 .size = 32 * MiB, 2411 .line_size = 64, 2412 .associativity = 16, 2413 .partitions = 1, 2414 .sets = 32768, 2415 .lines_per_tag = 1, 2416 .self_init = true, 2417 .inclusive = true, 2418 .complex_indexing = false, 2419 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2420 }, 2421 }; 2422 2423 static const CPUCaches epyc_genoa_cache_info = { 2424 .l1d_cache = &(CPUCacheInfo) { 2425 .type = DATA_CACHE, 2426 .level = 1, 2427 .size = 32 * KiB, 2428 .line_size = 64, 2429 .associativity = 8, 2430 .partitions = 1, 2431 .sets = 64, 2432 .lines_per_tag = 1, 2433 .self_init = 1, 2434 .no_invd_sharing = true, 2435 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2436 }, 2437 .l1i_cache = &(CPUCacheInfo) { 2438 .type = INSTRUCTION_CACHE, 2439 .level = 1, 2440 .size = 32 * KiB, 2441 .line_size = 64, 2442 .associativity = 8, 2443 .partitions = 1, 2444 .sets = 64, 2445 .lines_per_tag = 1, 2446 .self_init = 1, 2447 .no_invd_sharing = true, 2448 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2449 }, 2450 .l2_cache = &(CPUCacheInfo) { 2451 .type = UNIFIED_CACHE, 2452 .level = 2, 2453 .size = 1 * MiB, 2454 .line_size = 64, 2455 .associativity = 8, 2456 .partitions = 1, 2457 .sets = 2048, 2458 .lines_per_tag = 1, 2459 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2460 }, 2461 .l3_cache = &(CPUCacheInfo) { 2462 .type = UNIFIED_CACHE, 2463 .level = 3, 2464 .size = 32 * MiB, 2465 .line_size = 64, 2466 .associativity = 16, 2467 .partitions = 1, 2468 .sets = 32768, 2469 .lines_per_tag = 1, 2470 .self_init = true, 2471 .inclusive = true, 2472 .complex_indexing = false, 2473 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2474 }, 2475 }; 2476 2477 /* The following VMX features are not supported by KVM and are left out in the 2478 * CPU definitions: 2479 * 2480 * Dual-monitor support (all processors) 2481 * Entry to SMM 2482 * Deactivate dual-monitor treatment 2483 * Number of CR3-target values 2484 * Shutdown activity state 2485 * Wait-for-SIPI activity state 2486 * PAUSE-loop exiting (Westmere and newer) 2487 * EPT-violation #VE (Broadwell and newer) 2488 * Inject event with insn length=0 (Skylake and newer) 2489 * Conceal non-root operation from PT 2490 * Conceal VM exits from PT 2491 * Conceal VM entries from PT 2492 * Enable ENCLS exiting 2493 * Mode-based execute control (XS/XU) 2494 * TSC scaling (Skylake Server and newer) 2495 * GPA translation for PT (IceLake and newer) 2496 * User wait and pause 2497 * ENCLV exiting 2498 * Load IA32_RTIT_CTL 2499 * Clear IA32_RTIT_CTL 2500 * Advanced VM-exit information for EPT violations 2501 * Sub-page write permissions 2502 * PT in VMX operation 2503 */ 2504 2505 static const X86CPUDefinition builtin_x86_defs[] = { 2506 { 2507 .name = "qemu64", 2508 .level = 0xd, 2509 .vendor = CPUID_VENDOR_AMD, 2510 .family = 15, 2511 .model = 107, 2512 .stepping = 1, 2513 .features[FEAT_1_EDX] = 2514 PPRO_FEATURES | 2515 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2516 CPUID_PSE36, 2517 .features[FEAT_1_ECX] = 2518 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2519 .features[FEAT_8000_0001_EDX] = 2520 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2521 .features[FEAT_8000_0001_ECX] = 2522 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2523 .xlevel = 0x8000000A, 2524 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2525 }, 2526 { 2527 .name = "phenom", 2528 .level = 5, 2529 .vendor = CPUID_VENDOR_AMD, 2530 .family = 16, 2531 .model = 2, 2532 .stepping = 3, 2533 /* Missing: CPUID_HT */ 2534 .features[FEAT_1_EDX] = 2535 PPRO_FEATURES | 2536 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2537 CPUID_PSE36 | CPUID_VME, 2538 .features[FEAT_1_ECX] = 2539 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2540 CPUID_EXT_POPCNT, 2541 .features[FEAT_8000_0001_EDX] = 2542 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2543 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2544 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2545 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2546 CPUID_EXT3_CR8LEG, 2547 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2548 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2549 .features[FEAT_8000_0001_ECX] = 2550 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2551 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2552 /* Missing: CPUID_SVM_LBRV */ 2553 .features[FEAT_SVM] = 2554 CPUID_SVM_NPT, 2555 .xlevel = 0x8000001A, 2556 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2557 }, 2558 { 2559 .name = "core2duo", 2560 .level = 10, 2561 .vendor = CPUID_VENDOR_INTEL, 2562 .family = 6, 2563 .model = 15, 2564 .stepping = 11, 2565 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2566 .features[FEAT_1_EDX] = 2567 PPRO_FEATURES | 2568 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2569 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2570 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2571 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2572 .features[FEAT_1_ECX] = 2573 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2574 CPUID_EXT_CX16, 2575 .features[FEAT_8000_0001_EDX] = 2576 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2577 .features[FEAT_8000_0001_ECX] = 2578 CPUID_EXT3_LAHF_LM, 2579 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2580 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2581 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2582 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2583 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2584 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2585 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2586 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2587 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2588 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2589 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2590 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2591 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2592 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2593 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2594 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2595 .features[FEAT_VMX_SECONDARY_CTLS] = 2596 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2597 .xlevel = 0x80000008, 2598 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2599 }, 2600 { 2601 .name = "kvm64", 2602 .level = 0xd, 2603 .vendor = CPUID_VENDOR_INTEL, 2604 .family = 15, 2605 .model = 6, 2606 .stepping = 1, 2607 /* Missing: CPUID_HT */ 2608 .features[FEAT_1_EDX] = 2609 PPRO_FEATURES | CPUID_VME | 2610 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2611 CPUID_PSE36, 2612 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2613 .features[FEAT_1_ECX] = 2614 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2615 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2616 .features[FEAT_8000_0001_EDX] = 2617 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2618 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2619 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2620 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2621 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2622 .features[FEAT_8000_0001_ECX] = 2623 0, 2624 /* VMX features from Cedar Mill/Prescott */ 2625 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2626 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2627 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2628 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2629 VMX_PIN_BASED_NMI_EXITING, 2630 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2631 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2632 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2633 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2634 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2635 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2636 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2637 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2638 .xlevel = 0x80000008, 2639 .model_id = "Common KVM processor" 2640 }, 2641 { 2642 .name = "qemu32", 2643 .level = 4, 2644 .vendor = CPUID_VENDOR_INTEL, 2645 .family = 6, 2646 .model = 6, 2647 .stepping = 3, 2648 .features[FEAT_1_EDX] = 2649 PPRO_FEATURES, 2650 .features[FEAT_1_ECX] = 2651 CPUID_EXT_SSE3, 2652 .xlevel = 0x80000004, 2653 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2654 }, 2655 { 2656 .name = "kvm32", 2657 .level = 5, 2658 .vendor = CPUID_VENDOR_INTEL, 2659 .family = 15, 2660 .model = 6, 2661 .stepping = 1, 2662 .features[FEAT_1_EDX] = 2663 PPRO_FEATURES | CPUID_VME | 2664 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2665 .features[FEAT_1_ECX] = 2666 CPUID_EXT_SSE3, 2667 .features[FEAT_8000_0001_ECX] = 2668 0, 2669 /* VMX features from Yonah */ 2670 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2671 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2672 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2673 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2674 VMX_PIN_BASED_NMI_EXITING, 2675 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2676 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2677 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2678 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2679 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2680 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2681 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2682 .xlevel = 0x80000008, 2683 .model_id = "Common 32-bit KVM processor" 2684 }, 2685 { 2686 .name = "coreduo", 2687 .level = 10, 2688 .vendor = CPUID_VENDOR_INTEL, 2689 .family = 6, 2690 .model = 14, 2691 .stepping = 8, 2692 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2693 .features[FEAT_1_EDX] = 2694 PPRO_FEATURES | CPUID_VME | 2695 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2696 CPUID_SS, 2697 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2698 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2699 .features[FEAT_1_ECX] = 2700 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2701 .features[FEAT_8000_0001_EDX] = 2702 CPUID_EXT2_NX, 2703 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2704 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2705 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2706 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2707 VMX_PIN_BASED_NMI_EXITING, 2708 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2709 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2710 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2711 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2712 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2713 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2714 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2715 .xlevel = 0x80000008, 2716 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2717 }, 2718 { 2719 .name = "486", 2720 .level = 1, 2721 .vendor = CPUID_VENDOR_INTEL, 2722 .family = 4, 2723 .model = 8, 2724 .stepping = 0, 2725 .features[FEAT_1_EDX] = 2726 I486_FEATURES, 2727 .xlevel = 0, 2728 .model_id = "", 2729 }, 2730 { 2731 .name = "pentium", 2732 .level = 1, 2733 .vendor = CPUID_VENDOR_INTEL, 2734 .family = 5, 2735 .model = 4, 2736 .stepping = 3, 2737 .features[FEAT_1_EDX] = 2738 PENTIUM_FEATURES, 2739 .xlevel = 0, 2740 .model_id = "", 2741 }, 2742 { 2743 .name = "pentium2", 2744 .level = 2, 2745 .vendor = CPUID_VENDOR_INTEL, 2746 .family = 6, 2747 .model = 5, 2748 .stepping = 2, 2749 .features[FEAT_1_EDX] = 2750 PENTIUM2_FEATURES, 2751 .xlevel = 0, 2752 .model_id = "", 2753 }, 2754 { 2755 .name = "pentium3", 2756 .level = 3, 2757 .vendor = CPUID_VENDOR_INTEL, 2758 .family = 6, 2759 .model = 7, 2760 .stepping = 3, 2761 .features[FEAT_1_EDX] = 2762 PENTIUM3_FEATURES, 2763 .xlevel = 0, 2764 .model_id = "", 2765 }, 2766 { 2767 .name = "athlon", 2768 .level = 2, 2769 .vendor = CPUID_VENDOR_AMD, 2770 .family = 6, 2771 .model = 2, 2772 .stepping = 3, 2773 .features[FEAT_1_EDX] = 2774 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2775 CPUID_MCA, 2776 .features[FEAT_8000_0001_EDX] = 2777 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2778 .xlevel = 0x80000008, 2779 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2780 }, 2781 { 2782 .name = "n270", 2783 .level = 10, 2784 .vendor = CPUID_VENDOR_INTEL, 2785 .family = 6, 2786 .model = 28, 2787 .stepping = 2, 2788 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2789 .features[FEAT_1_EDX] = 2790 PPRO_FEATURES | 2791 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2792 CPUID_ACPI | CPUID_SS, 2793 /* Some CPUs got no CPUID_SEP */ 2794 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2795 * CPUID_EXT_XTPR */ 2796 .features[FEAT_1_ECX] = 2797 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2798 CPUID_EXT_MOVBE, 2799 .features[FEAT_8000_0001_EDX] = 2800 CPUID_EXT2_NX, 2801 .features[FEAT_8000_0001_ECX] = 2802 CPUID_EXT3_LAHF_LM, 2803 .xlevel = 0x80000008, 2804 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2805 }, 2806 { 2807 .name = "Conroe", 2808 .level = 10, 2809 .vendor = CPUID_VENDOR_INTEL, 2810 .family = 6, 2811 .model = 15, 2812 .stepping = 3, 2813 .features[FEAT_1_EDX] = 2814 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2815 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2816 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2817 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2818 CPUID_DE | CPUID_FP87, 2819 .features[FEAT_1_ECX] = 2820 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2821 .features[FEAT_8000_0001_EDX] = 2822 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2823 .features[FEAT_8000_0001_ECX] = 2824 CPUID_EXT3_LAHF_LM, 2825 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2826 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2827 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2828 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2829 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2830 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2831 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2832 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2833 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2834 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2835 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2836 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2837 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2838 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2839 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2840 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2841 .features[FEAT_VMX_SECONDARY_CTLS] = 2842 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2843 .xlevel = 0x80000008, 2844 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2845 }, 2846 { 2847 .name = "Penryn", 2848 .level = 10, 2849 .vendor = CPUID_VENDOR_INTEL, 2850 .family = 6, 2851 .model = 23, 2852 .stepping = 3, 2853 .features[FEAT_1_EDX] = 2854 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2855 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2856 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2857 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2858 CPUID_DE | CPUID_FP87, 2859 .features[FEAT_1_ECX] = 2860 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2861 CPUID_EXT_SSE3, 2862 .features[FEAT_8000_0001_EDX] = 2863 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2864 .features[FEAT_8000_0001_ECX] = 2865 CPUID_EXT3_LAHF_LM, 2866 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2867 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2868 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2869 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2870 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2871 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2872 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2873 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2874 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2875 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2876 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2877 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2878 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2879 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2880 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2881 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2882 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2883 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2884 .features[FEAT_VMX_SECONDARY_CTLS] = 2885 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2886 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2887 .xlevel = 0x80000008, 2888 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2889 }, 2890 { 2891 .name = "Nehalem", 2892 .level = 11, 2893 .vendor = CPUID_VENDOR_INTEL, 2894 .family = 6, 2895 .model = 26, 2896 .stepping = 3, 2897 .features[FEAT_1_EDX] = 2898 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2899 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2900 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2901 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2902 CPUID_DE | CPUID_FP87, 2903 .features[FEAT_1_ECX] = 2904 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2905 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2906 .features[FEAT_8000_0001_EDX] = 2907 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2908 .features[FEAT_8000_0001_ECX] = 2909 CPUID_EXT3_LAHF_LM, 2910 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2911 MSR_VMX_BASIC_TRUE_CTLS, 2912 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2913 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2914 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2915 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2916 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2917 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2918 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2919 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2920 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2921 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2922 .features[FEAT_VMX_EXIT_CTLS] = 2923 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2924 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2925 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2926 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2927 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2928 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2929 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2930 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2931 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2932 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2933 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2934 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2935 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2936 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2937 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2938 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2939 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2940 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2941 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2942 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2943 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2944 .features[FEAT_VMX_SECONDARY_CTLS] = 2945 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2946 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2947 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2948 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2949 VMX_SECONDARY_EXEC_ENABLE_VPID, 2950 .xlevel = 0x80000008, 2951 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2952 .versions = (X86CPUVersionDefinition[]) { 2953 { .version = 1 }, 2954 { 2955 .version = 2, 2956 .alias = "Nehalem-IBRS", 2957 .props = (PropValue[]) { 2958 { "spec-ctrl", "on" }, 2959 { "model-id", 2960 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2961 { /* end of list */ } 2962 } 2963 }, 2964 { /* end of list */ } 2965 } 2966 }, 2967 { 2968 .name = "Westmere", 2969 .level = 11, 2970 .vendor = CPUID_VENDOR_INTEL, 2971 .family = 6, 2972 .model = 44, 2973 .stepping = 1, 2974 .features[FEAT_1_EDX] = 2975 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2976 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2977 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2978 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2979 CPUID_DE | CPUID_FP87, 2980 .features[FEAT_1_ECX] = 2981 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2982 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2983 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2984 .features[FEAT_8000_0001_EDX] = 2985 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2986 .features[FEAT_8000_0001_ECX] = 2987 CPUID_EXT3_LAHF_LM, 2988 .features[FEAT_6_EAX] = 2989 CPUID_6_EAX_ARAT, 2990 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2991 MSR_VMX_BASIC_TRUE_CTLS, 2992 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2993 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2994 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2995 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2996 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2997 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2998 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2999 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3000 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3001 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3002 .features[FEAT_VMX_EXIT_CTLS] = 3003 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3004 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3005 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3006 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3007 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3008 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3009 MSR_VMX_MISC_STORE_LMA, 3010 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3011 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3012 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3013 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3014 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3015 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3016 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3017 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3018 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3019 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3020 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3021 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3022 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3023 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3024 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3025 .features[FEAT_VMX_SECONDARY_CTLS] = 3026 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3027 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3028 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3029 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3030 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3031 .xlevel = 0x80000008, 3032 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3033 .versions = (X86CPUVersionDefinition[]) { 3034 { .version = 1 }, 3035 { 3036 .version = 2, 3037 .alias = "Westmere-IBRS", 3038 .props = (PropValue[]) { 3039 { "spec-ctrl", "on" }, 3040 { "model-id", 3041 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3042 { /* end of list */ } 3043 } 3044 }, 3045 { /* end of list */ } 3046 } 3047 }, 3048 { 3049 .name = "SandyBridge", 3050 .level = 0xd, 3051 .vendor = CPUID_VENDOR_INTEL, 3052 .family = 6, 3053 .model = 42, 3054 .stepping = 1, 3055 .features[FEAT_1_EDX] = 3056 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3057 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3058 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3059 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3060 CPUID_DE | CPUID_FP87, 3061 .features[FEAT_1_ECX] = 3062 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3063 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3064 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3065 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3066 CPUID_EXT_SSE3, 3067 .features[FEAT_8000_0001_EDX] = 3068 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3069 CPUID_EXT2_SYSCALL, 3070 .features[FEAT_8000_0001_ECX] = 3071 CPUID_EXT3_LAHF_LM, 3072 .features[FEAT_XSAVE] = 3073 CPUID_XSAVE_XSAVEOPT, 3074 .features[FEAT_6_EAX] = 3075 CPUID_6_EAX_ARAT, 3076 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3077 MSR_VMX_BASIC_TRUE_CTLS, 3078 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3079 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3080 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3081 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3082 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3083 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3084 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3085 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3086 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3087 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3088 .features[FEAT_VMX_EXIT_CTLS] = 3089 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3090 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3091 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3092 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3093 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3094 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3095 MSR_VMX_MISC_STORE_LMA, 3096 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3097 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3098 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3099 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3100 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3101 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3102 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3103 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3104 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3105 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3106 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3107 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3108 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3109 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3110 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3111 .features[FEAT_VMX_SECONDARY_CTLS] = 3112 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3113 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3114 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3115 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3116 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3117 .xlevel = 0x80000008, 3118 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3119 .versions = (X86CPUVersionDefinition[]) { 3120 { .version = 1 }, 3121 { 3122 .version = 2, 3123 .alias = "SandyBridge-IBRS", 3124 .props = (PropValue[]) { 3125 { "spec-ctrl", "on" }, 3126 { "model-id", 3127 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3128 { /* end of list */ } 3129 } 3130 }, 3131 { /* end of list */ } 3132 } 3133 }, 3134 { 3135 .name = "IvyBridge", 3136 .level = 0xd, 3137 .vendor = CPUID_VENDOR_INTEL, 3138 .family = 6, 3139 .model = 58, 3140 .stepping = 9, 3141 .features[FEAT_1_EDX] = 3142 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3143 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3144 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3145 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3146 CPUID_DE | CPUID_FP87, 3147 .features[FEAT_1_ECX] = 3148 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3149 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3150 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3151 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3152 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3153 .features[FEAT_7_0_EBX] = 3154 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3155 CPUID_7_0_EBX_ERMS, 3156 .features[FEAT_8000_0001_EDX] = 3157 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3158 CPUID_EXT2_SYSCALL, 3159 .features[FEAT_8000_0001_ECX] = 3160 CPUID_EXT3_LAHF_LM, 3161 .features[FEAT_XSAVE] = 3162 CPUID_XSAVE_XSAVEOPT, 3163 .features[FEAT_6_EAX] = 3164 CPUID_6_EAX_ARAT, 3165 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3166 MSR_VMX_BASIC_TRUE_CTLS, 3167 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3168 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3169 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3170 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3171 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3172 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3173 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3174 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3175 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3176 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3177 .features[FEAT_VMX_EXIT_CTLS] = 3178 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3179 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3180 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3181 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3182 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3183 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3184 MSR_VMX_MISC_STORE_LMA, 3185 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3186 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3187 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3188 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3189 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3190 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3191 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3192 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3193 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3194 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3195 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3196 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3197 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3198 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3199 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3200 .features[FEAT_VMX_SECONDARY_CTLS] = 3201 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3202 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3203 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3204 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3205 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3206 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3207 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3208 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3209 .xlevel = 0x80000008, 3210 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3211 .versions = (X86CPUVersionDefinition[]) { 3212 { .version = 1 }, 3213 { 3214 .version = 2, 3215 .alias = "IvyBridge-IBRS", 3216 .props = (PropValue[]) { 3217 { "spec-ctrl", "on" }, 3218 { "model-id", 3219 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3220 { /* end of list */ } 3221 } 3222 }, 3223 { /* end of list */ } 3224 } 3225 }, 3226 { 3227 .name = "Haswell", 3228 .level = 0xd, 3229 .vendor = CPUID_VENDOR_INTEL, 3230 .family = 6, 3231 .model = 60, 3232 .stepping = 4, 3233 .features[FEAT_1_EDX] = 3234 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3235 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3236 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3237 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3238 CPUID_DE | CPUID_FP87, 3239 .features[FEAT_1_ECX] = 3240 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3241 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3242 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3243 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3244 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3245 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3246 .features[FEAT_8000_0001_EDX] = 3247 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3248 CPUID_EXT2_SYSCALL, 3249 .features[FEAT_8000_0001_ECX] = 3250 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3251 .features[FEAT_7_0_EBX] = 3252 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3253 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3254 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3255 CPUID_7_0_EBX_RTM, 3256 .features[FEAT_XSAVE] = 3257 CPUID_XSAVE_XSAVEOPT, 3258 .features[FEAT_6_EAX] = 3259 CPUID_6_EAX_ARAT, 3260 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3261 MSR_VMX_BASIC_TRUE_CTLS, 3262 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3263 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3264 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3265 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3266 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3267 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3268 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3269 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3270 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3271 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3272 .features[FEAT_VMX_EXIT_CTLS] = 3273 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3274 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3275 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3276 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3277 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3278 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3279 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3280 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3281 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3282 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3283 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3284 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3285 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3286 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3287 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3288 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3289 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3290 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3291 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3292 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3293 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3294 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3295 .features[FEAT_VMX_SECONDARY_CTLS] = 3296 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3297 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3298 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3299 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3300 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3301 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3302 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3303 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3304 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3305 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3306 .xlevel = 0x80000008, 3307 .model_id = "Intel Core Processor (Haswell)", 3308 .versions = (X86CPUVersionDefinition[]) { 3309 { .version = 1 }, 3310 { 3311 .version = 2, 3312 .alias = "Haswell-noTSX", 3313 .props = (PropValue[]) { 3314 { "hle", "off" }, 3315 { "rtm", "off" }, 3316 { "stepping", "1" }, 3317 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3318 { /* end of list */ } 3319 }, 3320 }, 3321 { 3322 .version = 3, 3323 .alias = "Haswell-IBRS", 3324 .props = (PropValue[]) { 3325 /* Restore TSX features removed by -v2 above */ 3326 { "hle", "on" }, 3327 { "rtm", "on" }, 3328 /* 3329 * Haswell and Haswell-IBRS had stepping=4 in 3330 * QEMU 4.0 and older 3331 */ 3332 { "stepping", "4" }, 3333 { "spec-ctrl", "on" }, 3334 { "model-id", 3335 "Intel Core Processor (Haswell, IBRS)" }, 3336 { /* end of list */ } 3337 } 3338 }, 3339 { 3340 .version = 4, 3341 .alias = "Haswell-noTSX-IBRS", 3342 .props = (PropValue[]) { 3343 { "hle", "off" }, 3344 { "rtm", "off" }, 3345 /* spec-ctrl was already enabled by -v3 above */ 3346 { "stepping", "1" }, 3347 { "model-id", 3348 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3349 { /* end of list */ } 3350 } 3351 }, 3352 { /* end of list */ } 3353 } 3354 }, 3355 { 3356 .name = "Broadwell", 3357 .level = 0xd, 3358 .vendor = CPUID_VENDOR_INTEL, 3359 .family = 6, 3360 .model = 61, 3361 .stepping = 2, 3362 .features[FEAT_1_EDX] = 3363 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3364 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3365 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3366 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3367 CPUID_DE | CPUID_FP87, 3368 .features[FEAT_1_ECX] = 3369 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3370 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3371 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3372 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3373 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3374 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3375 .features[FEAT_8000_0001_EDX] = 3376 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3377 CPUID_EXT2_SYSCALL, 3378 .features[FEAT_8000_0001_ECX] = 3379 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3380 .features[FEAT_7_0_EBX] = 3381 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3382 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3383 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3384 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3385 CPUID_7_0_EBX_SMAP, 3386 .features[FEAT_XSAVE] = 3387 CPUID_XSAVE_XSAVEOPT, 3388 .features[FEAT_6_EAX] = 3389 CPUID_6_EAX_ARAT, 3390 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3391 MSR_VMX_BASIC_TRUE_CTLS, 3392 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3393 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3394 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3395 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3396 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3397 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3398 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3399 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3400 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3401 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3402 .features[FEAT_VMX_EXIT_CTLS] = 3403 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3404 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3405 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3406 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3407 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3408 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3409 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3410 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3411 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3412 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3413 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3414 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3415 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3416 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3417 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3418 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3419 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3420 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3421 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3422 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3423 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3424 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3425 .features[FEAT_VMX_SECONDARY_CTLS] = 3426 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3427 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3428 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3429 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3430 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3431 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3432 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3433 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3434 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3435 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3436 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3437 .xlevel = 0x80000008, 3438 .model_id = "Intel Core Processor (Broadwell)", 3439 .versions = (X86CPUVersionDefinition[]) { 3440 { .version = 1 }, 3441 { 3442 .version = 2, 3443 .alias = "Broadwell-noTSX", 3444 .props = (PropValue[]) { 3445 { "hle", "off" }, 3446 { "rtm", "off" }, 3447 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3448 { /* end of list */ } 3449 }, 3450 }, 3451 { 3452 .version = 3, 3453 .alias = "Broadwell-IBRS", 3454 .props = (PropValue[]) { 3455 /* Restore TSX features removed by -v2 above */ 3456 { "hle", "on" }, 3457 { "rtm", "on" }, 3458 { "spec-ctrl", "on" }, 3459 { "model-id", 3460 "Intel Core Processor (Broadwell, IBRS)" }, 3461 { /* end of list */ } 3462 } 3463 }, 3464 { 3465 .version = 4, 3466 .alias = "Broadwell-noTSX-IBRS", 3467 .props = (PropValue[]) { 3468 { "hle", "off" }, 3469 { "rtm", "off" }, 3470 /* spec-ctrl was already enabled by -v3 above */ 3471 { "model-id", 3472 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3473 { /* end of list */ } 3474 } 3475 }, 3476 { /* end of list */ } 3477 } 3478 }, 3479 { 3480 .name = "Skylake-Client", 3481 .level = 0xd, 3482 .vendor = CPUID_VENDOR_INTEL, 3483 .family = 6, 3484 .model = 94, 3485 .stepping = 3, 3486 .features[FEAT_1_EDX] = 3487 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3488 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3489 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3490 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3491 CPUID_DE | CPUID_FP87, 3492 .features[FEAT_1_ECX] = 3493 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3494 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3495 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3496 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3497 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3498 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3499 .features[FEAT_8000_0001_EDX] = 3500 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3501 CPUID_EXT2_SYSCALL, 3502 .features[FEAT_8000_0001_ECX] = 3503 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3504 .features[FEAT_7_0_EBX] = 3505 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3506 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3507 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3508 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3509 CPUID_7_0_EBX_SMAP, 3510 /* XSAVES is added in version 4 */ 3511 .features[FEAT_XSAVE] = 3512 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3513 CPUID_XSAVE_XGETBV1, 3514 .features[FEAT_6_EAX] = 3515 CPUID_6_EAX_ARAT, 3516 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3517 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3518 MSR_VMX_BASIC_TRUE_CTLS, 3519 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3520 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3521 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3522 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3523 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3524 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3525 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3526 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3527 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3528 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3529 .features[FEAT_VMX_EXIT_CTLS] = 3530 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3531 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3532 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3533 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3534 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3535 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3536 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3537 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3538 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3539 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3540 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3541 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3542 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3543 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3544 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3545 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3546 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3547 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3548 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3549 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3550 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3551 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3552 .features[FEAT_VMX_SECONDARY_CTLS] = 3553 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3554 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3555 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3556 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3557 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3558 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3559 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3560 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3561 .xlevel = 0x80000008, 3562 .model_id = "Intel Core Processor (Skylake)", 3563 .versions = (X86CPUVersionDefinition[]) { 3564 { .version = 1 }, 3565 { 3566 .version = 2, 3567 .alias = "Skylake-Client-IBRS", 3568 .props = (PropValue[]) { 3569 { "spec-ctrl", "on" }, 3570 { "model-id", 3571 "Intel Core Processor (Skylake, IBRS)" }, 3572 { /* end of list */ } 3573 } 3574 }, 3575 { 3576 .version = 3, 3577 .alias = "Skylake-Client-noTSX-IBRS", 3578 .props = (PropValue[]) { 3579 { "hle", "off" }, 3580 { "rtm", "off" }, 3581 { "model-id", 3582 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3583 { /* end of list */ } 3584 } 3585 }, 3586 { 3587 .version = 4, 3588 .note = "IBRS, XSAVES, no TSX", 3589 .props = (PropValue[]) { 3590 { "xsaves", "on" }, 3591 { "vmx-xsaves", "on" }, 3592 { /* end of list */ } 3593 } 3594 }, 3595 { /* end of list */ } 3596 } 3597 }, 3598 { 3599 .name = "Skylake-Server", 3600 .level = 0xd, 3601 .vendor = CPUID_VENDOR_INTEL, 3602 .family = 6, 3603 .model = 85, 3604 .stepping = 4, 3605 .features[FEAT_1_EDX] = 3606 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3607 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3608 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3609 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3610 CPUID_DE | CPUID_FP87, 3611 .features[FEAT_1_ECX] = 3612 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3613 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3614 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3615 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3616 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3617 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3618 .features[FEAT_8000_0001_EDX] = 3619 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3620 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3621 .features[FEAT_8000_0001_ECX] = 3622 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3623 .features[FEAT_7_0_EBX] = 3624 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3625 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3626 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3627 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3628 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3629 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3630 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3631 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3632 .features[FEAT_7_0_ECX] = 3633 CPUID_7_0_ECX_PKU, 3634 /* XSAVES is added in version 5 */ 3635 .features[FEAT_XSAVE] = 3636 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3637 CPUID_XSAVE_XGETBV1, 3638 .features[FEAT_6_EAX] = 3639 CPUID_6_EAX_ARAT, 3640 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3641 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3642 MSR_VMX_BASIC_TRUE_CTLS, 3643 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3644 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3645 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3646 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3647 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3648 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3649 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3650 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3651 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3652 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3653 .features[FEAT_VMX_EXIT_CTLS] = 3654 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3655 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3656 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3657 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3658 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3659 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3660 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3661 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3662 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3663 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3664 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3665 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3666 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3667 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3668 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3669 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3670 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3671 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3672 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3673 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3674 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3675 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3676 .features[FEAT_VMX_SECONDARY_CTLS] = 3677 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3678 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3679 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3680 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3681 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3682 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3683 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3684 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3685 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3686 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3687 .xlevel = 0x80000008, 3688 .model_id = "Intel Xeon Processor (Skylake)", 3689 .versions = (X86CPUVersionDefinition[]) { 3690 { .version = 1 }, 3691 { 3692 .version = 2, 3693 .alias = "Skylake-Server-IBRS", 3694 .props = (PropValue[]) { 3695 /* clflushopt was not added to Skylake-Server-IBRS */ 3696 /* TODO: add -v3 including clflushopt */ 3697 { "clflushopt", "off" }, 3698 { "spec-ctrl", "on" }, 3699 { "model-id", 3700 "Intel Xeon Processor (Skylake, IBRS)" }, 3701 { /* end of list */ } 3702 } 3703 }, 3704 { 3705 .version = 3, 3706 .alias = "Skylake-Server-noTSX-IBRS", 3707 .props = (PropValue[]) { 3708 { "hle", "off" }, 3709 { "rtm", "off" }, 3710 { "model-id", 3711 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3712 { /* end of list */ } 3713 } 3714 }, 3715 { 3716 .version = 4, 3717 .note = "IBRS, EPT switching, no TSX", 3718 .props = (PropValue[]) { 3719 { "vmx-eptp-switching", "on" }, 3720 { /* end of list */ } 3721 } 3722 }, 3723 { 3724 .version = 5, 3725 .note = "IBRS, XSAVES, EPT switching, no TSX", 3726 .props = (PropValue[]) { 3727 { "xsaves", "on" }, 3728 { "vmx-xsaves", "on" }, 3729 { /* end of list */ } 3730 } 3731 }, 3732 { /* end of list */ } 3733 } 3734 }, 3735 { 3736 .name = "Cascadelake-Server", 3737 .level = 0xd, 3738 .vendor = CPUID_VENDOR_INTEL, 3739 .family = 6, 3740 .model = 85, 3741 .stepping = 6, 3742 .features[FEAT_1_EDX] = 3743 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3744 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3745 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3746 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3747 CPUID_DE | CPUID_FP87, 3748 .features[FEAT_1_ECX] = 3749 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3750 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3751 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3752 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3753 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3754 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3755 .features[FEAT_8000_0001_EDX] = 3756 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3757 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3758 .features[FEAT_8000_0001_ECX] = 3759 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3760 .features[FEAT_7_0_EBX] = 3761 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3762 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3763 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3764 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3765 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3766 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3767 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3768 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3769 .features[FEAT_7_0_ECX] = 3770 CPUID_7_0_ECX_PKU | 3771 CPUID_7_0_ECX_AVX512VNNI, 3772 .features[FEAT_7_0_EDX] = 3773 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3774 /* XSAVES is added in version 5 */ 3775 .features[FEAT_XSAVE] = 3776 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3777 CPUID_XSAVE_XGETBV1, 3778 .features[FEAT_6_EAX] = 3779 CPUID_6_EAX_ARAT, 3780 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3781 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3782 MSR_VMX_BASIC_TRUE_CTLS, 3783 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3784 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3785 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3786 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3787 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3788 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3789 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3790 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3791 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3792 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3793 .features[FEAT_VMX_EXIT_CTLS] = 3794 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3795 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3796 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3797 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3798 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3799 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3800 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3801 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3802 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3803 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3804 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3805 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3806 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3807 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3808 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3809 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3810 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3811 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3812 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3813 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3814 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3815 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3816 .features[FEAT_VMX_SECONDARY_CTLS] = 3817 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3818 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3819 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3820 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3821 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3822 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3823 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3824 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3825 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3826 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3827 .xlevel = 0x80000008, 3828 .model_id = "Intel Xeon Processor (Cascadelake)", 3829 .versions = (X86CPUVersionDefinition[]) { 3830 { .version = 1 }, 3831 { .version = 2, 3832 .note = "ARCH_CAPABILITIES", 3833 .props = (PropValue[]) { 3834 { "arch-capabilities", "on" }, 3835 { "rdctl-no", "on" }, 3836 { "ibrs-all", "on" }, 3837 { "skip-l1dfl-vmentry", "on" }, 3838 { "mds-no", "on" }, 3839 { /* end of list */ } 3840 }, 3841 }, 3842 { .version = 3, 3843 .alias = "Cascadelake-Server-noTSX", 3844 .note = "ARCH_CAPABILITIES, no TSX", 3845 .props = (PropValue[]) { 3846 { "hle", "off" }, 3847 { "rtm", "off" }, 3848 { /* end of list */ } 3849 }, 3850 }, 3851 { .version = 4, 3852 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 3853 .props = (PropValue[]) { 3854 { "vmx-eptp-switching", "on" }, 3855 { /* end of list */ } 3856 }, 3857 }, 3858 { .version = 5, 3859 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3860 .props = (PropValue[]) { 3861 { "xsaves", "on" }, 3862 { "vmx-xsaves", "on" }, 3863 { /* end of list */ } 3864 }, 3865 }, 3866 { /* end of list */ } 3867 } 3868 }, 3869 { 3870 .name = "Cooperlake", 3871 .level = 0xd, 3872 .vendor = CPUID_VENDOR_INTEL, 3873 .family = 6, 3874 .model = 85, 3875 .stepping = 10, 3876 .features[FEAT_1_EDX] = 3877 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3878 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3879 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3880 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3881 CPUID_DE | CPUID_FP87, 3882 .features[FEAT_1_ECX] = 3883 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3884 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3885 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3886 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3887 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3888 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3889 .features[FEAT_8000_0001_EDX] = 3890 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3891 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3892 .features[FEAT_8000_0001_ECX] = 3893 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3894 .features[FEAT_7_0_EBX] = 3895 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3896 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3897 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3898 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3899 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3900 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3901 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3902 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3903 .features[FEAT_7_0_ECX] = 3904 CPUID_7_0_ECX_PKU | 3905 CPUID_7_0_ECX_AVX512VNNI, 3906 .features[FEAT_7_0_EDX] = 3907 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3908 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3909 .features[FEAT_ARCH_CAPABILITIES] = 3910 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3911 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3912 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3913 .features[FEAT_7_1_EAX] = 3914 CPUID_7_1_EAX_AVX512_BF16, 3915 /* XSAVES is added in version 2 */ 3916 .features[FEAT_XSAVE] = 3917 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3918 CPUID_XSAVE_XGETBV1, 3919 .features[FEAT_6_EAX] = 3920 CPUID_6_EAX_ARAT, 3921 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3922 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3923 MSR_VMX_BASIC_TRUE_CTLS, 3924 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3925 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3926 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3927 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3928 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3929 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3930 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3931 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3932 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3933 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3934 .features[FEAT_VMX_EXIT_CTLS] = 3935 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3936 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3937 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3938 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3939 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3940 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3941 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3942 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3943 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3944 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3945 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3946 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3947 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3948 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3949 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3950 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3951 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3952 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3953 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3954 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3955 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3956 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3957 .features[FEAT_VMX_SECONDARY_CTLS] = 3958 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3959 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3960 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3961 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3962 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3963 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3964 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3965 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3966 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3967 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3968 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3969 .xlevel = 0x80000008, 3970 .model_id = "Intel Xeon Processor (Cooperlake)", 3971 .versions = (X86CPUVersionDefinition[]) { 3972 { .version = 1 }, 3973 { .version = 2, 3974 .note = "XSAVES", 3975 .props = (PropValue[]) { 3976 { "xsaves", "on" }, 3977 { "vmx-xsaves", "on" }, 3978 { /* end of list */ } 3979 }, 3980 }, 3981 { /* end of list */ } 3982 } 3983 }, 3984 { 3985 .name = "Icelake-Server", 3986 .level = 0xd, 3987 .vendor = CPUID_VENDOR_INTEL, 3988 .family = 6, 3989 .model = 134, 3990 .stepping = 0, 3991 .features[FEAT_1_EDX] = 3992 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3993 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3994 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3995 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3996 CPUID_DE | CPUID_FP87, 3997 .features[FEAT_1_ECX] = 3998 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3999 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4000 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4001 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4002 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4003 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4004 .features[FEAT_8000_0001_EDX] = 4005 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4006 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4007 .features[FEAT_8000_0001_ECX] = 4008 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4009 .features[FEAT_8000_0008_EBX] = 4010 CPUID_8000_0008_EBX_WBNOINVD, 4011 .features[FEAT_7_0_EBX] = 4012 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4013 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4014 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4015 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4016 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4017 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4018 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4019 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4020 .features[FEAT_7_0_ECX] = 4021 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4022 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4023 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4024 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4025 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4026 .features[FEAT_7_0_EDX] = 4027 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4028 /* XSAVES is added in version 5 */ 4029 .features[FEAT_XSAVE] = 4030 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4031 CPUID_XSAVE_XGETBV1, 4032 .features[FEAT_6_EAX] = 4033 CPUID_6_EAX_ARAT, 4034 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4035 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4036 MSR_VMX_BASIC_TRUE_CTLS, 4037 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4038 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4039 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4040 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4041 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4042 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4043 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4044 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4045 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4046 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4047 .features[FEAT_VMX_EXIT_CTLS] = 4048 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4049 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4050 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4051 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4052 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4053 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4054 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4055 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4056 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4057 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4058 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4059 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4060 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4061 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4062 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4063 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4064 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4065 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4066 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4067 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4068 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4069 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4070 .features[FEAT_VMX_SECONDARY_CTLS] = 4071 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4072 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4073 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4074 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4075 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4076 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4077 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4078 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4079 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4080 .xlevel = 0x80000008, 4081 .model_id = "Intel Xeon Processor (Icelake)", 4082 .versions = (X86CPUVersionDefinition[]) { 4083 { .version = 1 }, 4084 { 4085 .version = 2, 4086 .note = "no TSX", 4087 .alias = "Icelake-Server-noTSX", 4088 .props = (PropValue[]) { 4089 { "hle", "off" }, 4090 { "rtm", "off" }, 4091 { /* end of list */ } 4092 }, 4093 }, 4094 { 4095 .version = 3, 4096 .props = (PropValue[]) { 4097 { "arch-capabilities", "on" }, 4098 { "rdctl-no", "on" }, 4099 { "ibrs-all", "on" }, 4100 { "skip-l1dfl-vmentry", "on" }, 4101 { "mds-no", "on" }, 4102 { "pschange-mc-no", "on" }, 4103 { "taa-no", "on" }, 4104 { /* end of list */ } 4105 }, 4106 }, 4107 { 4108 .version = 4, 4109 .props = (PropValue[]) { 4110 { "sha-ni", "on" }, 4111 { "avx512ifma", "on" }, 4112 { "rdpid", "on" }, 4113 { "fsrm", "on" }, 4114 { "vmx-rdseed-exit", "on" }, 4115 { "vmx-pml", "on" }, 4116 { "vmx-eptp-switching", "on" }, 4117 { "model", "106" }, 4118 { /* end of list */ } 4119 }, 4120 }, 4121 { 4122 .version = 5, 4123 .note = "XSAVES", 4124 .props = (PropValue[]) { 4125 { "xsaves", "on" }, 4126 { "vmx-xsaves", "on" }, 4127 { /* end of list */ } 4128 }, 4129 }, 4130 { 4131 .version = 6, 4132 .note = "5-level EPT", 4133 .props = (PropValue[]) { 4134 { "vmx-page-walk-5", "on" }, 4135 { /* end of list */ } 4136 }, 4137 }, 4138 { 4139 .version = 7, 4140 .note = "TSX, taa-no", 4141 .props = (PropValue[]) { 4142 /* Restore TSX features removed by -v2 above */ 4143 { "hle", "on" }, 4144 { "rtm", "on" }, 4145 { /* end of list */ } 4146 }, 4147 }, 4148 { /* end of list */ } 4149 } 4150 }, 4151 { 4152 .name = "SapphireRapids", 4153 .level = 0x20, 4154 .vendor = CPUID_VENDOR_INTEL, 4155 .family = 6, 4156 .model = 143, 4157 .stepping = 4, 4158 /* 4159 * please keep the ascending order so that we can have a clear view of 4160 * bit position of each feature. 4161 */ 4162 .features[FEAT_1_EDX] = 4163 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4164 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4165 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4166 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4167 CPUID_SSE | CPUID_SSE2, 4168 .features[FEAT_1_ECX] = 4169 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4170 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4171 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4172 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4173 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4174 .features[FEAT_8000_0001_EDX] = 4175 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4176 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4177 .features[FEAT_8000_0001_ECX] = 4178 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4179 .features[FEAT_8000_0008_EBX] = 4180 CPUID_8000_0008_EBX_WBNOINVD, 4181 .features[FEAT_7_0_EBX] = 4182 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4183 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4184 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4185 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4186 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4187 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4188 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4189 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4190 .features[FEAT_7_0_ECX] = 4191 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4192 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4193 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4194 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4195 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4196 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4197 .features[FEAT_7_0_EDX] = 4198 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4199 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4200 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4201 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4202 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4203 .features[FEAT_ARCH_CAPABILITIES] = 4204 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4205 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4206 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4207 .features[FEAT_XSAVE] = 4208 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4209 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4210 .features[FEAT_6_EAX] = 4211 CPUID_6_EAX_ARAT, 4212 .features[FEAT_7_1_EAX] = 4213 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4214 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4215 .features[FEAT_VMX_BASIC] = 4216 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4217 .features[FEAT_VMX_ENTRY_CTLS] = 4218 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4219 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4220 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4221 .features[FEAT_VMX_EPT_VPID_CAPS] = 4222 MSR_VMX_EPT_EXECONLY | 4223 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4224 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4225 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4226 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4227 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4228 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4229 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4230 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4231 .features[FEAT_VMX_EXIT_CTLS] = 4232 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4233 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4234 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4235 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4236 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4237 .features[FEAT_VMX_MISC] = 4238 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4239 MSR_VMX_MISC_VMWRITE_VMEXIT, 4240 .features[FEAT_VMX_PINBASED_CTLS] = 4241 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4242 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4243 VMX_PIN_BASED_POSTED_INTR, 4244 .features[FEAT_VMX_PROCBASED_CTLS] = 4245 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4246 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4247 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4248 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4249 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4250 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4251 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4252 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4253 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4254 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4255 VMX_CPU_BASED_PAUSE_EXITING | 4256 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4257 .features[FEAT_VMX_SECONDARY_CTLS] = 4258 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4259 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4260 VMX_SECONDARY_EXEC_RDTSCP | 4261 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4262 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4263 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4264 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4265 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4266 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4267 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4268 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4269 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4270 VMX_SECONDARY_EXEC_XSAVES, 4271 .features[FEAT_VMX_VMFUNC] = 4272 MSR_VMX_VMFUNC_EPT_SWITCHING, 4273 .xlevel = 0x80000008, 4274 .model_id = "Intel Xeon Processor (SapphireRapids)", 4275 .versions = (X86CPUVersionDefinition[]) { 4276 { .version = 1 }, 4277 { 4278 .version = 2, 4279 .props = (PropValue[]) { 4280 { "sbdr-ssdp-no", "on" }, 4281 { "fbsdp-no", "on" }, 4282 { "psdp-no", "on" }, 4283 { /* end of list */ } 4284 } 4285 }, 4286 { 4287 .version = 3, 4288 .props = (PropValue[]) { 4289 { "ss", "on" }, 4290 { "tsc-adjust", "on" }, 4291 { "cldemote", "on" }, 4292 { "movdiri", "on" }, 4293 { "movdir64b", "on" }, 4294 { /* end of list */ } 4295 } 4296 }, 4297 { /* end of list */ } 4298 } 4299 }, 4300 { 4301 .name = "GraniteRapids", 4302 .level = 0x20, 4303 .vendor = CPUID_VENDOR_INTEL, 4304 .family = 6, 4305 .model = 173, 4306 .stepping = 0, 4307 /* 4308 * please keep the ascending order so that we can have a clear view of 4309 * bit position of each feature. 4310 */ 4311 .features[FEAT_1_EDX] = 4312 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4313 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4314 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4315 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4316 CPUID_SSE | CPUID_SSE2, 4317 .features[FEAT_1_ECX] = 4318 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4319 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4320 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4321 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4322 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4323 .features[FEAT_8000_0001_EDX] = 4324 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4325 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4326 .features[FEAT_8000_0001_ECX] = 4327 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4328 .features[FEAT_8000_0008_EBX] = 4329 CPUID_8000_0008_EBX_WBNOINVD, 4330 .features[FEAT_7_0_EBX] = 4331 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4332 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4333 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4334 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4335 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4336 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4337 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4338 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4339 .features[FEAT_7_0_ECX] = 4340 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4341 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4342 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4343 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4344 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4345 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4346 .features[FEAT_7_0_EDX] = 4347 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4348 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4349 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4350 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4351 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4352 .features[FEAT_ARCH_CAPABILITIES] = 4353 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4354 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4355 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4356 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4357 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4358 .features[FEAT_XSAVE] = 4359 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4360 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4361 .features[FEAT_6_EAX] = 4362 CPUID_6_EAX_ARAT, 4363 .features[FEAT_7_1_EAX] = 4364 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4365 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4366 CPUID_7_1_EAX_AMX_FP16, 4367 .features[FEAT_7_1_EDX] = 4368 CPUID_7_1_EDX_PREFETCHITI, 4369 .features[FEAT_7_2_EDX] = 4370 CPUID_7_2_EDX_MCDT_NO, 4371 .features[FEAT_VMX_BASIC] = 4372 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4373 .features[FEAT_VMX_ENTRY_CTLS] = 4374 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4375 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4376 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4377 .features[FEAT_VMX_EPT_VPID_CAPS] = 4378 MSR_VMX_EPT_EXECONLY | 4379 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4380 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4381 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4382 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4383 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4384 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4385 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4386 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4387 .features[FEAT_VMX_EXIT_CTLS] = 4388 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4389 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4390 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4391 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4392 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4393 .features[FEAT_VMX_MISC] = 4394 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4395 MSR_VMX_MISC_VMWRITE_VMEXIT, 4396 .features[FEAT_VMX_PINBASED_CTLS] = 4397 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4398 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4399 VMX_PIN_BASED_POSTED_INTR, 4400 .features[FEAT_VMX_PROCBASED_CTLS] = 4401 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4402 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4403 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4404 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4405 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4406 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4407 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4408 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4409 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4410 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4411 VMX_CPU_BASED_PAUSE_EXITING | 4412 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4413 .features[FEAT_VMX_SECONDARY_CTLS] = 4414 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4415 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4416 VMX_SECONDARY_EXEC_RDTSCP | 4417 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4418 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4419 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4420 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4421 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4422 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4423 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4424 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4425 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4426 VMX_SECONDARY_EXEC_XSAVES, 4427 .features[FEAT_VMX_VMFUNC] = 4428 MSR_VMX_VMFUNC_EPT_SWITCHING, 4429 .xlevel = 0x80000008, 4430 .model_id = "Intel Xeon Processor (GraniteRapids)", 4431 .versions = (X86CPUVersionDefinition[]) { 4432 { .version = 1 }, 4433 { 4434 .version = 2, 4435 .props = (PropValue[]) { 4436 { "ss", "on" }, 4437 { "tsc-adjust", "on" }, 4438 { "cldemote", "on" }, 4439 { "movdiri", "on" }, 4440 { "movdir64b", "on" }, 4441 { "avx10", "on" }, 4442 { "avx10-128", "on" }, 4443 { "avx10-256", "on" }, 4444 { "avx10-512", "on" }, 4445 { "avx10-version", "1" }, 4446 { "stepping", "1" }, 4447 { /* end of list */ } 4448 } 4449 }, 4450 { /* end of list */ }, 4451 }, 4452 }, 4453 { 4454 .name = "SierraForest", 4455 .level = 0x23, 4456 .vendor = CPUID_VENDOR_INTEL, 4457 .family = 6, 4458 .model = 175, 4459 .stepping = 0, 4460 /* 4461 * please keep the ascending order so that we can have a clear view of 4462 * bit position of each feature. 4463 */ 4464 .features[FEAT_1_EDX] = 4465 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4466 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4467 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4468 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4469 CPUID_SSE | CPUID_SSE2, 4470 .features[FEAT_1_ECX] = 4471 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4472 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4473 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4474 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4475 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4476 .features[FEAT_8000_0001_EDX] = 4477 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4478 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4479 .features[FEAT_8000_0001_ECX] = 4480 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4481 .features[FEAT_8000_0008_EBX] = 4482 CPUID_8000_0008_EBX_WBNOINVD, 4483 .features[FEAT_7_0_EBX] = 4484 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4485 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4486 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4487 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4488 CPUID_7_0_EBX_SHA_NI, 4489 .features[FEAT_7_0_ECX] = 4490 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4491 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4492 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4493 .features[FEAT_7_0_EDX] = 4494 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4495 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4496 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4497 .features[FEAT_ARCH_CAPABILITIES] = 4498 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4499 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4500 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4501 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4502 MSR_ARCH_CAP_PBRSB_NO, 4503 .features[FEAT_XSAVE] = 4504 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4505 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4506 .features[FEAT_6_EAX] = 4507 CPUID_6_EAX_ARAT, 4508 .features[FEAT_7_1_EAX] = 4509 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4510 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4511 .features[FEAT_7_1_EDX] = 4512 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4513 .features[FEAT_7_2_EDX] = 4514 CPUID_7_2_EDX_MCDT_NO, 4515 .features[FEAT_VMX_BASIC] = 4516 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4517 .features[FEAT_VMX_ENTRY_CTLS] = 4518 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4519 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4520 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4521 .features[FEAT_VMX_EPT_VPID_CAPS] = 4522 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4523 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4524 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4525 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4526 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4527 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4528 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4529 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4530 .features[FEAT_VMX_EXIT_CTLS] = 4531 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4532 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4533 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4534 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4535 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4536 .features[FEAT_VMX_MISC] = 4537 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4538 MSR_VMX_MISC_VMWRITE_VMEXIT, 4539 .features[FEAT_VMX_PINBASED_CTLS] = 4540 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4541 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4542 VMX_PIN_BASED_POSTED_INTR, 4543 .features[FEAT_VMX_PROCBASED_CTLS] = 4544 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4545 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4546 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4547 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4548 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4549 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4550 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4551 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4552 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4553 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4554 VMX_CPU_BASED_PAUSE_EXITING | 4555 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4556 .features[FEAT_VMX_SECONDARY_CTLS] = 4557 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4558 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4559 VMX_SECONDARY_EXEC_RDTSCP | 4560 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4561 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4562 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4563 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4564 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4565 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4566 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4567 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4568 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4569 VMX_SECONDARY_EXEC_XSAVES, 4570 .features[FEAT_VMX_VMFUNC] = 4571 MSR_VMX_VMFUNC_EPT_SWITCHING, 4572 .xlevel = 0x80000008, 4573 .model_id = "Intel Xeon Processor (SierraForest)", 4574 .versions = (X86CPUVersionDefinition[]) { 4575 { .version = 1 }, 4576 { 4577 .version = 2, 4578 .props = (PropValue[]) { 4579 { "ss", "on" }, 4580 { "tsc-adjust", "on" }, 4581 { "cldemote", "on" }, 4582 { "movdiri", "on" }, 4583 { "movdir64b", "on" }, 4584 { "gds-no", "on" }, 4585 { "rfds-no", "on" }, 4586 { "lam", "on" }, 4587 { "intel-psfd", "on"}, 4588 { "ipred-ctrl", "on"}, 4589 { "rrsba-ctrl", "on"}, 4590 { "bhi-ctrl", "on"}, 4591 { "stepping", "3" }, 4592 { /* end of list */ } 4593 } 4594 }, 4595 { /* end of list */ }, 4596 }, 4597 }, 4598 { 4599 .name = "ClearwaterForest", 4600 .level = 0x23, 4601 .xlevel = 0x80000008, 4602 .vendor = CPUID_VENDOR_INTEL, 4603 .family = 6, 4604 .model = 221, 4605 .stepping = 0, 4606 /* 4607 * please keep the ascending order so that we can have a clear view of 4608 * bit position of each feature. 4609 */ 4610 .features[FEAT_1_EDX] = 4611 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4612 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4613 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4614 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4615 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 4616 .features[FEAT_1_ECX] = 4617 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4618 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4619 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4620 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4621 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4622 .features[FEAT_8000_0001_EDX] = 4623 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4624 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4625 .features[FEAT_8000_0001_ECX] = 4626 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4627 .features[FEAT_8000_0008_EBX] = 4628 CPUID_8000_0008_EBX_WBNOINVD, 4629 .features[FEAT_7_0_EBX] = 4630 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 4631 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4632 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4633 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4634 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4635 CPUID_7_0_EBX_SHA_NI, 4636 .features[FEAT_7_0_ECX] = 4637 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4638 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4639 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 4640 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 4641 CPUID_7_0_ECX_MOVDIR64B, 4642 .features[FEAT_7_0_EDX] = 4643 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4644 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4645 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4646 .features[FEAT_ARCH_CAPABILITIES] = 4647 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4648 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4649 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4650 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4651 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 4652 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 4653 .features[FEAT_XSAVE] = 4654 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4655 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4656 .features[FEAT_6_EAX] = 4657 CPUID_6_EAX_ARAT, 4658 .features[FEAT_7_1_EAX] = 4659 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 4660 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4661 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 4662 CPUID_7_1_EAX_LAM, 4663 .features[FEAT_7_1_EDX] = 4664 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 4665 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 4666 .features[FEAT_7_2_EDX] = 4667 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 4668 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 4669 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 4670 .features[FEAT_VMX_BASIC] = 4671 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4672 .features[FEAT_VMX_ENTRY_CTLS] = 4673 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4674 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4675 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4676 .features[FEAT_VMX_EPT_VPID_CAPS] = 4677 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4678 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4679 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4680 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4681 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4682 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4683 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4684 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4685 .features[FEAT_VMX_EXIT_CTLS] = 4686 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4687 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4688 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4689 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4690 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4691 .features[FEAT_VMX_MISC] = 4692 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4693 MSR_VMX_MISC_VMWRITE_VMEXIT, 4694 .features[FEAT_VMX_PINBASED_CTLS] = 4695 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4696 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4697 VMX_PIN_BASED_POSTED_INTR, 4698 .features[FEAT_VMX_PROCBASED_CTLS] = 4699 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4700 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4701 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4702 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4703 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4704 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4705 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4706 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4707 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4708 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4709 VMX_CPU_BASED_PAUSE_EXITING | 4710 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4711 .features[FEAT_VMX_SECONDARY_CTLS] = 4712 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4713 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4714 VMX_SECONDARY_EXEC_RDTSCP | 4715 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4716 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4717 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4718 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4719 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4720 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4721 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4722 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4723 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4724 VMX_SECONDARY_EXEC_XSAVES, 4725 .features[FEAT_VMX_VMFUNC] = 4726 MSR_VMX_VMFUNC_EPT_SWITCHING, 4727 .model_id = "Intel Xeon Processor (ClearwaterForest)", 4728 .versions = (X86CPUVersionDefinition[]) { 4729 { .version = 1 }, 4730 { /* end of list */ }, 4731 }, 4732 }, 4733 { 4734 .name = "Denverton", 4735 .level = 21, 4736 .vendor = CPUID_VENDOR_INTEL, 4737 .family = 6, 4738 .model = 95, 4739 .stepping = 1, 4740 .features[FEAT_1_EDX] = 4741 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4742 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4743 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4744 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4745 CPUID_SSE | CPUID_SSE2, 4746 .features[FEAT_1_ECX] = 4747 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4748 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4749 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4750 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4751 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4752 .features[FEAT_8000_0001_EDX] = 4753 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4754 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4755 .features[FEAT_8000_0001_ECX] = 4756 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4757 .features[FEAT_7_0_EBX] = 4758 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4759 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4760 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4761 .features[FEAT_7_0_EDX] = 4762 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4763 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4764 /* XSAVES is added in version 3 */ 4765 .features[FEAT_XSAVE] = 4766 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4767 .features[FEAT_6_EAX] = 4768 CPUID_6_EAX_ARAT, 4769 .features[FEAT_ARCH_CAPABILITIES] = 4770 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4771 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4772 MSR_VMX_BASIC_TRUE_CTLS, 4773 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4774 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4775 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4776 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4777 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4778 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4779 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4780 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4781 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4782 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4783 .features[FEAT_VMX_EXIT_CTLS] = 4784 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4785 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4786 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4787 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4788 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4789 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4790 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4791 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4792 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4793 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4794 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4795 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4796 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4797 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4798 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4799 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4800 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4801 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4802 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4803 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4804 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4805 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4806 .features[FEAT_VMX_SECONDARY_CTLS] = 4807 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4808 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4809 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4810 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4811 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4812 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4813 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4814 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4815 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4816 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4817 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4818 .xlevel = 0x80000008, 4819 .model_id = "Intel Atom Processor (Denverton)", 4820 .versions = (X86CPUVersionDefinition[]) { 4821 { .version = 1 }, 4822 { 4823 .version = 2, 4824 .note = "no MPX, no MONITOR", 4825 .props = (PropValue[]) { 4826 { "monitor", "off" }, 4827 { "mpx", "off" }, 4828 { /* end of list */ }, 4829 }, 4830 }, 4831 { 4832 .version = 3, 4833 .note = "XSAVES, no MPX, no MONITOR", 4834 .props = (PropValue[]) { 4835 { "xsaves", "on" }, 4836 { "vmx-xsaves", "on" }, 4837 { /* end of list */ }, 4838 }, 4839 }, 4840 { /* end of list */ }, 4841 }, 4842 }, 4843 { 4844 .name = "Snowridge", 4845 .level = 27, 4846 .vendor = CPUID_VENDOR_INTEL, 4847 .family = 6, 4848 .model = 134, 4849 .stepping = 1, 4850 .features[FEAT_1_EDX] = 4851 /* missing: CPUID_PN CPUID_IA64 */ 4852 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4853 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4854 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4855 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4856 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4857 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4858 CPUID_MMX | 4859 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4860 .features[FEAT_1_ECX] = 4861 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4862 CPUID_EXT_SSSE3 | 4863 CPUID_EXT_CX16 | 4864 CPUID_EXT_SSE41 | 4865 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4866 CPUID_EXT_POPCNT | 4867 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4868 CPUID_EXT_RDRAND, 4869 .features[FEAT_8000_0001_EDX] = 4870 CPUID_EXT2_SYSCALL | 4871 CPUID_EXT2_NX | 4872 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4873 CPUID_EXT2_LM, 4874 .features[FEAT_8000_0001_ECX] = 4875 CPUID_EXT3_LAHF_LM | 4876 CPUID_EXT3_3DNOWPREFETCH, 4877 .features[FEAT_7_0_EBX] = 4878 CPUID_7_0_EBX_FSGSBASE | 4879 CPUID_7_0_EBX_SMEP | 4880 CPUID_7_0_EBX_ERMS | 4881 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4882 CPUID_7_0_EBX_RDSEED | 4883 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4884 CPUID_7_0_EBX_CLWB | 4885 CPUID_7_0_EBX_SHA_NI, 4886 .features[FEAT_7_0_ECX] = 4887 CPUID_7_0_ECX_UMIP | 4888 /* missing bit 5 */ 4889 CPUID_7_0_ECX_GFNI | 4890 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4891 CPUID_7_0_ECX_MOVDIR64B, 4892 .features[FEAT_7_0_EDX] = 4893 CPUID_7_0_EDX_SPEC_CTRL | 4894 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4895 CPUID_7_0_EDX_CORE_CAPABILITY, 4896 .features[FEAT_CORE_CAPABILITY] = 4897 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4898 /* XSAVES is added in version 3 */ 4899 .features[FEAT_XSAVE] = 4900 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4901 CPUID_XSAVE_XGETBV1, 4902 .features[FEAT_6_EAX] = 4903 CPUID_6_EAX_ARAT, 4904 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4905 MSR_VMX_BASIC_TRUE_CTLS, 4906 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4907 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4908 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4909 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4910 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4911 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4912 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4913 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4914 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4915 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4916 .features[FEAT_VMX_EXIT_CTLS] = 4917 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4918 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4919 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4920 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4921 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4922 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4923 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4924 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4925 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4926 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4927 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4928 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4929 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4930 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4931 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4932 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4933 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4934 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4935 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4936 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4937 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4938 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4939 .features[FEAT_VMX_SECONDARY_CTLS] = 4940 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4941 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4942 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4943 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4944 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4945 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4946 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4947 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4948 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4949 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4950 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4951 .xlevel = 0x80000008, 4952 .model_id = "Intel Atom Processor (SnowRidge)", 4953 .versions = (X86CPUVersionDefinition[]) { 4954 { .version = 1 }, 4955 { 4956 .version = 2, 4957 .props = (PropValue[]) { 4958 { "mpx", "off" }, 4959 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4960 { /* end of list */ }, 4961 }, 4962 }, 4963 { 4964 .version = 3, 4965 .note = "XSAVES, no MPX", 4966 .props = (PropValue[]) { 4967 { "xsaves", "on" }, 4968 { "vmx-xsaves", "on" }, 4969 { /* end of list */ }, 4970 }, 4971 }, 4972 { 4973 .version = 4, 4974 .note = "no split lock detect, no core-capability", 4975 .props = (PropValue[]) { 4976 { "split-lock-detect", "off" }, 4977 { "core-capability", "off" }, 4978 { /* end of list */ }, 4979 }, 4980 }, 4981 { /* end of list */ }, 4982 }, 4983 }, 4984 { 4985 .name = "KnightsMill", 4986 .level = 0xd, 4987 .vendor = CPUID_VENDOR_INTEL, 4988 .family = 6, 4989 .model = 133, 4990 .stepping = 0, 4991 .features[FEAT_1_EDX] = 4992 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4993 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4994 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4995 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4996 CPUID_PSE | CPUID_DE | CPUID_FP87, 4997 .features[FEAT_1_ECX] = 4998 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4999 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 5000 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 5001 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5002 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 5003 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5004 .features[FEAT_8000_0001_EDX] = 5005 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5006 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5007 .features[FEAT_8000_0001_ECX] = 5008 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5009 .features[FEAT_7_0_EBX] = 5010 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5011 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5012 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 5013 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 5014 CPUID_7_0_EBX_AVX512ER, 5015 .features[FEAT_7_0_ECX] = 5016 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 5017 .features[FEAT_7_0_EDX] = 5018 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 5019 .features[FEAT_XSAVE] = 5020 CPUID_XSAVE_XSAVEOPT, 5021 .features[FEAT_6_EAX] = 5022 CPUID_6_EAX_ARAT, 5023 .xlevel = 0x80000008, 5024 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5025 }, 5026 { 5027 .name = "Opteron_G1", 5028 .level = 5, 5029 .vendor = CPUID_VENDOR_AMD, 5030 .family = 15, 5031 .model = 6, 5032 .stepping = 1, 5033 .features[FEAT_1_EDX] = 5034 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5035 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5036 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5037 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5038 CPUID_DE | CPUID_FP87, 5039 .features[FEAT_1_ECX] = 5040 CPUID_EXT_SSE3, 5041 .features[FEAT_8000_0001_EDX] = 5042 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5043 .xlevel = 0x80000008, 5044 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5045 }, 5046 { 5047 .name = "Opteron_G2", 5048 .level = 5, 5049 .vendor = CPUID_VENDOR_AMD, 5050 .family = 15, 5051 .model = 6, 5052 .stepping = 1, 5053 .features[FEAT_1_EDX] = 5054 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5055 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5056 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5057 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5058 CPUID_DE | CPUID_FP87, 5059 .features[FEAT_1_ECX] = 5060 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5061 .features[FEAT_8000_0001_EDX] = 5062 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5063 .features[FEAT_8000_0001_ECX] = 5064 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5065 .xlevel = 0x80000008, 5066 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5067 }, 5068 { 5069 .name = "Opteron_G3", 5070 .level = 5, 5071 .vendor = CPUID_VENDOR_AMD, 5072 .family = 16, 5073 .model = 2, 5074 .stepping = 3, 5075 .features[FEAT_1_EDX] = 5076 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5077 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5078 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5079 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5080 CPUID_DE | CPUID_FP87, 5081 .features[FEAT_1_ECX] = 5082 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5083 CPUID_EXT_SSE3, 5084 .features[FEAT_8000_0001_EDX] = 5085 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5086 CPUID_EXT2_RDTSCP, 5087 .features[FEAT_8000_0001_ECX] = 5088 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5089 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5090 .xlevel = 0x80000008, 5091 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5092 }, 5093 { 5094 .name = "Opteron_G4", 5095 .level = 0xd, 5096 .vendor = CPUID_VENDOR_AMD, 5097 .family = 21, 5098 .model = 1, 5099 .stepping = 2, 5100 .features[FEAT_1_EDX] = 5101 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5102 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5103 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5104 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5105 CPUID_DE | CPUID_FP87, 5106 .features[FEAT_1_ECX] = 5107 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5108 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5109 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5110 CPUID_EXT_SSE3, 5111 .features[FEAT_8000_0001_EDX] = 5112 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5113 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5114 .features[FEAT_8000_0001_ECX] = 5115 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5116 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5117 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5118 CPUID_EXT3_LAHF_LM, 5119 .features[FEAT_SVM] = 5120 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5121 /* no xsaveopt! */ 5122 .xlevel = 0x8000001A, 5123 .model_id = "AMD Opteron 62xx class CPU", 5124 }, 5125 { 5126 .name = "Opteron_G5", 5127 .level = 0xd, 5128 .vendor = CPUID_VENDOR_AMD, 5129 .family = 21, 5130 .model = 2, 5131 .stepping = 0, 5132 .features[FEAT_1_EDX] = 5133 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5134 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5135 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5136 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5137 CPUID_DE | CPUID_FP87, 5138 .features[FEAT_1_ECX] = 5139 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5140 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5141 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5142 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5143 .features[FEAT_8000_0001_EDX] = 5144 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5145 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5146 .features[FEAT_8000_0001_ECX] = 5147 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5148 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5149 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5150 CPUID_EXT3_LAHF_LM, 5151 .features[FEAT_SVM] = 5152 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5153 /* no xsaveopt! */ 5154 .xlevel = 0x8000001A, 5155 .model_id = "AMD Opteron 63xx class CPU", 5156 }, 5157 { 5158 .name = "EPYC", 5159 .level = 0xd, 5160 .vendor = CPUID_VENDOR_AMD, 5161 .family = 23, 5162 .model = 1, 5163 .stepping = 2, 5164 .features[FEAT_1_EDX] = 5165 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5166 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5167 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5168 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5169 CPUID_VME | CPUID_FP87, 5170 .features[FEAT_1_ECX] = 5171 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5172 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5173 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5174 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5175 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5176 .features[FEAT_8000_0001_EDX] = 5177 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5178 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5179 CPUID_EXT2_SYSCALL, 5180 .features[FEAT_8000_0001_ECX] = 5181 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5182 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5183 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5184 CPUID_EXT3_TOPOEXT, 5185 .features[FEAT_7_0_EBX] = 5186 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5187 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5188 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5189 CPUID_7_0_EBX_SHA_NI, 5190 .features[FEAT_XSAVE] = 5191 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5192 CPUID_XSAVE_XGETBV1, 5193 .features[FEAT_6_EAX] = 5194 CPUID_6_EAX_ARAT, 5195 .features[FEAT_SVM] = 5196 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5197 .xlevel = 0x8000001E, 5198 .model_id = "AMD EPYC Processor", 5199 .cache_info = &epyc_cache_info, 5200 .versions = (X86CPUVersionDefinition[]) { 5201 { .version = 1 }, 5202 { 5203 .version = 2, 5204 .alias = "EPYC-IBPB", 5205 .props = (PropValue[]) { 5206 { "ibpb", "on" }, 5207 { "model-id", 5208 "AMD EPYC Processor (with IBPB)" }, 5209 { /* end of list */ } 5210 } 5211 }, 5212 { 5213 .version = 3, 5214 .props = (PropValue[]) { 5215 { "ibpb", "on" }, 5216 { "perfctr-core", "on" }, 5217 { "clzero", "on" }, 5218 { "xsaveerptr", "on" }, 5219 { "xsaves", "on" }, 5220 { "model-id", 5221 "AMD EPYC Processor" }, 5222 { /* end of list */ } 5223 } 5224 }, 5225 { 5226 .version = 4, 5227 .props = (PropValue[]) { 5228 { "model-id", 5229 "AMD EPYC-v4 Processor" }, 5230 { /* end of list */ } 5231 }, 5232 .cache_info = &epyc_v4_cache_info 5233 }, 5234 { /* end of list */ } 5235 } 5236 }, 5237 { 5238 .name = "Dhyana", 5239 .level = 0xd, 5240 .vendor = CPUID_VENDOR_HYGON, 5241 .family = 24, 5242 .model = 0, 5243 .stepping = 1, 5244 .features[FEAT_1_EDX] = 5245 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5246 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5247 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5248 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5249 CPUID_VME | CPUID_FP87, 5250 .features[FEAT_1_ECX] = 5251 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5252 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5253 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5254 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5255 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5256 .features[FEAT_8000_0001_EDX] = 5257 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5258 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5259 CPUID_EXT2_SYSCALL, 5260 .features[FEAT_8000_0001_ECX] = 5261 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5262 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5263 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5264 CPUID_EXT3_TOPOEXT, 5265 .features[FEAT_8000_0008_EBX] = 5266 CPUID_8000_0008_EBX_IBPB, 5267 .features[FEAT_7_0_EBX] = 5268 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5269 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5270 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5271 /* XSAVES is added in version 2 */ 5272 .features[FEAT_XSAVE] = 5273 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5274 CPUID_XSAVE_XGETBV1, 5275 .features[FEAT_6_EAX] = 5276 CPUID_6_EAX_ARAT, 5277 .features[FEAT_SVM] = 5278 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5279 .xlevel = 0x8000001E, 5280 .model_id = "Hygon Dhyana Processor", 5281 .cache_info = &epyc_cache_info, 5282 .versions = (X86CPUVersionDefinition[]) { 5283 { .version = 1 }, 5284 { .version = 2, 5285 .note = "XSAVES", 5286 .props = (PropValue[]) { 5287 { "xsaves", "on" }, 5288 { /* end of list */ } 5289 }, 5290 }, 5291 { /* end of list */ } 5292 } 5293 }, 5294 { 5295 .name = "EPYC-Rome", 5296 .level = 0xd, 5297 .vendor = CPUID_VENDOR_AMD, 5298 .family = 23, 5299 .model = 49, 5300 .stepping = 0, 5301 .features[FEAT_1_EDX] = 5302 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5303 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5304 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5305 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5306 CPUID_VME | CPUID_FP87, 5307 .features[FEAT_1_ECX] = 5308 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5309 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5310 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5311 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5312 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5313 .features[FEAT_8000_0001_EDX] = 5314 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5315 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5316 CPUID_EXT2_SYSCALL, 5317 .features[FEAT_8000_0001_ECX] = 5318 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5319 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5320 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5321 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5322 .features[FEAT_8000_0008_EBX] = 5323 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5324 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5325 CPUID_8000_0008_EBX_STIBP, 5326 .features[FEAT_7_0_EBX] = 5327 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5328 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5329 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5330 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5331 .features[FEAT_7_0_ECX] = 5332 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5333 .features[FEAT_XSAVE] = 5334 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5335 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5336 .features[FEAT_6_EAX] = 5337 CPUID_6_EAX_ARAT, 5338 .features[FEAT_SVM] = 5339 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5340 .xlevel = 0x8000001E, 5341 .model_id = "AMD EPYC-Rome Processor", 5342 .cache_info = &epyc_rome_cache_info, 5343 .versions = (X86CPUVersionDefinition[]) { 5344 { .version = 1 }, 5345 { 5346 .version = 2, 5347 .props = (PropValue[]) { 5348 { "ibrs", "on" }, 5349 { "amd-ssbd", "on" }, 5350 { /* end of list */ } 5351 } 5352 }, 5353 { 5354 .version = 3, 5355 .props = (PropValue[]) { 5356 { "model-id", 5357 "AMD EPYC-Rome-v3 Processor" }, 5358 { /* end of list */ } 5359 }, 5360 .cache_info = &epyc_rome_v3_cache_info 5361 }, 5362 { 5363 .version = 4, 5364 .props = (PropValue[]) { 5365 /* Erratum 1386 */ 5366 { "model-id", 5367 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5368 { "xsaves", "off" }, 5369 { /* end of list */ } 5370 }, 5371 }, 5372 { /* end of list */ } 5373 } 5374 }, 5375 { 5376 .name = "EPYC-Milan", 5377 .level = 0xd, 5378 .vendor = CPUID_VENDOR_AMD, 5379 .family = 25, 5380 .model = 1, 5381 .stepping = 1, 5382 .features[FEAT_1_EDX] = 5383 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5384 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5385 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5386 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5387 CPUID_VME | CPUID_FP87, 5388 .features[FEAT_1_ECX] = 5389 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5390 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5391 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5392 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5393 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5394 CPUID_EXT_PCID, 5395 .features[FEAT_8000_0001_EDX] = 5396 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5397 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5398 CPUID_EXT2_SYSCALL, 5399 .features[FEAT_8000_0001_ECX] = 5400 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5401 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5402 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5403 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5404 .features[FEAT_8000_0008_EBX] = 5405 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5406 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5407 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5408 CPUID_8000_0008_EBX_AMD_SSBD, 5409 .features[FEAT_7_0_EBX] = 5410 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5411 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5412 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5413 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5414 CPUID_7_0_EBX_INVPCID, 5415 .features[FEAT_7_0_ECX] = 5416 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5417 .features[FEAT_7_0_EDX] = 5418 CPUID_7_0_EDX_FSRM, 5419 .features[FEAT_XSAVE] = 5420 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5421 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5422 .features[FEAT_6_EAX] = 5423 CPUID_6_EAX_ARAT, 5424 .features[FEAT_SVM] = 5425 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5426 .xlevel = 0x8000001E, 5427 .model_id = "AMD EPYC-Milan Processor", 5428 .cache_info = &epyc_milan_cache_info, 5429 .versions = (X86CPUVersionDefinition[]) { 5430 { .version = 1 }, 5431 { 5432 .version = 2, 5433 .props = (PropValue[]) { 5434 { "model-id", 5435 "AMD EPYC-Milan-v2 Processor" }, 5436 { "vaes", "on" }, 5437 { "vpclmulqdq", "on" }, 5438 { "stibp-always-on", "on" }, 5439 { "amd-psfd", "on" }, 5440 { "no-nested-data-bp", "on" }, 5441 { "lfence-always-serializing", "on" }, 5442 { "null-sel-clr-base", "on" }, 5443 { /* end of list */ } 5444 }, 5445 .cache_info = &epyc_milan_v2_cache_info 5446 }, 5447 { /* end of list */ } 5448 } 5449 }, 5450 { 5451 .name = "EPYC-Genoa", 5452 .level = 0xd, 5453 .vendor = CPUID_VENDOR_AMD, 5454 .family = 25, 5455 .model = 17, 5456 .stepping = 0, 5457 .features[FEAT_1_EDX] = 5458 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5459 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5460 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5461 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5462 CPUID_VME | CPUID_FP87, 5463 .features[FEAT_1_ECX] = 5464 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5465 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5466 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5467 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5468 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5469 CPUID_EXT_SSE3, 5470 .features[FEAT_8000_0001_EDX] = 5471 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5472 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5473 CPUID_EXT2_SYSCALL, 5474 .features[FEAT_8000_0001_ECX] = 5475 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5476 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5477 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5478 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5479 .features[FEAT_8000_0008_EBX] = 5480 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5481 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5482 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5483 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5484 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5485 .features[FEAT_8000_0021_EAX] = 5486 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5487 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5488 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5489 CPUID_8000_0021_EAX_AUTO_IBRS, 5490 .features[FEAT_7_0_EBX] = 5491 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5492 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5493 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5494 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5495 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5496 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5497 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5498 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5499 .features[FEAT_7_0_ECX] = 5500 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5501 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5502 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5503 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5504 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5505 CPUID_7_0_ECX_RDPID, 5506 .features[FEAT_7_0_EDX] = 5507 CPUID_7_0_EDX_FSRM, 5508 .features[FEAT_7_1_EAX] = 5509 CPUID_7_1_EAX_AVX512_BF16, 5510 .features[FEAT_XSAVE] = 5511 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5512 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5513 .features[FEAT_6_EAX] = 5514 CPUID_6_EAX_ARAT, 5515 .features[FEAT_SVM] = 5516 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5517 CPUID_SVM_SVME_ADDR_CHK, 5518 .xlevel = 0x80000022, 5519 .model_id = "AMD EPYC-Genoa Processor", 5520 .cache_info = &epyc_genoa_cache_info, 5521 }, 5522 { 5523 .name = "YongFeng", 5524 .level = 0x1F, 5525 .vendor = CPUID_VENDOR_ZHAOXIN1, 5526 .family = 7, 5527 .model = 11, 5528 .stepping = 3, 5529 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 5530 .features[FEAT_1_EDX] = 5531 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5532 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5533 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5534 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5535 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 5536 /* 5537 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 5538 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 5539 */ 5540 .features[FEAT_1_ECX] = 5541 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5542 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 5543 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 5544 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 5545 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5546 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5547 .features[FEAT_7_0_EBX] = 5548 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 5549 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 5550 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 5551 CPUID_7_0_EBX_FSGSBASE, 5552 /* missing: CPUID_7_0_ECX_OSPKE */ 5553 .features[FEAT_7_0_ECX] = 5554 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 5555 .features[FEAT_7_0_EDX] = 5556 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 5557 .features[FEAT_8000_0001_EDX] = 5558 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5559 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5560 .features[FEAT_8000_0001_ECX] = 5561 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 5562 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 5563 /* 5564 * TODO: When the Linux kernel introduces other existing definitions 5565 * for this leaf, remember to update the definitions here. 5566 */ 5567 .features[FEAT_C000_0001_EDX] = 5568 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 5569 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 5570 CPUID_C000_0001_EDX_ACE2 | 5571 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 5572 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 5573 .features[FEAT_XSAVE] = 5574 CPUID_XSAVE_XSAVEOPT, 5575 .features[FEAT_ARCH_CAPABILITIES] = 5576 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 5577 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 5578 MSR_ARCH_CAP_SSB_NO, 5579 .features[FEAT_VMX_PROCBASED_CTLS] = 5580 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 5581 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 5582 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 5583 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 5584 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 5585 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 5586 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 5587 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5588 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 5589 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5590 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5591 /* 5592 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 5593 * VMX_SECONDARY_EXEC_TSC_SCALING 5594 */ 5595 .features[FEAT_VMX_SECONDARY_CTLS] = 5596 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5597 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5598 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 5599 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5600 VMX_SECONDARY_EXEC_WBINVD_EXITING | 5601 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5602 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5603 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5604 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5605 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5606 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 5607 VMX_SECONDARY_EXEC_SHADOW_VMCS | 5608 VMX_SECONDARY_EXEC_ENABLE_PML, 5609 .features[FEAT_VMX_PINBASED_CTLS] = 5610 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5611 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5612 VMX_PIN_BASED_POSTED_INTR, 5613 .features[FEAT_VMX_EXIT_CTLS] = 5614 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 5615 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5616 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5617 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5618 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5619 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 5620 .features[FEAT_VMX_ENTRY_CTLS] = 5621 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5622 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5623 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5624 /* 5625 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 5626 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 5627 */ 5628 .features[FEAT_VMX_MISC] = 5629 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5630 MSR_VMX_MISC_VMWRITE_VMEXIT, 5631 /* missing: MSR_VMX_EPT_UC */ 5632 .features[FEAT_VMX_EPT_VPID_CAPS] = 5633 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5634 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5635 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5636 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5637 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 5638 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5639 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5640 .features[FEAT_VMX_BASIC] = 5641 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5642 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5643 .xlevel = 0x80000008, 5644 .model_id = "Zhaoxin YongFeng Processor", 5645 .versions = (X86CPUVersionDefinition[]) { 5646 { .version = 1 }, 5647 { 5648 .version = 2, 5649 .note = "with the correct model number", 5650 .props = (PropValue[]) { 5651 { "model", "0x5b" }, 5652 { /* end of list */ } 5653 } 5654 }, 5655 { /* end of list */ } 5656 } 5657 }, 5658 }; 5659 5660 /* 5661 * We resolve CPU model aliases using -v1 when using "-machine 5662 * none", but this is just for compatibility while libvirt isn't 5663 * adapted to resolve CPU model versions before creating VMs. 5664 * See "Runnability guarantee of CPU models" at 5665 * docs/about/deprecated.rst. 5666 */ 5667 X86CPUVersion default_cpu_version = 1; 5668 5669 void x86_cpu_set_default_version(X86CPUVersion version) 5670 { 5671 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5672 assert(version != CPU_VERSION_AUTO); 5673 default_cpu_version = version; 5674 } 5675 5676 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5677 { 5678 int v = 0; 5679 const X86CPUVersionDefinition *vdef = 5680 x86_cpu_def_get_versions(model->cpudef); 5681 while (vdef->version) { 5682 v = vdef->version; 5683 vdef++; 5684 } 5685 return v; 5686 } 5687 5688 /* Return the actual version being used for a specific CPU model */ 5689 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5690 { 5691 X86CPUVersion v = model->version; 5692 if (v == CPU_VERSION_AUTO) { 5693 v = default_cpu_version; 5694 } 5695 if (v == CPU_VERSION_LATEST) { 5696 return x86_cpu_model_last_version(model); 5697 } 5698 return v; 5699 } 5700 5701 static const Property max_x86_cpu_properties[] = { 5702 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5703 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5704 }; 5705 5706 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5707 { 5708 Object *obj = OBJECT(dev); 5709 5710 if (!object_property_get_int(obj, "family", &error_abort)) { 5711 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5712 object_property_set_int(obj, "family", 15, &error_abort); 5713 object_property_set_int(obj, "model", 107, &error_abort); 5714 object_property_set_int(obj, "stepping", 1, &error_abort); 5715 } else { 5716 object_property_set_int(obj, "family", 6, &error_abort); 5717 object_property_set_int(obj, "model", 6, &error_abort); 5718 object_property_set_int(obj, "stepping", 3, &error_abort); 5719 } 5720 } 5721 5722 x86_cpu_realizefn(dev, errp); 5723 } 5724 5725 static void max_x86_cpu_class_init(ObjectClass *oc, const void *data) 5726 { 5727 DeviceClass *dc = DEVICE_CLASS(oc); 5728 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5729 5730 xcc->ordering = 9; 5731 5732 xcc->model_description = 5733 "Enables all features supported by the accelerator in the current host"; 5734 5735 device_class_set_props(dc, max_x86_cpu_properties); 5736 dc->realize = max_x86_cpu_realize; 5737 } 5738 5739 static void max_x86_cpu_initfn(Object *obj) 5740 { 5741 X86CPU *cpu = X86_CPU(obj); 5742 5743 /* We can't fill the features array here because we don't know yet if 5744 * "migratable" is true or false. 5745 */ 5746 cpu->max_features = true; 5747 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5748 5749 /* 5750 * these defaults are used for TCG and all other accelerators 5751 * besides KVM and HVF, which overwrite these values 5752 */ 5753 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5754 &error_abort); 5755 object_property_set_str(OBJECT(cpu), "model-id", 5756 "QEMU TCG CPU version " QEMU_HW_VERSION, 5757 &error_abort); 5758 } 5759 5760 static const TypeInfo max_x86_cpu_type_info = { 5761 .name = X86_CPU_TYPE_NAME("max"), 5762 .parent = TYPE_X86_CPU, 5763 .instance_init = max_x86_cpu_initfn, 5764 .class_init = max_x86_cpu_class_init, 5765 }; 5766 5767 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5768 { 5769 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5770 5771 switch (f->type) { 5772 case CPUID_FEATURE_WORD: 5773 { 5774 const char *reg = get_register_name_32(f->cpuid.reg); 5775 assert(reg); 5776 return g_strdup_printf("CPUID.%02XH:%s", 5777 f->cpuid.eax, reg); 5778 } 5779 case MSR_FEATURE_WORD: 5780 return g_strdup_printf("MSR(%02XH)", 5781 f->msr.index); 5782 } 5783 5784 return NULL; 5785 } 5786 5787 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5788 { 5789 FeatureWord w; 5790 5791 for (w = 0; w < FEATURE_WORDS; w++) { 5792 if (cpu->filtered_features[w]) { 5793 return true; 5794 } 5795 } 5796 5797 return false; 5798 } 5799 5800 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5801 const char *verbose_prefix) 5802 { 5803 CPUX86State *env = &cpu->env; 5804 FeatureWordInfo *f = &feature_word_info[w]; 5805 int i; 5806 5807 if (!cpu->force_features) { 5808 env->features[w] &= ~mask; 5809 } 5810 cpu->filtered_features[w] |= mask; 5811 5812 if (!verbose_prefix) { 5813 return; 5814 } 5815 5816 for (i = 0; i < 64; ++i) { 5817 if ((1ULL << i) & mask) { 5818 g_autofree char *feat_word_str = feature_word_description(f, i); 5819 warn_report("%s: %s%s%s [bit %d]", 5820 verbose_prefix, 5821 feat_word_str, 5822 f->feat_names[i] ? "." : "", 5823 f->feat_names[i] ? f->feat_names[i] : "", i); 5824 } 5825 } 5826 } 5827 5828 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5829 const char *name, void *opaque, 5830 Error **errp) 5831 { 5832 X86CPU *cpu = X86_CPU(obj); 5833 CPUX86State *env = &cpu->env; 5834 uint64_t value; 5835 5836 value = (env->cpuid_version >> 8) & 0xf; 5837 if (value == 0xf) { 5838 value += (env->cpuid_version >> 20) & 0xff; 5839 } 5840 visit_type_uint64(v, name, &value, errp); 5841 } 5842 5843 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5844 const char *name, void *opaque, 5845 Error **errp) 5846 { 5847 X86CPU *cpu = X86_CPU(obj); 5848 CPUX86State *env = &cpu->env; 5849 const uint64_t max = 0xff + 0xf; 5850 uint64_t value; 5851 5852 if (!visit_type_uint64(v, name, &value, errp)) { 5853 return; 5854 } 5855 if (value > max) { 5856 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5857 name ? name : "null", max); 5858 return; 5859 } 5860 5861 env->cpuid_version &= ~0xff00f00; 5862 if (value > 0x0f) { 5863 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5864 } else { 5865 env->cpuid_version |= value << 8; 5866 } 5867 } 5868 5869 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5870 const char *name, void *opaque, 5871 Error **errp) 5872 { 5873 X86CPU *cpu = X86_CPU(obj); 5874 CPUX86State *env = &cpu->env; 5875 uint64_t value; 5876 5877 value = (env->cpuid_version >> 4) & 0xf; 5878 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5879 visit_type_uint64(v, name, &value, errp); 5880 } 5881 5882 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5883 const char *name, void *opaque, 5884 Error **errp) 5885 { 5886 X86CPU *cpu = X86_CPU(obj); 5887 CPUX86State *env = &cpu->env; 5888 const uint64_t max = 0xff; 5889 uint64_t value; 5890 5891 if (!visit_type_uint64(v, name, &value, errp)) { 5892 return; 5893 } 5894 if (value > max) { 5895 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5896 name ? name : "null", max); 5897 return; 5898 } 5899 5900 env->cpuid_version &= ~0xf00f0; 5901 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5902 } 5903 5904 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5905 const char *name, void *opaque, 5906 Error **errp) 5907 { 5908 X86CPU *cpu = X86_CPU(obj); 5909 CPUX86State *env = &cpu->env; 5910 uint64_t value; 5911 5912 value = env->cpuid_version & 0xf; 5913 visit_type_uint64(v, name, &value, errp); 5914 } 5915 5916 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5917 const char *name, void *opaque, 5918 Error **errp) 5919 { 5920 X86CPU *cpu = X86_CPU(obj); 5921 CPUX86State *env = &cpu->env; 5922 const uint64_t max = 0xf; 5923 uint64_t value; 5924 5925 if (!visit_type_uint64(v, name, &value, errp)) { 5926 return; 5927 } 5928 if (value > max) { 5929 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5930 name ? name : "null", max); 5931 return; 5932 } 5933 5934 env->cpuid_version &= ~0xf; 5935 env->cpuid_version |= value & 0xf; 5936 } 5937 5938 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5939 { 5940 X86CPU *cpu = X86_CPU(obj); 5941 CPUX86State *env = &cpu->env; 5942 char *value; 5943 5944 value = g_malloc(CPUID_VENDOR_SZ + 1); 5945 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5946 env->cpuid_vendor3); 5947 return value; 5948 } 5949 5950 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5951 Error **errp) 5952 { 5953 X86CPU *cpu = X86_CPU(obj); 5954 CPUX86State *env = &cpu->env; 5955 int i; 5956 5957 if (strlen(value) != CPUID_VENDOR_SZ) { 5958 error_setg(errp, "value of property 'vendor' must consist of" 5959 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5960 return; 5961 } 5962 5963 env->cpuid_vendor1 = 0; 5964 env->cpuid_vendor2 = 0; 5965 env->cpuid_vendor3 = 0; 5966 for (i = 0; i < 4; i++) { 5967 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5968 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5969 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5970 } 5971 } 5972 5973 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5974 { 5975 X86CPU *cpu = X86_CPU(obj); 5976 CPUX86State *env = &cpu->env; 5977 char *value; 5978 int i; 5979 5980 value = g_malloc(48 + 1); 5981 for (i = 0; i < 48; i++) { 5982 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5983 } 5984 value[48] = '\0'; 5985 return value; 5986 } 5987 5988 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5989 Error **errp) 5990 { 5991 X86CPU *cpu = X86_CPU(obj); 5992 CPUX86State *env = &cpu->env; 5993 int c, len, i; 5994 5995 if (model_id == NULL) { 5996 model_id = ""; 5997 } 5998 len = strlen(model_id); 5999 memset(env->cpuid_model, 0, 48); 6000 for (i = 0; i < 48; i++) { 6001 if (i >= len) { 6002 c = '\0'; 6003 } else { 6004 c = (uint8_t)model_id[i]; 6005 } 6006 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 6007 } 6008 } 6009 6010 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 6011 void *opaque, Error **errp) 6012 { 6013 X86CPU *cpu = X86_CPU(obj); 6014 int64_t value; 6015 6016 value = cpu->env.tsc_khz * 1000; 6017 visit_type_int(v, name, &value, errp); 6018 } 6019 6020 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 6021 void *opaque, Error **errp) 6022 { 6023 X86CPU *cpu = X86_CPU(obj); 6024 const int64_t max = INT64_MAX; 6025 int64_t value; 6026 6027 if (!visit_type_int(v, name, &value, errp)) { 6028 return; 6029 } 6030 if (value < 0 || value > max) { 6031 error_setg(errp, "parameter '%s' can be at most %" PRId64, 6032 name ? name : "null", max); 6033 return; 6034 } 6035 6036 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 6037 } 6038 6039 /* Generic getter for "feature-words" and "filtered-features" properties */ 6040 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 6041 const char *name, void *opaque, 6042 Error **errp) 6043 { 6044 uint64_t *array = (uint64_t *)opaque; 6045 FeatureWord w; 6046 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 6047 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 6048 X86CPUFeatureWordInfoList *list = NULL; 6049 6050 for (w = 0; w < FEATURE_WORDS; w++) { 6051 FeatureWordInfo *wi = &feature_word_info[w]; 6052 /* 6053 * We didn't have MSR features when "feature-words" was 6054 * introduced. Therefore skipped other type entries. 6055 */ 6056 if (wi->type != CPUID_FEATURE_WORD) { 6057 continue; 6058 } 6059 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 6060 qwi->cpuid_input_eax = wi->cpuid.eax; 6061 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 6062 qwi->cpuid_input_ecx = wi->cpuid.ecx; 6063 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 6064 qwi->features = array[w]; 6065 6066 /* List will be in reverse order, but order shouldn't matter */ 6067 list_entries[w].next = list; 6068 list_entries[w].value = &word_infos[w]; 6069 list = &list_entries[w]; 6070 } 6071 6072 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 6073 } 6074 6075 /* Convert all '_' in a feature string option name to '-', to make feature 6076 * name conform to QOM property naming rule, which uses '-' instead of '_'. 6077 */ 6078 static inline void feat2prop(char *s) 6079 { 6080 while ((s = strchr(s, '_'))) { 6081 *s = '-'; 6082 } 6083 } 6084 6085 /* Return the feature property name for a feature flag bit */ 6086 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 6087 { 6088 const char *name; 6089 /* XSAVE components are automatically enabled by other features, 6090 * so return the original feature name instead 6091 */ 6092 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 6093 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 6094 6095 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 6096 x86_ext_save_areas[comp].bits) { 6097 w = x86_ext_save_areas[comp].feature; 6098 bitnr = ctz32(x86_ext_save_areas[comp].bits); 6099 } 6100 } 6101 6102 assert(bitnr < 64); 6103 assert(w < FEATURE_WORDS); 6104 name = feature_word_info[w].feat_names[bitnr]; 6105 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 6106 return name; 6107 } 6108 6109 /* Compatibility hack to maintain legacy +-feat semantic, 6110 * where +-feat overwrites any feature set by 6111 * feat=on|feat even if the later is parsed after +-feat 6112 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 6113 */ 6114 static GList *plus_features, *minus_features; 6115 6116 static gint compare_string(gconstpointer a, gconstpointer b) 6117 { 6118 return g_strcmp0(a, b); 6119 } 6120 6121 /* Parse "+feature,-feature,feature=foo" CPU feature string 6122 */ 6123 static void x86_cpu_parse_featurestr(const char *typename, char *features, 6124 Error **errp) 6125 { 6126 char *featurestr; /* Single 'key=value" string being parsed */ 6127 static bool cpu_globals_initialized; 6128 bool ambiguous = false; 6129 6130 if (cpu_globals_initialized) { 6131 return; 6132 } 6133 cpu_globals_initialized = true; 6134 6135 if (!features) { 6136 return; 6137 } 6138 6139 for (featurestr = strtok(features, ","); 6140 featurestr; 6141 featurestr = strtok(NULL, ",")) { 6142 const char *name; 6143 const char *val = NULL; 6144 char *eq = NULL; 6145 char num[32]; 6146 GlobalProperty *prop; 6147 6148 /* Compatibility syntax: */ 6149 if (featurestr[0] == '+') { 6150 plus_features = g_list_append(plus_features, 6151 g_strdup(featurestr + 1)); 6152 continue; 6153 } else if (featurestr[0] == '-') { 6154 minus_features = g_list_append(minus_features, 6155 g_strdup(featurestr + 1)); 6156 continue; 6157 } 6158 6159 eq = strchr(featurestr, '='); 6160 if (eq) { 6161 *eq++ = 0; 6162 val = eq; 6163 } else { 6164 val = "on"; 6165 } 6166 6167 feat2prop(featurestr); 6168 name = featurestr; 6169 6170 if (g_list_find_custom(plus_features, name, compare_string)) { 6171 warn_report("Ambiguous CPU model string. " 6172 "Don't mix both \"+%s\" and \"%s=%s\"", 6173 name, name, val); 6174 ambiguous = true; 6175 } 6176 if (g_list_find_custom(minus_features, name, compare_string)) { 6177 warn_report("Ambiguous CPU model string. " 6178 "Don't mix both \"-%s\" and \"%s=%s\"", 6179 name, name, val); 6180 ambiguous = true; 6181 } 6182 6183 /* Special case: */ 6184 if (!strcmp(name, "tsc-freq")) { 6185 int ret; 6186 uint64_t tsc_freq; 6187 6188 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 6189 if (ret < 0 || tsc_freq > INT64_MAX) { 6190 error_setg(errp, "bad numerical value %s", val); 6191 return; 6192 } 6193 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 6194 val = num; 6195 name = "tsc-frequency"; 6196 } 6197 6198 prop = g_new0(typeof(*prop), 1); 6199 prop->driver = typename; 6200 prop->property = g_strdup(name); 6201 prop->value = g_strdup(val); 6202 qdev_prop_register_global(prop); 6203 } 6204 6205 if (ambiguous) { 6206 warn_report("Compatibility of ambiguous CPU model " 6207 "strings won't be kept on future QEMU versions"); 6208 } 6209 } 6210 6211 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 6212 6213 /* Build a list with the name of all features on a feature word array */ 6214 static void x86_cpu_list_feature_names(FeatureWordArray features, 6215 strList **list) 6216 { 6217 strList **tail = list; 6218 FeatureWord w; 6219 6220 for (w = 0; w < FEATURE_WORDS; w++) { 6221 uint64_t filtered = features[w]; 6222 int i; 6223 for (i = 0; i < 64; i++) { 6224 if (filtered & (1ULL << i)) { 6225 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 6226 } 6227 } 6228 } 6229 } 6230 6231 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 6232 const char *name, void *opaque, 6233 Error **errp) 6234 { 6235 X86CPU *xc = X86_CPU(obj); 6236 strList *result = NULL; 6237 6238 x86_cpu_list_feature_names(xc->filtered_features, &result); 6239 visit_type_strList(v, "unavailable-features", &result, errp); 6240 } 6241 6242 /* Print all cpuid feature names in featureset 6243 */ 6244 static void listflags(GList *features) 6245 { 6246 size_t len = 0; 6247 GList *tmp; 6248 6249 for (tmp = features; tmp; tmp = tmp->next) { 6250 const char *name = tmp->data; 6251 if ((len + strlen(name) + 1) >= 75) { 6252 qemu_printf("\n"); 6253 len = 0; 6254 } 6255 qemu_printf("%s%s", len == 0 ? " " : " ", name); 6256 len += strlen(name) + 1; 6257 } 6258 qemu_printf("\n"); 6259 } 6260 6261 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 6262 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d) 6263 { 6264 ObjectClass *class_a = (ObjectClass *)a; 6265 ObjectClass *class_b = (ObjectClass *)b; 6266 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 6267 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 6268 int ret; 6269 6270 if (cc_a->ordering != cc_b->ordering) { 6271 ret = cc_a->ordering - cc_b->ordering; 6272 } else { 6273 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 6274 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 6275 ret = strcmp(name_a, name_b); 6276 } 6277 return ret; 6278 } 6279 6280 static GSList *get_sorted_cpu_model_list(void) 6281 { 6282 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 6283 list = g_slist_sort_with_data(list, x86_cpu_list_compare, NULL); 6284 return list; 6285 } 6286 6287 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 6288 { 6289 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 6290 char *r = object_property_get_str(obj, "model-id", &error_abort); 6291 object_unref(obj); 6292 return r; 6293 } 6294 6295 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 6296 { 6297 X86CPUVersion version; 6298 6299 if (!cc->model || !cc->model->is_alias) { 6300 return NULL; 6301 } 6302 version = x86_cpu_model_resolve_version(cc->model); 6303 if (version <= 0) { 6304 return NULL; 6305 } 6306 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 6307 } 6308 6309 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 6310 { 6311 ObjectClass *oc = data; 6312 X86CPUClass *cc = X86_CPU_CLASS(oc); 6313 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6314 g_autofree char *desc = g_strdup(cc->model_description); 6315 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6316 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6317 6318 if (!desc && alias_of) { 6319 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6320 desc = g_strdup("(alias configured by machine type)"); 6321 } else { 6322 desc = g_strdup_printf("(alias of %s)", alias_of); 6323 } 6324 } 6325 if (!desc && cc->model && cc->model->note) { 6326 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6327 } 6328 if (!desc) { 6329 desc = g_strdup(model_id); 6330 } 6331 6332 if (cc->model && cc->model->cpudef->deprecation_note) { 6333 g_autofree char *olddesc = desc; 6334 desc = g_strdup_printf("%s (deprecated)", olddesc); 6335 } 6336 6337 qemu_printf(" %-20s %s\n", name, desc); 6338 } 6339 6340 static gint strcmp_wrap(gconstpointer a, gconstpointer b, gpointer d) 6341 { 6342 return strcmp(a, b); 6343 } 6344 6345 /* list available CPU models and flags */ 6346 static void x86_cpu_list(void) 6347 { 6348 int i, j; 6349 GSList *list; 6350 GList *names = NULL; 6351 6352 qemu_printf("Available CPUs:\n"); 6353 list = get_sorted_cpu_model_list(); 6354 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6355 g_slist_free(list); 6356 6357 names = NULL; 6358 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6359 FeatureWordInfo *fw = &feature_word_info[i]; 6360 for (j = 0; j < 64; j++) { 6361 if (fw->feat_names[j]) { 6362 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6363 } 6364 } 6365 } 6366 6367 names = g_list_sort_with_data(names, strcmp_wrap, NULL); 6368 6369 qemu_printf("\nRecognized CPUID flags:\n"); 6370 listflags(names); 6371 qemu_printf("\n"); 6372 g_list_free(names); 6373 } 6374 6375 #ifndef CONFIG_USER_ONLY 6376 6377 /* Check for missing features that may prevent the CPU class from 6378 * running using the current machine and accelerator. 6379 */ 6380 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6381 strList **list) 6382 { 6383 strList **tail = list; 6384 X86CPU *xc; 6385 Error *err = NULL; 6386 6387 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6388 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6389 return; 6390 } 6391 6392 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6393 6394 x86_cpu_expand_features(xc, &err); 6395 if (err) { 6396 /* Errors at x86_cpu_expand_features should never happen, 6397 * but in case it does, just report the model as not 6398 * runnable at all using the "type" property. 6399 */ 6400 QAPI_LIST_APPEND(tail, g_strdup("type")); 6401 error_free(err); 6402 } 6403 6404 x86_cpu_filter_features(xc, false); 6405 6406 x86_cpu_list_feature_names(xc->filtered_features, tail); 6407 6408 object_unref(OBJECT(xc)); 6409 } 6410 6411 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6412 { 6413 ObjectClass *oc = data; 6414 X86CPUClass *cc = X86_CPU_CLASS(oc); 6415 CpuDefinitionInfoList **cpu_list = user_data; 6416 CpuDefinitionInfo *info; 6417 6418 info = g_malloc0(sizeof(*info)); 6419 info->name = x86_cpu_class_get_model_name(cc); 6420 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6421 info->has_unavailable_features = true; 6422 info->q_typename = g_strdup(object_class_get_name(oc)); 6423 info->migration_safe = cc->migration_safe; 6424 info->has_migration_safe = true; 6425 info->q_static = cc->static_model; 6426 if (cc->model && cc->model->cpudef->deprecation_note) { 6427 info->deprecated = true; 6428 } else { 6429 info->deprecated = false; 6430 } 6431 /* 6432 * Old machine types won't report aliases, so that alias translation 6433 * doesn't break compatibility with previous QEMU versions. 6434 */ 6435 if (default_cpu_version != CPU_VERSION_LEGACY) { 6436 info->alias_of = x86_cpu_class_get_alias_of(cc); 6437 } 6438 6439 QAPI_LIST_PREPEND(*cpu_list, info); 6440 } 6441 6442 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6443 { 6444 CpuDefinitionInfoList *cpu_list = NULL; 6445 GSList *list = get_sorted_cpu_model_list(); 6446 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6447 g_slist_free(list); 6448 return cpu_list; 6449 } 6450 6451 #endif /* !CONFIG_USER_ONLY */ 6452 6453 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6454 { 6455 FeatureWordInfo *wi = &feature_word_info[w]; 6456 uint64_t r = 0; 6457 uint64_t unavail = 0; 6458 6459 if (kvm_enabled()) { 6460 switch (wi->type) { 6461 case CPUID_FEATURE_WORD: 6462 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6463 wi->cpuid.ecx, 6464 wi->cpuid.reg); 6465 break; 6466 case MSR_FEATURE_WORD: 6467 r = kvm_arch_get_supported_msr_feature(kvm_state, 6468 wi->msr.index); 6469 break; 6470 } 6471 } else if (hvf_enabled()) { 6472 if (wi->type != CPUID_FEATURE_WORD) { 6473 return 0; 6474 } 6475 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6476 wi->cpuid.ecx, 6477 wi->cpuid.reg); 6478 } else if (tcg_enabled()) { 6479 r = wi->tcg_features; 6480 } else { 6481 return ~0; 6482 } 6483 6484 switch (w) { 6485 #ifndef TARGET_X86_64 6486 case FEAT_8000_0001_EDX: 6487 /* 6488 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6489 * way for userspace to get out of its 32-bit jail, we can leave 6490 * the LM bit set. 6491 */ 6492 unavail = tcg_enabled() 6493 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6494 : CPUID_EXT2_LM; 6495 break; 6496 #endif 6497 6498 case FEAT_8000_0007_EBX: 6499 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6500 /* Disable AMD machine check architecture for Intel CPU. */ 6501 unavail = ~0; 6502 } 6503 break; 6504 6505 case FEAT_7_0_EBX: 6506 #ifndef CONFIG_USER_ONLY 6507 if (!check_sgx_support()) { 6508 unavail = CPUID_7_0_EBX_SGX; 6509 } 6510 #endif 6511 break; 6512 case FEAT_7_0_ECX: 6513 #ifndef CONFIG_USER_ONLY 6514 if (!check_sgx_support()) { 6515 unavail = CPUID_7_0_ECX_SGX_LC; 6516 } 6517 #endif 6518 break; 6519 6520 default: 6521 break; 6522 } 6523 6524 r &= ~unavail; 6525 if (cpu && cpu->migratable) { 6526 r &= x86_cpu_get_migratable_flags(cpu, w); 6527 } 6528 return r; 6529 } 6530 6531 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6532 uint32_t *eax, uint32_t *ebx, 6533 uint32_t *ecx, uint32_t *edx) 6534 { 6535 if (kvm_enabled()) { 6536 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6537 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6538 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6539 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6540 } else if (hvf_enabled()) { 6541 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6542 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6543 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6544 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6545 } else { 6546 *eax = 0; 6547 *ebx = 0; 6548 *ecx = 0; 6549 *edx = 0; 6550 } 6551 } 6552 6553 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6554 uint32_t *eax, uint32_t *ebx, 6555 uint32_t *ecx, uint32_t *edx) 6556 { 6557 uint32_t level, unused; 6558 6559 /* Only return valid host leaves. */ 6560 switch (func) { 6561 case 2: 6562 case 4: 6563 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6564 break; 6565 case 0x80000005: 6566 case 0x80000006: 6567 case 0x8000001d: 6568 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6569 break; 6570 default: 6571 return; 6572 } 6573 6574 if (func > level) { 6575 *eax = 0; 6576 *ebx = 0; 6577 *ecx = 0; 6578 *edx = 0; 6579 } else { 6580 host_cpuid(func, index, eax, ebx, ecx, edx); 6581 } 6582 } 6583 6584 /* 6585 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6586 */ 6587 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6588 { 6589 PropValue *pv; 6590 for (pv = props; pv->prop; pv++) { 6591 if (!pv->value) { 6592 continue; 6593 } 6594 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6595 &error_abort); 6596 } 6597 } 6598 6599 /* 6600 * Apply properties for the CPU model version specified in model. 6601 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6602 */ 6603 6604 static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) 6605 { 6606 const X86CPUVersionDefinition *vdef; 6607 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6608 6609 if (version == CPU_VERSION_LEGACY) { 6610 return; 6611 } 6612 6613 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6614 PropValue *p; 6615 6616 for (p = vdef->props; p && p->prop; p++) { 6617 object_property_parse(OBJECT(cpu), p->prop, p->value, 6618 &error_abort); 6619 } 6620 6621 if (vdef->version == version) { 6622 break; 6623 } 6624 } 6625 6626 /* 6627 * If we reached the end of the list, version number was invalid 6628 */ 6629 assert(vdef->version == version); 6630 } 6631 6632 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6633 const X86CPUModel *model) 6634 { 6635 const X86CPUVersionDefinition *vdef; 6636 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6637 const CPUCaches *cache_info = model->cpudef->cache_info; 6638 6639 if (version == CPU_VERSION_LEGACY) { 6640 return cache_info; 6641 } 6642 6643 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6644 if (vdef->cache_info) { 6645 cache_info = vdef->cache_info; 6646 } 6647 6648 if (vdef->version == version) { 6649 break; 6650 } 6651 } 6652 6653 assert(vdef->version == version); 6654 return cache_info; 6655 } 6656 6657 /* 6658 * Load data from X86CPUDefinition into a X86CPU object. 6659 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6660 */ 6661 static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) 6662 { 6663 const X86CPUDefinition *def = model->cpudef; 6664 CPUX86State *env = &cpu->env; 6665 FeatureWord w; 6666 6667 /*NOTE: any property set by this function should be returned by 6668 * x86_cpu_static_props(), so static expansion of 6669 * query-cpu-model-expansion is always complete. 6670 */ 6671 6672 /* CPU models only set _minimum_ values for level/xlevel: */ 6673 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6674 &error_abort); 6675 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6676 &error_abort); 6677 6678 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6679 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6680 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6681 &error_abort); 6682 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6683 &error_abort); 6684 for (w = 0; w < FEATURE_WORDS; w++) { 6685 env->features[w] = def->features[w]; 6686 } 6687 6688 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6689 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6690 6691 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6692 6693 /* sysenter isn't supported in compatibility mode on AMD, 6694 * syscall isn't supported in compatibility mode on Intel. 6695 * Normally we advertise the actual CPU vendor, but you can 6696 * override this using the 'vendor' property if you want to use 6697 * KVM's sysenter/syscall emulation in compatibility mode and 6698 * when doing cross vendor migration 6699 */ 6700 6701 /* 6702 * vendor property is set here but then overloaded with the 6703 * host cpu vendor for KVM and HVF. 6704 */ 6705 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6706 6707 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 6708 &error_abort); 6709 6710 x86_cpu_apply_version_props(cpu, model); 6711 6712 /* 6713 * Properties in versioned CPU model are not user specified features. 6714 * We can simply clear env->user_features here since it will be filled later 6715 * in x86_cpu_expand_features() based on plus_features and minus_features. 6716 */ 6717 memset(&env->user_features, 0, sizeof(env->user_features)); 6718 } 6719 6720 static const gchar *x86_gdb_arch_name(CPUState *cs) 6721 { 6722 #ifdef TARGET_X86_64 6723 return "i386:x86-64"; 6724 #else 6725 return "i386"; 6726 #endif 6727 } 6728 6729 static void x86_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 6730 { 6731 const X86CPUModel *model = data; 6732 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6733 CPUClass *cc = CPU_CLASS(oc); 6734 6735 xcc->model = model; 6736 xcc->migration_safe = true; 6737 cc->deprecation_note = model->cpudef->deprecation_note; 6738 } 6739 6740 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6741 { 6742 g_autofree char *typename = x86_cpu_type_name(name); 6743 TypeInfo ti = { 6744 .name = typename, 6745 .parent = TYPE_X86_CPU, 6746 .class_init = x86_cpu_cpudef_class_init, 6747 .class_data = model, 6748 }; 6749 6750 type_register_static(&ti); 6751 } 6752 6753 6754 /* 6755 * register builtin_x86_defs; 6756 * "max", "base" and subclasses ("host") are not registered here. 6757 * See x86_cpu_register_types for all model registrations. 6758 */ 6759 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6760 { 6761 X86CPUModel *m; 6762 const X86CPUVersionDefinition *vdef; 6763 6764 /* AMD aliases are handled at runtime based on CPUID vendor, so 6765 * they shouldn't be set on the CPU model table. 6766 */ 6767 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6768 /* catch mistakes instead of silently truncating model_id when too long */ 6769 assert(def->model_id && strlen(def->model_id) <= 48); 6770 6771 /* Unversioned model: */ 6772 m = g_new0(X86CPUModel, 1); 6773 m->cpudef = def; 6774 m->version = CPU_VERSION_AUTO; 6775 m->is_alias = true; 6776 x86_register_cpu_model_type(def->name, m); 6777 6778 /* Versioned models: */ 6779 6780 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6781 g_autofree char *name = 6782 x86_cpu_versioned_model_name(def, vdef->version); 6783 6784 m = g_new0(X86CPUModel, 1); 6785 m->cpudef = def; 6786 m->version = vdef->version; 6787 m->note = vdef->note; 6788 x86_register_cpu_model_type(name, m); 6789 6790 if (vdef->alias) { 6791 X86CPUModel *am = g_new0(X86CPUModel, 1); 6792 am->cpudef = def; 6793 am->version = vdef->version; 6794 am->is_alias = true; 6795 x86_register_cpu_model_type(vdef->alias, am); 6796 } 6797 } 6798 6799 } 6800 6801 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6802 { 6803 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6804 return 57; /* 57 bits virtual */ 6805 } else { 6806 return 48; /* 48 bits virtual */ 6807 } 6808 } 6809 6810 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6811 uint32_t *eax, uint32_t *ebx, 6812 uint32_t *ecx, uint32_t *edx) 6813 { 6814 X86CPU *cpu = env_archcpu(env); 6815 CPUState *cs = env_cpu(env); 6816 uint32_t limit; 6817 uint32_t signature[3]; 6818 X86CPUTopoInfo *topo_info = &env->topo_info; 6819 uint32_t threads_per_pkg; 6820 6821 threads_per_pkg = x86_threads_per_pkg(topo_info); 6822 6823 /* Calculate & apply limits for different index ranges */ 6824 if (index >= 0xC0000000) { 6825 limit = env->cpuid_xlevel2; 6826 } else if (index >= 0x80000000) { 6827 limit = env->cpuid_xlevel; 6828 } else if (index >= 0x40000000) { 6829 limit = 0x40000001; 6830 } else { 6831 limit = env->cpuid_level; 6832 } 6833 6834 if (index > limit) { 6835 /* Intel documentation states that invalid EAX input will 6836 * return the same information as EAX=cpuid_level 6837 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6838 */ 6839 index = env->cpuid_level; 6840 } 6841 6842 switch(index) { 6843 case 0: 6844 *eax = env->cpuid_level; 6845 *ebx = env->cpuid_vendor1; 6846 *edx = env->cpuid_vendor2; 6847 *ecx = env->cpuid_vendor3; 6848 break; 6849 case 1: 6850 *eax = env->cpuid_version; 6851 *ebx = (cpu->apic_id << 24) | 6852 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6853 *ecx = env->features[FEAT_1_ECX]; 6854 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6855 *ecx |= CPUID_EXT_OSXSAVE; 6856 } 6857 *edx = env->features[FEAT_1_EDX]; 6858 if (threads_per_pkg > 1) { 6859 *ebx |= threads_per_pkg << 16; 6860 } 6861 if (!cpu->enable_pmu) { 6862 *ecx &= ~CPUID_EXT_PDCM; 6863 } 6864 break; 6865 case 2: 6866 /* cache info: needed for Pentium Pro compatibility */ 6867 if (cpu->cache_info_passthrough) { 6868 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6869 break; 6870 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6871 *eax = *ebx = *ecx = *edx = 0; 6872 break; 6873 } 6874 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6875 *ebx = 0; 6876 if (!cpu->enable_l3_cache) { 6877 *ecx = 0; 6878 } else { 6879 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6880 } 6881 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6882 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6883 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6884 break; 6885 case 4: 6886 /* cache info: needed for Core compatibility */ 6887 if (cpu->cache_info_passthrough) { 6888 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6889 /* 6890 * QEMU has its own number of cores/logical cpus, 6891 * set 24..14, 31..26 bit to configured values 6892 */ 6893 if (*eax & 31) { 6894 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6895 6896 *eax &= ~0xFC000000; 6897 *eax |= max_core_ids_in_package(topo_info) << 26; 6898 if (host_vcpus_per_cache > threads_per_pkg) { 6899 *eax &= ~0x3FFC000; 6900 6901 /* Share the cache at package level. */ 6902 *eax |= max_thread_ids_for_cache(topo_info, 6903 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 6904 } 6905 } 6906 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6907 *eax = *ebx = *ecx = *edx = 0; 6908 } else { 6909 *eax = 0; 6910 6911 switch (count) { 6912 case 0: /* L1 dcache info */ 6913 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6914 topo_info, 6915 eax, ebx, ecx, edx); 6916 if (!cpu->l1_cache_per_core) { 6917 *eax &= ~MAKE_64BIT_MASK(14, 12); 6918 } 6919 break; 6920 case 1: /* L1 icache info */ 6921 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6922 topo_info, 6923 eax, ebx, ecx, edx); 6924 if (!cpu->l1_cache_per_core) { 6925 *eax &= ~MAKE_64BIT_MASK(14, 12); 6926 } 6927 break; 6928 case 2: /* L2 cache info */ 6929 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6930 topo_info, 6931 eax, ebx, ecx, edx); 6932 break; 6933 case 3: /* L3 cache info */ 6934 if (cpu->enable_l3_cache) { 6935 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6936 topo_info, 6937 eax, ebx, ecx, edx); 6938 break; 6939 } 6940 /* fall through */ 6941 default: /* end of info */ 6942 *eax = *ebx = *ecx = *edx = 0; 6943 break; 6944 } 6945 } 6946 break; 6947 case 5: 6948 /* MONITOR/MWAIT Leaf */ 6949 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6950 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6951 *ecx = cpu->mwait.ecx; /* flags */ 6952 *edx = cpu->mwait.edx; /* mwait substates */ 6953 break; 6954 case 6: 6955 /* Thermal and Power Leaf */ 6956 *eax = env->features[FEAT_6_EAX]; 6957 *ebx = 0; 6958 *ecx = 0; 6959 *edx = 0; 6960 break; 6961 case 7: 6962 /* Structured Extended Feature Flags Enumeration Leaf */ 6963 if (count == 0) { 6964 /* Maximum ECX value for sub-leaves */ 6965 *eax = env->cpuid_level_func7; 6966 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6967 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6968 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6969 *ecx |= CPUID_7_0_ECX_OSPKE; 6970 } 6971 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6972 } else if (count == 1) { 6973 *eax = env->features[FEAT_7_1_EAX]; 6974 *edx = env->features[FEAT_7_1_EDX]; 6975 *ebx = 0; 6976 *ecx = 0; 6977 } else if (count == 2) { 6978 *edx = env->features[FEAT_7_2_EDX]; 6979 *eax = 0; 6980 *ebx = 0; 6981 *ecx = 0; 6982 } else { 6983 *eax = 0; 6984 *ebx = 0; 6985 *ecx = 0; 6986 *edx = 0; 6987 } 6988 break; 6989 case 9: 6990 /* Direct Cache Access Information Leaf */ 6991 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6992 *ebx = 0; 6993 *ecx = 0; 6994 *edx = 0; 6995 break; 6996 case 0xA: 6997 /* Architectural Performance Monitoring Leaf */ 6998 if (cpu->enable_pmu) { 6999 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 7000 } else { 7001 *eax = 0; 7002 *ebx = 0; 7003 *ecx = 0; 7004 *edx = 0; 7005 } 7006 break; 7007 case 0xB: 7008 /* Extended Topology Enumeration Leaf */ 7009 if (!cpu->enable_cpuid_0xb) { 7010 *eax = *ebx = *ecx = *edx = 0; 7011 break; 7012 } 7013 7014 *ecx = count & 0xff; 7015 *edx = cpu->apic_id; 7016 7017 switch (count) { 7018 case 0: 7019 *eax = apicid_core_offset(topo_info); 7020 *ebx = topo_info->threads_per_core; 7021 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 7022 break; 7023 case 1: 7024 *eax = apicid_pkg_offset(topo_info); 7025 *ebx = threads_per_pkg; 7026 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 7027 break; 7028 default: 7029 *eax = 0; 7030 *ebx = 0; 7031 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 7032 } 7033 7034 assert(!(*eax & ~0x1f)); 7035 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 7036 break; 7037 case 0x1C: 7038 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7039 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 7040 *edx = 0; 7041 } 7042 break; 7043 case 0x1F: 7044 /* V2 Extended Topology Enumeration Leaf */ 7045 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 7046 *eax = *ebx = *ecx = *edx = 0; 7047 break; 7048 } 7049 7050 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 7051 break; 7052 case 0xD: { 7053 /* Processor Extended State */ 7054 *eax = 0; 7055 *ebx = 0; 7056 *ecx = 0; 7057 *edx = 0; 7058 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7059 break; 7060 } 7061 7062 if (count == 0) { 7063 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 7064 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 7065 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 7066 /* 7067 * The initial value of xcr0 and ebx == 0, On host without kvm 7068 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 7069 * even through guest update xcr0, this will crash some legacy guest 7070 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 7071 */ 7072 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 7073 } else if (count == 1) { 7074 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 7075 x86_cpu_xsave_xss_components(cpu); 7076 7077 *eax = env->features[FEAT_XSAVE]; 7078 *ebx = xsave_area_size(xstate, true); 7079 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 7080 *edx = env->features[FEAT_XSAVE_XSS_HI]; 7081 if (kvm_enabled() && cpu->enable_pmu && 7082 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 7083 (*eax & CPUID_XSAVE_XSAVES)) { 7084 *ecx |= XSTATE_ARCH_LBR_MASK; 7085 } else { 7086 *ecx &= ~XSTATE_ARCH_LBR_MASK; 7087 } 7088 } else if (count == 0xf && cpu->enable_pmu 7089 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7090 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 7091 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 7092 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 7093 7094 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 7095 *eax = esa->size; 7096 *ebx = esa->offset; 7097 *ecx = esa->ecx & 7098 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 7099 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 7100 *eax = esa->size; 7101 *ebx = 0; 7102 *ecx = 1; 7103 } 7104 } 7105 break; 7106 } 7107 case 0x12: 7108 #ifndef CONFIG_USER_ONLY 7109 if (!kvm_enabled() || 7110 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 7111 *eax = *ebx = *ecx = *edx = 0; 7112 break; 7113 } 7114 7115 /* 7116 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 7117 * the EPC properties, e.g. confidentiality and integrity, from the 7118 * host's first EPC section, i.e. assume there is one EPC section or 7119 * that all EPC sections have the same security properties. 7120 */ 7121 if (count > 1) { 7122 uint64_t epc_addr, epc_size; 7123 7124 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 7125 *eax = *ebx = *ecx = *edx = 0; 7126 break; 7127 } 7128 host_cpuid(index, 2, eax, ebx, ecx, edx); 7129 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 7130 *ebx = (uint32_t)(epc_addr >> 32); 7131 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 7132 *edx = (uint32_t)(epc_size >> 32); 7133 break; 7134 } 7135 7136 /* 7137 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 7138 * and KVM, i.e. QEMU cannot emulate features to override what KVM 7139 * supports. Features can be further restricted by userspace, but not 7140 * made more permissive. 7141 */ 7142 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 7143 7144 if (count == 0) { 7145 *eax &= env->features[FEAT_SGX_12_0_EAX]; 7146 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 7147 } else { 7148 *eax &= env->features[FEAT_SGX_12_1_EAX]; 7149 *ebx &= 0; /* ebx reserve */ 7150 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 7151 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 7152 7153 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 7154 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 7155 7156 /* Access to PROVISIONKEY requires additional credentials. */ 7157 if ((*eax & (1U << 4)) && 7158 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 7159 *eax &= ~(1U << 4); 7160 } 7161 } 7162 #endif 7163 break; 7164 case 0x14: { 7165 /* Intel Processor Trace Enumeration */ 7166 *eax = 0; 7167 *ebx = 0; 7168 *ecx = 0; 7169 *edx = 0; 7170 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 7171 !kvm_enabled()) { 7172 break; 7173 } 7174 7175 /* 7176 * If these are changed, they should stay in sync with 7177 * x86_cpu_filter_features(). 7178 */ 7179 if (count == 0) { 7180 *eax = INTEL_PT_MAX_SUBLEAF; 7181 *ebx = INTEL_PT_MINIMAL_EBX; 7182 *ecx = INTEL_PT_MINIMAL_ECX; 7183 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 7184 *ecx |= CPUID_14_0_ECX_LIP; 7185 } 7186 } else if (count == 1) { 7187 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 7188 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 7189 } 7190 break; 7191 } 7192 case 0x1D: { 7193 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 7194 *eax = 0; 7195 *ebx = 0; 7196 *ecx = 0; 7197 *edx = 0; 7198 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7199 break; 7200 } 7201 7202 if (count == 0) { 7203 /* Highest numbered palette subleaf */ 7204 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 7205 } else if (count == 1) { 7206 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 7207 (INTEL_AMX_BYTES_PER_TILE << 16); 7208 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 7209 *ecx = INTEL_AMX_TILE_MAX_ROWS; 7210 } 7211 break; 7212 } 7213 case 0x1E: { 7214 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 7215 *eax = 0; 7216 *ebx = 0; 7217 *ecx = 0; 7218 *edx = 0; 7219 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7220 break; 7221 } 7222 7223 if (count == 0) { 7224 /* Highest numbered palette subleaf */ 7225 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 7226 } 7227 break; 7228 } 7229 case 0x24: { 7230 *eax = 0; 7231 *ebx = 0; 7232 *ecx = 0; 7233 *edx = 0; 7234 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 7235 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 7236 } 7237 break; 7238 } 7239 case 0x40000000: 7240 /* 7241 * CPUID code in kvm_arch_init_vcpu() ignores stuff 7242 * set here, but we restrict to TCG none the less. 7243 */ 7244 if (tcg_enabled() && cpu->expose_tcg) { 7245 memcpy(signature, "TCGTCGTCGTCG", 12); 7246 *eax = 0x40000001; 7247 *ebx = signature[0]; 7248 *ecx = signature[1]; 7249 *edx = signature[2]; 7250 } else { 7251 *eax = 0; 7252 *ebx = 0; 7253 *ecx = 0; 7254 *edx = 0; 7255 } 7256 break; 7257 case 0x40000001: 7258 *eax = 0; 7259 *ebx = 0; 7260 *ecx = 0; 7261 *edx = 0; 7262 break; 7263 case 0x80000000: 7264 *eax = env->cpuid_xlevel; 7265 *ebx = env->cpuid_vendor1; 7266 *edx = env->cpuid_vendor2; 7267 *ecx = env->cpuid_vendor3; 7268 break; 7269 case 0x80000001: 7270 *eax = env->cpuid_version; 7271 *ebx = 0; 7272 *ecx = env->features[FEAT_8000_0001_ECX]; 7273 *edx = env->features[FEAT_8000_0001_EDX]; 7274 7275 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 7276 !(env->hflags & HF_LMA_MASK)) { 7277 *edx &= ~CPUID_EXT2_SYSCALL; 7278 } 7279 break; 7280 case 0x80000002: 7281 case 0x80000003: 7282 case 0x80000004: 7283 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 7284 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 7285 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 7286 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 7287 break; 7288 case 0x80000005: 7289 /* cache info (L1 cache) */ 7290 if (cpu->cache_info_passthrough) { 7291 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7292 break; 7293 } 7294 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 7295 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 7296 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 7297 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7298 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7299 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7300 break; 7301 case 0x80000006: 7302 /* cache info (L2 cache) */ 7303 if (cpu->cache_info_passthrough) { 7304 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7305 break; 7306 } 7307 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7308 (L2_DTLB_2M_ENTRIES << 16) | 7309 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7310 (L2_ITLB_2M_ENTRIES); 7311 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7312 (L2_DTLB_4K_ENTRIES << 16) | 7313 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7314 (L2_ITLB_4K_ENTRIES); 7315 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7316 cpu->enable_l3_cache ? 7317 env->cache_info_amd.l3_cache : NULL, 7318 ecx, edx); 7319 break; 7320 case 0x80000007: 7321 *eax = 0; 7322 *ebx = env->features[FEAT_8000_0007_EBX]; 7323 *ecx = 0; 7324 *edx = env->features[FEAT_8000_0007_EDX]; 7325 break; 7326 case 0x80000008: 7327 /* virtual & phys address size in low 2 bytes. */ 7328 *eax = cpu->phys_bits; 7329 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7330 /* 64 bit processor */ 7331 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7332 *eax |= (cpu->guest_phys_bits << 16); 7333 } 7334 *ebx = env->features[FEAT_8000_0008_EBX]; 7335 if (threads_per_pkg > 1) { 7336 /* 7337 * Bits 15:12 is "The number of bits in the initial 7338 * Core::X86::Apic::ApicId[ApicId] value that indicate 7339 * thread ID within a package". 7340 * Bits 7:0 is "The number of threads in the package is NC+1" 7341 */ 7342 *ecx = (apicid_pkg_offset(topo_info) << 12) | 7343 (threads_per_pkg - 1); 7344 } else { 7345 *ecx = 0; 7346 } 7347 *edx = 0; 7348 break; 7349 case 0x8000000A: 7350 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7351 *eax = 0x00000001; /* SVM Revision */ 7352 *ebx = 0x00000010; /* nr of ASIDs */ 7353 *ecx = 0; 7354 *edx = env->features[FEAT_SVM]; /* optional features */ 7355 } else { 7356 *eax = 0; 7357 *ebx = 0; 7358 *ecx = 0; 7359 *edx = 0; 7360 } 7361 break; 7362 case 0x8000001D: 7363 *eax = 0; 7364 if (cpu->cache_info_passthrough) { 7365 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7366 break; 7367 } 7368 switch (count) { 7369 case 0: /* L1 dcache info */ 7370 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7371 topo_info, eax, ebx, ecx, edx); 7372 break; 7373 case 1: /* L1 icache info */ 7374 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7375 topo_info, eax, ebx, ecx, edx); 7376 break; 7377 case 2: /* L2 cache info */ 7378 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7379 topo_info, eax, ebx, ecx, edx); 7380 break; 7381 case 3: /* L3 cache info */ 7382 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7383 topo_info, eax, ebx, ecx, edx); 7384 break; 7385 default: /* end of info */ 7386 *eax = *ebx = *ecx = *edx = 0; 7387 break; 7388 } 7389 if (cpu->amd_topoext_features_only) { 7390 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7391 } 7392 break; 7393 case 0x8000001E: 7394 if (cpu->core_id <= 255) { 7395 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 7396 } else { 7397 *eax = 0; 7398 *ebx = 0; 7399 *ecx = 0; 7400 *edx = 0; 7401 } 7402 break; 7403 case 0x80000022: 7404 *eax = *ebx = *ecx = *edx = 0; 7405 /* AMD Extended Performance Monitoring and Debug */ 7406 if (kvm_enabled() && cpu->enable_pmu && 7407 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7408 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7409 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7410 R_EBX) & 0xf; 7411 } 7412 break; 7413 case 0xC0000000: 7414 *eax = env->cpuid_xlevel2; 7415 *ebx = 0; 7416 *ecx = 0; 7417 *edx = 0; 7418 break; 7419 case 0xC0000001: 7420 /* Support for VIA CPU's CPUID instruction */ 7421 *eax = env->cpuid_version; 7422 *ebx = 0; 7423 *ecx = 0; 7424 *edx = env->features[FEAT_C000_0001_EDX]; 7425 break; 7426 case 0xC0000002: 7427 case 0xC0000003: 7428 case 0xC0000004: 7429 /* Reserved for the future, and now filled with zero */ 7430 *eax = 0; 7431 *ebx = 0; 7432 *ecx = 0; 7433 *edx = 0; 7434 break; 7435 case 0x8000001F: 7436 *eax = *ebx = *ecx = *edx = 0; 7437 if (sev_enabled()) { 7438 *eax = 0x2; 7439 *eax |= sev_es_enabled() ? 0x8 : 0; 7440 *eax |= sev_snp_enabled() ? 0x10 : 0; 7441 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7442 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7443 } 7444 break; 7445 case 0x80000021: 7446 *eax = *ebx = *ecx = *edx = 0; 7447 *eax = env->features[FEAT_8000_0021_EAX]; 7448 *ebx = env->features[FEAT_8000_0021_EBX]; 7449 break; 7450 default: 7451 /* reserved values: zero */ 7452 *eax = 0; 7453 *ebx = 0; 7454 *ecx = 0; 7455 *edx = 0; 7456 break; 7457 } 7458 } 7459 7460 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7461 { 7462 #ifndef CONFIG_USER_ONLY 7463 /* Those default values are defined in Skylake HW */ 7464 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7465 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7466 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7467 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7468 #endif 7469 } 7470 7471 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7472 { 7473 if (!esa->size) { 7474 return false; 7475 } 7476 7477 if (env->features[esa->feature] & esa->bits) { 7478 return true; 7479 } 7480 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7481 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7482 return true; 7483 } 7484 7485 return false; 7486 } 7487 7488 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7489 { 7490 CPUState *cs = CPU(obj); 7491 X86CPU *cpu = X86_CPU(cs); 7492 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7493 CPUX86State *env = &cpu->env; 7494 target_ulong cr4; 7495 uint64_t xcr0; 7496 int i; 7497 7498 if (xcc->parent_phases.hold) { 7499 xcc->parent_phases.hold(obj, type); 7500 } 7501 7502 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7503 7504 if (tcg_enabled()) { 7505 cpu_init_fp_statuses(env); 7506 } 7507 7508 env->old_exception = -1; 7509 7510 /* init to reset state */ 7511 env->int_ctl = 0; 7512 env->hflags2 |= HF2_GIF_MASK; 7513 env->hflags2 |= HF2_VGIF_MASK; 7514 env->hflags &= ~HF_GUEST_MASK; 7515 7516 cpu_x86_update_cr0(env, 0x60000010); 7517 env->a20_mask = ~0x0; 7518 env->smbase = 0x30000; 7519 env->msr_smi_count = 0; 7520 7521 env->idt.limit = 0xffff; 7522 env->gdt.limit = 0xffff; 7523 env->ldt.limit = 0xffff; 7524 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7525 env->tr.limit = 0xffff; 7526 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7527 7528 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7529 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7530 DESC_R_MASK | DESC_A_MASK); 7531 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7532 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7533 DESC_A_MASK); 7534 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7535 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7536 DESC_A_MASK); 7537 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7538 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7539 DESC_A_MASK); 7540 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7541 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7542 DESC_A_MASK); 7543 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7544 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7545 DESC_A_MASK); 7546 7547 env->eip = 0xfff0; 7548 env->regs[R_EDX] = env->cpuid_version; 7549 7550 env->eflags = 0x2; 7551 7552 /* FPU init */ 7553 for (i = 0; i < 8; i++) { 7554 env->fptags[i] = 1; 7555 } 7556 cpu_set_fpuc(env, 0x37f); 7557 7558 env->mxcsr = 0x1f80; 7559 /* All units are in INIT state. */ 7560 env->xstate_bv = 0; 7561 7562 env->pat = 0x0007040600070406ULL; 7563 7564 if (kvm_enabled()) { 7565 /* 7566 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7567 * a new CPU, use 1 instead to force a reset. 7568 */ 7569 if (env->tsc != 0) { 7570 env->tsc = 1; 7571 } 7572 } else { 7573 env->tsc = 0; 7574 } 7575 7576 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7577 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7578 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7579 } 7580 7581 memset(env->dr, 0, sizeof(env->dr)); 7582 env->dr[6] = DR6_FIXED_1; 7583 env->dr[7] = DR7_FIXED_1; 7584 cpu_breakpoint_remove_all(cs, BP_CPU); 7585 cpu_watchpoint_remove_all(cs, BP_CPU); 7586 7587 cr4 = 0; 7588 xcr0 = XSTATE_FP_MASK; 7589 7590 #ifdef CONFIG_USER_ONLY 7591 /* Enable all the features for user-mode. */ 7592 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7593 xcr0 |= XSTATE_SSE_MASK; 7594 } 7595 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7596 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7597 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7598 continue; 7599 } 7600 if (cpuid_has_xsave_feature(env, esa)) { 7601 xcr0 |= 1ull << i; 7602 } 7603 } 7604 7605 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7606 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7607 } 7608 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7609 cr4 |= CR4_FSGSBASE_MASK; 7610 } 7611 #endif 7612 7613 env->xcr0 = xcr0; 7614 cpu_x86_update_cr4(env, cr4); 7615 7616 /* 7617 * SDM 11.11.5 requires: 7618 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7619 * - IA32_MTRR_PHYSMASKn.V = 0 7620 * All other bits are undefined. For simplification, zero it all. 7621 */ 7622 env->mtrr_deftype = 0; 7623 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7624 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7625 7626 env->interrupt_injected = -1; 7627 env->exception_nr = -1; 7628 env->exception_pending = 0; 7629 env->exception_injected = 0; 7630 env->exception_has_payload = false; 7631 env->exception_payload = 0; 7632 env->nmi_injected = false; 7633 env->triple_fault_pending = false; 7634 #if !defined(CONFIG_USER_ONLY) 7635 /* We hard-wire the BSP to the first CPU. */ 7636 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7637 7638 cs->halted = !cpu_is_bsp(cpu); 7639 7640 if (kvm_enabled()) { 7641 kvm_arch_reset_vcpu(cpu); 7642 } 7643 7644 x86_cpu_set_sgxlepubkeyhash(env); 7645 7646 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7647 7648 #endif 7649 } 7650 7651 void x86_cpu_after_reset(X86CPU *cpu) 7652 { 7653 #ifndef CONFIG_USER_ONLY 7654 if (kvm_enabled()) { 7655 kvm_arch_after_reset_vcpu(cpu); 7656 } 7657 7658 if (cpu->apic_state) { 7659 device_cold_reset(cpu->apic_state); 7660 } 7661 #endif 7662 } 7663 7664 static void mce_init(X86CPU *cpu) 7665 { 7666 CPUX86State *cenv = &cpu->env; 7667 unsigned int bank; 7668 7669 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7670 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7671 (CPUID_MCE | CPUID_MCA)) { 7672 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7673 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7674 cenv->mcg_ctl = ~(uint64_t)0; 7675 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7676 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7677 } 7678 } 7679 } 7680 7681 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7682 { 7683 if (*min < value) { 7684 *min = value; 7685 } 7686 } 7687 7688 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7689 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7690 { 7691 CPUX86State *env = &cpu->env; 7692 FeatureWordInfo *fi = &feature_word_info[w]; 7693 uint32_t eax = fi->cpuid.eax; 7694 uint32_t region = eax & 0xF0000000; 7695 7696 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7697 if (!env->features[w]) { 7698 return; 7699 } 7700 7701 switch (region) { 7702 case 0x00000000: 7703 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7704 break; 7705 case 0x80000000: 7706 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7707 break; 7708 case 0xC0000000: 7709 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7710 break; 7711 } 7712 7713 if (eax == 7) { 7714 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7715 fi->cpuid.ecx); 7716 } 7717 } 7718 7719 /* Calculate XSAVE components based on the configured CPU feature flags */ 7720 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7721 { 7722 CPUX86State *env = &cpu->env; 7723 int i; 7724 uint64_t mask; 7725 static bool request_perm; 7726 7727 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7728 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7729 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7730 env->features[FEAT_XSAVE_XSS_LO] = 0; 7731 env->features[FEAT_XSAVE_XSS_HI] = 0; 7732 return; 7733 } 7734 7735 mask = 0; 7736 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7737 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7738 if (cpuid_has_xsave_feature(env, esa)) { 7739 mask |= (1ULL << i); 7740 } 7741 } 7742 7743 /* Only request permission for first vcpu */ 7744 if (kvm_enabled() && !request_perm) { 7745 kvm_request_xsave_components(cpu, mask); 7746 request_perm = true; 7747 } 7748 7749 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7750 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7751 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7752 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7753 } 7754 7755 /***** Steps involved on loading and filtering CPUID data 7756 * 7757 * When initializing and realizing a CPU object, the steps 7758 * involved in setting up CPUID data are: 7759 * 7760 * 1) Loading CPU model definition (X86CPUDefinition). This is 7761 * implemented by x86_cpu_load_model() and should be completely 7762 * transparent, as it is done automatically by instance_init. 7763 * No code should need to look at X86CPUDefinition structs 7764 * outside instance_init. 7765 * 7766 * 2) CPU expansion. This is done by realize before CPUID 7767 * filtering, and will make sure host/accelerator data is 7768 * loaded for CPU models that depend on host capabilities 7769 * (e.g. "host"). Done by x86_cpu_expand_features(). 7770 * 7771 * 3) CPUID filtering. This initializes extra data related to 7772 * CPUID, and checks if the host supports all capabilities 7773 * required by the CPU. Runnability of a CPU model is 7774 * determined at this step. Done by x86_cpu_filter_features(). 7775 * 7776 * Some operations don't require all steps to be performed. 7777 * More precisely: 7778 * 7779 * - CPU instance creation (instance_init) will run only CPU 7780 * model loading. CPU expansion can't run at instance_init-time 7781 * because host/accelerator data may be not available yet. 7782 * - CPU realization will perform both CPU model expansion and CPUID 7783 * filtering, and return an error in case one of them fails. 7784 * - query-cpu-definitions needs to run all 3 steps. It needs 7785 * to run CPUID filtering, as the 'unavailable-features' 7786 * field is set based on the filtering results. 7787 * - The query-cpu-model-expansion QMP command only needs to run 7788 * CPU model loading and CPU expansion. It should not filter 7789 * any CPUID data based on host capabilities. 7790 */ 7791 7792 /* Expand CPU configuration data, based on configured features 7793 * and host/accelerator capabilities when appropriate. 7794 */ 7795 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7796 { 7797 CPUX86State *env = &cpu->env; 7798 FeatureWord w; 7799 int i; 7800 GList *l; 7801 7802 for (l = plus_features; l; l = l->next) { 7803 const char *prop = l->data; 7804 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7805 return; 7806 } 7807 } 7808 7809 for (l = minus_features; l; l = l->next) { 7810 const char *prop = l->data; 7811 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7812 return; 7813 } 7814 } 7815 7816 /*TODO: Now cpu->max_features doesn't overwrite features 7817 * set using QOM properties, and we can convert 7818 * plus_features & minus_features to global properties 7819 * inside x86_cpu_parse_featurestr() too. 7820 */ 7821 if (cpu->max_features) { 7822 for (w = 0; w < FEATURE_WORDS; w++) { 7823 /* Override only features that weren't set explicitly 7824 * by the user. 7825 */ 7826 env->features[w] |= 7827 x86_cpu_get_supported_feature_word(cpu, w) & 7828 ~env->user_features[w] & 7829 ~feature_word_info[w].no_autoenable_flags; 7830 } 7831 7832 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 7833 uint32_t eax, ebx, ecx, edx; 7834 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 7835 env->avx10_version = ebx & 0xff; 7836 } 7837 } 7838 7839 if (x86_threads_per_pkg(&env->topo_info) > 1) { 7840 env->features[FEAT_1_EDX] |= CPUID_HT; 7841 7842 /* 7843 * The Linux kernel checks for the CMPLegacy bit and 7844 * discards multiple thread information if it is set. 7845 * So don't set it here for Intel (and other processors 7846 * following Intel's behavior) to make Linux guests happy. 7847 */ 7848 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 7849 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 7850 } 7851 } 7852 7853 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7854 FeatureDep *d = &feature_dependencies[i]; 7855 if (!(env->features[d->from.index] & d->from.mask)) { 7856 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7857 7858 /* Not an error unless the dependent feature was added explicitly. */ 7859 mark_unavailable_features(cpu, d->to.index, 7860 unavailable_features & env->user_features[d->to.index], 7861 "This feature depends on other features that were not requested"); 7862 7863 env->features[d->to.index] &= ~unavailable_features; 7864 } 7865 } 7866 7867 if (!kvm_enabled() || !cpu->expose_kvm) { 7868 env->features[FEAT_KVM] = 0; 7869 } 7870 7871 x86_cpu_enable_xsave_components(cpu); 7872 7873 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7874 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7875 if (cpu->full_cpuid_auto_level) { 7876 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7877 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7878 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7879 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7880 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7881 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7882 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7883 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7884 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7885 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7886 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7887 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7888 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7889 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7890 7891 /* Intel Processor Trace requires CPUID[0x14] */ 7892 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7893 if (cpu->intel_pt_auto_level) { 7894 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7895 } else if (cpu->env.cpuid_min_level < 0x14) { 7896 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7897 CPUID_7_0_EBX_INTEL_PT, 7898 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7899 } 7900 } 7901 7902 /* 7903 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7904 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7905 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7906 * cpu->vendor_cpuid_only has been unset for compatibility with older 7907 * machine types. 7908 */ 7909 if (x86_has_extended_topo(env->avail_cpu_topo) && 7910 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7911 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7912 } 7913 7914 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 7915 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7916 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 7917 } 7918 7919 /* SVM requires CPUID[0x8000000A] */ 7920 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7921 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7922 } 7923 7924 /* SEV requires CPUID[0x8000001F] */ 7925 if (sev_enabled()) { 7926 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7927 } 7928 7929 if (env->features[FEAT_8000_0021_EAX]) { 7930 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7931 } 7932 7933 /* SGX requires CPUID[0x12] for EPC enumeration */ 7934 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7935 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7936 } 7937 } 7938 7939 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7940 if (env->cpuid_level_func7 == UINT32_MAX) { 7941 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7942 } 7943 if (env->cpuid_level == UINT32_MAX) { 7944 env->cpuid_level = env->cpuid_min_level; 7945 } 7946 if (env->cpuid_xlevel == UINT32_MAX) { 7947 env->cpuid_xlevel = env->cpuid_min_xlevel; 7948 } 7949 if (env->cpuid_xlevel2 == UINT32_MAX) { 7950 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7951 } 7952 7953 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7954 return; 7955 } 7956 } 7957 7958 /* 7959 * Finishes initialization of CPUID data, filters CPU feature 7960 * words based on host availability of each feature. 7961 * 7962 * Returns: true if any flag is not supported by the host, false otherwise. 7963 */ 7964 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7965 { 7966 CPUX86State *env = &cpu->env; 7967 FeatureWord w; 7968 const char *prefix = NULL; 7969 bool have_filtered_features; 7970 7971 uint32_t eax_0, ebx_0, ecx_0, edx_0; 7972 uint32_t eax_1, ebx_1, ecx_1, edx_1; 7973 7974 if (verbose) { 7975 prefix = accel_uses_host_cpuid() 7976 ? "host doesn't support requested feature" 7977 : "TCG doesn't support requested feature"; 7978 } 7979 7980 for (w = 0; w < FEATURE_WORDS; w++) { 7981 uint64_t host_feat = 7982 x86_cpu_get_supported_feature_word(NULL, w); 7983 uint64_t requested_features = env->features[w]; 7984 uint64_t unavailable_features = requested_features & ~host_feat; 7985 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7986 } 7987 7988 /* 7989 * Check that KVM actually allows the processor tracing features that 7990 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7991 */ 7992 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7993 kvm_enabled()) { 7994 x86_cpu_get_supported_cpuid(0x14, 0, 7995 &eax_0, &ebx_0, &ecx_0, &edx_0); 7996 x86_cpu_get_supported_cpuid(0x14, 1, 7997 &eax_1, &ebx_1, &ecx_1, &edx_1); 7998 7999 if (!eax_0 || 8000 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 8001 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 8002 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 8003 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 8004 INTEL_PT_ADDR_RANGES_NUM) || 8005 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 8006 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 8007 ((ecx_0 & CPUID_14_0_ECX_LIP) != 8008 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 8009 /* 8010 * Processor Trace capabilities aren't configurable, so if the 8011 * host can't emulate the capabilities we report on 8012 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 8013 */ 8014 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 8015 } 8016 } 8017 8018 have_filtered_features = x86_cpu_have_filtered_features(cpu); 8019 8020 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 8021 x86_cpu_get_supported_cpuid(0x24, 0, 8022 &eax_0, &ebx_0, &ecx_0, &edx_0); 8023 uint8_t version = ebx_0 & 0xff; 8024 8025 if (version < env->avx10_version) { 8026 if (prefix) { 8027 warn_report("%s: avx10.%d. Adjust to avx10.%d", 8028 prefix, env->avx10_version, version); 8029 } 8030 env->avx10_version = version; 8031 have_filtered_features = true; 8032 } 8033 } else if (env->avx10_version) { 8034 if (prefix) { 8035 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 8036 } 8037 have_filtered_features = true; 8038 } 8039 8040 return have_filtered_features; 8041 } 8042 8043 static void x86_cpu_hyperv_realize(X86CPU *cpu) 8044 { 8045 size_t len; 8046 8047 /* Hyper-V vendor id */ 8048 if (!cpu->hyperv_vendor) { 8049 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 8050 &error_abort); 8051 } 8052 len = strlen(cpu->hyperv_vendor); 8053 if (len > 12) { 8054 warn_report("hv-vendor-id truncated to 12 characters"); 8055 len = 12; 8056 } 8057 memset(cpu->hyperv_vendor_id, 0, 12); 8058 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 8059 8060 /* 'Hv#1' interface identification*/ 8061 cpu->hyperv_interface_id[0] = 0x31237648; 8062 cpu->hyperv_interface_id[1] = 0; 8063 cpu->hyperv_interface_id[2] = 0; 8064 cpu->hyperv_interface_id[3] = 0; 8065 8066 /* Hypervisor implementation limits */ 8067 cpu->hyperv_limits[0] = 64; 8068 cpu->hyperv_limits[1] = 0; 8069 cpu->hyperv_limits[2] = 0; 8070 } 8071 8072 #ifndef CONFIG_USER_ONLY 8073 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 8074 Error **errp) 8075 { 8076 CPUX86State *env = &cpu->env; 8077 CpuTopologyLevel level; 8078 8079 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 8080 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8081 env->cache_info_cpuid4.l1d_cache->share_level = level; 8082 env->cache_info_amd.l1d_cache->share_level = level; 8083 } else { 8084 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8085 env->cache_info_cpuid4.l1d_cache->share_level); 8086 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8087 env->cache_info_amd.l1d_cache->share_level); 8088 } 8089 8090 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 8091 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8092 env->cache_info_cpuid4.l1i_cache->share_level = level; 8093 env->cache_info_amd.l1i_cache->share_level = level; 8094 } else { 8095 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8096 env->cache_info_cpuid4.l1i_cache->share_level); 8097 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8098 env->cache_info_amd.l1i_cache->share_level); 8099 } 8100 8101 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 8102 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8103 env->cache_info_cpuid4.l2_cache->share_level = level; 8104 env->cache_info_amd.l2_cache->share_level = level; 8105 } else { 8106 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8107 env->cache_info_cpuid4.l2_cache->share_level); 8108 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8109 env->cache_info_amd.l2_cache->share_level); 8110 } 8111 8112 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 8113 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8114 env->cache_info_cpuid4.l3_cache->share_level = level; 8115 env->cache_info_amd.l3_cache->share_level = level; 8116 } else { 8117 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8118 env->cache_info_cpuid4.l3_cache->share_level); 8119 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8120 env->cache_info_amd.l3_cache->share_level); 8121 } 8122 8123 if (!machine_check_smp_cache(ms, errp)) { 8124 return false; 8125 } 8126 return true; 8127 } 8128 #endif 8129 8130 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 8131 { 8132 CPUState *cs = CPU(dev); 8133 X86CPU *cpu = X86_CPU(dev); 8134 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8135 CPUX86State *env = &cpu->env; 8136 Error *local_err = NULL; 8137 unsigned requested_lbr_fmt; 8138 8139 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 8140 /* Use pc-relative instructions in system-mode */ 8141 tcg_cflags_set(cs, CF_PCREL); 8142 #endif 8143 8144 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 8145 error_setg(errp, "apic-id property was not initialized properly"); 8146 return; 8147 } 8148 8149 /* 8150 * Process Hyper-V enlightenments. 8151 * Note: this currently has to happen before the expansion of CPU features. 8152 */ 8153 x86_cpu_hyperv_realize(cpu); 8154 8155 x86_cpu_expand_features(cpu, &local_err); 8156 if (local_err) { 8157 goto out; 8158 } 8159 8160 /* 8161 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 8162 * with user-provided setting. 8163 */ 8164 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 8165 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 8166 error_setg(errp, "invalid lbr-fmt"); 8167 return; 8168 } 8169 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 8170 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 8171 } 8172 8173 /* 8174 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 8175 * 3)vPMU LBR format matches that of host setting. 8176 */ 8177 requested_lbr_fmt = 8178 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 8179 if (requested_lbr_fmt && kvm_enabled()) { 8180 uint64_t host_perf_cap = 8181 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 8182 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 8183 8184 if (!cpu->enable_pmu) { 8185 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 8186 return; 8187 } 8188 if (requested_lbr_fmt != host_lbr_fmt) { 8189 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 8190 "the host value (0x%x).", 8191 requested_lbr_fmt, host_lbr_fmt); 8192 return; 8193 } 8194 } 8195 8196 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 8197 if (cpu->enforce_cpuid) { 8198 error_setg(&local_err, 8199 accel_uses_host_cpuid() ? 8200 "Host doesn't support requested features" : 8201 "TCG doesn't support requested features"); 8202 goto out; 8203 } 8204 } 8205 8206 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 8207 * CPUID[1].EDX. 8208 */ 8209 if (IS_AMD_CPU(env)) { 8210 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 8211 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 8212 & CPUID_EXT2_AMD_ALIASES); 8213 } 8214 8215 x86_cpu_set_sgxlepubkeyhash(env); 8216 8217 /* 8218 * note: the call to the framework needs to happen after feature expansion, 8219 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 8220 * These may be set by the accel-specific code, 8221 * and the results are subsequently checked / assumed in this function. 8222 */ 8223 cpu_exec_realizefn(cs, &local_err); 8224 if (local_err != NULL) { 8225 error_propagate(errp, local_err); 8226 return; 8227 } 8228 8229 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 8230 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8231 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 8232 goto out; 8233 } 8234 8235 if (cpu->guest_phys_bits == -1) { 8236 /* 8237 * If it was not set by the user, or by the accelerator via 8238 * cpu_exec_realizefn, clear. 8239 */ 8240 cpu->guest_phys_bits = 0; 8241 } 8242 8243 if (cpu->ucode_rev == 0) { 8244 /* 8245 * The default is the same as KVM's. Note that this check 8246 * needs to happen after the evenual setting of ucode_rev in 8247 * accel-specific code in cpu_exec_realizefn. 8248 */ 8249 if (IS_AMD_CPU(env)) { 8250 cpu->ucode_rev = 0x01000065; 8251 } else { 8252 cpu->ucode_rev = 0x100000000ULL; 8253 } 8254 } 8255 8256 /* 8257 * mwait extended info: needed for Core compatibility 8258 * We always wake on interrupt even if host does not have the capability. 8259 * 8260 * requires the accel-specific code in cpu_exec_realizefn to 8261 * have already acquired the CPUID data into cpu->mwait. 8262 */ 8263 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 8264 8265 /* 8266 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 8267 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8268 * based on inputs (sockets,cores,threads), it is still better to give 8269 * users a warning. 8270 */ 8271 if (IS_AMD_CPU(env) && 8272 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8273 env->topo_info.threads_per_core > 1) { 8274 warn_report_once("This family of AMD CPU doesn't support " 8275 "hyperthreading(%d). Please configure -smp " 8276 "options properly or try enabling topoext " 8277 "feature.", env->topo_info.threads_per_core); 8278 } 8279 8280 /* For 64bit systems think about the number of physical bits to present. 8281 * ideally this should be the same as the host; anything other than matching 8282 * the host can cause incorrect guest behaviour. 8283 * QEMU used to pick the magic value of 40 bits that corresponds to 8284 * consumer AMD devices but nothing else. 8285 * 8286 * Note that this code assumes features expansion has already been done 8287 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 8288 * phys_bits adjustments to match the host have been already done in 8289 * accel-specific code in cpu_exec_realizefn. 8290 */ 8291 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8292 if (cpu->phys_bits && 8293 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 8294 cpu->phys_bits < 32)) { 8295 error_setg(errp, "phys-bits should be between 32 and %u " 8296 " (but is %u)", 8297 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 8298 return; 8299 } 8300 /* 8301 * 0 means it was not explicitly set by the user (or by machine 8302 * compat_props or by the host code in host-cpu.c). 8303 * In this case, the default is the value used by TCG (40). 8304 */ 8305 if (cpu->phys_bits == 0) { 8306 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 8307 } 8308 if (cpu->guest_phys_bits && 8309 (cpu->guest_phys_bits > cpu->phys_bits || 8310 cpu->guest_phys_bits < 32)) { 8311 error_setg(errp, "guest-phys-bits should be between 32 and %u " 8312 " (but is %u)", 8313 cpu->phys_bits, cpu->guest_phys_bits); 8314 return; 8315 } 8316 } else { 8317 /* For 32 bit systems don't use the user set value, but keep 8318 * phys_bits consistent with what we tell the guest. 8319 */ 8320 if (cpu->phys_bits != 0) { 8321 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 8322 return; 8323 } 8324 if (cpu->guest_phys_bits != 0) { 8325 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 8326 return; 8327 } 8328 8329 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 8330 cpu->phys_bits = 36; 8331 } else { 8332 cpu->phys_bits = 32; 8333 } 8334 } 8335 8336 /* Cache information initialization */ 8337 if (!cpu->legacy_cache) { 8338 const CPUCaches *cache_info = 8339 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 8340 8341 if (!xcc->model || !cache_info) { 8342 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8343 error_setg(errp, 8344 "CPU model '%s' doesn't support legacy-cache=off", name); 8345 return; 8346 } 8347 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 8348 *cache_info; 8349 } else { 8350 /* Build legacy cache information */ 8351 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 8352 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 8353 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 8354 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 8355 8356 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 8357 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 8358 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 8359 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 8360 8361 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 8362 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 8363 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 8364 env->cache_info_amd.l3_cache = &legacy_l3_cache; 8365 } 8366 8367 #ifndef CONFIG_USER_ONLY 8368 MachineState *ms = MACHINE(qdev_get_machine()); 8369 MachineClass *mc = MACHINE_GET_CLASS(ms); 8370 8371 if (mc->smp_props.has_caches) { 8372 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 8373 return; 8374 } 8375 } 8376 8377 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 8378 8379 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 8380 x86_cpu_apic_create(cpu, &local_err); 8381 if (local_err != NULL) { 8382 goto out; 8383 } 8384 } 8385 #endif 8386 8387 mce_init(cpu); 8388 8389 x86_cpu_gdb_init(cs); 8390 qemu_init_vcpu(cs); 8391 8392 #ifndef CONFIG_USER_ONLY 8393 x86_cpu_apic_realize(cpu, &local_err); 8394 if (local_err != NULL) { 8395 goto out; 8396 } 8397 #endif /* !CONFIG_USER_ONLY */ 8398 cpu_reset(cs); 8399 8400 xcc->parent_realize(dev, &local_err); 8401 8402 out: 8403 if (local_err != NULL) { 8404 error_propagate(errp, local_err); 8405 return; 8406 } 8407 } 8408 8409 static void x86_cpu_unrealizefn(DeviceState *dev) 8410 { 8411 X86CPU *cpu = X86_CPU(dev); 8412 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8413 8414 #ifndef CONFIG_USER_ONLY 8415 cpu_remove_sync(CPU(dev)); 8416 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8417 #endif 8418 8419 if (cpu->apic_state) { 8420 object_unparent(OBJECT(cpu->apic_state)); 8421 cpu->apic_state = NULL; 8422 } 8423 8424 xcc->parent_unrealize(dev); 8425 } 8426 8427 typedef struct BitProperty { 8428 FeatureWord w; 8429 uint64_t mask; 8430 } BitProperty; 8431 8432 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8433 void *opaque, Error **errp) 8434 { 8435 X86CPU *cpu = X86_CPU(obj); 8436 BitProperty *fp = opaque; 8437 uint64_t f = cpu->env.features[fp->w]; 8438 bool value = (f & fp->mask) == fp->mask; 8439 visit_type_bool(v, name, &value, errp); 8440 } 8441 8442 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8443 void *opaque, Error **errp) 8444 { 8445 DeviceState *dev = DEVICE(obj); 8446 X86CPU *cpu = X86_CPU(obj); 8447 BitProperty *fp = opaque; 8448 bool value; 8449 8450 if (dev->realized) { 8451 qdev_prop_set_after_realize(dev, name, errp); 8452 return; 8453 } 8454 8455 if (!visit_type_bool(v, name, &value, errp)) { 8456 return; 8457 } 8458 8459 if (value) { 8460 cpu->env.features[fp->w] |= fp->mask; 8461 } else { 8462 cpu->env.features[fp->w] &= ~fp->mask; 8463 } 8464 cpu->env.user_features[fp->w] |= fp->mask; 8465 } 8466 8467 /* Register a boolean property to get/set a single bit in a uint32_t field. 8468 * 8469 * The same property name can be registered multiple times to make it affect 8470 * multiple bits in the same FeatureWord. In that case, the getter will return 8471 * true only if all bits are set. 8472 */ 8473 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8474 const char *prop_name, 8475 FeatureWord w, 8476 int bitnr) 8477 { 8478 ObjectClass *oc = OBJECT_CLASS(xcc); 8479 BitProperty *fp; 8480 ObjectProperty *op; 8481 uint64_t mask = (1ULL << bitnr); 8482 8483 op = object_class_property_find(oc, prop_name); 8484 if (op) { 8485 fp = op->opaque; 8486 assert(fp->w == w); 8487 fp->mask |= mask; 8488 } else { 8489 fp = g_new0(BitProperty, 1); 8490 fp->w = w; 8491 fp->mask = mask; 8492 object_class_property_add(oc, prop_name, "bool", 8493 x86_cpu_get_bit_prop, 8494 x86_cpu_set_bit_prop, 8495 NULL, fp); 8496 } 8497 } 8498 8499 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8500 FeatureWord w, 8501 int bitnr) 8502 { 8503 FeatureWordInfo *fi = &feature_word_info[w]; 8504 const char *name = fi->feat_names[bitnr]; 8505 8506 if (!name) { 8507 return; 8508 } 8509 8510 /* Property names should use "-" instead of "_". 8511 * Old names containing underscores are registered as aliases 8512 * using object_property_add_alias() 8513 */ 8514 assert(!strchr(name, '_')); 8515 /* aliases don't use "|" delimiters anymore, they are registered 8516 * manually using object_property_add_alias() */ 8517 assert(!strchr(name, '|')); 8518 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8519 } 8520 8521 static void x86_cpu_post_initfn(Object *obj) 8522 { 8523 static bool first = true; 8524 uint64_t supported_xcr0; 8525 int i; 8526 8527 if (first) { 8528 first = false; 8529 8530 supported_xcr0 = 8531 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 8532 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 8533 8534 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 8535 ExtSaveArea *esa = &x86_ext_save_areas[i]; 8536 8537 if (!(supported_xcr0 & (1 << i))) { 8538 esa->size = 0; 8539 } 8540 } 8541 } 8542 8543 accel_cpu_instance_init(CPU(obj)); 8544 } 8545 8546 static void x86_cpu_init_default_topo(X86CPU *cpu) 8547 { 8548 CPUX86State *env = &cpu->env; 8549 8550 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 8551 8552 /* thread, core and socket levels are set by default. */ 8553 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 8554 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 8555 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 8556 } 8557 8558 static void x86_cpu_initfn(Object *obj) 8559 { 8560 X86CPU *cpu = X86_CPU(obj); 8561 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8562 CPUX86State *env = &cpu->env; 8563 8564 x86_cpu_init_default_topo(cpu); 8565 8566 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8567 x86_cpu_get_feature_words, 8568 NULL, NULL, (void *)env->features); 8569 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8570 x86_cpu_get_feature_words, 8571 NULL, NULL, (void *)cpu->filtered_features); 8572 8573 object_property_add_alias(obj, "sse3", obj, "pni"); 8574 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8575 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8576 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8577 object_property_add_alias(obj, "xd", obj, "nx"); 8578 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8579 object_property_add_alias(obj, "i64", obj, "lm"); 8580 8581 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8582 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8583 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8584 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8585 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8586 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8587 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8588 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8589 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8590 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8591 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8592 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8593 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8594 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8595 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8596 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8597 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8598 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8599 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8600 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8601 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8602 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8603 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8604 8605 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8606 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8607 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8608 8609 if (xcc->model) { 8610 x86_cpu_load_model(cpu, xcc->model); 8611 } 8612 } 8613 8614 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8615 { 8616 X86CPU *cpu = X86_CPU(cs); 8617 8618 return cpu->apic_id; 8619 } 8620 8621 #if !defined(CONFIG_USER_ONLY) 8622 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8623 { 8624 X86CPU *cpu = X86_CPU(cs); 8625 8626 return cpu->env.cr[0] & CR0_PG_MASK; 8627 } 8628 #endif /* !CONFIG_USER_ONLY */ 8629 8630 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8631 { 8632 X86CPU *cpu = X86_CPU(cs); 8633 8634 cpu->env.eip = value; 8635 } 8636 8637 static vaddr x86_cpu_get_pc(CPUState *cs) 8638 { 8639 X86CPU *cpu = X86_CPU(cs); 8640 8641 /* Match cpu_get_tb_cpu_state. */ 8642 return cpu->env.eip + cpu->env.segs[R_CS].base; 8643 } 8644 8645 #if !defined(CONFIG_USER_ONLY) 8646 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8647 { 8648 X86CPU *cpu = X86_CPU(cs); 8649 CPUX86State *env = &cpu->env; 8650 8651 if (interrupt_request & CPU_INTERRUPT_POLL) { 8652 return CPU_INTERRUPT_POLL; 8653 } 8654 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8655 return CPU_INTERRUPT_SIPI; 8656 } 8657 8658 if (env->hflags2 & HF2_GIF_MASK) { 8659 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8660 !(env->hflags & HF_SMM_MASK)) { 8661 return CPU_INTERRUPT_SMI; 8662 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8663 !(env->hflags2 & HF2_NMI_MASK)) { 8664 return CPU_INTERRUPT_NMI; 8665 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8666 return CPU_INTERRUPT_MCE; 8667 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8668 (((env->hflags2 & HF2_VINTR_MASK) && 8669 (env->hflags2 & HF2_HIF_MASK)) || 8670 (!(env->hflags2 & HF2_VINTR_MASK) && 8671 (env->eflags & IF_MASK && 8672 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8673 return CPU_INTERRUPT_HARD; 8674 } else if (env->hflags2 & HF2_VGIF_MASK) { 8675 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8676 (env->eflags & IF_MASK) && 8677 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8678 return CPU_INTERRUPT_VIRQ; 8679 } 8680 } 8681 } 8682 8683 return 0; 8684 } 8685 8686 static bool x86_cpu_has_work(CPUState *cs) 8687 { 8688 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8689 } 8690 #endif /* !CONFIG_USER_ONLY */ 8691 8692 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8693 { 8694 X86CPU *cpu = X86_CPU(cs); 8695 CPUX86State *env = &cpu->env; 8696 8697 info->endian = BFD_ENDIAN_LITTLE; 8698 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8699 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8700 : bfd_mach_i386_i8086); 8701 8702 info->cap_arch = CS_ARCH_X86; 8703 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8704 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8705 : CS_MODE_16); 8706 info->cap_insn_unit = 1; 8707 info->cap_insn_split = 8; 8708 } 8709 8710 void x86_update_hflags(CPUX86State *env) 8711 { 8712 uint32_t hflags; 8713 #define HFLAG_COPY_MASK \ 8714 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8715 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8716 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8717 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8718 8719 hflags = env->hflags & HFLAG_COPY_MASK; 8720 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8721 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8722 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8723 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8724 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8725 8726 if (env->cr[4] & CR4_OSFXSR_MASK) { 8727 hflags |= HF_OSFXSR_MASK; 8728 } 8729 8730 if (env->efer & MSR_EFER_LMA) { 8731 hflags |= HF_LMA_MASK; 8732 } 8733 8734 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8735 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8736 } else { 8737 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8738 (DESC_B_SHIFT - HF_CS32_SHIFT); 8739 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8740 (DESC_B_SHIFT - HF_SS32_SHIFT); 8741 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8742 !(hflags & HF_CS32_MASK)) { 8743 hflags |= HF_ADDSEG_MASK; 8744 } else { 8745 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8746 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8747 } 8748 } 8749 env->hflags = hflags; 8750 } 8751 8752 static const Property x86_cpu_properties[] = { 8753 #ifdef CONFIG_USER_ONLY 8754 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8755 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8756 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8757 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8758 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8759 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8760 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8761 #else 8762 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8763 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8764 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8765 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8766 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8767 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8768 #endif 8769 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8770 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8771 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8772 8773 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8774 HYPERV_SPINLOCK_NEVER_NOTIFY), 8775 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8776 HYPERV_FEAT_RELAXED, 0), 8777 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8778 HYPERV_FEAT_VAPIC, 0), 8779 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8780 HYPERV_FEAT_TIME, 0), 8781 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8782 HYPERV_FEAT_CRASH, 0), 8783 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8784 HYPERV_FEAT_RESET, 0), 8785 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8786 HYPERV_FEAT_VPINDEX, 0), 8787 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8788 HYPERV_FEAT_RUNTIME, 0), 8789 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8790 HYPERV_FEAT_SYNIC, 0), 8791 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8792 HYPERV_FEAT_STIMER, 0), 8793 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8794 HYPERV_FEAT_FREQUENCIES, 0), 8795 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8796 HYPERV_FEAT_REENLIGHTENMENT, 0), 8797 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8798 HYPERV_FEAT_TLBFLUSH, 0), 8799 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8800 HYPERV_FEAT_EVMCS, 0), 8801 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8802 HYPERV_FEAT_IPI, 0), 8803 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8804 HYPERV_FEAT_STIMER_DIRECT, 0), 8805 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8806 HYPERV_FEAT_AVIC, 0), 8807 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8808 HYPERV_FEAT_MSR_BITMAP, 0), 8809 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8810 HYPERV_FEAT_XMM_INPUT, 0), 8811 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8812 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8813 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8814 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8815 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8816 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8817 #ifdef CONFIG_SYNDBG 8818 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8819 HYPERV_FEAT_SYNDBG, 0), 8820 #endif 8821 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8822 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8823 8824 /* WS2008R2 identify by default */ 8825 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8826 0x3839), 8827 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8828 0x000A), 8829 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8830 0x0000), 8831 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8832 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8833 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8834 8835 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8836 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8837 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8838 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8839 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8840 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8841 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8842 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8843 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8844 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8845 UINT32_MAX), 8846 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8847 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8848 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8849 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8850 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8851 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8852 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 8853 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8854 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8855 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8856 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8857 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8858 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8859 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8860 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8861 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8862 false), 8863 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8864 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8865 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8866 true), 8867 /* 8868 * lecacy_cache defaults to true unless the CPU model provides its 8869 * own cache information (see x86_cpu_load_def()). 8870 */ 8871 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8872 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8873 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8874 8875 /* 8876 * From "Requirements for Implementing the Microsoft 8877 * Hypervisor Interface": 8878 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8879 * 8880 * "Starting with Windows Server 2012 and Windows 8, if 8881 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8882 * the hypervisor imposes no specific limit to the number of VPs. 8883 * In this case, Windows Server 2012 guest VMs may use more than 8884 * 64 VPs, up to the maximum supported number of processors applicable 8885 * to the specific Windows version being used." 8886 */ 8887 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8888 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8889 false), 8890 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8891 true), 8892 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8893 }; 8894 8895 #ifndef CONFIG_USER_ONLY 8896 #include "hw/core/sysemu-cpu-ops.h" 8897 8898 static const struct SysemuCPUOps i386_sysemu_ops = { 8899 .has_work = x86_cpu_has_work, 8900 .get_memory_mapping = x86_cpu_get_memory_mapping, 8901 .get_paging_enabled = x86_cpu_get_paging_enabled, 8902 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8903 .asidx_from_attrs = x86_asidx_from_attrs, 8904 .get_crash_info = x86_cpu_get_crash_info, 8905 .write_elf32_note = x86_cpu_write_elf32_note, 8906 .write_elf64_note = x86_cpu_write_elf64_note, 8907 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8908 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8909 .legacy_vmsd = &vmstate_x86_cpu, 8910 }; 8911 #endif 8912 8913 static void x86_cpu_common_class_init(ObjectClass *oc, const void *data) 8914 { 8915 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8916 CPUClass *cc = CPU_CLASS(oc); 8917 DeviceClass *dc = DEVICE_CLASS(oc); 8918 ResettableClass *rc = RESETTABLE_CLASS(oc); 8919 FeatureWord w; 8920 8921 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8922 &xcc->parent_realize); 8923 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8924 &xcc->parent_unrealize); 8925 device_class_set_props(dc, x86_cpu_properties); 8926 8927 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8928 &xcc->parent_phases); 8929 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8930 8931 cc->class_by_name = x86_cpu_class_by_name; 8932 cc->list_cpus = x86_cpu_list; 8933 cc->parse_features = x86_cpu_parse_featurestr; 8934 cc->dump_state = x86_cpu_dump_state; 8935 cc->set_pc = x86_cpu_set_pc; 8936 cc->get_pc = x86_cpu_get_pc; 8937 cc->gdb_read_register = x86_cpu_gdb_read_register; 8938 cc->gdb_write_register = x86_cpu_gdb_write_register; 8939 cc->get_arch_id = x86_cpu_get_arch_id; 8940 8941 #ifndef CONFIG_USER_ONLY 8942 cc->sysemu_ops = &i386_sysemu_ops; 8943 #endif /* !CONFIG_USER_ONLY */ 8944 #ifdef CONFIG_TCG 8945 cc->tcg_ops = &x86_tcg_ops; 8946 #endif /* CONFIG_TCG */ 8947 8948 cc->gdb_arch_name = x86_gdb_arch_name; 8949 #ifdef TARGET_X86_64 8950 cc->gdb_core_xml_file = "i386-64bit.xml"; 8951 #else 8952 cc->gdb_core_xml_file = "i386-32bit.xml"; 8953 #endif 8954 cc->disas_set_info = x86_disas_set_info; 8955 8956 dc->user_creatable = true; 8957 8958 object_class_property_add(oc, "family", "int", 8959 x86_cpuid_version_get_family, 8960 x86_cpuid_version_set_family, NULL, NULL); 8961 object_class_property_add(oc, "model", "int", 8962 x86_cpuid_version_get_model, 8963 x86_cpuid_version_set_model, NULL, NULL); 8964 object_class_property_add(oc, "stepping", "int", 8965 x86_cpuid_version_get_stepping, 8966 x86_cpuid_version_set_stepping, NULL, NULL); 8967 object_class_property_add_str(oc, "vendor", 8968 x86_cpuid_get_vendor, 8969 x86_cpuid_set_vendor); 8970 object_class_property_add_str(oc, "model-id", 8971 x86_cpuid_get_model_id, 8972 x86_cpuid_set_model_id); 8973 object_class_property_add(oc, "tsc-frequency", "int", 8974 x86_cpuid_get_tsc_freq, 8975 x86_cpuid_set_tsc_freq, NULL, NULL); 8976 /* 8977 * The "unavailable-features" property has the same semantics as 8978 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8979 * QMP command: they list the features that would have prevented the 8980 * CPU from running if the "enforce" flag was set. 8981 */ 8982 object_class_property_add(oc, "unavailable-features", "strList", 8983 x86_cpu_get_unavailable_features, 8984 NULL, NULL, NULL); 8985 8986 #if !defined(CONFIG_USER_ONLY) 8987 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8988 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8989 #endif 8990 8991 for (w = 0; w < FEATURE_WORDS; w++) { 8992 int bitnr; 8993 for (bitnr = 0; bitnr < 64; bitnr++) { 8994 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8995 } 8996 } 8997 } 8998 8999 static const TypeInfo x86_cpu_type_info = { 9000 .name = TYPE_X86_CPU, 9001 .parent = TYPE_CPU, 9002 .instance_size = sizeof(X86CPU), 9003 .instance_align = __alignof(X86CPU), 9004 .instance_init = x86_cpu_initfn, 9005 .instance_post_init = x86_cpu_post_initfn, 9006 9007 .abstract = true, 9008 .class_size = sizeof(X86CPUClass), 9009 .class_init = x86_cpu_common_class_init, 9010 }; 9011 9012 /* "base" CPU model, used by query-cpu-model-expansion */ 9013 static void x86_cpu_base_class_init(ObjectClass *oc, const void *data) 9014 { 9015 X86CPUClass *xcc = X86_CPU_CLASS(oc); 9016 9017 xcc->static_model = true; 9018 xcc->migration_safe = true; 9019 xcc->model_description = "base CPU model type with no features enabled"; 9020 xcc->ordering = 8; 9021 } 9022 9023 static const TypeInfo x86_base_cpu_type_info = { 9024 .name = X86_CPU_TYPE_NAME("base"), 9025 .parent = TYPE_X86_CPU, 9026 .class_init = x86_cpu_base_class_init, 9027 }; 9028 9029 static void x86_cpu_register_types(void) 9030 { 9031 int i; 9032 9033 type_register_static(&x86_cpu_type_info); 9034 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 9035 x86_register_cpudef_types(&builtin_x86_defs[i]); 9036 } 9037 type_register_static(&max_x86_cpu_type_info); 9038 type_register_static(&x86_base_cpu_type_info); 9039 } 9040 9041 type_init(x86_cpu_register_types) 9042