1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #include "exec/watchpoint.h" 39 #ifndef CONFIG_USER_ONLY 40 #include "system/reset.h" 41 #include "qapi/qapi-commands-machine-target.h" 42 #include "system/address-spaces.h" 43 #include "hw/boards.h" 44 #include "hw/i386/sgx-epc.h" 45 #endif 46 #include "tcg/tcg-cpu.h" 47 48 #include "disas/capstone.h" 49 #include "cpu-internal.h" 50 51 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 52 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 53 uint32_t *eax, uint32_t *ebx, 54 uint32_t *ecx, uint32_t *edx); 55 56 /* Helpers for building CPUID[2] descriptors: */ 57 58 struct CPUID2CacheDescriptorInfo { 59 enum CacheType type; 60 int level; 61 int size; 62 int line_size; 63 int associativity; 64 }; 65 66 /* 67 * Known CPUID 2 cache descriptors. 68 * From Intel SDM Volume 2A, CPUID instruction 69 */ 70 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 71 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 72 .associativity = 4, .line_size = 32, }, 73 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 76 .associativity = 4, .line_size = 64, }, 77 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 78 .associativity = 2, .line_size = 32, }, 79 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 80 .associativity = 4, .line_size = 32, }, 81 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 82 .associativity = 4, .line_size = 64, }, 83 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 84 .associativity = 6, .line_size = 64, }, 85 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 86 .associativity = 2, .line_size = 64, }, 87 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 88 .associativity = 8, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x22, 0x23 are not included 91 */ 92 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 93 .associativity = 16, .line_size = 64, }, 94 /* lines per sector is not supported cpuid2_cache_descriptor(), 95 * so descriptors 0x25, 0x20 are not included 96 */ 97 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 98 .associativity = 8, .line_size = 64, }, 99 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 100 .associativity = 8, .line_size = 64, }, 101 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 106 .associativity = 4, .line_size = 32, }, 107 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 108 .associativity = 4, .line_size = 32, }, 109 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 110 .associativity = 4, .line_size = 32, }, 111 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 112 .associativity = 4, .line_size = 64, }, 113 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 114 .associativity = 8, .line_size = 64, }, 115 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 116 .associativity = 12, .line_size = 64, }, 117 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 118 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 119 .associativity = 12, .line_size = 64, }, 120 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 121 .associativity = 16, .line_size = 64, }, 122 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 123 .associativity = 12, .line_size = 64, }, 124 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 125 .associativity = 16, .line_size = 64, }, 126 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 127 .associativity = 24, .line_size = 64, }, 128 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 129 .associativity = 8, .line_size = 64, }, 130 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 131 .associativity = 4, .line_size = 64, }, 132 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 133 .associativity = 4, .line_size = 64, }, 134 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 135 .associativity = 4, .line_size = 64, }, 136 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 137 .associativity = 4, .line_size = 64, }, 138 /* lines per sector is not supported cpuid2_cache_descriptor(), 139 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 140 */ 141 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 142 .associativity = 8, .line_size = 64, }, 143 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 2, .line_size = 64, }, 145 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 146 .associativity = 8, .line_size = 64, }, 147 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 150 .associativity = 8, .line_size = 32, }, 151 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 152 .associativity = 8, .line_size = 32, }, 153 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 154 .associativity = 8, .line_size = 32, }, 155 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 156 .associativity = 4, .line_size = 64, }, 157 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 158 .associativity = 8, .line_size = 64, }, 159 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 160 .associativity = 4, .line_size = 64, }, 161 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 162 .associativity = 4, .line_size = 64, }, 163 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 164 .associativity = 4, .line_size = 64, }, 165 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 166 .associativity = 8, .line_size = 64, }, 167 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 168 .associativity = 8, .line_size = 64, }, 169 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 170 .associativity = 8, .line_size = 64, }, 171 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 172 .associativity = 12, .line_size = 64, }, 173 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 174 .associativity = 12, .line_size = 64, }, 175 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 176 .associativity = 12, .line_size = 64, }, 177 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 178 .associativity = 16, .line_size = 64, }, 179 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 180 .associativity = 16, .line_size = 64, }, 181 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 182 .associativity = 16, .line_size = 64, }, 183 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 184 .associativity = 24, .line_size = 64, }, 185 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 186 .associativity = 24, .line_size = 64, }, 187 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 188 .associativity = 24, .line_size = 64, }, 189 }; 190 191 /* 192 * "CPUID leaf 2 does not report cache descriptor information, 193 * use CPUID leaf 4 to query cache parameters" 194 */ 195 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 196 197 /* 198 * Return a CPUID 2 cache descriptor for a given cache. 199 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 200 */ 201 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 202 { 203 int i; 204 205 assert(cache->size > 0); 206 assert(cache->level > 0); 207 assert(cache->line_size > 0); 208 assert(cache->associativity > 0); 209 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 210 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 211 if (d->level == cache->level && d->type == cache->type && 212 d->size == cache->size && d->line_size == cache->line_size && 213 d->associativity == cache->associativity) { 214 return i; 215 } 216 } 217 218 return CACHE_DESCRIPTOR_UNAVAILABLE; 219 } 220 221 /* CPUID Leaf 4 constants: */ 222 223 /* EAX: */ 224 #define CACHE_TYPE_D 1 225 #define CACHE_TYPE_I 2 226 #define CACHE_TYPE_UNIFIED 3 227 228 #define CACHE_LEVEL(l) (l << 5) 229 230 #define CACHE_SELF_INIT_LEVEL (1 << 8) 231 232 /* EDX: */ 233 #define CACHE_NO_INVD_SHARING (1 << 0) 234 #define CACHE_INCLUSIVE (1 << 1) 235 #define CACHE_COMPLEX_IDX (1 << 2) 236 237 /* Encode CacheType for CPUID[4].EAX */ 238 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 239 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 240 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 241 0 /* Invalid value */) 242 243 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 244 enum CpuTopologyLevel share_level) 245 { 246 uint32_t num_ids = 0; 247 248 switch (share_level) { 249 case CPU_TOPOLOGY_LEVEL_CORE: 250 num_ids = 1 << apicid_core_offset(topo_info); 251 break; 252 case CPU_TOPOLOGY_LEVEL_MODULE: 253 num_ids = 1 << apicid_module_offset(topo_info); 254 break; 255 case CPU_TOPOLOGY_LEVEL_DIE: 256 num_ids = 1 << apicid_die_offset(topo_info); 257 break; 258 case CPU_TOPOLOGY_LEVEL_SOCKET: 259 num_ids = 1 << apicid_pkg_offset(topo_info); 260 break; 261 default: 262 /* 263 * Currently there is no use case for THREAD, so use 264 * assert directly to facilitate debugging. 265 */ 266 g_assert_not_reached(); 267 } 268 269 return num_ids - 1; 270 } 271 272 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 273 { 274 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 275 apicid_core_offset(topo_info)); 276 return num_cores - 1; 277 } 278 279 /* Encode cache info for CPUID[4] */ 280 static void encode_cache_cpuid4(CPUCacheInfo *cache, 281 X86CPUTopoInfo *topo_info, 282 uint32_t *eax, uint32_t *ebx, 283 uint32_t *ecx, uint32_t *edx) 284 { 285 assert(cache->size == cache->line_size * cache->associativity * 286 cache->partitions * cache->sets); 287 288 *eax = CACHE_TYPE(cache->type) | 289 CACHE_LEVEL(cache->level) | 290 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 291 (max_core_ids_in_package(topo_info) << 26) | 292 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 293 294 assert(cache->line_size > 0); 295 assert(cache->partitions > 0); 296 assert(cache->associativity > 0); 297 /* We don't implement fully-associative caches */ 298 assert(cache->associativity < cache->sets); 299 *ebx = (cache->line_size - 1) | 300 ((cache->partitions - 1) << 12) | 301 ((cache->associativity - 1) << 22); 302 303 assert(cache->sets > 0); 304 *ecx = cache->sets - 1; 305 306 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 307 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 308 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 309 } 310 311 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 312 enum CpuTopologyLevel topo_level) 313 { 314 switch (topo_level) { 315 case CPU_TOPOLOGY_LEVEL_THREAD: 316 return 1; 317 case CPU_TOPOLOGY_LEVEL_CORE: 318 return topo_info->threads_per_core; 319 case CPU_TOPOLOGY_LEVEL_MODULE: 320 return x86_threads_per_module(topo_info); 321 case CPU_TOPOLOGY_LEVEL_DIE: 322 return x86_threads_per_die(topo_info); 323 case CPU_TOPOLOGY_LEVEL_SOCKET: 324 return x86_threads_per_pkg(topo_info); 325 default: 326 g_assert_not_reached(); 327 } 328 return 0; 329 } 330 331 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 332 enum CpuTopologyLevel topo_level) 333 { 334 switch (topo_level) { 335 case CPU_TOPOLOGY_LEVEL_THREAD: 336 return 0; 337 case CPU_TOPOLOGY_LEVEL_CORE: 338 return apicid_core_offset(topo_info); 339 case CPU_TOPOLOGY_LEVEL_MODULE: 340 return apicid_module_offset(topo_info); 341 case CPU_TOPOLOGY_LEVEL_DIE: 342 return apicid_die_offset(topo_info); 343 case CPU_TOPOLOGY_LEVEL_SOCKET: 344 return apicid_pkg_offset(topo_info); 345 default: 346 g_assert_not_reached(); 347 } 348 return 0; 349 } 350 351 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 352 { 353 switch (topo_level) { 354 case CPU_TOPOLOGY_LEVEL_INVALID: 355 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 356 case CPU_TOPOLOGY_LEVEL_THREAD: 357 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 358 case CPU_TOPOLOGY_LEVEL_CORE: 359 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 360 case CPU_TOPOLOGY_LEVEL_MODULE: 361 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 362 case CPU_TOPOLOGY_LEVEL_DIE: 363 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 364 default: 365 /* Other types are not supported in QEMU. */ 366 g_assert_not_reached(); 367 } 368 return 0; 369 } 370 371 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 372 X86CPUTopoInfo *topo_info, 373 uint32_t *eax, uint32_t *ebx, 374 uint32_t *ecx, uint32_t *edx) 375 { 376 X86CPU *cpu = env_archcpu(env); 377 unsigned long level, base_level, next_level; 378 uint32_t num_threads_next_level, offset_next_level; 379 380 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 381 382 /* 383 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 384 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 385 */ 386 level = CPU_TOPOLOGY_LEVEL_THREAD; 387 base_level = level; 388 for (int i = 0; i <= count; i++) { 389 level = find_next_bit(env->avail_cpu_topo, 390 CPU_TOPOLOGY_LEVEL_SOCKET, 391 base_level); 392 393 /* 394 * CPUID[0x1f] doesn't explicitly encode the package level, 395 * and it just encodes the invalid level (all fields are 0) 396 * into the last subleaf of 0x1f. 397 */ 398 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 399 level = CPU_TOPOLOGY_LEVEL_INVALID; 400 break; 401 } 402 /* Search the next level. */ 403 base_level = level + 1; 404 } 405 406 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 407 num_threads_next_level = 0; 408 offset_next_level = 0; 409 } else { 410 next_level = find_next_bit(env->avail_cpu_topo, 411 CPU_TOPOLOGY_LEVEL_SOCKET, 412 level + 1); 413 num_threads_next_level = num_threads_by_topo_level(topo_info, 414 next_level); 415 offset_next_level = apicid_offset_by_topo_level(topo_info, 416 next_level); 417 } 418 419 *eax = offset_next_level; 420 /* The count (bits 15-00) doesn't need to be reliable. */ 421 *ebx = num_threads_next_level & 0xffff; 422 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 423 *edx = cpu->apic_id; 424 425 assert(!(*eax & ~0x1f)); 426 } 427 428 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 429 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 430 { 431 assert(cache->size % 1024 == 0); 432 assert(cache->lines_per_tag > 0); 433 assert(cache->associativity > 0); 434 assert(cache->line_size > 0); 435 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 436 (cache->lines_per_tag << 8) | (cache->line_size); 437 } 438 439 #define ASSOC_FULL 0xFF 440 441 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 442 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 443 a == 2 ? 0x2 : \ 444 a == 4 ? 0x4 : \ 445 a == 8 ? 0x6 : \ 446 a == 16 ? 0x8 : \ 447 a == 32 ? 0xA : \ 448 a == 48 ? 0xB : \ 449 a == 64 ? 0xC : \ 450 a == 96 ? 0xD : \ 451 a == 128 ? 0xE : \ 452 a == ASSOC_FULL ? 0xF : \ 453 0 /* invalid value */) 454 455 /* 456 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 457 * @l3 can be NULL. 458 */ 459 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 460 CPUCacheInfo *l3, 461 uint32_t *ecx, uint32_t *edx) 462 { 463 assert(l2->size % 1024 == 0); 464 assert(l2->associativity > 0); 465 assert(l2->lines_per_tag > 0); 466 assert(l2->line_size > 0); 467 *ecx = ((l2->size / 1024) << 16) | 468 (AMD_ENC_ASSOC(l2->associativity) << 12) | 469 (l2->lines_per_tag << 8) | (l2->line_size); 470 471 if (l3) { 472 assert(l3->size % (512 * 1024) == 0); 473 assert(l3->associativity > 0); 474 assert(l3->lines_per_tag > 0); 475 assert(l3->line_size > 0); 476 *edx = ((l3->size / (512 * 1024)) << 18) | 477 (AMD_ENC_ASSOC(l3->associativity) << 12) | 478 (l3->lines_per_tag << 8) | (l3->line_size); 479 } else { 480 *edx = 0; 481 } 482 } 483 484 /* Encode cache info for CPUID[8000001D] */ 485 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 486 X86CPUTopoInfo *topo_info, 487 uint32_t *eax, uint32_t *ebx, 488 uint32_t *ecx, uint32_t *edx) 489 { 490 assert(cache->size == cache->line_size * cache->associativity * 491 cache->partitions * cache->sets); 492 493 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 494 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 495 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 496 497 assert(cache->line_size > 0); 498 assert(cache->partitions > 0); 499 assert(cache->associativity > 0); 500 /* We don't implement fully-associative caches */ 501 assert(cache->associativity < cache->sets); 502 *ebx = (cache->line_size - 1) | 503 ((cache->partitions - 1) << 12) | 504 ((cache->associativity - 1) << 22); 505 506 assert(cache->sets > 0); 507 *ecx = cache->sets - 1; 508 509 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 510 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 511 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 512 } 513 514 /* Encode cache info for CPUID[8000001E] */ 515 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 516 uint32_t *eax, uint32_t *ebx, 517 uint32_t *ecx, uint32_t *edx) 518 { 519 X86CPUTopoIDs topo_ids; 520 521 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 522 523 *eax = cpu->apic_id; 524 525 /* 526 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 527 * Read-only. Reset: 0000_XXXXh. 528 * See Core::X86::Cpuid::ExtApicId. 529 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 530 * Bits Description 531 * 31:16 Reserved. 532 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 533 * The number of threads per core is ThreadsPerCore+1. 534 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 535 * 536 * NOTE: CoreId is already part of apic_id. Just use it. We can 537 * use all the 8 bits to represent the core_id here. 538 */ 539 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 540 541 /* 542 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 543 * Read-only. Reset: 0000_0XXXh. 544 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 545 * Bits Description 546 * 31:11 Reserved. 547 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 548 * ValidValues: 549 * Value Description 550 * 0h 1 node per processor. 551 * 7h-1h Reserved. 552 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 553 * 554 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 555 * But users can create more nodes than the actual hardware can 556 * support. To genaralize we can use all the upper 8 bits for nodes. 557 * NodeId is combination of node and socket_id which is already decoded 558 * in apic_id. Just use it by shifting. 559 */ 560 if (cpu->legacy_multi_node) { 561 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 562 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 563 } else { 564 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 565 } 566 567 *edx = 0; 568 } 569 570 /* 571 * Definitions of the hardcoded cache entries we expose: 572 * These are legacy cache values. If there is a need to change any 573 * of these values please use builtin_x86_defs 574 */ 575 576 /* L1 data cache: */ 577 static CPUCacheInfo legacy_l1d_cache = { 578 .type = DATA_CACHE, 579 .level = 1, 580 .size = 32 * KiB, 581 .self_init = 1, 582 .line_size = 64, 583 .associativity = 8, 584 .sets = 64, 585 .partitions = 1, 586 .no_invd_sharing = true, 587 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 588 }; 589 590 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 591 static CPUCacheInfo legacy_l1d_cache_amd = { 592 .type = DATA_CACHE, 593 .level = 1, 594 .size = 64 * KiB, 595 .self_init = 1, 596 .line_size = 64, 597 .associativity = 2, 598 .sets = 512, 599 .partitions = 1, 600 .lines_per_tag = 1, 601 .no_invd_sharing = true, 602 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 603 }; 604 605 /* L1 instruction cache: */ 606 static CPUCacheInfo legacy_l1i_cache = { 607 .type = INSTRUCTION_CACHE, 608 .level = 1, 609 .size = 32 * KiB, 610 .self_init = 1, 611 .line_size = 64, 612 .associativity = 8, 613 .sets = 64, 614 .partitions = 1, 615 .no_invd_sharing = true, 616 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 617 }; 618 619 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 620 static CPUCacheInfo legacy_l1i_cache_amd = { 621 .type = INSTRUCTION_CACHE, 622 .level = 1, 623 .size = 64 * KiB, 624 .self_init = 1, 625 .line_size = 64, 626 .associativity = 2, 627 .sets = 512, 628 .partitions = 1, 629 .lines_per_tag = 1, 630 .no_invd_sharing = true, 631 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 632 }; 633 634 /* Level 2 unified cache: */ 635 static CPUCacheInfo legacy_l2_cache = { 636 .type = UNIFIED_CACHE, 637 .level = 2, 638 .size = 4 * MiB, 639 .self_init = 1, 640 .line_size = 64, 641 .associativity = 16, 642 .sets = 4096, 643 .partitions = 1, 644 .no_invd_sharing = true, 645 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 646 }; 647 648 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 649 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 650 .type = UNIFIED_CACHE, 651 .level = 2, 652 .size = 2 * MiB, 653 .line_size = 64, 654 .associativity = 8, 655 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 656 }; 657 658 659 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 660 static CPUCacheInfo legacy_l2_cache_amd = { 661 .type = UNIFIED_CACHE, 662 .level = 2, 663 .size = 512 * KiB, 664 .line_size = 64, 665 .lines_per_tag = 1, 666 .associativity = 16, 667 .sets = 512, 668 .partitions = 1, 669 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 670 }; 671 672 /* Level 3 unified cache: */ 673 static CPUCacheInfo legacy_l3_cache = { 674 .type = UNIFIED_CACHE, 675 .level = 3, 676 .size = 16 * MiB, 677 .line_size = 64, 678 .associativity = 16, 679 .sets = 16384, 680 .partitions = 1, 681 .lines_per_tag = 1, 682 .self_init = true, 683 .inclusive = true, 684 .complex_indexing = true, 685 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 686 }; 687 688 /* TLB definitions: */ 689 690 #define L1_DTLB_2M_ASSOC 1 691 #define L1_DTLB_2M_ENTRIES 255 692 #define L1_DTLB_4K_ASSOC 1 693 #define L1_DTLB_4K_ENTRIES 255 694 695 #define L1_ITLB_2M_ASSOC 1 696 #define L1_ITLB_2M_ENTRIES 255 697 #define L1_ITLB_4K_ASSOC 1 698 #define L1_ITLB_4K_ENTRIES 255 699 700 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 701 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 702 #define L2_DTLB_4K_ASSOC 4 703 #define L2_DTLB_4K_ENTRIES 512 704 705 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 706 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 707 #define L2_ITLB_4K_ASSOC 4 708 #define L2_ITLB_4K_ENTRIES 512 709 710 /* CPUID Leaf 0x14 constants: */ 711 #define INTEL_PT_MAX_SUBLEAF 0x1 712 /* 713 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 714 * MSR can be accessed; 715 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 716 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 717 * of Intel PT MSRs across warm reset; 718 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 719 */ 720 #define INTEL_PT_MINIMAL_EBX 0xf 721 /* 722 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 723 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 724 * accessed; 725 * bit[01]: ToPA tables can hold any number of output entries, up to the 726 * maximum allowed by the MaskOrTableOffset field of 727 * IA32_RTIT_OUTPUT_MASK_PTRS; 728 * bit[02]: Support Single-Range Output scheme; 729 */ 730 #define INTEL_PT_MINIMAL_ECX 0x7 731 /* generated packets which contain IP payloads have LIP values */ 732 #define INTEL_PT_IP_LIP (1 << 31) 733 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 734 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 735 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 736 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 737 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 738 739 /* CPUID Leaf 0x1D constants: */ 740 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 741 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 742 #define INTEL_AMX_BYTES_PER_TILE 0x400 743 #define INTEL_AMX_BYTES_PER_ROW 0x40 744 #define INTEL_AMX_TILE_MAX_NAMES 0x8 745 #define INTEL_AMX_TILE_MAX_ROWS 0x10 746 747 /* CPUID Leaf 0x1E constants: */ 748 #define INTEL_AMX_TMUL_MAX_K 0x10 749 #define INTEL_AMX_TMUL_MAX_N 0x40 750 751 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 752 uint32_t vendor2, uint32_t vendor3) 753 { 754 int i; 755 for (i = 0; i < 4; i++) { 756 dst[i] = vendor1 >> (8 * i); 757 dst[i + 4] = vendor2 >> (8 * i); 758 dst[i + 8] = vendor3 >> (8 * i); 759 } 760 dst[CPUID_VENDOR_SZ] = '\0'; 761 } 762 763 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 764 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 765 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 766 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 767 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 768 CPUID_PSE36 | CPUID_FXSR) 769 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 770 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 771 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 772 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 773 CPUID_PAE | CPUID_SEP | CPUID_APIC) 774 775 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 776 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 777 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 778 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 779 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 780 /* partly implemented: 781 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 782 /* missing: 783 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 784 785 /* 786 * Kernel-only features that can be shown to usermode programs even if 787 * they aren't actually supported by TCG, because qemu-user only runs 788 * in CPL=3; remove them if they are ever implemented for system emulation. 789 */ 790 #if defined CONFIG_USER_ONLY 791 #define CPUID_EXT_KERNEL_FEATURES \ 792 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 793 #else 794 #define CPUID_EXT_KERNEL_FEATURES 0 795 #endif 796 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 797 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 798 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 799 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 800 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 801 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 802 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 803 /* missing: 804 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 805 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 806 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 807 CPUID_EXT_TSC_DEADLINE_TIMER 808 */ 809 810 #ifdef TARGET_X86_64 811 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 812 #else 813 #define TCG_EXT2_X86_64_FEATURES 0 814 #endif 815 816 /* 817 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 818 * in usermode or by 32-bit programs. Those are added to supported 819 * TCG features unconditionally in user-mode emulation mode. This may 820 * indeed seem strange or incorrect, but it works because code running 821 * under usermode emulation cannot access them. 822 * 823 * Even for long mode, qemu-i386 is not running "a userspace program on a 824 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 825 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 826 * but again the difference is only visible in kernel mode. 827 */ 828 #if defined CONFIG_LINUX_USER 829 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 830 #elif defined CONFIG_USER_ONLY 831 /* FIXME: Long mode not yet supported for i386 bsd-user */ 832 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 833 #else 834 #define CPUID_EXT2_KERNEL_FEATURES 0 835 #endif 836 837 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 838 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 839 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 840 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 841 CPUID_EXT2_KERNEL_FEATURES) 842 843 #if defined CONFIG_USER_ONLY 844 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 845 #else 846 #define CPUID_EXT3_KERNEL_FEATURES 0 847 #endif 848 849 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 850 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 851 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 852 853 #define TCG_EXT4_FEATURES 0 854 855 #if defined CONFIG_USER_ONLY 856 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 857 #else 858 #define CPUID_SVM_KERNEL_FEATURES 0 859 #endif 860 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 861 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 862 863 #define TCG_KVM_FEATURES 0 864 865 #if defined CONFIG_USER_ONLY 866 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 867 #else 868 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 869 #endif 870 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 871 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 872 CPUID_7_0_EBX_CLFLUSHOPT | \ 873 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 874 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 875 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 876 /* missing: 877 CPUID_7_0_EBX_HLE 878 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 879 880 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 881 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 882 #else 883 #define TCG_7_0_ECX_RDPID 0 884 #endif 885 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 886 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 887 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 888 TCG_7_0_ECX_RDPID) 889 890 #if defined CONFIG_USER_ONLY 891 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 892 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 893 #else 894 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 895 #endif 896 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 897 898 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 899 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 900 #define TCG_7_1_EDX_FEATURES 0 901 #define TCG_7_2_EDX_FEATURES 0 902 #define TCG_APM_FEATURES 0 903 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 904 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 905 /* missing: 906 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 907 #define TCG_14_0_ECX_FEATURES 0 908 #define TCG_SGX_12_0_EAX_FEATURES 0 909 #define TCG_SGX_12_0_EBX_FEATURES 0 910 #define TCG_SGX_12_1_EAX_FEATURES 0 911 #define TCG_24_0_EBX_FEATURES 0 912 913 #if defined CONFIG_USER_ONLY 914 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 915 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 916 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 917 CPUID_8000_0008_EBX_AMD_PSFD) 918 #else 919 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 920 #endif 921 922 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 923 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 924 925 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 926 [FEAT_1_EDX] = { 927 .type = CPUID_FEATURE_WORD, 928 .feat_names = { 929 "fpu", "vme", "de", "pse", 930 "tsc", "msr", "pae", "mce", 931 "cx8", "apic", NULL, "sep", 932 "mtrr", "pge", "mca", "cmov", 933 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 934 NULL, "ds" /* Intel dts */, "acpi", "mmx", 935 "fxsr", "sse", "sse2", "ss", 936 "ht" /* Intel htt */, "tm", "ia64", "pbe", 937 }, 938 .cpuid = {.eax = 1, .reg = R_EDX, }, 939 .tcg_features = TCG_FEATURES, 940 .no_autoenable_flags = CPUID_HT, 941 }, 942 [FEAT_1_ECX] = { 943 .type = CPUID_FEATURE_WORD, 944 .feat_names = { 945 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 946 "ds-cpl", "vmx", "smx", "est", 947 "tm2", "ssse3", "cid", NULL, 948 "fma", "cx16", "xtpr", "pdcm", 949 NULL, "pcid", "dca", "sse4.1", 950 "sse4.2", "x2apic", "movbe", "popcnt", 951 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 952 "avx", "f16c", "rdrand", "hypervisor", 953 }, 954 .cpuid = { .eax = 1, .reg = R_ECX, }, 955 .tcg_features = TCG_EXT_FEATURES, 956 }, 957 /* Feature names that are already defined on feature_name[] but 958 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 959 * names on feat_names below. They are copied automatically 960 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 961 */ 962 [FEAT_8000_0001_EDX] = { 963 .type = CPUID_FEATURE_WORD, 964 .feat_names = { 965 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 966 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 967 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 968 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 969 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 970 "nx", NULL, "mmxext", NULL /* mmx */, 971 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 972 NULL, "lm", "3dnowext", "3dnow", 973 }, 974 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 975 .tcg_features = TCG_EXT2_FEATURES, 976 }, 977 [FEAT_8000_0001_ECX] = { 978 .type = CPUID_FEATURE_WORD, 979 .feat_names = { 980 "lahf-lm", "cmp-legacy", "svm", "extapic", 981 "cr8legacy", "abm", "sse4a", "misalignsse", 982 "3dnowprefetch", "osvw", "ibs", "xop", 983 "skinit", "wdt", NULL, "lwp", 984 "fma4", "tce", NULL, "nodeid-msr", 985 NULL, "tbm", "topoext", "perfctr-core", 986 "perfctr-nb", NULL, NULL, NULL, 987 NULL, NULL, NULL, NULL, 988 }, 989 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 990 .tcg_features = TCG_EXT3_FEATURES, 991 /* 992 * TOPOEXT is always allowed but can't be enabled blindly by 993 * "-cpu host", as it requires consistent cache topology info 994 * to be provided so it doesn't confuse guests. 995 */ 996 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 997 }, 998 [FEAT_C000_0001_EDX] = { 999 .type = CPUID_FEATURE_WORD, 1000 .feat_names = { 1001 NULL, NULL, "xstore", "xstore-en", 1002 NULL, NULL, "xcrypt", "xcrypt-en", 1003 "ace2", "ace2-en", "phe", "phe-en", 1004 "pmm", "pmm-en", NULL, NULL, 1005 NULL, NULL, NULL, NULL, 1006 NULL, NULL, NULL, NULL, 1007 NULL, NULL, NULL, NULL, 1008 NULL, NULL, NULL, NULL, 1009 }, 1010 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1011 .tcg_features = TCG_EXT4_FEATURES, 1012 }, 1013 [FEAT_KVM] = { 1014 .type = CPUID_FEATURE_WORD, 1015 .feat_names = { 1016 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1017 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1018 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1019 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1020 NULL, NULL, NULL, NULL, 1021 NULL, NULL, NULL, NULL, 1022 "kvmclock-stable-bit", NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 }, 1025 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1026 .tcg_features = TCG_KVM_FEATURES, 1027 }, 1028 [FEAT_KVM_HINTS] = { 1029 .type = CPUID_FEATURE_WORD, 1030 .feat_names = { 1031 "kvm-hint-dedicated", NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 NULL, NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 NULL, NULL, NULL, NULL, 1036 NULL, NULL, NULL, NULL, 1037 NULL, NULL, NULL, NULL, 1038 NULL, NULL, NULL, NULL, 1039 }, 1040 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1041 .tcg_features = TCG_KVM_FEATURES, 1042 /* 1043 * KVM hints aren't auto-enabled by -cpu host, they need to be 1044 * explicitly enabled in the command-line. 1045 */ 1046 .no_autoenable_flags = ~0U, 1047 }, 1048 [FEAT_SVM] = { 1049 .type = CPUID_FEATURE_WORD, 1050 .feat_names = { 1051 "npt", "lbrv", "svm-lock", "nrip-save", 1052 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1053 NULL, NULL, "pause-filter", NULL, 1054 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1055 "vgif", NULL, NULL, NULL, 1056 NULL, NULL, NULL, NULL, 1057 NULL, "vnmi", NULL, NULL, 1058 "svme-addr-chk", NULL, NULL, NULL, 1059 }, 1060 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1061 .tcg_features = TCG_SVM_FEATURES, 1062 }, 1063 [FEAT_7_0_EBX] = { 1064 .type = CPUID_FEATURE_WORD, 1065 .feat_names = { 1066 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1067 "hle", "avx2", "fdp-excptn-only", "smep", 1068 "bmi2", "erms", "invpcid", "rtm", 1069 NULL, "zero-fcs-fds", "mpx", NULL, 1070 "avx512f", "avx512dq", "rdseed", "adx", 1071 "smap", "avx512ifma", "pcommit", "clflushopt", 1072 "clwb", "intel-pt", "avx512pf", "avx512er", 1073 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1074 }, 1075 .cpuid = { 1076 .eax = 7, 1077 .needs_ecx = true, .ecx = 0, 1078 .reg = R_EBX, 1079 }, 1080 .tcg_features = TCG_7_0_EBX_FEATURES, 1081 }, 1082 [FEAT_7_0_ECX] = { 1083 .type = CPUID_FEATURE_WORD, 1084 .feat_names = { 1085 NULL, "avx512vbmi", "umip", "pku", 1086 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1087 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1088 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1089 "la57", NULL, NULL, NULL, 1090 NULL, NULL, "rdpid", NULL, 1091 "bus-lock-detect", "cldemote", NULL, "movdiri", 1092 "movdir64b", NULL, "sgxlc", "pks", 1093 }, 1094 .cpuid = { 1095 .eax = 7, 1096 .needs_ecx = true, .ecx = 0, 1097 .reg = R_ECX, 1098 }, 1099 .tcg_features = TCG_7_0_ECX_FEATURES, 1100 }, 1101 [FEAT_7_0_EDX] = { 1102 .type = CPUID_FEATURE_WORD, 1103 .feat_names = { 1104 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1105 "fsrm", NULL, NULL, NULL, 1106 "avx512-vp2intersect", NULL, "md-clear", NULL, 1107 NULL, NULL, "serialize", NULL, 1108 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1109 NULL, NULL, "amx-bf16", "avx512-fp16", 1110 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1111 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1112 }, 1113 .cpuid = { 1114 .eax = 7, 1115 .needs_ecx = true, .ecx = 0, 1116 .reg = R_EDX, 1117 }, 1118 .tcg_features = TCG_7_0_EDX_FEATURES, 1119 }, 1120 [FEAT_7_1_EAX] = { 1121 .type = CPUID_FEATURE_WORD, 1122 .feat_names = { 1123 "sha512", "sm3", "sm4", NULL, 1124 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1125 NULL, NULL, "fzrm", "fsrs", 1126 "fsrc", NULL, NULL, NULL, 1127 NULL, "fred", "lkgs", "wrmsrns", 1128 NULL, "amx-fp16", NULL, "avx-ifma", 1129 NULL, NULL, "lam", NULL, 1130 NULL, NULL, NULL, NULL, 1131 }, 1132 .cpuid = { 1133 .eax = 7, 1134 .needs_ecx = true, .ecx = 1, 1135 .reg = R_EAX, 1136 }, 1137 .tcg_features = TCG_7_1_EAX_FEATURES, 1138 }, 1139 [FEAT_7_1_EDX] = { 1140 .type = CPUID_FEATURE_WORD, 1141 .feat_names = { 1142 NULL, NULL, NULL, NULL, 1143 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1144 "amx-complex", NULL, "avx-vnni-int16", NULL, 1145 NULL, NULL, "prefetchiti", NULL, 1146 NULL, NULL, NULL, "avx10", 1147 NULL, NULL, NULL, NULL, 1148 NULL, NULL, NULL, NULL, 1149 NULL, NULL, NULL, NULL, 1150 }, 1151 .cpuid = { 1152 .eax = 7, 1153 .needs_ecx = true, .ecx = 1, 1154 .reg = R_EDX, 1155 }, 1156 .tcg_features = TCG_7_1_EDX_FEATURES, 1157 }, 1158 [FEAT_7_2_EDX] = { 1159 .type = CPUID_FEATURE_WORD, 1160 .feat_names = { 1161 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1162 "bhi-ctrl", "mcdt-no", NULL, NULL, 1163 NULL, NULL, NULL, NULL, 1164 NULL, NULL, NULL, NULL, 1165 NULL, NULL, NULL, NULL, 1166 NULL, NULL, NULL, NULL, 1167 NULL, NULL, NULL, NULL, 1168 NULL, NULL, NULL, NULL, 1169 }, 1170 .cpuid = { 1171 .eax = 7, 1172 .needs_ecx = true, .ecx = 2, 1173 .reg = R_EDX, 1174 }, 1175 .tcg_features = TCG_7_2_EDX_FEATURES, 1176 }, 1177 [FEAT_24_0_EBX] = { 1178 .type = CPUID_FEATURE_WORD, 1179 .feat_names = { 1180 [16] = "avx10-128", 1181 [17] = "avx10-256", 1182 [18] = "avx10-512", 1183 }, 1184 .cpuid = { 1185 .eax = 0x24, 1186 .needs_ecx = true, .ecx = 0, 1187 .reg = R_EBX, 1188 }, 1189 .tcg_features = TCG_24_0_EBX_FEATURES, 1190 }, 1191 [FEAT_8000_0007_EDX] = { 1192 .type = CPUID_FEATURE_WORD, 1193 .feat_names = { 1194 NULL, NULL, NULL, NULL, 1195 NULL, NULL, NULL, NULL, 1196 "invtsc", NULL, NULL, NULL, 1197 NULL, NULL, NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 NULL, NULL, NULL, NULL, 1200 NULL, NULL, NULL, NULL, 1201 NULL, NULL, NULL, NULL, 1202 }, 1203 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1204 .tcg_features = TCG_APM_FEATURES, 1205 .unmigratable_flags = CPUID_APM_INVTSC, 1206 }, 1207 [FEAT_8000_0007_EBX] = { 1208 .type = CPUID_FEATURE_WORD, 1209 .feat_names = { 1210 "overflow-recov", "succor", NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 NULL, NULL, NULL, NULL, 1216 NULL, NULL, NULL, NULL, 1217 NULL, NULL, NULL, NULL, 1218 }, 1219 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1220 .tcg_features = 0, 1221 .unmigratable_flags = 0, 1222 }, 1223 [FEAT_8000_0008_EBX] = { 1224 .type = CPUID_FEATURE_WORD, 1225 .feat_names = { 1226 "clzero", NULL, "xsaveerptr", NULL, 1227 NULL, NULL, NULL, NULL, 1228 NULL, "wbnoinvd", NULL, NULL, 1229 "ibpb", NULL, "ibrs", "amd-stibp", 1230 NULL, "stibp-always-on", NULL, NULL, 1231 NULL, NULL, NULL, NULL, 1232 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1233 "amd-psfd", NULL, NULL, NULL, 1234 }, 1235 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1236 .tcg_features = TCG_8000_0008_EBX, 1237 .unmigratable_flags = 0, 1238 }, 1239 [FEAT_8000_0021_EAX] = { 1240 .type = CPUID_FEATURE_WORD, 1241 .feat_names = { 1242 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1243 NULL, NULL, "null-sel-clr-base", NULL, 1244 "auto-ibrs", NULL, NULL, NULL, 1245 NULL, NULL, NULL, NULL, 1246 NULL, NULL, NULL, NULL, 1247 NULL, NULL, NULL, NULL, 1248 "eraps", NULL, NULL, "sbpb", 1249 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1250 }, 1251 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1252 .tcg_features = 0, 1253 .unmigratable_flags = 0, 1254 }, 1255 [FEAT_8000_0021_EBX] = { 1256 .type = CPUID_FEATURE_WORD, 1257 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1258 .tcg_features = 0, 1259 .unmigratable_flags = 0, 1260 }, 1261 [FEAT_8000_0022_EAX] = { 1262 .type = CPUID_FEATURE_WORD, 1263 .feat_names = { 1264 "perfmon-v2", NULL, NULL, NULL, 1265 NULL, NULL, NULL, NULL, 1266 NULL, NULL, NULL, NULL, 1267 NULL, NULL, NULL, NULL, 1268 NULL, NULL, NULL, NULL, 1269 NULL, NULL, NULL, NULL, 1270 NULL, NULL, NULL, NULL, 1271 NULL, NULL, NULL, NULL, 1272 }, 1273 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1274 .tcg_features = 0, 1275 .unmigratable_flags = 0, 1276 }, 1277 [FEAT_XSAVE] = { 1278 .type = CPUID_FEATURE_WORD, 1279 .feat_names = { 1280 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1281 "xfd", NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 NULL, NULL, NULL, NULL, 1287 NULL, NULL, NULL, NULL, 1288 }, 1289 .cpuid = { 1290 .eax = 0xd, 1291 .needs_ecx = true, .ecx = 1, 1292 .reg = R_EAX, 1293 }, 1294 .tcg_features = TCG_XSAVE_FEATURES, 1295 }, 1296 [FEAT_XSAVE_XSS_LO] = { 1297 .type = CPUID_FEATURE_WORD, 1298 .feat_names = { 1299 NULL, NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 NULL, NULL, NULL, NULL, 1302 NULL, NULL, NULL, NULL, 1303 NULL, NULL, NULL, NULL, 1304 NULL, NULL, NULL, NULL, 1305 NULL, NULL, NULL, NULL, 1306 NULL, NULL, NULL, NULL, 1307 }, 1308 .cpuid = { 1309 .eax = 0xD, 1310 .needs_ecx = true, 1311 .ecx = 1, 1312 .reg = R_ECX, 1313 }, 1314 }, 1315 [FEAT_XSAVE_XSS_HI] = { 1316 .type = CPUID_FEATURE_WORD, 1317 .cpuid = { 1318 .eax = 0xD, 1319 .needs_ecx = true, 1320 .ecx = 1, 1321 .reg = R_EDX 1322 }, 1323 }, 1324 [FEAT_6_EAX] = { 1325 .type = CPUID_FEATURE_WORD, 1326 .feat_names = { 1327 NULL, NULL, "arat", NULL, 1328 NULL, NULL, NULL, NULL, 1329 NULL, NULL, NULL, NULL, 1330 NULL, NULL, NULL, NULL, 1331 NULL, NULL, NULL, NULL, 1332 NULL, NULL, NULL, NULL, 1333 NULL, NULL, NULL, NULL, 1334 NULL, NULL, NULL, NULL, 1335 }, 1336 .cpuid = { .eax = 6, .reg = R_EAX, }, 1337 .tcg_features = TCG_6_EAX_FEATURES, 1338 }, 1339 [FEAT_XSAVE_XCR0_LO] = { 1340 .type = CPUID_FEATURE_WORD, 1341 .cpuid = { 1342 .eax = 0xD, 1343 .needs_ecx = true, .ecx = 0, 1344 .reg = R_EAX, 1345 }, 1346 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1347 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1348 XSTATE_PKRU_MASK, 1349 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1350 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1351 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1352 XSTATE_PKRU_MASK, 1353 }, 1354 [FEAT_XSAVE_XCR0_HI] = { 1355 .type = CPUID_FEATURE_WORD, 1356 .cpuid = { 1357 .eax = 0xD, 1358 .needs_ecx = true, .ecx = 0, 1359 .reg = R_EDX, 1360 }, 1361 .tcg_features = 0U, 1362 }, 1363 /*Below are MSR exposed features*/ 1364 [FEAT_ARCH_CAPABILITIES] = { 1365 .type = MSR_FEATURE_WORD, 1366 .feat_names = { 1367 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1368 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1369 "taa-no", NULL, NULL, NULL, 1370 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1371 NULL, "fb-clear", NULL, NULL, 1372 "bhi-no", NULL, NULL, NULL, 1373 "pbrsb-no", NULL, "gds-no", "rfds-no", 1374 "rfds-clear", NULL, NULL, NULL, 1375 }, 1376 .msr = { 1377 .index = MSR_IA32_ARCH_CAPABILITIES, 1378 }, 1379 /* 1380 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1381 * cannot be read from user mode. Therefore, it has no impact 1382 > on any user-mode operation, and warnings about unsupported 1383 * features do not matter. 1384 */ 1385 .tcg_features = ~0U, 1386 }, 1387 [FEAT_CORE_CAPABILITY] = { 1388 .type = MSR_FEATURE_WORD, 1389 .feat_names = { 1390 NULL, NULL, NULL, NULL, 1391 NULL, "split-lock-detect", NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 NULL, NULL, NULL, NULL, 1395 NULL, NULL, NULL, NULL, 1396 NULL, NULL, NULL, NULL, 1397 NULL, NULL, NULL, NULL, 1398 }, 1399 .msr = { 1400 .index = MSR_IA32_CORE_CAPABILITY, 1401 }, 1402 }, 1403 [FEAT_PERF_CAPABILITIES] = { 1404 .type = MSR_FEATURE_WORD, 1405 .feat_names = { 1406 NULL, NULL, NULL, NULL, 1407 NULL, NULL, NULL, NULL, 1408 NULL, NULL, NULL, NULL, 1409 NULL, "full-width-write", NULL, NULL, 1410 NULL, NULL, NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 }, 1415 .msr = { 1416 .index = MSR_IA32_PERF_CAPABILITIES, 1417 }, 1418 }, 1419 1420 [FEAT_VMX_PROCBASED_CTLS] = { 1421 .type = MSR_FEATURE_WORD, 1422 .feat_names = { 1423 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1424 NULL, NULL, NULL, "vmx-hlt-exit", 1425 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1426 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1427 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1428 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1429 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1430 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1431 }, 1432 .msr = { 1433 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1434 } 1435 }, 1436 1437 [FEAT_VMX_SECONDARY_CTLS] = { 1438 .type = MSR_FEATURE_WORD, 1439 .feat_names = { 1440 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1441 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1442 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1443 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1444 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1445 "vmx-xsaves", NULL, NULL, NULL, 1446 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1447 NULL, NULL, NULL, NULL, 1448 }, 1449 .msr = { 1450 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1451 } 1452 }, 1453 1454 [FEAT_VMX_PINBASED_CTLS] = { 1455 .type = MSR_FEATURE_WORD, 1456 .feat_names = { 1457 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1458 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1459 NULL, NULL, NULL, NULL, 1460 NULL, NULL, NULL, NULL, 1461 NULL, NULL, NULL, NULL, 1462 NULL, NULL, NULL, NULL, 1463 NULL, NULL, NULL, NULL, 1464 NULL, NULL, NULL, NULL, 1465 }, 1466 .msr = { 1467 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1468 } 1469 }, 1470 1471 [FEAT_VMX_EXIT_CTLS] = { 1472 .type = MSR_FEATURE_WORD, 1473 /* 1474 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1475 * the LM CPUID bit. 1476 */ 1477 .feat_names = { 1478 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1479 NULL, NULL, NULL, NULL, 1480 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1481 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1482 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1483 "vmx-exit-save-efer", "vmx-exit-load-efer", 1484 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1485 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1486 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1487 }, 1488 .msr = { 1489 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1490 } 1491 }, 1492 1493 [FEAT_VMX_ENTRY_CTLS] = { 1494 .type = MSR_FEATURE_WORD, 1495 .feat_names = { 1496 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1497 NULL, NULL, NULL, NULL, 1498 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1499 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1500 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1501 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1502 NULL, NULL, NULL, NULL, 1503 NULL, NULL, NULL, NULL, 1504 }, 1505 .msr = { 1506 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1507 } 1508 }, 1509 1510 [FEAT_VMX_MISC] = { 1511 .type = MSR_FEATURE_WORD, 1512 .feat_names = { 1513 NULL, NULL, NULL, NULL, 1514 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1515 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1516 NULL, NULL, NULL, NULL, 1517 NULL, NULL, NULL, NULL, 1518 NULL, NULL, NULL, NULL, 1519 NULL, NULL, NULL, NULL, 1520 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1521 }, 1522 .msr = { 1523 .index = MSR_IA32_VMX_MISC, 1524 } 1525 }, 1526 1527 [FEAT_VMX_EPT_VPID_CAPS] = { 1528 .type = MSR_FEATURE_WORD, 1529 .feat_names = { 1530 "vmx-ept-execonly", NULL, NULL, NULL, 1531 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1532 NULL, NULL, NULL, NULL, 1533 NULL, NULL, NULL, NULL, 1534 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1535 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1536 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1537 NULL, NULL, NULL, NULL, 1538 "vmx-invvpid", NULL, NULL, NULL, 1539 NULL, NULL, NULL, NULL, 1540 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1541 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1542 NULL, NULL, NULL, NULL, 1543 NULL, NULL, NULL, NULL, 1544 NULL, NULL, NULL, NULL, 1545 NULL, NULL, NULL, NULL, 1546 NULL, NULL, NULL, NULL, 1547 }, 1548 .msr = { 1549 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1550 } 1551 }, 1552 1553 [FEAT_VMX_BASIC] = { 1554 .type = MSR_FEATURE_WORD, 1555 .feat_names = { 1556 [54] = "vmx-ins-outs", 1557 [55] = "vmx-true-ctls", 1558 [56] = "vmx-any-errcode", 1559 [58] = "vmx-nested-exception", 1560 }, 1561 .msr = { 1562 .index = MSR_IA32_VMX_BASIC, 1563 }, 1564 /* Just to be safe - we don't support setting the MSEG version field. */ 1565 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1566 }, 1567 1568 [FEAT_VMX_VMFUNC] = { 1569 .type = MSR_FEATURE_WORD, 1570 .feat_names = { 1571 [0] = "vmx-eptp-switching", 1572 }, 1573 .msr = { 1574 .index = MSR_IA32_VMX_VMFUNC, 1575 } 1576 }, 1577 1578 [FEAT_14_0_ECX] = { 1579 .type = CPUID_FEATURE_WORD, 1580 .feat_names = { 1581 NULL, NULL, NULL, NULL, 1582 NULL, NULL, NULL, NULL, 1583 NULL, NULL, NULL, NULL, 1584 NULL, NULL, NULL, NULL, 1585 NULL, NULL, NULL, NULL, 1586 NULL, NULL, NULL, NULL, 1587 NULL, NULL, NULL, NULL, 1588 NULL, NULL, NULL, "intel-pt-lip", 1589 }, 1590 .cpuid = { 1591 .eax = 0x14, 1592 .needs_ecx = true, .ecx = 0, 1593 .reg = R_ECX, 1594 }, 1595 .tcg_features = TCG_14_0_ECX_FEATURES, 1596 }, 1597 1598 [FEAT_SGX_12_0_EAX] = { 1599 .type = CPUID_FEATURE_WORD, 1600 .feat_names = { 1601 "sgx1", "sgx2", NULL, NULL, 1602 NULL, NULL, NULL, NULL, 1603 NULL, NULL, NULL, "sgx-edeccssa", 1604 NULL, NULL, NULL, NULL, 1605 NULL, NULL, NULL, NULL, 1606 NULL, NULL, NULL, NULL, 1607 NULL, NULL, NULL, NULL, 1608 NULL, NULL, NULL, NULL, 1609 }, 1610 .cpuid = { 1611 .eax = 0x12, 1612 .needs_ecx = true, .ecx = 0, 1613 .reg = R_EAX, 1614 }, 1615 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1616 }, 1617 1618 [FEAT_SGX_12_0_EBX] = { 1619 .type = CPUID_FEATURE_WORD, 1620 .feat_names = { 1621 "sgx-exinfo" , NULL, NULL, NULL, 1622 NULL, NULL, NULL, NULL, 1623 NULL, NULL, NULL, NULL, 1624 NULL, NULL, NULL, NULL, 1625 NULL, NULL, NULL, NULL, 1626 NULL, NULL, NULL, NULL, 1627 NULL, NULL, NULL, NULL, 1628 NULL, NULL, NULL, NULL, 1629 }, 1630 .cpuid = { 1631 .eax = 0x12, 1632 .needs_ecx = true, .ecx = 0, 1633 .reg = R_EBX, 1634 }, 1635 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1636 }, 1637 1638 [FEAT_SGX_12_1_EAX] = { 1639 .type = CPUID_FEATURE_WORD, 1640 .feat_names = { 1641 NULL, "sgx-debug", "sgx-mode64", NULL, 1642 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1643 NULL, NULL, "sgx-aex-notify", NULL, 1644 NULL, NULL, NULL, NULL, 1645 NULL, NULL, NULL, NULL, 1646 NULL, NULL, NULL, NULL, 1647 NULL, NULL, NULL, NULL, 1648 NULL, NULL, NULL, NULL, 1649 }, 1650 .cpuid = { 1651 .eax = 0x12, 1652 .needs_ecx = true, .ecx = 1, 1653 .reg = R_EAX, 1654 }, 1655 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1656 }, 1657 }; 1658 1659 typedef struct FeatureMask { 1660 FeatureWord index; 1661 uint64_t mask; 1662 } FeatureMask; 1663 1664 typedef struct FeatureDep { 1665 FeatureMask from, to; 1666 } FeatureDep; 1667 1668 static FeatureDep feature_dependencies[] = { 1669 { 1670 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1671 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1672 }, 1673 { 1674 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1675 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1676 }, 1677 { 1678 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1679 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1680 }, 1681 { 1682 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1683 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1684 }, 1685 { 1686 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1687 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1688 }, 1689 { 1690 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1691 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1692 }, 1693 { 1694 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1695 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1696 }, 1697 { 1698 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1699 .to = { FEAT_VMX_MISC, ~0ull }, 1700 }, 1701 { 1702 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1703 .to = { FEAT_VMX_BASIC, ~0ull }, 1704 }, 1705 { 1706 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1707 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1708 }, 1709 { 1710 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1711 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1712 }, 1713 { 1714 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1715 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1716 }, 1717 { 1718 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1719 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1720 }, 1721 { 1722 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1723 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1724 }, 1725 { 1726 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1727 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1728 }, 1729 { 1730 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1731 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1732 }, 1733 { 1734 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1735 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1736 }, 1737 { 1738 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1739 .to = { FEAT_14_0_ECX, ~0ull }, 1740 }, 1741 { 1742 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1743 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1744 }, 1745 { 1746 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1747 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1748 }, 1749 { 1750 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1751 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1752 }, 1753 { 1754 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1755 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1756 }, 1757 { 1758 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1759 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1760 }, 1761 { 1762 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1763 .to = { FEAT_SVM, ~0ull }, 1764 }, 1765 { 1766 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1767 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1768 }, 1769 { 1770 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1771 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1772 }, 1773 { 1774 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1775 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1776 }, 1777 { 1778 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1779 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1780 }, 1781 { 1782 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1783 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1784 }, 1785 { 1786 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1787 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1788 }, 1789 { 1790 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1791 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1792 }, 1793 { 1794 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1795 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1796 }, 1797 { 1798 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1799 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1800 }, 1801 { 1802 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1803 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1804 }, 1805 { 1806 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1807 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1808 }, 1809 { 1810 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1811 .to = { FEAT_24_0_EBX, ~0ull }, 1812 }, 1813 }; 1814 1815 typedef struct X86RegisterInfo32 { 1816 /* Name of register */ 1817 const char *name; 1818 /* QAPI enum value register */ 1819 X86CPURegister32 qapi_enum; 1820 } X86RegisterInfo32; 1821 1822 #define REGISTER(reg) \ 1823 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1824 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1825 REGISTER(EAX), 1826 REGISTER(ECX), 1827 REGISTER(EDX), 1828 REGISTER(EBX), 1829 REGISTER(ESP), 1830 REGISTER(EBP), 1831 REGISTER(ESI), 1832 REGISTER(EDI), 1833 }; 1834 #undef REGISTER 1835 1836 /* CPUID feature bits available in XSS */ 1837 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1838 1839 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1840 [XSTATE_FP_BIT] = { 1841 /* x87 FP state component is always enabled if XSAVE is supported */ 1842 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1843 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1844 }, 1845 [XSTATE_SSE_BIT] = { 1846 /* SSE state component is always enabled if XSAVE is supported */ 1847 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1848 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1849 }, 1850 [XSTATE_YMM_BIT] = 1851 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1852 .size = sizeof(XSaveAVX) }, 1853 [XSTATE_BNDREGS_BIT] = 1854 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1855 .size = sizeof(XSaveBNDREG) }, 1856 [XSTATE_BNDCSR_BIT] = 1857 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1858 .size = sizeof(XSaveBNDCSR) }, 1859 [XSTATE_OPMASK_BIT] = 1860 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1861 .size = sizeof(XSaveOpmask) }, 1862 [XSTATE_ZMM_Hi256_BIT] = 1863 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1864 .size = sizeof(XSaveZMM_Hi256) }, 1865 [XSTATE_Hi16_ZMM_BIT] = 1866 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1867 .size = sizeof(XSaveHi16_ZMM) }, 1868 [XSTATE_PKRU_BIT] = 1869 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1870 .size = sizeof(XSavePKRU) }, 1871 [XSTATE_ARCH_LBR_BIT] = { 1872 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1873 .offset = 0 /*supervisor mode component, offset = 0 */, 1874 .size = sizeof(XSavesArchLBR) }, 1875 [XSTATE_XTILE_CFG_BIT] = { 1876 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1877 .size = sizeof(XSaveXTILECFG), 1878 }, 1879 [XSTATE_XTILE_DATA_BIT] = { 1880 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1881 .size = sizeof(XSaveXTILEDATA) 1882 }, 1883 }; 1884 1885 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1886 { 1887 uint64_t ret = x86_ext_save_areas[0].size; 1888 const ExtSaveArea *esa; 1889 uint32_t offset = 0; 1890 int i; 1891 1892 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1893 esa = &x86_ext_save_areas[i]; 1894 if ((mask >> i) & 1) { 1895 offset = compacted ? ret : esa->offset; 1896 ret = MAX(ret, offset + esa->size); 1897 } 1898 } 1899 return ret; 1900 } 1901 1902 static inline bool accel_uses_host_cpuid(void) 1903 { 1904 return kvm_enabled() || hvf_enabled(); 1905 } 1906 1907 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1908 { 1909 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1910 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1911 } 1912 1913 /* Return name of 32-bit register, from a R_* constant */ 1914 static const char *get_register_name_32(unsigned int reg) 1915 { 1916 if (reg >= CPU_NB_REGS32) { 1917 return NULL; 1918 } 1919 return x86_reg_info_32[reg].name; 1920 } 1921 1922 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1923 { 1924 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1925 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1926 } 1927 1928 /* 1929 * Returns the set of feature flags that are supported and migratable by 1930 * QEMU, for a given FeatureWord. 1931 */ 1932 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1933 { 1934 FeatureWordInfo *wi = &feature_word_info[w]; 1935 CPUX86State *env = &cpu->env; 1936 uint64_t r = 0; 1937 int i; 1938 1939 for (i = 0; i < 64; i++) { 1940 uint64_t f = 1ULL << i; 1941 1942 /* If the feature name is known, it is implicitly considered migratable, 1943 * unless it is explicitly set in unmigratable_flags */ 1944 if ((wi->migratable_flags & f) || 1945 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1946 r |= f; 1947 } 1948 } 1949 1950 /* when tsc-khz is set explicitly, invtsc is migratable */ 1951 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1952 r |= CPUID_APM_INVTSC; 1953 } 1954 1955 return r; 1956 } 1957 1958 void host_cpuid(uint32_t function, uint32_t count, 1959 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1960 { 1961 uint32_t vec[4]; 1962 1963 #ifdef __x86_64__ 1964 asm volatile("cpuid" 1965 : "=a"(vec[0]), "=b"(vec[1]), 1966 "=c"(vec[2]), "=d"(vec[3]) 1967 : "0"(function), "c"(count) : "cc"); 1968 #elif defined(__i386__) 1969 asm volatile("pusha \n\t" 1970 "cpuid \n\t" 1971 "mov %%eax, 0(%2) \n\t" 1972 "mov %%ebx, 4(%2) \n\t" 1973 "mov %%ecx, 8(%2) \n\t" 1974 "mov %%edx, 12(%2) \n\t" 1975 "popa" 1976 : : "a"(function), "c"(count), "S"(vec) 1977 : "memory", "cc"); 1978 #else 1979 abort(); 1980 #endif 1981 1982 if (eax) 1983 *eax = vec[0]; 1984 if (ebx) 1985 *ebx = vec[1]; 1986 if (ecx) 1987 *ecx = vec[2]; 1988 if (edx) 1989 *edx = vec[3]; 1990 } 1991 1992 /* CPU class name definitions: */ 1993 1994 /* Return type name for a given CPU model name 1995 * Caller is responsible for freeing the returned string. 1996 */ 1997 static char *x86_cpu_type_name(const char *model_name) 1998 { 1999 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 2000 } 2001 2002 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2003 { 2004 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2005 return object_class_by_name(typename); 2006 } 2007 2008 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2009 { 2010 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2011 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2012 return cpu_model_from_type(class_name); 2013 } 2014 2015 typedef struct X86CPUVersionDefinition { 2016 X86CPUVersion version; 2017 const char *alias; 2018 const char *note; 2019 PropValue *props; 2020 const CPUCaches *const cache_info; 2021 } X86CPUVersionDefinition; 2022 2023 /* Base definition for a CPU model */ 2024 typedef struct X86CPUDefinition { 2025 const char *name; 2026 uint32_t level; 2027 uint32_t xlevel; 2028 /* vendor is zero-terminated, 12 character ASCII string */ 2029 char vendor[CPUID_VENDOR_SZ + 1]; 2030 int family; 2031 int model; 2032 int stepping; 2033 uint8_t avx10_version; 2034 FeatureWordArray features; 2035 const char *model_id; 2036 const CPUCaches *const cache_info; 2037 /* 2038 * Definitions for alternative versions of CPU model. 2039 * List is terminated by item with version == 0. 2040 * If NULL, version 1 will be registered automatically. 2041 */ 2042 const X86CPUVersionDefinition *versions; 2043 const char *deprecation_note; 2044 } X86CPUDefinition; 2045 2046 /* Reference to a specific CPU model version */ 2047 struct X86CPUModel { 2048 /* Base CPU definition */ 2049 const X86CPUDefinition *cpudef; 2050 /* CPU model version */ 2051 X86CPUVersion version; 2052 const char *note; 2053 /* 2054 * If true, this is an alias CPU model. 2055 * This matters only for "-cpu help" and query-cpu-definitions 2056 */ 2057 bool is_alias; 2058 }; 2059 2060 /* Get full model name for CPU version */ 2061 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2062 X86CPUVersion version) 2063 { 2064 assert(version > 0); 2065 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2066 } 2067 2068 static const X86CPUVersionDefinition * 2069 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2070 { 2071 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2072 static const X86CPUVersionDefinition default_version_list[] = { 2073 { 1 }, 2074 { /* end of list */ } 2075 }; 2076 2077 return def->versions ?: default_version_list; 2078 } 2079 2080 static const CPUCaches epyc_cache_info = { 2081 .l1d_cache = &(CPUCacheInfo) { 2082 .type = DATA_CACHE, 2083 .level = 1, 2084 .size = 32 * KiB, 2085 .line_size = 64, 2086 .associativity = 8, 2087 .partitions = 1, 2088 .sets = 64, 2089 .lines_per_tag = 1, 2090 .self_init = 1, 2091 .no_invd_sharing = true, 2092 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2093 }, 2094 .l1i_cache = &(CPUCacheInfo) { 2095 .type = INSTRUCTION_CACHE, 2096 .level = 1, 2097 .size = 64 * KiB, 2098 .line_size = 64, 2099 .associativity = 4, 2100 .partitions = 1, 2101 .sets = 256, 2102 .lines_per_tag = 1, 2103 .self_init = 1, 2104 .no_invd_sharing = true, 2105 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2106 }, 2107 .l2_cache = &(CPUCacheInfo) { 2108 .type = UNIFIED_CACHE, 2109 .level = 2, 2110 .size = 512 * KiB, 2111 .line_size = 64, 2112 .associativity = 8, 2113 .partitions = 1, 2114 .sets = 1024, 2115 .lines_per_tag = 1, 2116 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2117 }, 2118 .l3_cache = &(CPUCacheInfo) { 2119 .type = UNIFIED_CACHE, 2120 .level = 3, 2121 .size = 8 * MiB, 2122 .line_size = 64, 2123 .associativity = 16, 2124 .partitions = 1, 2125 .sets = 8192, 2126 .lines_per_tag = 1, 2127 .self_init = true, 2128 .inclusive = true, 2129 .complex_indexing = true, 2130 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2131 }, 2132 }; 2133 2134 static CPUCaches epyc_v4_cache_info = { 2135 .l1d_cache = &(CPUCacheInfo) { 2136 .type = DATA_CACHE, 2137 .level = 1, 2138 .size = 32 * KiB, 2139 .line_size = 64, 2140 .associativity = 8, 2141 .partitions = 1, 2142 .sets = 64, 2143 .lines_per_tag = 1, 2144 .self_init = 1, 2145 .no_invd_sharing = true, 2146 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2147 }, 2148 .l1i_cache = &(CPUCacheInfo) { 2149 .type = INSTRUCTION_CACHE, 2150 .level = 1, 2151 .size = 64 * KiB, 2152 .line_size = 64, 2153 .associativity = 4, 2154 .partitions = 1, 2155 .sets = 256, 2156 .lines_per_tag = 1, 2157 .self_init = 1, 2158 .no_invd_sharing = true, 2159 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2160 }, 2161 .l2_cache = &(CPUCacheInfo) { 2162 .type = UNIFIED_CACHE, 2163 .level = 2, 2164 .size = 512 * KiB, 2165 .line_size = 64, 2166 .associativity = 8, 2167 .partitions = 1, 2168 .sets = 1024, 2169 .lines_per_tag = 1, 2170 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2171 }, 2172 .l3_cache = &(CPUCacheInfo) { 2173 .type = UNIFIED_CACHE, 2174 .level = 3, 2175 .size = 8 * MiB, 2176 .line_size = 64, 2177 .associativity = 16, 2178 .partitions = 1, 2179 .sets = 8192, 2180 .lines_per_tag = 1, 2181 .self_init = true, 2182 .inclusive = true, 2183 .complex_indexing = false, 2184 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2185 }, 2186 }; 2187 2188 static const CPUCaches epyc_rome_cache_info = { 2189 .l1d_cache = &(CPUCacheInfo) { 2190 .type = DATA_CACHE, 2191 .level = 1, 2192 .size = 32 * KiB, 2193 .line_size = 64, 2194 .associativity = 8, 2195 .partitions = 1, 2196 .sets = 64, 2197 .lines_per_tag = 1, 2198 .self_init = 1, 2199 .no_invd_sharing = true, 2200 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2201 }, 2202 .l1i_cache = &(CPUCacheInfo) { 2203 .type = INSTRUCTION_CACHE, 2204 .level = 1, 2205 .size = 32 * KiB, 2206 .line_size = 64, 2207 .associativity = 8, 2208 .partitions = 1, 2209 .sets = 64, 2210 .lines_per_tag = 1, 2211 .self_init = 1, 2212 .no_invd_sharing = true, 2213 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2214 }, 2215 .l2_cache = &(CPUCacheInfo) { 2216 .type = UNIFIED_CACHE, 2217 .level = 2, 2218 .size = 512 * KiB, 2219 .line_size = 64, 2220 .associativity = 8, 2221 .partitions = 1, 2222 .sets = 1024, 2223 .lines_per_tag = 1, 2224 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2225 }, 2226 .l3_cache = &(CPUCacheInfo) { 2227 .type = UNIFIED_CACHE, 2228 .level = 3, 2229 .size = 16 * MiB, 2230 .line_size = 64, 2231 .associativity = 16, 2232 .partitions = 1, 2233 .sets = 16384, 2234 .lines_per_tag = 1, 2235 .self_init = true, 2236 .inclusive = true, 2237 .complex_indexing = true, 2238 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2239 }, 2240 }; 2241 2242 static const CPUCaches epyc_rome_v3_cache_info = { 2243 .l1d_cache = &(CPUCacheInfo) { 2244 .type = DATA_CACHE, 2245 .level = 1, 2246 .size = 32 * KiB, 2247 .line_size = 64, 2248 .associativity = 8, 2249 .partitions = 1, 2250 .sets = 64, 2251 .lines_per_tag = 1, 2252 .self_init = 1, 2253 .no_invd_sharing = true, 2254 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2255 }, 2256 .l1i_cache = &(CPUCacheInfo) { 2257 .type = INSTRUCTION_CACHE, 2258 .level = 1, 2259 .size = 32 * KiB, 2260 .line_size = 64, 2261 .associativity = 8, 2262 .partitions = 1, 2263 .sets = 64, 2264 .lines_per_tag = 1, 2265 .self_init = 1, 2266 .no_invd_sharing = true, 2267 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2268 }, 2269 .l2_cache = &(CPUCacheInfo) { 2270 .type = UNIFIED_CACHE, 2271 .level = 2, 2272 .size = 512 * KiB, 2273 .line_size = 64, 2274 .associativity = 8, 2275 .partitions = 1, 2276 .sets = 1024, 2277 .lines_per_tag = 1, 2278 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2279 }, 2280 .l3_cache = &(CPUCacheInfo) { 2281 .type = UNIFIED_CACHE, 2282 .level = 3, 2283 .size = 16 * MiB, 2284 .line_size = 64, 2285 .associativity = 16, 2286 .partitions = 1, 2287 .sets = 16384, 2288 .lines_per_tag = 1, 2289 .self_init = true, 2290 .inclusive = true, 2291 .complex_indexing = false, 2292 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2293 }, 2294 }; 2295 2296 static const CPUCaches epyc_milan_cache_info = { 2297 .l1d_cache = &(CPUCacheInfo) { 2298 .type = DATA_CACHE, 2299 .level = 1, 2300 .size = 32 * KiB, 2301 .line_size = 64, 2302 .associativity = 8, 2303 .partitions = 1, 2304 .sets = 64, 2305 .lines_per_tag = 1, 2306 .self_init = 1, 2307 .no_invd_sharing = true, 2308 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2309 }, 2310 .l1i_cache = &(CPUCacheInfo) { 2311 .type = INSTRUCTION_CACHE, 2312 .level = 1, 2313 .size = 32 * KiB, 2314 .line_size = 64, 2315 .associativity = 8, 2316 .partitions = 1, 2317 .sets = 64, 2318 .lines_per_tag = 1, 2319 .self_init = 1, 2320 .no_invd_sharing = true, 2321 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2322 }, 2323 .l2_cache = &(CPUCacheInfo) { 2324 .type = UNIFIED_CACHE, 2325 .level = 2, 2326 .size = 512 * KiB, 2327 .line_size = 64, 2328 .associativity = 8, 2329 .partitions = 1, 2330 .sets = 1024, 2331 .lines_per_tag = 1, 2332 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2333 }, 2334 .l3_cache = &(CPUCacheInfo) { 2335 .type = UNIFIED_CACHE, 2336 .level = 3, 2337 .size = 32 * MiB, 2338 .line_size = 64, 2339 .associativity = 16, 2340 .partitions = 1, 2341 .sets = 32768, 2342 .lines_per_tag = 1, 2343 .self_init = true, 2344 .inclusive = true, 2345 .complex_indexing = true, 2346 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2347 }, 2348 }; 2349 2350 static const CPUCaches epyc_milan_v2_cache_info = { 2351 .l1d_cache = &(CPUCacheInfo) { 2352 .type = DATA_CACHE, 2353 .level = 1, 2354 .size = 32 * KiB, 2355 .line_size = 64, 2356 .associativity = 8, 2357 .partitions = 1, 2358 .sets = 64, 2359 .lines_per_tag = 1, 2360 .self_init = 1, 2361 .no_invd_sharing = true, 2362 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2363 }, 2364 .l1i_cache = &(CPUCacheInfo) { 2365 .type = INSTRUCTION_CACHE, 2366 .level = 1, 2367 .size = 32 * KiB, 2368 .line_size = 64, 2369 .associativity = 8, 2370 .partitions = 1, 2371 .sets = 64, 2372 .lines_per_tag = 1, 2373 .self_init = 1, 2374 .no_invd_sharing = true, 2375 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2376 }, 2377 .l2_cache = &(CPUCacheInfo) { 2378 .type = UNIFIED_CACHE, 2379 .level = 2, 2380 .size = 512 * KiB, 2381 .line_size = 64, 2382 .associativity = 8, 2383 .partitions = 1, 2384 .sets = 1024, 2385 .lines_per_tag = 1, 2386 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2387 }, 2388 .l3_cache = &(CPUCacheInfo) { 2389 .type = UNIFIED_CACHE, 2390 .level = 3, 2391 .size = 32 * MiB, 2392 .line_size = 64, 2393 .associativity = 16, 2394 .partitions = 1, 2395 .sets = 32768, 2396 .lines_per_tag = 1, 2397 .self_init = true, 2398 .inclusive = true, 2399 .complex_indexing = false, 2400 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2401 }, 2402 }; 2403 2404 static const CPUCaches epyc_genoa_cache_info = { 2405 .l1d_cache = &(CPUCacheInfo) { 2406 .type = DATA_CACHE, 2407 .level = 1, 2408 .size = 32 * KiB, 2409 .line_size = 64, 2410 .associativity = 8, 2411 .partitions = 1, 2412 .sets = 64, 2413 .lines_per_tag = 1, 2414 .self_init = 1, 2415 .no_invd_sharing = true, 2416 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2417 }, 2418 .l1i_cache = &(CPUCacheInfo) { 2419 .type = INSTRUCTION_CACHE, 2420 .level = 1, 2421 .size = 32 * KiB, 2422 .line_size = 64, 2423 .associativity = 8, 2424 .partitions = 1, 2425 .sets = 64, 2426 .lines_per_tag = 1, 2427 .self_init = 1, 2428 .no_invd_sharing = true, 2429 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2430 }, 2431 .l2_cache = &(CPUCacheInfo) { 2432 .type = UNIFIED_CACHE, 2433 .level = 2, 2434 .size = 1 * MiB, 2435 .line_size = 64, 2436 .associativity = 8, 2437 .partitions = 1, 2438 .sets = 2048, 2439 .lines_per_tag = 1, 2440 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2441 }, 2442 .l3_cache = &(CPUCacheInfo) { 2443 .type = UNIFIED_CACHE, 2444 .level = 3, 2445 .size = 32 * MiB, 2446 .line_size = 64, 2447 .associativity = 16, 2448 .partitions = 1, 2449 .sets = 32768, 2450 .lines_per_tag = 1, 2451 .self_init = true, 2452 .inclusive = true, 2453 .complex_indexing = false, 2454 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2455 }, 2456 }; 2457 2458 /* The following VMX features are not supported by KVM and are left out in the 2459 * CPU definitions: 2460 * 2461 * Dual-monitor support (all processors) 2462 * Entry to SMM 2463 * Deactivate dual-monitor treatment 2464 * Number of CR3-target values 2465 * Shutdown activity state 2466 * Wait-for-SIPI activity state 2467 * PAUSE-loop exiting (Westmere and newer) 2468 * EPT-violation #VE (Broadwell and newer) 2469 * Inject event with insn length=0 (Skylake and newer) 2470 * Conceal non-root operation from PT 2471 * Conceal VM exits from PT 2472 * Conceal VM entries from PT 2473 * Enable ENCLS exiting 2474 * Mode-based execute control (XS/XU) 2475 * TSC scaling (Skylake Server and newer) 2476 * GPA translation for PT (IceLake and newer) 2477 * User wait and pause 2478 * ENCLV exiting 2479 * Load IA32_RTIT_CTL 2480 * Clear IA32_RTIT_CTL 2481 * Advanced VM-exit information for EPT violations 2482 * Sub-page write permissions 2483 * PT in VMX operation 2484 */ 2485 2486 static const X86CPUDefinition builtin_x86_defs[] = { 2487 { 2488 .name = "qemu64", 2489 .level = 0xd, 2490 .vendor = CPUID_VENDOR_AMD, 2491 .family = 15, 2492 .model = 107, 2493 .stepping = 1, 2494 .features[FEAT_1_EDX] = 2495 PPRO_FEATURES | 2496 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2497 CPUID_PSE36, 2498 .features[FEAT_1_ECX] = 2499 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2500 .features[FEAT_8000_0001_EDX] = 2501 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2502 .features[FEAT_8000_0001_ECX] = 2503 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2504 .xlevel = 0x8000000A, 2505 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2506 }, 2507 { 2508 .name = "phenom", 2509 .level = 5, 2510 .vendor = CPUID_VENDOR_AMD, 2511 .family = 16, 2512 .model = 2, 2513 .stepping = 3, 2514 /* Missing: CPUID_HT */ 2515 .features[FEAT_1_EDX] = 2516 PPRO_FEATURES | 2517 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2518 CPUID_PSE36 | CPUID_VME, 2519 .features[FEAT_1_ECX] = 2520 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2521 CPUID_EXT_POPCNT, 2522 .features[FEAT_8000_0001_EDX] = 2523 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2524 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2525 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2526 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2527 CPUID_EXT3_CR8LEG, 2528 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2529 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2530 .features[FEAT_8000_0001_ECX] = 2531 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2532 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2533 /* Missing: CPUID_SVM_LBRV */ 2534 .features[FEAT_SVM] = 2535 CPUID_SVM_NPT, 2536 .xlevel = 0x8000001A, 2537 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2538 }, 2539 { 2540 .name = "core2duo", 2541 .level = 10, 2542 .vendor = CPUID_VENDOR_INTEL, 2543 .family = 6, 2544 .model = 15, 2545 .stepping = 11, 2546 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2547 .features[FEAT_1_EDX] = 2548 PPRO_FEATURES | 2549 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2550 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2551 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2552 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2553 .features[FEAT_1_ECX] = 2554 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2555 CPUID_EXT_CX16, 2556 .features[FEAT_8000_0001_EDX] = 2557 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2558 .features[FEAT_8000_0001_ECX] = 2559 CPUID_EXT3_LAHF_LM, 2560 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2561 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2562 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2563 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2564 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2565 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2566 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2567 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2568 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2569 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2570 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2571 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2572 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2573 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2574 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2575 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2576 .features[FEAT_VMX_SECONDARY_CTLS] = 2577 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2578 .xlevel = 0x80000008, 2579 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2580 }, 2581 { 2582 .name = "kvm64", 2583 .level = 0xd, 2584 .vendor = CPUID_VENDOR_INTEL, 2585 .family = 15, 2586 .model = 6, 2587 .stepping = 1, 2588 /* Missing: CPUID_HT */ 2589 .features[FEAT_1_EDX] = 2590 PPRO_FEATURES | CPUID_VME | 2591 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2592 CPUID_PSE36, 2593 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2594 .features[FEAT_1_ECX] = 2595 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2596 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2597 .features[FEAT_8000_0001_EDX] = 2598 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2599 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2600 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2601 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2602 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2603 .features[FEAT_8000_0001_ECX] = 2604 0, 2605 /* VMX features from Cedar Mill/Prescott */ 2606 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2607 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2608 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2609 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2610 VMX_PIN_BASED_NMI_EXITING, 2611 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2612 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2613 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2614 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2615 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2616 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2617 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2618 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2619 .xlevel = 0x80000008, 2620 .model_id = "Common KVM processor" 2621 }, 2622 { 2623 .name = "qemu32", 2624 .level = 4, 2625 .vendor = CPUID_VENDOR_INTEL, 2626 .family = 6, 2627 .model = 6, 2628 .stepping = 3, 2629 .features[FEAT_1_EDX] = 2630 PPRO_FEATURES, 2631 .features[FEAT_1_ECX] = 2632 CPUID_EXT_SSE3, 2633 .xlevel = 0x80000004, 2634 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2635 }, 2636 { 2637 .name = "kvm32", 2638 .level = 5, 2639 .vendor = CPUID_VENDOR_INTEL, 2640 .family = 15, 2641 .model = 6, 2642 .stepping = 1, 2643 .features[FEAT_1_EDX] = 2644 PPRO_FEATURES | CPUID_VME | 2645 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2646 .features[FEAT_1_ECX] = 2647 CPUID_EXT_SSE3, 2648 .features[FEAT_8000_0001_ECX] = 2649 0, 2650 /* VMX features from Yonah */ 2651 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2652 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2653 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2654 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2655 VMX_PIN_BASED_NMI_EXITING, 2656 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2657 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2658 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2659 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2660 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2661 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2662 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2663 .xlevel = 0x80000008, 2664 .model_id = "Common 32-bit KVM processor" 2665 }, 2666 { 2667 .name = "coreduo", 2668 .level = 10, 2669 .vendor = CPUID_VENDOR_INTEL, 2670 .family = 6, 2671 .model = 14, 2672 .stepping = 8, 2673 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2674 .features[FEAT_1_EDX] = 2675 PPRO_FEATURES | CPUID_VME | 2676 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2677 CPUID_SS, 2678 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2679 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2680 .features[FEAT_1_ECX] = 2681 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2682 .features[FEAT_8000_0001_EDX] = 2683 CPUID_EXT2_NX, 2684 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2685 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2686 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2687 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2688 VMX_PIN_BASED_NMI_EXITING, 2689 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2690 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2691 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2692 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2693 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2694 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2695 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2696 .xlevel = 0x80000008, 2697 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2698 }, 2699 { 2700 .name = "486", 2701 .level = 1, 2702 .vendor = CPUID_VENDOR_INTEL, 2703 .family = 4, 2704 .model = 8, 2705 .stepping = 0, 2706 .features[FEAT_1_EDX] = 2707 I486_FEATURES, 2708 .xlevel = 0, 2709 .model_id = "", 2710 }, 2711 { 2712 .name = "pentium", 2713 .level = 1, 2714 .vendor = CPUID_VENDOR_INTEL, 2715 .family = 5, 2716 .model = 4, 2717 .stepping = 3, 2718 .features[FEAT_1_EDX] = 2719 PENTIUM_FEATURES, 2720 .xlevel = 0, 2721 .model_id = "", 2722 }, 2723 { 2724 .name = "pentium2", 2725 .level = 2, 2726 .vendor = CPUID_VENDOR_INTEL, 2727 .family = 6, 2728 .model = 5, 2729 .stepping = 2, 2730 .features[FEAT_1_EDX] = 2731 PENTIUM2_FEATURES, 2732 .xlevel = 0, 2733 .model_id = "", 2734 }, 2735 { 2736 .name = "pentium3", 2737 .level = 3, 2738 .vendor = CPUID_VENDOR_INTEL, 2739 .family = 6, 2740 .model = 7, 2741 .stepping = 3, 2742 .features[FEAT_1_EDX] = 2743 PENTIUM3_FEATURES, 2744 .xlevel = 0, 2745 .model_id = "", 2746 }, 2747 { 2748 .name = "athlon", 2749 .level = 2, 2750 .vendor = CPUID_VENDOR_AMD, 2751 .family = 6, 2752 .model = 2, 2753 .stepping = 3, 2754 .features[FEAT_1_EDX] = 2755 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2756 CPUID_MCA, 2757 .features[FEAT_8000_0001_EDX] = 2758 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2759 .xlevel = 0x80000008, 2760 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2761 }, 2762 { 2763 .name = "n270", 2764 .level = 10, 2765 .vendor = CPUID_VENDOR_INTEL, 2766 .family = 6, 2767 .model = 28, 2768 .stepping = 2, 2769 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2770 .features[FEAT_1_EDX] = 2771 PPRO_FEATURES | 2772 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2773 CPUID_ACPI | CPUID_SS, 2774 /* Some CPUs got no CPUID_SEP */ 2775 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2776 * CPUID_EXT_XTPR */ 2777 .features[FEAT_1_ECX] = 2778 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2779 CPUID_EXT_MOVBE, 2780 .features[FEAT_8000_0001_EDX] = 2781 CPUID_EXT2_NX, 2782 .features[FEAT_8000_0001_ECX] = 2783 CPUID_EXT3_LAHF_LM, 2784 .xlevel = 0x80000008, 2785 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2786 }, 2787 { 2788 .name = "Conroe", 2789 .level = 10, 2790 .vendor = CPUID_VENDOR_INTEL, 2791 .family = 6, 2792 .model = 15, 2793 .stepping = 3, 2794 .features[FEAT_1_EDX] = 2795 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2796 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2797 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2798 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2799 CPUID_DE | CPUID_FP87, 2800 .features[FEAT_1_ECX] = 2801 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2802 .features[FEAT_8000_0001_EDX] = 2803 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2804 .features[FEAT_8000_0001_ECX] = 2805 CPUID_EXT3_LAHF_LM, 2806 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2807 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2808 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2809 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2810 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2811 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2812 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2813 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2814 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2815 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2816 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2817 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2818 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2819 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2820 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2821 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2822 .features[FEAT_VMX_SECONDARY_CTLS] = 2823 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2824 .xlevel = 0x80000008, 2825 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2826 }, 2827 { 2828 .name = "Penryn", 2829 .level = 10, 2830 .vendor = CPUID_VENDOR_INTEL, 2831 .family = 6, 2832 .model = 23, 2833 .stepping = 3, 2834 .features[FEAT_1_EDX] = 2835 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2836 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2837 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2838 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2839 CPUID_DE | CPUID_FP87, 2840 .features[FEAT_1_ECX] = 2841 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2842 CPUID_EXT_SSE3, 2843 .features[FEAT_8000_0001_EDX] = 2844 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2845 .features[FEAT_8000_0001_ECX] = 2846 CPUID_EXT3_LAHF_LM, 2847 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2848 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2849 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2850 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2851 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2852 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2853 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2854 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2855 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2856 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2857 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2858 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2859 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2860 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2861 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2862 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2863 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2864 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2865 .features[FEAT_VMX_SECONDARY_CTLS] = 2866 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2867 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2868 .xlevel = 0x80000008, 2869 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2870 }, 2871 { 2872 .name = "Nehalem", 2873 .level = 11, 2874 .vendor = CPUID_VENDOR_INTEL, 2875 .family = 6, 2876 .model = 26, 2877 .stepping = 3, 2878 .features[FEAT_1_EDX] = 2879 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2880 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2881 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2882 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2883 CPUID_DE | CPUID_FP87, 2884 .features[FEAT_1_ECX] = 2885 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2886 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2887 .features[FEAT_8000_0001_EDX] = 2888 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2889 .features[FEAT_8000_0001_ECX] = 2890 CPUID_EXT3_LAHF_LM, 2891 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2892 MSR_VMX_BASIC_TRUE_CTLS, 2893 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2894 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2895 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2896 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2897 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2898 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2899 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2900 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2901 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2902 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2903 .features[FEAT_VMX_EXIT_CTLS] = 2904 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2905 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2906 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2907 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2908 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2909 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2910 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2911 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2912 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2913 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2914 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2915 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2916 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2917 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2918 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2919 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2920 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2921 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2922 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2923 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2924 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2925 .features[FEAT_VMX_SECONDARY_CTLS] = 2926 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2927 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2928 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2929 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2930 VMX_SECONDARY_EXEC_ENABLE_VPID, 2931 .xlevel = 0x80000008, 2932 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2933 .versions = (X86CPUVersionDefinition[]) { 2934 { .version = 1 }, 2935 { 2936 .version = 2, 2937 .alias = "Nehalem-IBRS", 2938 .props = (PropValue[]) { 2939 { "spec-ctrl", "on" }, 2940 { "model-id", 2941 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2942 { /* end of list */ } 2943 } 2944 }, 2945 { /* end of list */ } 2946 } 2947 }, 2948 { 2949 .name = "Westmere", 2950 .level = 11, 2951 .vendor = CPUID_VENDOR_INTEL, 2952 .family = 6, 2953 .model = 44, 2954 .stepping = 1, 2955 .features[FEAT_1_EDX] = 2956 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2957 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2958 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2959 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2960 CPUID_DE | CPUID_FP87, 2961 .features[FEAT_1_ECX] = 2962 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2963 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2964 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2965 .features[FEAT_8000_0001_EDX] = 2966 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2967 .features[FEAT_8000_0001_ECX] = 2968 CPUID_EXT3_LAHF_LM, 2969 .features[FEAT_6_EAX] = 2970 CPUID_6_EAX_ARAT, 2971 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2972 MSR_VMX_BASIC_TRUE_CTLS, 2973 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2974 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2975 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2976 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2977 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2978 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2979 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2980 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2981 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2982 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2983 .features[FEAT_VMX_EXIT_CTLS] = 2984 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2985 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2986 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2987 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2988 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2989 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2990 MSR_VMX_MISC_STORE_LMA, 2991 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2992 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2993 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2994 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2995 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2996 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2997 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2998 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2999 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3000 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3001 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3002 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3003 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3004 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3005 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3006 .features[FEAT_VMX_SECONDARY_CTLS] = 3007 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3008 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3009 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3010 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3011 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3012 .xlevel = 0x80000008, 3013 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3014 .versions = (X86CPUVersionDefinition[]) { 3015 { .version = 1 }, 3016 { 3017 .version = 2, 3018 .alias = "Westmere-IBRS", 3019 .props = (PropValue[]) { 3020 { "spec-ctrl", "on" }, 3021 { "model-id", 3022 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3023 { /* end of list */ } 3024 } 3025 }, 3026 { /* end of list */ } 3027 } 3028 }, 3029 { 3030 .name = "SandyBridge", 3031 .level = 0xd, 3032 .vendor = CPUID_VENDOR_INTEL, 3033 .family = 6, 3034 .model = 42, 3035 .stepping = 1, 3036 .features[FEAT_1_EDX] = 3037 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3038 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3039 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3040 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3041 CPUID_DE | CPUID_FP87, 3042 .features[FEAT_1_ECX] = 3043 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3044 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3045 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3046 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3047 CPUID_EXT_SSE3, 3048 .features[FEAT_8000_0001_EDX] = 3049 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3050 CPUID_EXT2_SYSCALL, 3051 .features[FEAT_8000_0001_ECX] = 3052 CPUID_EXT3_LAHF_LM, 3053 .features[FEAT_XSAVE] = 3054 CPUID_XSAVE_XSAVEOPT, 3055 .features[FEAT_6_EAX] = 3056 CPUID_6_EAX_ARAT, 3057 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3058 MSR_VMX_BASIC_TRUE_CTLS, 3059 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3060 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3061 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3062 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3063 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3064 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3065 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3066 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3067 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3068 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3069 .features[FEAT_VMX_EXIT_CTLS] = 3070 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3071 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3072 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3073 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3074 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3075 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3076 MSR_VMX_MISC_STORE_LMA, 3077 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3078 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3079 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3080 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3081 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3082 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3083 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3084 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3085 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3086 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3087 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3088 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3089 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3090 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3091 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3092 .features[FEAT_VMX_SECONDARY_CTLS] = 3093 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3094 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3095 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3096 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3097 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3098 .xlevel = 0x80000008, 3099 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3100 .versions = (X86CPUVersionDefinition[]) { 3101 { .version = 1 }, 3102 { 3103 .version = 2, 3104 .alias = "SandyBridge-IBRS", 3105 .props = (PropValue[]) { 3106 { "spec-ctrl", "on" }, 3107 { "model-id", 3108 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3109 { /* end of list */ } 3110 } 3111 }, 3112 { /* end of list */ } 3113 } 3114 }, 3115 { 3116 .name = "IvyBridge", 3117 .level = 0xd, 3118 .vendor = CPUID_VENDOR_INTEL, 3119 .family = 6, 3120 .model = 58, 3121 .stepping = 9, 3122 .features[FEAT_1_EDX] = 3123 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3124 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3125 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3126 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3127 CPUID_DE | CPUID_FP87, 3128 .features[FEAT_1_ECX] = 3129 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3130 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3131 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3132 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3133 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3134 .features[FEAT_7_0_EBX] = 3135 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3136 CPUID_7_0_EBX_ERMS, 3137 .features[FEAT_8000_0001_EDX] = 3138 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3139 CPUID_EXT2_SYSCALL, 3140 .features[FEAT_8000_0001_ECX] = 3141 CPUID_EXT3_LAHF_LM, 3142 .features[FEAT_XSAVE] = 3143 CPUID_XSAVE_XSAVEOPT, 3144 .features[FEAT_6_EAX] = 3145 CPUID_6_EAX_ARAT, 3146 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3147 MSR_VMX_BASIC_TRUE_CTLS, 3148 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3149 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3150 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3151 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3152 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3153 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3154 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3155 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3156 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3157 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3158 .features[FEAT_VMX_EXIT_CTLS] = 3159 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3160 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3161 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3162 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3163 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3164 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3165 MSR_VMX_MISC_STORE_LMA, 3166 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3167 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3168 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3169 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3170 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3171 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3172 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3173 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3174 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3175 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3176 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3177 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3178 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3179 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3180 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3181 .features[FEAT_VMX_SECONDARY_CTLS] = 3182 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3183 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3184 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3185 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3186 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3187 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3188 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3189 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3190 .xlevel = 0x80000008, 3191 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3192 .versions = (X86CPUVersionDefinition[]) { 3193 { .version = 1 }, 3194 { 3195 .version = 2, 3196 .alias = "IvyBridge-IBRS", 3197 .props = (PropValue[]) { 3198 { "spec-ctrl", "on" }, 3199 { "model-id", 3200 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3201 { /* end of list */ } 3202 } 3203 }, 3204 { /* end of list */ } 3205 } 3206 }, 3207 { 3208 .name = "Haswell", 3209 .level = 0xd, 3210 .vendor = CPUID_VENDOR_INTEL, 3211 .family = 6, 3212 .model = 60, 3213 .stepping = 4, 3214 .features[FEAT_1_EDX] = 3215 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3216 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3217 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3218 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3219 CPUID_DE | CPUID_FP87, 3220 .features[FEAT_1_ECX] = 3221 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3222 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3223 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3224 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3225 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3226 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3227 .features[FEAT_8000_0001_EDX] = 3228 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3229 CPUID_EXT2_SYSCALL, 3230 .features[FEAT_8000_0001_ECX] = 3231 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3232 .features[FEAT_7_0_EBX] = 3233 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3234 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3235 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3236 CPUID_7_0_EBX_RTM, 3237 .features[FEAT_XSAVE] = 3238 CPUID_XSAVE_XSAVEOPT, 3239 .features[FEAT_6_EAX] = 3240 CPUID_6_EAX_ARAT, 3241 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3242 MSR_VMX_BASIC_TRUE_CTLS, 3243 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3244 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3245 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3246 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3247 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3248 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3249 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3250 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3251 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3252 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3253 .features[FEAT_VMX_EXIT_CTLS] = 3254 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3255 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3256 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3257 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3258 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3259 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3260 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3261 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3262 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3263 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3264 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3265 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3266 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3267 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3268 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3269 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3270 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3271 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3272 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3273 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3274 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3275 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3276 .features[FEAT_VMX_SECONDARY_CTLS] = 3277 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3278 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3279 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3280 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3281 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3282 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3283 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3284 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3285 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3286 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3287 .xlevel = 0x80000008, 3288 .model_id = "Intel Core Processor (Haswell)", 3289 .versions = (X86CPUVersionDefinition[]) { 3290 { .version = 1 }, 3291 { 3292 .version = 2, 3293 .alias = "Haswell-noTSX", 3294 .props = (PropValue[]) { 3295 { "hle", "off" }, 3296 { "rtm", "off" }, 3297 { "stepping", "1" }, 3298 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3299 { /* end of list */ } 3300 }, 3301 }, 3302 { 3303 .version = 3, 3304 .alias = "Haswell-IBRS", 3305 .props = (PropValue[]) { 3306 /* Restore TSX features removed by -v2 above */ 3307 { "hle", "on" }, 3308 { "rtm", "on" }, 3309 /* 3310 * Haswell and Haswell-IBRS had stepping=4 in 3311 * QEMU 4.0 and older 3312 */ 3313 { "stepping", "4" }, 3314 { "spec-ctrl", "on" }, 3315 { "model-id", 3316 "Intel Core Processor (Haswell, IBRS)" }, 3317 { /* end of list */ } 3318 } 3319 }, 3320 { 3321 .version = 4, 3322 .alias = "Haswell-noTSX-IBRS", 3323 .props = (PropValue[]) { 3324 { "hle", "off" }, 3325 { "rtm", "off" }, 3326 /* spec-ctrl was already enabled by -v3 above */ 3327 { "stepping", "1" }, 3328 { "model-id", 3329 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3330 { /* end of list */ } 3331 } 3332 }, 3333 { /* end of list */ } 3334 } 3335 }, 3336 { 3337 .name = "Broadwell", 3338 .level = 0xd, 3339 .vendor = CPUID_VENDOR_INTEL, 3340 .family = 6, 3341 .model = 61, 3342 .stepping = 2, 3343 .features[FEAT_1_EDX] = 3344 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3345 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3346 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3347 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3348 CPUID_DE | CPUID_FP87, 3349 .features[FEAT_1_ECX] = 3350 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3351 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3352 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3353 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3354 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3355 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3356 .features[FEAT_8000_0001_EDX] = 3357 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3358 CPUID_EXT2_SYSCALL, 3359 .features[FEAT_8000_0001_ECX] = 3360 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3361 .features[FEAT_7_0_EBX] = 3362 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3363 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3364 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3365 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3366 CPUID_7_0_EBX_SMAP, 3367 .features[FEAT_XSAVE] = 3368 CPUID_XSAVE_XSAVEOPT, 3369 .features[FEAT_6_EAX] = 3370 CPUID_6_EAX_ARAT, 3371 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3372 MSR_VMX_BASIC_TRUE_CTLS, 3373 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3374 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3375 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3376 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3377 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3378 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3379 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3380 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3381 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3382 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3383 .features[FEAT_VMX_EXIT_CTLS] = 3384 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3385 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3386 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3387 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3388 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3389 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3390 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3391 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3392 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3393 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3394 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3395 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3396 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3397 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3398 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3399 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3400 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3401 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3402 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3403 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3404 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3405 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3406 .features[FEAT_VMX_SECONDARY_CTLS] = 3407 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3408 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3409 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3410 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3411 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3412 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3413 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3414 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3415 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3416 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3417 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3418 .xlevel = 0x80000008, 3419 .model_id = "Intel Core Processor (Broadwell)", 3420 .versions = (X86CPUVersionDefinition[]) { 3421 { .version = 1 }, 3422 { 3423 .version = 2, 3424 .alias = "Broadwell-noTSX", 3425 .props = (PropValue[]) { 3426 { "hle", "off" }, 3427 { "rtm", "off" }, 3428 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3429 { /* end of list */ } 3430 }, 3431 }, 3432 { 3433 .version = 3, 3434 .alias = "Broadwell-IBRS", 3435 .props = (PropValue[]) { 3436 /* Restore TSX features removed by -v2 above */ 3437 { "hle", "on" }, 3438 { "rtm", "on" }, 3439 { "spec-ctrl", "on" }, 3440 { "model-id", 3441 "Intel Core Processor (Broadwell, IBRS)" }, 3442 { /* end of list */ } 3443 } 3444 }, 3445 { 3446 .version = 4, 3447 .alias = "Broadwell-noTSX-IBRS", 3448 .props = (PropValue[]) { 3449 { "hle", "off" }, 3450 { "rtm", "off" }, 3451 /* spec-ctrl was already enabled by -v3 above */ 3452 { "model-id", 3453 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3454 { /* end of list */ } 3455 } 3456 }, 3457 { /* end of list */ } 3458 } 3459 }, 3460 { 3461 .name = "Skylake-Client", 3462 .level = 0xd, 3463 .vendor = CPUID_VENDOR_INTEL, 3464 .family = 6, 3465 .model = 94, 3466 .stepping = 3, 3467 .features[FEAT_1_EDX] = 3468 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3469 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3470 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3471 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3472 CPUID_DE | CPUID_FP87, 3473 .features[FEAT_1_ECX] = 3474 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3475 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3476 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3477 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3478 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3479 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3480 .features[FEAT_8000_0001_EDX] = 3481 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3482 CPUID_EXT2_SYSCALL, 3483 .features[FEAT_8000_0001_ECX] = 3484 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3485 .features[FEAT_7_0_EBX] = 3486 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3487 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3488 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3489 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3490 CPUID_7_0_EBX_SMAP, 3491 /* XSAVES is added in version 4 */ 3492 .features[FEAT_XSAVE] = 3493 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3494 CPUID_XSAVE_XGETBV1, 3495 .features[FEAT_6_EAX] = 3496 CPUID_6_EAX_ARAT, 3497 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3498 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3499 MSR_VMX_BASIC_TRUE_CTLS, 3500 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3501 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3502 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3503 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3504 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3505 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3506 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3507 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3508 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3509 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3510 .features[FEAT_VMX_EXIT_CTLS] = 3511 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3512 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3513 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3514 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3515 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3516 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3517 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3518 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3519 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3520 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3521 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3522 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3523 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3524 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3525 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3526 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3527 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3528 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3529 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3530 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3531 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3532 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3533 .features[FEAT_VMX_SECONDARY_CTLS] = 3534 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3535 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3536 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3537 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3538 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3539 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3540 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3541 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3542 .xlevel = 0x80000008, 3543 .model_id = "Intel Core Processor (Skylake)", 3544 .versions = (X86CPUVersionDefinition[]) { 3545 { .version = 1 }, 3546 { 3547 .version = 2, 3548 .alias = "Skylake-Client-IBRS", 3549 .props = (PropValue[]) { 3550 { "spec-ctrl", "on" }, 3551 { "model-id", 3552 "Intel Core Processor (Skylake, IBRS)" }, 3553 { /* end of list */ } 3554 } 3555 }, 3556 { 3557 .version = 3, 3558 .alias = "Skylake-Client-noTSX-IBRS", 3559 .props = (PropValue[]) { 3560 { "hle", "off" }, 3561 { "rtm", "off" }, 3562 { "model-id", 3563 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3564 { /* end of list */ } 3565 } 3566 }, 3567 { 3568 .version = 4, 3569 .note = "IBRS, XSAVES, no TSX", 3570 .props = (PropValue[]) { 3571 { "xsaves", "on" }, 3572 { "vmx-xsaves", "on" }, 3573 { /* end of list */ } 3574 } 3575 }, 3576 { /* end of list */ } 3577 } 3578 }, 3579 { 3580 .name = "Skylake-Server", 3581 .level = 0xd, 3582 .vendor = CPUID_VENDOR_INTEL, 3583 .family = 6, 3584 .model = 85, 3585 .stepping = 4, 3586 .features[FEAT_1_EDX] = 3587 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3588 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3589 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3590 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3591 CPUID_DE | CPUID_FP87, 3592 .features[FEAT_1_ECX] = 3593 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3594 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3595 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3596 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3597 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3598 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3599 .features[FEAT_8000_0001_EDX] = 3600 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3601 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3602 .features[FEAT_8000_0001_ECX] = 3603 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3604 .features[FEAT_7_0_EBX] = 3605 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3606 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3607 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3608 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3609 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3610 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3611 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3612 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3613 .features[FEAT_7_0_ECX] = 3614 CPUID_7_0_ECX_PKU, 3615 /* XSAVES is added in version 5 */ 3616 .features[FEAT_XSAVE] = 3617 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3618 CPUID_XSAVE_XGETBV1, 3619 .features[FEAT_6_EAX] = 3620 CPUID_6_EAX_ARAT, 3621 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3622 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3623 MSR_VMX_BASIC_TRUE_CTLS, 3624 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3625 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3626 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3627 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3628 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3629 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3630 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3631 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3632 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3633 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3634 .features[FEAT_VMX_EXIT_CTLS] = 3635 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3636 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3637 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3638 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3639 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3640 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3641 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3642 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3643 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3644 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3645 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3646 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3647 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3648 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3649 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3650 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3651 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3652 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3653 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3654 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3655 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3656 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3657 .features[FEAT_VMX_SECONDARY_CTLS] = 3658 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3659 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3660 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3661 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3662 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3663 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3664 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3665 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3666 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3667 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3668 .xlevel = 0x80000008, 3669 .model_id = "Intel Xeon Processor (Skylake)", 3670 .versions = (X86CPUVersionDefinition[]) { 3671 { .version = 1 }, 3672 { 3673 .version = 2, 3674 .alias = "Skylake-Server-IBRS", 3675 .props = (PropValue[]) { 3676 /* clflushopt was not added to Skylake-Server-IBRS */ 3677 /* TODO: add -v3 including clflushopt */ 3678 { "clflushopt", "off" }, 3679 { "spec-ctrl", "on" }, 3680 { "model-id", 3681 "Intel Xeon Processor (Skylake, IBRS)" }, 3682 { /* end of list */ } 3683 } 3684 }, 3685 { 3686 .version = 3, 3687 .alias = "Skylake-Server-noTSX-IBRS", 3688 .props = (PropValue[]) { 3689 { "hle", "off" }, 3690 { "rtm", "off" }, 3691 { "model-id", 3692 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3693 { /* end of list */ } 3694 } 3695 }, 3696 { 3697 .version = 4, 3698 .note = "IBRS, EPT switching, no TSX", 3699 .props = (PropValue[]) { 3700 { "vmx-eptp-switching", "on" }, 3701 { /* end of list */ } 3702 } 3703 }, 3704 { 3705 .version = 5, 3706 .note = "IBRS, XSAVES, EPT switching, no TSX", 3707 .props = (PropValue[]) { 3708 { "xsaves", "on" }, 3709 { "vmx-xsaves", "on" }, 3710 { /* end of list */ } 3711 } 3712 }, 3713 { /* end of list */ } 3714 } 3715 }, 3716 { 3717 .name = "Cascadelake-Server", 3718 .level = 0xd, 3719 .vendor = CPUID_VENDOR_INTEL, 3720 .family = 6, 3721 .model = 85, 3722 .stepping = 6, 3723 .features[FEAT_1_EDX] = 3724 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3725 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3726 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3727 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3728 CPUID_DE | CPUID_FP87, 3729 .features[FEAT_1_ECX] = 3730 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3731 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3732 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3733 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3734 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3735 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3736 .features[FEAT_8000_0001_EDX] = 3737 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3738 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3739 .features[FEAT_8000_0001_ECX] = 3740 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3741 .features[FEAT_7_0_EBX] = 3742 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3743 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3744 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3745 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3746 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3747 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3748 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3749 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3750 .features[FEAT_7_0_ECX] = 3751 CPUID_7_0_ECX_PKU | 3752 CPUID_7_0_ECX_AVX512VNNI, 3753 .features[FEAT_7_0_EDX] = 3754 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3755 /* XSAVES is added in version 5 */ 3756 .features[FEAT_XSAVE] = 3757 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3758 CPUID_XSAVE_XGETBV1, 3759 .features[FEAT_6_EAX] = 3760 CPUID_6_EAX_ARAT, 3761 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3762 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3763 MSR_VMX_BASIC_TRUE_CTLS, 3764 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3765 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3766 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3767 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3768 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3769 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3770 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3771 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3772 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3773 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3774 .features[FEAT_VMX_EXIT_CTLS] = 3775 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3776 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3777 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3778 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3779 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3780 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3781 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3782 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3783 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3784 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3785 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3786 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3787 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3788 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3789 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3790 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3791 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3792 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3793 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3794 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3795 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3796 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3797 .features[FEAT_VMX_SECONDARY_CTLS] = 3798 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3799 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3800 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3801 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3802 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3803 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3804 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3805 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3806 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3807 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3808 .xlevel = 0x80000008, 3809 .model_id = "Intel Xeon Processor (Cascadelake)", 3810 .versions = (X86CPUVersionDefinition[]) { 3811 { .version = 1 }, 3812 { .version = 2, 3813 .note = "ARCH_CAPABILITIES", 3814 .props = (PropValue[]) { 3815 { "arch-capabilities", "on" }, 3816 { "rdctl-no", "on" }, 3817 { "ibrs-all", "on" }, 3818 { "skip-l1dfl-vmentry", "on" }, 3819 { "mds-no", "on" }, 3820 { /* end of list */ } 3821 }, 3822 }, 3823 { .version = 3, 3824 .alias = "Cascadelake-Server-noTSX", 3825 .note = "ARCH_CAPABILITIES, no TSX", 3826 .props = (PropValue[]) { 3827 { "hle", "off" }, 3828 { "rtm", "off" }, 3829 { /* end of list */ } 3830 }, 3831 }, 3832 { .version = 4, 3833 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 3834 .props = (PropValue[]) { 3835 { "vmx-eptp-switching", "on" }, 3836 { /* end of list */ } 3837 }, 3838 }, 3839 { .version = 5, 3840 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3841 .props = (PropValue[]) { 3842 { "xsaves", "on" }, 3843 { "vmx-xsaves", "on" }, 3844 { /* end of list */ } 3845 }, 3846 }, 3847 { /* end of list */ } 3848 } 3849 }, 3850 { 3851 .name = "Cooperlake", 3852 .level = 0xd, 3853 .vendor = CPUID_VENDOR_INTEL, 3854 .family = 6, 3855 .model = 85, 3856 .stepping = 10, 3857 .features[FEAT_1_EDX] = 3858 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3859 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3860 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3861 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3862 CPUID_DE | CPUID_FP87, 3863 .features[FEAT_1_ECX] = 3864 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3865 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3866 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3867 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3868 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3869 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3870 .features[FEAT_8000_0001_EDX] = 3871 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3872 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3873 .features[FEAT_8000_0001_ECX] = 3874 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3875 .features[FEAT_7_0_EBX] = 3876 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3877 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3878 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3879 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3880 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3881 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3882 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3883 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3884 .features[FEAT_7_0_ECX] = 3885 CPUID_7_0_ECX_PKU | 3886 CPUID_7_0_ECX_AVX512VNNI, 3887 .features[FEAT_7_0_EDX] = 3888 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3889 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3890 .features[FEAT_ARCH_CAPABILITIES] = 3891 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3892 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3893 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3894 .features[FEAT_7_1_EAX] = 3895 CPUID_7_1_EAX_AVX512_BF16, 3896 /* XSAVES is added in version 2 */ 3897 .features[FEAT_XSAVE] = 3898 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3899 CPUID_XSAVE_XGETBV1, 3900 .features[FEAT_6_EAX] = 3901 CPUID_6_EAX_ARAT, 3902 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3903 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3904 MSR_VMX_BASIC_TRUE_CTLS, 3905 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3906 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3907 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3908 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3909 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3910 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3911 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3912 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3913 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3914 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3915 .features[FEAT_VMX_EXIT_CTLS] = 3916 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3917 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3918 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3919 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3920 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3921 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3922 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3923 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3924 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3925 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3926 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3927 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3928 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3929 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3930 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3931 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3932 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3933 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3934 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3935 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3936 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3937 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3938 .features[FEAT_VMX_SECONDARY_CTLS] = 3939 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3940 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3941 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3942 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3943 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3944 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3945 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3946 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3947 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3948 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3949 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3950 .xlevel = 0x80000008, 3951 .model_id = "Intel Xeon Processor (Cooperlake)", 3952 .versions = (X86CPUVersionDefinition[]) { 3953 { .version = 1 }, 3954 { .version = 2, 3955 .note = "XSAVES", 3956 .props = (PropValue[]) { 3957 { "xsaves", "on" }, 3958 { "vmx-xsaves", "on" }, 3959 { /* end of list */ } 3960 }, 3961 }, 3962 { /* end of list */ } 3963 } 3964 }, 3965 { 3966 .name = "Icelake-Server", 3967 .level = 0xd, 3968 .vendor = CPUID_VENDOR_INTEL, 3969 .family = 6, 3970 .model = 134, 3971 .stepping = 0, 3972 .features[FEAT_1_EDX] = 3973 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3974 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3975 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3976 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3977 CPUID_DE | CPUID_FP87, 3978 .features[FEAT_1_ECX] = 3979 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3980 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3981 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3982 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3983 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3984 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3985 .features[FEAT_8000_0001_EDX] = 3986 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3987 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3988 .features[FEAT_8000_0001_ECX] = 3989 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3990 .features[FEAT_8000_0008_EBX] = 3991 CPUID_8000_0008_EBX_WBNOINVD, 3992 .features[FEAT_7_0_EBX] = 3993 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3994 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3995 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3996 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3997 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3998 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3999 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4000 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4001 .features[FEAT_7_0_ECX] = 4002 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4003 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4004 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4005 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4006 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4007 .features[FEAT_7_0_EDX] = 4008 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4009 /* XSAVES is added in version 5 */ 4010 .features[FEAT_XSAVE] = 4011 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4012 CPUID_XSAVE_XGETBV1, 4013 .features[FEAT_6_EAX] = 4014 CPUID_6_EAX_ARAT, 4015 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4016 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4017 MSR_VMX_BASIC_TRUE_CTLS, 4018 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4019 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4020 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4021 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4022 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4023 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4024 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4025 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4026 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4027 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4028 .features[FEAT_VMX_EXIT_CTLS] = 4029 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4030 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4031 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4032 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4033 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4034 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4035 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4036 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4037 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4038 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4039 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4040 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4041 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4042 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4043 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4044 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4045 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4046 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4047 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4048 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4049 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4050 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4051 .features[FEAT_VMX_SECONDARY_CTLS] = 4052 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4053 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4054 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4055 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4056 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4057 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4058 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4059 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4060 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4061 .xlevel = 0x80000008, 4062 .model_id = "Intel Xeon Processor (Icelake)", 4063 .versions = (X86CPUVersionDefinition[]) { 4064 { .version = 1 }, 4065 { 4066 .version = 2, 4067 .note = "no TSX", 4068 .alias = "Icelake-Server-noTSX", 4069 .props = (PropValue[]) { 4070 { "hle", "off" }, 4071 { "rtm", "off" }, 4072 { /* end of list */ } 4073 }, 4074 }, 4075 { 4076 .version = 3, 4077 .props = (PropValue[]) { 4078 { "arch-capabilities", "on" }, 4079 { "rdctl-no", "on" }, 4080 { "ibrs-all", "on" }, 4081 { "skip-l1dfl-vmentry", "on" }, 4082 { "mds-no", "on" }, 4083 { "pschange-mc-no", "on" }, 4084 { "taa-no", "on" }, 4085 { /* end of list */ } 4086 }, 4087 }, 4088 { 4089 .version = 4, 4090 .props = (PropValue[]) { 4091 { "sha-ni", "on" }, 4092 { "avx512ifma", "on" }, 4093 { "rdpid", "on" }, 4094 { "fsrm", "on" }, 4095 { "vmx-rdseed-exit", "on" }, 4096 { "vmx-pml", "on" }, 4097 { "vmx-eptp-switching", "on" }, 4098 { "model", "106" }, 4099 { /* end of list */ } 4100 }, 4101 }, 4102 { 4103 .version = 5, 4104 .note = "XSAVES", 4105 .props = (PropValue[]) { 4106 { "xsaves", "on" }, 4107 { "vmx-xsaves", "on" }, 4108 { /* end of list */ } 4109 }, 4110 }, 4111 { 4112 .version = 6, 4113 .note = "5-level EPT", 4114 .props = (PropValue[]) { 4115 { "vmx-page-walk-5", "on" }, 4116 { /* end of list */ } 4117 }, 4118 }, 4119 { 4120 .version = 7, 4121 .note = "TSX, taa-no", 4122 .props = (PropValue[]) { 4123 /* Restore TSX features removed by -v2 above */ 4124 { "hle", "on" }, 4125 { "rtm", "on" }, 4126 { /* end of list */ } 4127 }, 4128 }, 4129 { /* end of list */ } 4130 } 4131 }, 4132 { 4133 .name = "SapphireRapids", 4134 .level = 0x20, 4135 .vendor = CPUID_VENDOR_INTEL, 4136 .family = 6, 4137 .model = 143, 4138 .stepping = 4, 4139 /* 4140 * please keep the ascending order so that we can have a clear view of 4141 * bit position of each feature. 4142 */ 4143 .features[FEAT_1_EDX] = 4144 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4145 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4146 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4147 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4148 CPUID_SSE | CPUID_SSE2, 4149 .features[FEAT_1_ECX] = 4150 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4151 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4152 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4153 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4154 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4155 .features[FEAT_8000_0001_EDX] = 4156 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4157 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4158 .features[FEAT_8000_0001_ECX] = 4159 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4160 .features[FEAT_8000_0008_EBX] = 4161 CPUID_8000_0008_EBX_WBNOINVD, 4162 .features[FEAT_7_0_EBX] = 4163 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4164 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4165 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4166 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4167 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4168 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4169 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4170 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4171 .features[FEAT_7_0_ECX] = 4172 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4173 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4174 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4175 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4176 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4177 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4178 .features[FEAT_7_0_EDX] = 4179 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4180 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4181 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4182 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4183 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4184 .features[FEAT_ARCH_CAPABILITIES] = 4185 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4186 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4187 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4188 .features[FEAT_XSAVE] = 4189 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4190 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4191 .features[FEAT_6_EAX] = 4192 CPUID_6_EAX_ARAT, 4193 .features[FEAT_7_1_EAX] = 4194 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4195 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4196 .features[FEAT_VMX_BASIC] = 4197 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4198 .features[FEAT_VMX_ENTRY_CTLS] = 4199 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4200 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4201 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4202 .features[FEAT_VMX_EPT_VPID_CAPS] = 4203 MSR_VMX_EPT_EXECONLY | 4204 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4205 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4206 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4207 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4208 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4209 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4210 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4211 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4212 .features[FEAT_VMX_EXIT_CTLS] = 4213 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4214 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4215 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4216 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4217 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4218 .features[FEAT_VMX_MISC] = 4219 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4220 MSR_VMX_MISC_VMWRITE_VMEXIT, 4221 .features[FEAT_VMX_PINBASED_CTLS] = 4222 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4223 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4224 VMX_PIN_BASED_POSTED_INTR, 4225 .features[FEAT_VMX_PROCBASED_CTLS] = 4226 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4227 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4228 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4229 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4230 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4231 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4232 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4233 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4234 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4235 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4236 VMX_CPU_BASED_PAUSE_EXITING | 4237 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4238 .features[FEAT_VMX_SECONDARY_CTLS] = 4239 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4240 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4241 VMX_SECONDARY_EXEC_RDTSCP | 4242 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4243 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4244 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4245 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4246 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4247 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4248 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4249 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4250 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4251 VMX_SECONDARY_EXEC_XSAVES, 4252 .features[FEAT_VMX_VMFUNC] = 4253 MSR_VMX_VMFUNC_EPT_SWITCHING, 4254 .xlevel = 0x80000008, 4255 .model_id = "Intel Xeon Processor (SapphireRapids)", 4256 .versions = (X86CPUVersionDefinition[]) { 4257 { .version = 1 }, 4258 { 4259 .version = 2, 4260 .props = (PropValue[]) { 4261 { "sbdr-ssdp-no", "on" }, 4262 { "fbsdp-no", "on" }, 4263 { "psdp-no", "on" }, 4264 { /* end of list */ } 4265 } 4266 }, 4267 { 4268 .version = 3, 4269 .props = (PropValue[]) { 4270 { "ss", "on" }, 4271 { "tsc-adjust", "on" }, 4272 { "cldemote", "on" }, 4273 { "movdiri", "on" }, 4274 { "movdir64b", "on" }, 4275 { /* end of list */ } 4276 } 4277 }, 4278 { /* end of list */ } 4279 } 4280 }, 4281 { 4282 .name = "GraniteRapids", 4283 .level = 0x20, 4284 .vendor = CPUID_VENDOR_INTEL, 4285 .family = 6, 4286 .model = 173, 4287 .stepping = 0, 4288 /* 4289 * please keep the ascending order so that we can have a clear view of 4290 * bit position of each feature. 4291 */ 4292 .features[FEAT_1_EDX] = 4293 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4294 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4295 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4296 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4297 CPUID_SSE | CPUID_SSE2, 4298 .features[FEAT_1_ECX] = 4299 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4300 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4301 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4302 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4303 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4304 .features[FEAT_8000_0001_EDX] = 4305 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4306 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4307 .features[FEAT_8000_0001_ECX] = 4308 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4309 .features[FEAT_8000_0008_EBX] = 4310 CPUID_8000_0008_EBX_WBNOINVD, 4311 .features[FEAT_7_0_EBX] = 4312 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4313 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4314 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4315 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4316 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4317 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4318 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4319 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4320 .features[FEAT_7_0_ECX] = 4321 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4322 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4323 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4324 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4325 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4326 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4327 .features[FEAT_7_0_EDX] = 4328 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4329 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4330 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4331 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4332 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4333 .features[FEAT_ARCH_CAPABILITIES] = 4334 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4335 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4336 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4337 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4338 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4339 .features[FEAT_XSAVE] = 4340 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4341 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4342 .features[FEAT_6_EAX] = 4343 CPUID_6_EAX_ARAT, 4344 .features[FEAT_7_1_EAX] = 4345 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4346 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4347 CPUID_7_1_EAX_AMX_FP16, 4348 .features[FEAT_7_1_EDX] = 4349 CPUID_7_1_EDX_PREFETCHITI, 4350 .features[FEAT_7_2_EDX] = 4351 CPUID_7_2_EDX_MCDT_NO, 4352 .features[FEAT_VMX_BASIC] = 4353 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4354 .features[FEAT_VMX_ENTRY_CTLS] = 4355 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4356 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4357 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4358 .features[FEAT_VMX_EPT_VPID_CAPS] = 4359 MSR_VMX_EPT_EXECONLY | 4360 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4361 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4362 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4363 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4364 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4365 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4366 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4367 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4368 .features[FEAT_VMX_EXIT_CTLS] = 4369 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4370 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4371 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4372 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4373 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4374 .features[FEAT_VMX_MISC] = 4375 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4376 MSR_VMX_MISC_VMWRITE_VMEXIT, 4377 .features[FEAT_VMX_PINBASED_CTLS] = 4378 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4379 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4380 VMX_PIN_BASED_POSTED_INTR, 4381 .features[FEAT_VMX_PROCBASED_CTLS] = 4382 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4383 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4384 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4385 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4386 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4387 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4388 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4389 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4390 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4391 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4392 VMX_CPU_BASED_PAUSE_EXITING | 4393 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4394 .features[FEAT_VMX_SECONDARY_CTLS] = 4395 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4396 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4397 VMX_SECONDARY_EXEC_RDTSCP | 4398 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4399 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4400 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4401 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4402 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4403 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4404 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4405 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4406 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4407 VMX_SECONDARY_EXEC_XSAVES, 4408 .features[FEAT_VMX_VMFUNC] = 4409 MSR_VMX_VMFUNC_EPT_SWITCHING, 4410 .xlevel = 0x80000008, 4411 .model_id = "Intel Xeon Processor (GraniteRapids)", 4412 .versions = (X86CPUVersionDefinition[]) { 4413 { .version = 1 }, 4414 { 4415 .version = 2, 4416 .props = (PropValue[]) { 4417 { "ss", "on" }, 4418 { "tsc-adjust", "on" }, 4419 { "cldemote", "on" }, 4420 { "movdiri", "on" }, 4421 { "movdir64b", "on" }, 4422 { "avx10", "on" }, 4423 { "avx10-128", "on" }, 4424 { "avx10-256", "on" }, 4425 { "avx10-512", "on" }, 4426 { "avx10-version", "1" }, 4427 { "stepping", "1" }, 4428 { /* end of list */ } 4429 } 4430 }, 4431 { /* end of list */ }, 4432 }, 4433 }, 4434 { 4435 .name = "SierraForest", 4436 .level = 0x23, 4437 .vendor = CPUID_VENDOR_INTEL, 4438 .family = 6, 4439 .model = 175, 4440 .stepping = 0, 4441 /* 4442 * please keep the ascending order so that we can have a clear view of 4443 * bit position of each feature. 4444 */ 4445 .features[FEAT_1_EDX] = 4446 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4447 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4448 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4449 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4450 CPUID_SSE | CPUID_SSE2, 4451 .features[FEAT_1_ECX] = 4452 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4453 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4454 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4455 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4456 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4457 .features[FEAT_8000_0001_EDX] = 4458 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4459 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4460 .features[FEAT_8000_0001_ECX] = 4461 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4462 .features[FEAT_8000_0008_EBX] = 4463 CPUID_8000_0008_EBX_WBNOINVD, 4464 .features[FEAT_7_0_EBX] = 4465 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4466 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4467 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4468 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4469 CPUID_7_0_EBX_SHA_NI, 4470 .features[FEAT_7_0_ECX] = 4471 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4472 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4473 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4474 .features[FEAT_7_0_EDX] = 4475 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4476 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4477 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4478 .features[FEAT_ARCH_CAPABILITIES] = 4479 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4480 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4481 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4482 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4483 MSR_ARCH_CAP_PBRSB_NO, 4484 .features[FEAT_XSAVE] = 4485 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4486 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4487 .features[FEAT_6_EAX] = 4488 CPUID_6_EAX_ARAT, 4489 .features[FEAT_7_1_EAX] = 4490 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4491 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4492 .features[FEAT_7_1_EDX] = 4493 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4494 .features[FEAT_7_2_EDX] = 4495 CPUID_7_2_EDX_MCDT_NO, 4496 .features[FEAT_VMX_BASIC] = 4497 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4498 .features[FEAT_VMX_ENTRY_CTLS] = 4499 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4500 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4501 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4502 .features[FEAT_VMX_EPT_VPID_CAPS] = 4503 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4504 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4505 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4506 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4507 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4508 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4509 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4510 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4511 .features[FEAT_VMX_EXIT_CTLS] = 4512 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4513 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4514 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4515 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4516 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4517 .features[FEAT_VMX_MISC] = 4518 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4519 MSR_VMX_MISC_VMWRITE_VMEXIT, 4520 .features[FEAT_VMX_PINBASED_CTLS] = 4521 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4522 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4523 VMX_PIN_BASED_POSTED_INTR, 4524 .features[FEAT_VMX_PROCBASED_CTLS] = 4525 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4526 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4527 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4528 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4529 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4530 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4531 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4532 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4533 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4534 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4535 VMX_CPU_BASED_PAUSE_EXITING | 4536 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4537 .features[FEAT_VMX_SECONDARY_CTLS] = 4538 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4539 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4540 VMX_SECONDARY_EXEC_RDTSCP | 4541 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4542 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4543 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4544 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4545 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4546 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4547 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4548 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4549 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4550 VMX_SECONDARY_EXEC_XSAVES, 4551 .features[FEAT_VMX_VMFUNC] = 4552 MSR_VMX_VMFUNC_EPT_SWITCHING, 4553 .xlevel = 0x80000008, 4554 .model_id = "Intel Xeon Processor (SierraForest)", 4555 .versions = (X86CPUVersionDefinition[]) { 4556 { .version = 1 }, 4557 { 4558 .version = 2, 4559 .props = (PropValue[]) { 4560 { "ss", "on" }, 4561 { "tsc-adjust", "on" }, 4562 { "cldemote", "on" }, 4563 { "movdiri", "on" }, 4564 { "movdir64b", "on" }, 4565 { "gds-no", "on" }, 4566 { "rfds-no", "on" }, 4567 { "lam", "on" }, 4568 { "intel-psfd", "on"}, 4569 { "ipred-ctrl", "on"}, 4570 { "rrsba-ctrl", "on"}, 4571 { "bhi-ctrl", "on"}, 4572 { "stepping", "3" }, 4573 { /* end of list */ } 4574 } 4575 }, 4576 { /* end of list */ }, 4577 }, 4578 }, 4579 { 4580 .name = "ClearwaterForest", 4581 .level = 0x23, 4582 .xlevel = 0x80000008, 4583 .vendor = CPUID_VENDOR_INTEL, 4584 .family = 6, 4585 .model = 221, 4586 .stepping = 0, 4587 /* 4588 * please keep the ascending order so that we can have a clear view of 4589 * bit position of each feature. 4590 */ 4591 .features[FEAT_1_EDX] = 4592 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4593 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4594 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4595 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4596 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 4597 .features[FEAT_1_ECX] = 4598 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4599 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4600 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4601 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4602 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4603 .features[FEAT_8000_0001_EDX] = 4604 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4605 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4606 .features[FEAT_8000_0001_ECX] = 4607 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4608 .features[FEAT_8000_0008_EBX] = 4609 CPUID_8000_0008_EBX_WBNOINVD, 4610 .features[FEAT_7_0_EBX] = 4611 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 4612 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4613 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4614 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4615 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4616 CPUID_7_0_EBX_SHA_NI, 4617 .features[FEAT_7_0_ECX] = 4618 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4619 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4620 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 4621 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 4622 CPUID_7_0_ECX_MOVDIR64B, 4623 .features[FEAT_7_0_EDX] = 4624 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4625 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4626 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4627 .features[FEAT_ARCH_CAPABILITIES] = 4628 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4629 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4630 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4631 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4632 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 4633 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 4634 .features[FEAT_XSAVE] = 4635 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4636 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4637 .features[FEAT_6_EAX] = 4638 CPUID_6_EAX_ARAT, 4639 .features[FEAT_7_1_EAX] = 4640 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 4641 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4642 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 4643 CPUID_7_1_EAX_LAM, 4644 .features[FEAT_7_1_EDX] = 4645 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 4646 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 4647 .features[FEAT_7_2_EDX] = 4648 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 4649 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 4650 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 4651 .features[FEAT_VMX_BASIC] = 4652 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4653 .features[FEAT_VMX_ENTRY_CTLS] = 4654 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4655 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4656 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4657 .features[FEAT_VMX_EPT_VPID_CAPS] = 4658 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4659 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4660 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4661 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4662 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4663 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4664 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4665 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4666 .features[FEAT_VMX_EXIT_CTLS] = 4667 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4668 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4669 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4670 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4671 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4672 .features[FEAT_VMX_MISC] = 4673 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4674 MSR_VMX_MISC_VMWRITE_VMEXIT, 4675 .features[FEAT_VMX_PINBASED_CTLS] = 4676 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4677 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4678 VMX_PIN_BASED_POSTED_INTR, 4679 .features[FEAT_VMX_PROCBASED_CTLS] = 4680 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4681 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4682 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4683 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4684 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4685 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4686 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4687 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4688 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4689 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4690 VMX_CPU_BASED_PAUSE_EXITING | 4691 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4692 .features[FEAT_VMX_SECONDARY_CTLS] = 4693 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4694 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4695 VMX_SECONDARY_EXEC_RDTSCP | 4696 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4697 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4698 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4699 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4700 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4701 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4702 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4703 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4704 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4705 VMX_SECONDARY_EXEC_XSAVES, 4706 .features[FEAT_VMX_VMFUNC] = 4707 MSR_VMX_VMFUNC_EPT_SWITCHING, 4708 .model_id = "Intel Xeon Processor (ClearwaterForest)", 4709 .versions = (X86CPUVersionDefinition[]) { 4710 { .version = 1 }, 4711 { /* end of list */ }, 4712 }, 4713 }, 4714 { 4715 .name = "Denverton", 4716 .level = 21, 4717 .vendor = CPUID_VENDOR_INTEL, 4718 .family = 6, 4719 .model = 95, 4720 .stepping = 1, 4721 .features[FEAT_1_EDX] = 4722 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4723 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4724 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4725 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4726 CPUID_SSE | CPUID_SSE2, 4727 .features[FEAT_1_ECX] = 4728 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4729 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4730 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4731 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4732 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4733 .features[FEAT_8000_0001_EDX] = 4734 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4735 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4736 .features[FEAT_8000_0001_ECX] = 4737 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4738 .features[FEAT_7_0_EBX] = 4739 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4740 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4741 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4742 .features[FEAT_7_0_EDX] = 4743 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4744 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4745 /* XSAVES is added in version 3 */ 4746 .features[FEAT_XSAVE] = 4747 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4748 .features[FEAT_6_EAX] = 4749 CPUID_6_EAX_ARAT, 4750 .features[FEAT_ARCH_CAPABILITIES] = 4751 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4752 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4753 MSR_VMX_BASIC_TRUE_CTLS, 4754 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4755 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4756 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4757 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4758 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4759 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4760 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4761 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4762 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4763 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4764 .features[FEAT_VMX_EXIT_CTLS] = 4765 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4766 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4767 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4768 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4769 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4770 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4771 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4772 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4773 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4774 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4775 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4776 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4777 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4778 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4779 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4780 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4781 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4782 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4783 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4784 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4785 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4786 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4787 .features[FEAT_VMX_SECONDARY_CTLS] = 4788 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4789 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4790 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4791 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4792 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4793 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4794 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4795 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4796 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4797 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4798 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4799 .xlevel = 0x80000008, 4800 .model_id = "Intel Atom Processor (Denverton)", 4801 .versions = (X86CPUVersionDefinition[]) { 4802 { .version = 1 }, 4803 { 4804 .version = 2, 4805 .note = "no MPX, no MONITOR", 4806 .props = (PropValue[]) { 4807 { "monitor", "off" }, 4808 { "mpx", "off" }, 4809 { /* end of list */ }, 4810 }, 4811 }, 4812 { 4813 .version = 3, 4814 .note = "XSAVES, no MPX, no MONITOR", 4815 .props = (PropValue[]) { 4816 { "xsaves", "on" }, 4817 { "vmx-xsaves", "on" }, 4818 { /* end of list */ }, 4819 }, 4820 }, 4821 { /* end of list */ }, 4822 }, 4823 }, 4824 { 4825 .name = "Snowridge", 4826 .level = 27, 4827 .vendor = CPUID_VENDOR_INTEL, 4828 .family = 6, 4829 .model = 134, 4830 .stepping = 1, 4831 .features[FEAT_1_EDX] = 4832 /* missing: CPUID_PN CPUID_IA64 */ 4833 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4834 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4835 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4836 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4837 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4838 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4839 CPUID_MMX | 4840 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4841 .features[FEAT_1_ECX] = 4842 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4843 CPUID_EXT_SSSE3 | 4844 CPUID_EXT_CX16 | 4845 CPUID_EXT_SSE41 | 4846 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4847 CPUID_EXT_POPCNT | 4848 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4849 CPUID_EXT_RDRAND, 4850 .features[FEAT_8000_0001_EDX] = 4851 CPUID_EXT2_SYSCALL | 4852 CPUID_EXT2_NX | 4853 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4854 CPUID_EXT2_LM, 4855 .features[FEAT_8000_0001_ECX] = 4856 CPUID_EXT3_LAHF_LM | 4857 CPUID_EXT3_3DNOWPREFETCH, 4858 .features[FEAT_7_0_EBX] = 4859 CPUID_7_0_EBX_FSGSBASE | 4860 CPUID_7_0_EBX_SMEP | 4861 CPUID_7_0_EBX_ERMS | 4862 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4863 CPUID_7_0_EBX_RDSEED | 4864 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4865 CPUID_7_0_EBX_CLWB | 4866 CPUID_7_0_EBX_SHA_NI, 4867 .features[FEAT_7_0_ECX] = 4868 CPUID_7_0_ECX_UMIP | 4869 /* missing bit 5 */ 4870 CPUID_7_0_ECX_GFNI | 4871 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4872 CPUID_7_0_ECX_MOVDIR64B, 4873 .features[FEAT_7_0_EDX] = 4874 CPUID_7_0_EDX_SPEC_CTRL | 4875 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4876 CPUID_7_0_EDX_CORE_CAPABILITY, 4877 .features[FEAT_CORE_CAPABILITY] = 4878 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4879 /* XSAVES is added in version 3 */ 4880 .features[FEAT_XSAVE] = 4881 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4882 CPUID_XSAVE_XGETBV1, 4883 .features[FEAT_6_EAX] = 4884 CPUID_6_EAX_ARAT, 4885 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4886 MSR_VMX_BASIC_TRUE_CTLS, 4887 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4888 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4889 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4890 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4891 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4892 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4893 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4894 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4895 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4896 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4897 .features[FEAT_VMX_EXIT_CTLS] = 4898 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4899 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4900 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4901 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4902 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4903 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4904 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4905 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4906 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4907 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4908 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4909 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4910 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4911 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4912 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4913 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4914 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4915 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4916 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4917 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4918 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4919 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4920 .features[FEAT_VMX_SECONDARY_CTLS] = 4921 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4922 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4923 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4924 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4925 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4926 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4927 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4928 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4929 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4930 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4931 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4932 .xlevel = 0x80000008, 4933 .model_id = "Intel Atom Processor (SnowRidge)", 4934 .versions = (X86CPUVersionDefinition[]) { 4935 { .version = 1 }, 4936 { 4937 .version = 2, 4938 .props = (PropValue[]) { 4939 { "mpx", "off" }, 4940 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4941 { /* end of list */ }, 4942 }, 4943 }, 4944 { 4945 .version = 3, 4946 .note = "XSAVES, no MPX", 4947 .props = (PropValue[]) { 4948 { "xsaves", "on" }, 4949 { "vmx-xsaves", "on" }, 4950 { /* end of list */ }, 4951 }, 4952 }, 4953 { 4954 .version = 4, 4955 .note = "no split lock detect, no core-capability", 4956 .props = (PropValue[]) { 4957 { "split-lock-detect", "off" }, 4958 { "core-capability", "off" }, 4959 { /* end of list */ }, 4960 }, 4961 }, 4962 { /* end of list */ }, 4963 }, 4964 }, 4965 { 4966 .name = "KnightsMill", 4967 .level = 0xd, 4968 .vendor = CPUID_VENDOR_INTEL, 4969 .family = 6, 4970 .model = 133, 4971 .stepping = 0, 4972 .features[FEAT_1_EDX] = 4973 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4974 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4975 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4976 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4977 CPUID_PSE | CPUID_DE | CPUID_FP87, 4978 .features[FEAT_1_ECX] = 4979 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4980 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4981 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4982 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4983 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4984 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4985 .features[FEAT_8000_0001_EDX] = 4986 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4987 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4988 .features[FEAT_8000_0001_ECX] = 4989 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4990 .features[FEAT_7_0_EBX] = 4991 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4992 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4993 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4994 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4995 CPUID_7_0_EBX_AVX512ER, 4996 .features[FEAT_7_0_ECX] = 4997 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4998 .features[FEAT_7_0_EDX] = 4999 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 5000 .features[FEAT_XSAVE] = 5001 CPUID_XSAVE_XSAVEOPT, 5002 .features[FEAT_6_EAX] = 5003 CPUID_6_EAX_ARAT, 5004 .xlevel = 0x80000008, 5005 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5006 }, 5007 { 5008 .name = "Opteron_G1", 5009 .level = 5, 5010 .vendor = CPUID_VENDOR_AMD, 5011 .family = 15, 5012 .model = 6, 5013 .stepping = 1, 5014 .features[FEAT_1_EDX] = 5015 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5016 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5017 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5018 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5019 CPUID_DE | CPUID_FP87, 5020 .features[FEAT_1_ECX] = 5021 CPUID_EXT_SSE3, 5022 .features[FEAT_8000_0001_EDX] = 5023 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5024 .xlevel = 0x80000008, 5025 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5026 }, 5027 { 5028 .name = "Opteron_G2", 5029 .level = 5, 5030 .vendor = CPUID_VENDOR_AMD, 5031 .family = 15, 5032 .model = 6, 5033 .stepping = 1, 5034 .features[FEAT_1_EDX] = 5035 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5036 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5037 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5038 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5039 CPUID_DE | CPUID_FP87, 5040 .features[FEAT_1_ECX] = 5041 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5042 .features[FEAT_8000_0001_EDX] = 5043 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5044 .features[FEAT_8000_0001_ECX] = 5045 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5046 .xlevel = 0x80000008, 5047 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5048 }, 5049 { 5050 .name = "Opteron_G3", 5051 .level = 5, 5052 .vendor = CPUID_VENDOR_AMD, 5053 .family = 16, 5054 .model = 2, 5055 .stepping = 3, 5056 .features[FEAT_1_EDX] = 5057 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5058 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5059 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5060 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5061 CPUID_DE | CPUID_FP87, 5062 .features[FEAT_1_ECX] = 5063 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5064 CPUID_EXT_SSE3, 5065 .features[FEAT_8000_0001_EDX] = 5066 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5067 CPUID_EXT2_RDTSCP, 5068 .features[FEAT_8000_0001_ECX] = 5069 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5070 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5071 .xlevel = 0x80000008, 5072 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5073 }, 5074 { 5075 .name = "Opteron_G4", 5076 .level = 0xd, 5077 .vendor = CPUID_VENDOR_AMD, 5078 .family = 21, 5079 .model = 1, 5080 .stepping = 2, 5081 .features[FEAT_1_EDX] = 5082 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5083 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5084 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5085 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5086 CPUID_DE | CPUID_FP87, 5087 .features[FEAT_1_ECX] = 5088 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5089 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5090 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5091 CPUID_EXT_SSE3, 5092 .features[FEAT_8000_0001_EDX] = 5093 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5094 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5095 .features[FEAT_8000_0001_ECX] = 5096 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5097 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5098 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5099 CPUID_EXT3_LAHF_LM, 5100 .features[FEAT_SVM] = 5101 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5102 /* no xsaveopt! */ 5103 .xlevel = 0x8000001A, 5104 .model_id = "AMD Opteron 62xx class CPU", 5105 }, 5106 { 5107 .name = "Opteron_G5", 5108 .level = 0xd, 5109 .vendor = CPUID_VENDOR_AMD, 5110 .family = 21, 5111 .model = 2, 5112 .stepping = 0, 5113 .features[FEAT_1_EDX] = 5114 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5115 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5116 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5117 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5118 CPUID_DE | CPUID_FP87, 5119 .features[FEAT_1_ECX] = 5120 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5121 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5122 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5123 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5124 .features[FEAT_8000_0001_EDX] = 5125 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5126 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5127 .features[FEAT_8000_0001_ECX] = 5128 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5129 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5130 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5131 CPUID_EXT3_LAHF_LM, 5132 .features[FEAT_SVM] = 5133 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5134 /* no xsaveopt! */ 5135 .xlevel = 0x8000001A, 5136 .model_id = "AMD Opteron 63xx class CPU", 5137 }, 5138 { 5139 .name = "EPYC", 5140 .level = 0xd, 5141 .vendor = CPUID_VENDOR_AMD, 5142 .family = 23, 5143 .model = 1, 5144 .stepping = 2, 5145 .features[FEAT_1_EDX] = 5146 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5147 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5148 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5149 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5150 CPUID_VME | CPUID_FP87, 5151 .features[FEAT_1_ECX] = 5152 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5153 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5154 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5155 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5156 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5157 .features[FEAT_8000_0001_EDX] = 5158 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5159 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5160 CPUID_EXT2_SYSCALL, 5161 .features[FEAT_8000_0001_ECX] = 5162 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5163 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5164 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5165 CPUID_EXT3_TOPOEXT, 5166 .features[FEAT_7_0_EBX] = 5167 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5168 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5169 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5170 CPUID_7_0_EBX_SHA_NI, 5171 .features[FEAT_XSAVE] = 5172 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5173 CPUID_XSAVE_XGETBV1, 5174 .features[FEAT_6_EAX] = 5175 CPUID_6_EAX_ARAT, 5176 .features[FEAT_SVM] = 5177 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5178 .xlevel = 0x8000001E, 5179 .model_id = "AMD EPYC Processor", 5180 .cache_info = &epyc_cache_info, 5181 .versions = (X86CPUVersionDefinition[]) { 5182 { .version = 1 }, 5183 { 5184 .version = 2, 5185 .alias = "EPYC-IBPB", 5186 .props = (PropValue[]) { 5187 { "ibpb", "on" }, 5188 { "model-id", 5189 "AMD EPYC Processor (with IBPB)" }, 5190 { /* end of list */ } 5191 } 5192 }, 5193 { 5194 .version = 3, 5195 .props = (PropValue[]) { 5196 { "ibpb", "on" }, 5197 { "perfctr-core", "on" }, 5198 { "clzero", "on" }, 5199 { "xsaveerptr", "on" }, 5200 { "xsaves", "on" }, 5201 { "model-id", 5202 "AMD EPYC Processor" }, 5203 { /* end of list */ } 5204 } 5205 }, 5206 { 5207 .version = 4, 5208 .props = (PropValue[]) { 5209 { "model-id", 5210 "AMD EPYC-v4 Processor" }, 5211 { /* end of list */ } 5212 }, 5213 .cache_info = &epyc_v4_cache_info 5214 }, 5215 { /* end of list */ } 5216 } 5217 }, 5218 { 5219 .name = "Dhyana", 5220 .level = 0xd, 5221 .vendor = CPUID_VENDOR_HYGON, 5222 .family = 24, 5223 .model = 0, 5224 .stepping = 1, 5225 .features[FEAT_1_EDX] = 5226 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5227 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5228 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5229 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5230 CPUID_VME | CPUID_FP87, 5231 .features[FEAT_1_ECX] = 5232 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5233 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5234 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5235 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5236 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5237 .features[FEAT_8000_0001_EDX] = 5238 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5239 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5240 CPUID_EXT2_SYSCALL, 5241 .features[FEAT_8000_0001_ECX] = 5242 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5243 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5244 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5245 CPUID_EXT3_TOPOEXT, 5246 .features[FEAT_8000_0008_EBX] = 5247 CPUID_8000_0008_EBX_IBPB, 5248 .features[FEAT_7_0_EBX] = 5249 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5250 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5251 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5252 /* XSAVES is added in version 2 */ 5253 .features[FEAT_XSAVE] = 5254 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5255 CPUID_XSAVE_XGETBV1, 5256 .features[FEAT_6_EAX] = 5257 CPUID_6_EAX_ARAT, 5258 .features[FEAT_SVM] = 5259 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5260 .xlevel = 0x8000001E, 5261 .model_id = "Hygon Dhyana Processor", 5262 .cache_info = &epyc_cache_info, 5263 .versions = (X86CPUVersionDefinition[]) { 5264 { .version = 1 }, 5265 { .version = 2, 5266 .note = "XSAVES", 5267 .props = (PropValue[]) { 5268 { "xsaves", "on" }, 5269 { /* end of list */ } 5270 }, 5271 }, 5272 { /* end of list */ } 5273 } 5274 }, 5275 { 5276 .name = "EPYC-Rome", 5277 .level = 0xd, 5278 .vendor = CPUID_VENDOR_AMD, 5279 .family = 23, 5280 .model = 49, 5281 .stepping = 0, 5282 .features[FEAT_1_EDX] = 5283 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5284 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5285 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5286 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5287 CPUID_VME | CPUID_FP87, 5288 .features[FEAT_1_ECX] = 5289 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5290 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5291 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5292 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5293 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5294 .features[FEAT_8000_0001_EDX] = 5295 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5296 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5297 CPUID_EXT2_SYSCALL, 5298 .features[FEAT_8000_0001_ECX] = 5299 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5300 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5301 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5302 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5303 .features[FEAT_8000_0008_EBX] = 5304 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5305 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5306 CPUID_8000_0008_EBX_STIBP, 5307 .features[FEAT_7_0_EBX] = 5308 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5309 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5310 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5311 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5312 .features[FEAT_7_0_ECX] = 5313 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5314 .features[FEAT_XSAVE] = 5315 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5316 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5317 .features[FEAT_6_EAX] = 5318 CPUID_6_EAX_ARAT, 5319 .features[FEAT_SVM] = 5320 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5321 .xlevel = 0x8000001E, 5322 .model_id = "AMD EPYC-Rome Processor", 5323 .cache_info = &epyc_rome_cache_info, 5324 .versions = (X86CPUVersionDefinition[]) { 5325 { .version = 1 }, 5326 { 5327 .version = 2, 5328 .props = (PropValue[]) { 5329 { "ibrs", "on" }, 5330 { "amd-ssbd", "on" }, 5331 { /* end of list */ } 5332 } 5333 }, 5334 { 5335 .version = 3, 5336 .props = (PropValue[]) { 5337 { "model-id", 5338 "AMD EPYC-Rome-v3 Processor" }, 5339 { /* end of list */ } 5340 }, 5341 .cache_info = &epyc_rome_v3_cache_info 5342 }, 5343 { 5344 .version = 4, 5345 .props = (PropValue[]) { 5346 /* Erratum 1386 */ 5347 { "model-id", 5348 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5349 { "xsaves", "off" }, 5350 { /* end of list */ } 5351 }, 5352 }, 5353 { /* end of list */ } 5354 } 5355 }, 5356 { 5357 .name = "EPYC-Milan", 5358 .level = 0xd, 5359 .vendor = CPUID_VENDOR_AMD, 5360 .family = 25, 5361 .model = 1, 5362 .stepping = 1, 5363 .features[FEAT_1_EDX] = 5364 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5365 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5366 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5367 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5368 CPUID_VME | CPUID_FP87, 5369 .features[FEAT_1_ECX] = 5370 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5371 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5372 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5373 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5374 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5375 CPUID_EXT_PCID, 5376 .features[FEAT_8000_0001_EDX] = 5377 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5378 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5379 CPUID_EXT2_SYSCALL, 5380 .features[FEAT_8000_0001_ECX] = 5381 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5382 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5383 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5384 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5385 .features[FEAT_8000_0008_EBX] = 5386 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5387 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5388 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5389 CPUID_8000_0008_EBX_AMD_SSBD, 5390 .features[FEAT_7_0_EBX] = 5391 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5392 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5393 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5394 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5395 CPUID_7_0_EBX_INVPCID, 5396 .features[FEAT_7_0_ECX] = 5397 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5398 .features[FEAT_7_0_EDX] = 5399 CPUID_7_0_EDX_FSRM, 5400 .features[FEAT_XSAVE] = 5401 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5402 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5403 .features[FEAT_6_EAX] = 5404 CPUID_6_EAX_ARAT, 5405 .features[FEAT_SVM] = 5406 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5407 .xlevel = 0x8000001E, 5408 .model_id = "AMD EPYC-Milan Processor", 5409 .cache_info = &epyc_milan_cache_info, 5410 .versions = (X86CPUVersionDefinition[]) { 5411 { .version = 1 }, 5412 { 5413 .version = 2, 5414 .props = (PropValue[]) { 5415 { "model-id", 5416 "AMD EPYC-Milan-v2 Processor" }, 5417 { "vaes", "on" }, 5418 { "vpclmulqdq", "on" }, 5419 { "stibp-always-on", "on" }, 5420 { "amd-psfd", "on" }, 5421 { "no-nested-data-bp", "on" }, 5422 { "lfence-always-serializing", "on" }, 5423 { "null-sel-clr-base", "on" }, 5424 { /* end of list */ } 5425 }, 5426 .cache_info = &epyc_milan_v2_cache_info 5427 }, 5428 { /* end of list */ } 5429 } 5430 }, 5431 { 5432 .name = "EPYC-Genoa", 5433 .level = 0xd, 5434 .vendor = CPUID_VENDOR_AMD, 5435 .family = 25, 5436 .model = 17, 5437 .stepping = 0, 5438 .features[FEAT_1_EDX] = 5439 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5440 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5441 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5442 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5443 CPUID_VME | CPUID_FP87, 5444 .features[FEAT_1_ECX] = 5445 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5446 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5447 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5448 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5449 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5450 CPUID_EXT_SSE3, 5451 .features[FEAT_8000_0001_EDX] = 5452 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5453 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5454 CPUID_EXT2_SYSCALL, 5455 .features[FEAT_8000_0001_ECX] = 5456 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5457 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5458 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5459 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5460 .features[FEAT_8000_0008_EBX] = 5461 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5462 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5463 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5464 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5465 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5466 .features[FEAT_8000_0021_EAX] = 5467 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5468 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5469 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5470 CPUID_8000_0021_EAX_AUTO_IBRS, 5471 .features[FEAT_7_0_EBX] = 5472 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5473 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5474 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5475 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5476 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5477 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5478 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5479 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5480 .features[FEAT_7_0_ECX] = 5481 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5482 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5483 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5484 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5485 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5486 CPUID_7_0_ECX_RDPID, 5487 .features[FEAT_7_0_EDX] = 5488 CPUID_7_0_EDX_FSRM, 5489 .features[FEAT_7_1_EAX] = 5490 CPUID_7_1_EAX_AVX512_BF16, 5491 .features[FEAT_XSAVE] = 5492 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5493 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5494 .features[FEAT_6_EAX] = 5495 CPUID_6_EAX_ARAT, 5496 .features[FEAT_SVM] = 5497 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5498 CPUID_SVM_SVME_ADDR_CHK, 5499 .xlevel = 0x80000022, 5500 .model_id = "AMD EPYC-Genoa Processor", 5501 .cache_info = &epyc_genoa_cache_info, 5502 }, 5503 { 5504 .name = "YongFeng", 5505 .level = 0x1F, 5506 .vendor = CPUID_VENDOR_ZHAOXIN1, 5507 .family = 7, 5508 .model = 11, 5509 .stepping = 3, 5510 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 5511 .features[FEAT_1_EDX] = 5512 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5513 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5514 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5515 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5516 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 5517 /* 5518 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 5519 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 5520 */ 5521 .features[FEAT_1_ECX] = 5522 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5523 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 5524 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 5525 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 5526 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5527 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5528 .features[FEAT_7_0_EBX] = 5529 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 5530 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 5531 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 5532 CPUID_7_0_EBX_FSGSBASE, 5533 /* missing: CPUID_7_0_ECX_OSPKE */ 5534 .features[FEAT_7_0_ECX] = 5535 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 5536 .features[FEAT_7_0_EDX] = 5537 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 5538 .features[FEAT_8000_0001_EDX] = 5539 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5540 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5541 .features[FEAT_8000_0001_ECX] = 5542 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 5543 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 5544 /* 5545 * TODO: When the Linux kernel introduces other existing definitions 5546 * for this leaf, remember to update the definitions here. 5547 */ 5548 .features[FEAT_C000_0001_EDX] = 5549 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 5550 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 5551 CPUID_C000_0001_EDX_ACE2 | 5552 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 5553 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 5554 .features[FEAT_XSAVE] = 5555 CPUID_XSAVE_XSAVEOPT, 5556 .features[FEAT_ARCH_CAPABILITIES] = 5557 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 5558 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 5559 MSR_ARCH_CAP_SSB_NO, 5560 .features[FEAT_VMX_PROCBASED_CTLS] = 5561 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 5562 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 5563 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 5564 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 5565 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 5566 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 5567 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 5568 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5569 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 5570 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5571 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5572 /* 5573 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 5574 * VMX_SECONDARY_EXEC_TSC_SCALING 5575 */ 5576 .features[FEAT_VMX_SECONDARY_CTLS] = 5577 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5578 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5579 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 5580 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5581 VMX_SECONDARY_EXEC_WBINVD_EXITING | 5582 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5583 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5584 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5585 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5586 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5587 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 5588 VMX_SECONDARY_EXEC_SHADOW_VMCS | 5589 VMX_SECONDARY_EXEC_ENABLE_PML, 5590 .features[FEAT_VMX_PINBASED_CTLS] = 5591 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5592 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5593 VMX_PIN_BASED_POSTED_INTR, 5594 .features[FEAT_VMX_EXIT_CTLS] = 5595 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 5596 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5597 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5598 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5599 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5600 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 5601 .features[FEAT_VMX_ENTRY_CTLS] = 5602 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5603 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5604 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5605 /* 5606 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 5607 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 5608 */ 5609 .features[FEAT_VMX_MISC] = 5610 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5611 MSR_VMX_MISC_VMWRITE_VMEXIT, 5612 /* missing: MSR_VMX_EPT_UC */ 5613 .features[FEAT_VMX_EPT_VPID_CAPS] = 5614 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5615 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5616 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5617 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5618 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 5619 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5620 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5621 .features[FEAT_VMX_BASIC] = 5622 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5623 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5624 .xlevel = 0x80000008, 5625 .model_id = "Zhaoxin YongFeng Processor", 5626 .versions = (X86CPUVersionDefinition[]) { 5627 { .version = 1 }, 5628 { 5629 .version = 2, 5630 .note = "with the correct model number", 5631 .props = (PropValue[]) { 5632 { "model", "0x5b" }, 5633 { /* end of list */ } 5634 } 5635 }, 5636 { /* end of list */ } 5637 } 5638 }, 5639 }; 5640 5641 /* 5642 * We resolve CPU model aliases using -v1 when using "-machine 5643 * none", but this is just for compatibility while libvirt isn't 5644 * adapted to resolve CPU model versions before creating VMs. 5645 * See "Runnability guarantee of CPU models" at 5646 * docs/about/deprecated.rst. 5647 */ 5648 X86CPUVersion default_cpu_version = 1; 5649 5650 void x86_cpu_set_default_version(X86CPUVersion version) 5651 { 5652 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5653 assert(version != CPU_VERSION_AUTO); 5654 default_cpu_version = version; 5655 } 5656 5657 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5658 { 5659 int v = 0; 5660 const X86CPUVersionDefinition *vdef = 5661 x86_cpu_def_get_versions(model->cpudef); 5662 while (vdef->version) { 5663 v = vdef->version; 5664 vdef++; 5665 } 5666 return v; 5667 } 5668 5669 /* Return the actual version being used for a specific CPU model */ 5670 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5671 { 5672 X86CPUVersion v = model->version; 5673 if (v == CPU_VERSION_AUTO) { 5674 v = default_cpu_version; 5675 } 5676 if (v == CPU_VERSION_LATEST) { 5677 return x86_cpu_model_last_version(model); 5678 } 5679 return v; 5680 } 5681 5682 static const Property max_x86_cpu_properties[] = { 5683 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5684 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5685 }; 5686 5687 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5688 { 5689 Object *obj = OBJECT(dev); 5690 5691 if (!object_property_get_int(obj, "family", &error_abort)) { 5692 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5693 object_property_set_int(obj, "family", 15, &error_abort); 5694 object_property_set_int(obj, "model", 107, &error_abort); 5695 object_property_set_int(obj, "stepping", 1, &error_abort); 5696 } else { 5697 object_property_set_int(obj, "family", 6, &error_abort); 5698 object_property_set_int(obj, "model", 6, &error_abort); 5699 object_property_set_int(obj, "stepping", 3, &error_abort); 5700 } 5701 } 5702 5703 x86_cpu_realizefn(dev, errp); 5704 } 5705 5706 static void max_x86_cpu_class_init(ObjectClass *oc, const void *data) 5707 { 5708 DeviceClass *dc = DEVICE_CLASS(oc); 5709 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5710 5711 xcc->ordering = 9; 5712 5713 xcc->model_description = 5714 "Enables all features supported by the accelerator in the current host"; 5715 5716 device_class_set_props(dc, max_x86_cpu_properties); 5717 dc->realize = max_x86_cpu_realize; 5718 } 5719 5720 static void max_x86_cpu_initfn(Object *obj) 5721 { 5722 X86CPU *cpu = X86_CPU(obj); 5723 5724 /* We can't fill the features array here because we don't know yet if 5725 * "migratable" is true or false. 5726 */ 5727 cpu->max_features = true; 5728 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5729 5730 /* 5731 * these defaults are used for TCG and all other accelerators 5732 * besides KVM and HVF, which overwrite these values 5733 */ 5734 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5735 &error_abort); 5736 object_property_set_str(OBJECT(cpu), "model-id", 5737 "QEMU TCG CPU version " QEMU_HW_VERSION, 5738 &error_abort); 5739 } 5740 5741 static const TypeInfo max_x86_cpu_type_info = { 5742 .name = X86_CPU_TYPE_NAME("max"), 5743 .parent = TYPE_X86_CPU, 5744 .instance_init = max_x86_cpu_initfn, 5745 .class_init = max_x86_cpu_class_init, 5746 }; 5747 5748 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5749 { 5750 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5751 5752 switch (f->type) { 5753 case CPUID_FEATURE_WORD: 5754 { 5755 const char *reg = get_register_name_32(f->cpuid.reg); 5756 assert(reg); 5757 return g_strdup_printf("CPUID.%02XH:%s", 5758 f->cpuid.eax, reg); 5759 } 5760 case MSR_FEATURE_WORD: 5761 return g_strdup_printf("MSR(%02XH)", 5762 f->msr.index); 5763 } 5764 5765 return NULL; 5766 } 5767 5768 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5769 { 5770 FeatureWord w; 5771 5772 for (w = 0; w < FEATURE_WORDS; w++) { 5773 if (cpu->filtered_features[w]) { 5774 return true; 5775 } 5776 } 5777 5778 return false; 5779 } 5780 5781 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5782 const char *verbose_prefix) 5783 { 5784 CPUX86State *env = &cpu->env; 5785 FeatureWordInfo *f = &feature_word_info[w]; 5786 int i; 5787 5788 if (!cpu->force_features) { 5789 env->features[w] &= ~mask; 5790 } 5791 cpu->filtered_features[w] |= mask; 5792 5793 if (!verbose_prefix) { 5794 return; 5795 } 5796 5797 for (i = 0; i < 64; ++i) { 5798 if ((1ULL << i) & mask) { 5799 g_autofree char *feat_word_str = feature_word_description(f, i); 5800 warn_report("%s: %s%s%s [bit %d]", 5801 verbose_prefix, 5802 feat_word_str, 5803 f->feat_names[i] ? "." : "", 5804 f->feat_names[i] ? f->feat_names[i] : "", i); 5805 } 5806 } 5807 } 5808 5809 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5810 const char *name, void *opaque, 5811 Error **errp) 5812 { 5813 X86CPU *cpu = X86_CPU(obj); 5814 CPUX86State *env = &cpu->env; 5815 uint64_t value; 5816 5817 value = (env->cpuid_version >> 8) & 0xf; 5818 if (value == 0xf) { 5819 value += (env->cpuid_version >> 20) & 0xff; 5820 } 5821 visit_type_uint64(v, name, &value, errp); 5822 } 5823 5824 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5825 const char *name, void *opaque, 5826 Error **errp) 5827 { 5828 X86CPU *cpu = X86_CPU(obj); 5829 CPUX86State *env = &cpu->env; 5830 const uint64_t max = 0xff + 0xf; 5831 uint64_t value; 5832 5833 if (!visit_type_uint64(v, name, &value, errp)) { 5834 return; 5835 } 5836 if (value > max) { 5837 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5838 name ? name : "null", max); 5839 return; 5840 } 5841 5842 env->cpuid_version &= ~0xff00f00; 5843 if (value > 0x0f) { 5844 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5845 } else { 5846 env->cpuid_version |= value << 8; 5847 } 5848 } 5849 5850 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5851 const char *name, void *opaque, 5852 Error **errp) 5853 { 5854 X86CPU *cpu = X86_CPU(obj); 5855 CPUX86State *env = &cpu->env; 5856 uint64_t value; 5857 5858 value = (env->cpuid_version >> 4) & 0xf; 5859 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5860 visit_type_uint64(v, name, &value, errp); 5861 } 5862 5863 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5864 const char *name, void *opaque, 5865 Error **errp) 5866 { 5867 X86CPU *cpu = X86_CPU(obj); 5868 CPUX86State *env = &cpu->env; 5869 const uint64_t max = 0xff; 5870 uint64_t value; 5871 5872 if (!visit_type_uint64(v, name, &value, errp)) { 5873 return; 5874 } 5875 if (value > max) { 5876 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5877 name ? name : "null", max); 5878 return; 5879 } 5880 5881 env->cpuid_version &= ~0xf00f0; 5882 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5883 } 5884 5885 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5886 const char *name, void *opaque, 5887 Error **errp) 5888 { 5889 X86CPU *cpu = X86_CPU(obj); 5890 CPUX86State *env = &cpu->env; 5891 uint64_t value; 5892 5893 value = env->cpuid_version & 0xf; 5894 visit_type_uint64(v, name, &value, errp); 5895 } 5896 5897 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5898 const char *name, void *opaque, 5899 Error **errp) 5900 { 5901 X86CPU *cpu = X86_CPU(obj); 5902 CPUX86State *env = &cpu->env; 5903 const uint64_t max = 0xf; 5904 uint64_t value; 5905 5906 if (!visit_type_uint64(v, name, &value, errp)) { 5907 return; 5908 } 5909 if (value > max) { 5910 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5911 name ? name : "null", max); 5912 return; 5913 } 5914 5915 env->cpuid_version &= ~0xf; 5916 env->cpuid_version |= value & 0xf; 5917 } 5918 5919 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5920 { 5921 X86CPU *cpu = X86_CPU(obj); 5922 CPUX86State *env = &cpu->env; 5923 char *value; 5924 5925 value = g_malloc(CPUID_VENDOR_SZ + 1); 5926 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5927 env->cpuid_vendor3); 5928 return value; 5929 } 5930 5931 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5932 Error **errp) 5933 { 5934 X86CPU *cpu = X86_CPU(obj); 5935 CPUX86State *env = &cpu->env; 5936 int i; 5937 5938 if (strlen(value) != CPUID_VENDOR_SZ) { 5939 error_setg(errp, "value of property 'vendor' must consist of" 5940 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5941 return; 5942 } 5943 5944 env->cpuid_vendor1 = 0; 5945 env->cpuid_vendor2 = 0; 5946 env->cpuid_vendor3 = 0; 5947 for (i = 0; i < 4; i++) { 5948 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5949 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5950 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5951 } 5952 } 5953 5954 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5955 { 5956 X86CPU *cpu = X86_CPU(obj); 5957 CPUX86State *env = &cpu->env; 5958 char *value; 5959 int i; 5960 5961 value = g_malloc(48 + 1); 5962 for (i = 0; i < 48; i++) { 5963 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5964 } 5965 value[48] = '\0'; 5966 return value; 5967 } 5968 5969 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5970 Error **errp) 5971 { 5972 X86CPU *cpu = X86_CPU(obj); 5973 CPUX86State *env = &cpu->env; 5974 int c, len, i; 5975 5976 if (model_id == NULL) { 5977 model_id = ""; 5978 } 5979 len = strlen(model_id); 5980 memset(env->cpuid_model, 0, 48); 5981 for (i = 0; i < 48; i++) { 5982 if (i >= len) { 5983 c = '\0'; 5984 } else { 5985 c = (uint8_t)model_id[i]; 5986 } 5987 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5988 } 5989 } 5990 5991 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5992 void *opaque, Error **errp) 5993 { 5994 X86CPU *cpu = X86_CPU(obj); 5995 int64_t value; 5996 5997 value = cpu->env.tsc_khz * 1000; 5998 visit_type_int(v, name, &value, errp); 5999 } 6000 6001 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 6002 void *opaque, Error **errp) 6003 { 6004 X86CPU *cpu = X86_CPU(obj); 6005 const int64_t max = INT64_MAX; 6006 int64_t value; 6007 6008 if (!visit_type_int(v, name, &value, errp)) { 6009 return; 6010 } 6011 if (value < 0 || value > max) { 6012 error_setg(errp, "parameter '%s' can be at most %" PRId64, 6013 name ? name : "null", max); 6014 return; 6015 } 6016 6017 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 6018 } 6019 6020 /* Generic getter for "feature-words" and "filtered-features" properties */ 6021 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 6022 const char *name, void *opaque, 6023 Error **errp) 6024 { 6025 uint64_t *array = (uint64_t *)opaque; 6026 FeatureWord w; 6027 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 6028 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 6029 X86CPUFeatureWordInfoList *list = NULL; 6030 6031 for (w = 0; w < FEATURE_WORDS; w++) { 6032 FeatureWordInfo *wi = &feature_word_info[w]; 6033 /* 6034 * We didn't have MSR features when "feature-words" was 6035 * introduced. Therefore skipped other type entries. 6036 */ 6037 if (wi->type != CPUID_FEATURE_WORD) { 6038 continue; 6039 } 6040 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 6041 qwi->cpuid_input_eax = wi->cpuid.eax; 6042 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 6043 qwi->cpuid_input_ecx = wi->cpuid.ecx; 6044 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 6045 qwi->features = array[w]; 6046 6047 /* List will be in reverse order, but order shouldn't matter */ 6048 list_entries[w].next = list; 6049 list_entries[w].value = &word_infos[w]; 6050 list = &list_entries[w]; 6051 } 6052 6053 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 6054 } 6055 6056 /* Convert all '_' in a feature string option name to '-', to make feature 6057 * name conform to QOM property naming rule, which uses '-' instead of '_'. 6058 */ 6059 static inline void feat2prop(char *s) 6060 { 6061 while ((s = strchr(s, '_'))) { 6062 *s = '-'; 6063 } 6064 } 6065 6066 /* Return the feature property name for a feature flag bit */ 6067 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 6068 { 6069 const char *name; 6070 /* XSAVE components are automatically enabled by other features, 6071 * so return the original feature name instead 6072 */ 6073 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 6074 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 6075 6076 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 6077 x86_ext_save_areas[comp].bits) { 6078 w = x86_ext_save_areas[comp].feature; 6079 bitnr = ctz32(x86_ext_save_areas[comp].bits); 6080 } 6081 } 6082 6083 assert(bitnr < 64); 6084 assert(w < FEATURE_WORDS); 6085 name = feature_word_info[w].feat_names[bitnr]; 6086 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 6087 return name; 6088 } 6089 6090 /* Compatibility hack to maintain legacy +-feat semantic, 6091 * where +-feat overwrites any feature set by 6092 * feat=on|feat even if the later is parsed after +-feat 6093 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 6094 */ 6095 static GList *plus_features, *minus_features; 6096 6097 static gint compare_string(gconstpointer a, gconstpointer b) 6098 { 6099 return g_strcmp0(a, b); 6100 } 6101 6102 /* Parse "+feature,-feature,feature=foo" CPU feature string 6103 */ 6104 static void x86_cpu_parse_featurestr(const char *typename, char *features, 6105 Error **errp) 6106 { 6107 char *featurestr; /* Single 'key=value" string being parsed */ 6108 static bool cpu_globals_initialized; 6109 bool ambiguous = false; 6110 6111 if (cpu_globals_initialized) { 6112 return; 6113 } 6114 cpu_globals_initialized = true; 6115 6116 if (!features) { 6117 return; 6118 } 6119 6120 for (featurestr = strtok(features, ","); 6121 featurestr; 6122 featurestr = strtok(NULL, ",")) { 6123 const char *name; 6124 const char *val = NULL; 6125 char *eq = NULL; 6126 char num[32]; 6127 GlobalProperty *prop; 6128 6129 /* Compatibility syntax: */ 6130 if (featurestr[0] == '+') { 6131 plus_features = g_list_append(plus_features, 6132 g_strdup(featurestr + 1)); 6133 continue; 6134 } else if (featurestr[0] == '-') { 6135 minus_features = g_list_append(minus_features, 6136 g_strdup(featurestr + 1)); 6137 continue; 6138 } 6139 6140 eq = strchr(featurestr, '='); 6141 if (eq) { 6142 *eq++ = 0; 6143 val = eq; 6144 } else { 6145 val = "on"; 6146 } 6147 6148 feat2prop(featurestr); 6149 name = featurestr; 6150 6151 if (g_list_find_custom(plus_features, name, compare_string)) { 6152 warn_report("Ambiguous CPU model string. " 6153 "Don't mix both \"+%s\" and \"%s=%s\"", 6154 name, name, val); 6155 ambiguous = true; 6156 } 6157 if (g_list_find_custom(minus_features, name, compare_string)) { 6158 warn_report("Ambiguous CPU model string. " 6159 "Don't mix both \"-%s\" and \"%s=%s\"", 6160 name, name, val); 6161 ambiguous = true; 6162 } 6163 6164 /* Special case: */ 6165 if (!strcmp(name, "tsc-freq")) { 6166 int ret; 6167 uint64_t tsc_freq; 6168 6169 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 6170 if (ret < 0 || tsc_freq > INT64_MAX) { 6171 error_setg(errp, "bad numerical value %s", val); 6172 return; 6173 } 6174 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 6175 val = num; 6176 name = "tsc-frequency"; 6177 } 6178 6179 prop = g_new0(typeof(*prop), 1); 6180 prop->driver = typename; 6181 prop->property = g_strdup(name); 6182 prop->value = g_strdup(val); 6183 qdev_prop_register_global(prop); 6184 } 6185 6186 if (ambiguous) { 6187 warn_report("Compatibility of ambiguous CPU model " 6188 "strings won't be kept on future QEMU versions"); 6189 } 6190 } 6191 6192 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 6193 6194 /* Build a list with the name of all features on a feature word array */ 6195 static void x86_cpu_list_feature_names(FeatureWordArray features, 6196 strList **list) 6197 { 6198 strList **tail = list; 6199 FeatureWord w; 6200 6201 for (w = 0; w < FEATURE_WORDS; w++) { 6202 uint64_t filtered = features[w]; 6203 int i; 6204 for (i = 0; i < 64; i++) { 6205 if (filtered & (1ULL << i)) { 6206 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 6207 } 6208 } 6209 } 6210 } 6211 6212 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 6213 const char *name, void *opaque, 6214 Error **errp) 6215 { 6216 X86CPU *xc = X86_CPU(obj); 6217 strList *result = NULL; 6218 6219 x86_cpu_list_feature_names(xc->filtered_features, &result); 6220 visit_type_strList(v, "unavailable-features", &result, errp); 6221 } 6222 6223 /* Print all cpuid feature names in featureset 6224 */ 6225 static void listflags(GList *features) 6226 { 6227 size_t len = 0; 6228 GList *tmp; 6229 6230 for (tmp = features; tmp; tmp = tmp->next) { 6231 const char *name = tmp->data; 6232 if ((len + strlen(name) + 1) >= 75) { 6233 qemu_printf("\n"); 6234 len = 0; 6235 } 6236 qemu_printf("%s%s", len == 0 ? " " : " ", name); 6237 len += strlen(name) + 1; 6238 } 6239 qemu_printf("\n"); 6240 } 6241 6242 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 6243 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d) 6244 { 6245 ObjectClass *class_a = (ObjectClass *)a; 6246 ObjectClass *class_b = (ObjectClass *)b; 6247 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 6248 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 6249 int ret; 6250 6251 if (cc_a->ordering != cc_b->ordering) { 6252 ret = cc_a->ordering - cc_b->ordering; 6253 } else { 6254 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 6255 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 6256 ret = strcmp(name_a, name_b); 6257 } 6258 return ret; 6259 } 6260 6261 static GSList *get_sorted_cpu_model_list(void) 6262 { 6263 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 6264 list = g_slist_sort_with_data(list, x86_cpu_list_compare, NULL); 6265 return list; 6266 } 6267 6268 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 6269 { 6270 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 6271 char *r = object_property_get_str(obj, "model-id", &error_abort); 6272 object_unref(obj); 6273 return r; 6274 } 6275 6276 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 6277 { 6278 X86CPUVersion version; 6279 6280 if (!cc->model || !cc->model->is_alias) { 6281 return NULL; 6282 } 6283 version = x86_cpu_model_resolve_version(cc->model); 6284 if (version <= 0) { 6285 return NULL; 6286 } 6287 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 6288 } 6289 6290 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 6291 { 6292 ObjectClass *oc = data; 6293 X86CPUClass *cc = X86_CPU_CLASS(oc); 6294 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6295 g_autofree char *desc = g_strdup(cc->model_description); 6296 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6297 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6298 6299 if (!desc && alias_of) { 6300 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6301 desc = g_strdup("(alias configured by machine type)"); 6302 } else { 6303 desc = g_strdup_printf("(alias of %s)", alias_of); 6304 } 6305 } 6306 if (!desc && cc->model && cc->model->note) { 6307 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6308 } 6309 if (!desc) { 6310 desc = g_strdup(model_id); 6311 } 6312 6313 if (cc->model && cc->model->cpudef->deprecation_note) { 6314 g_autofree char *olddesc = desc; 6315 desc = g_strdup_printf("%s (deprecated)", olddesc); 6316 } 6317 6318 qemu_printf(" %-20s %s\n", name, desc); 6319 } 6320 6321 static gint strcmp_wrap(gconstpointer a, gconstpointer b, gpointer d) 6322 { 6323 return strcmp(a, b); 6324 } 6325 6326 /* list available CPU models and flags */ 6327 static void x86_cpu_list(void) 6328 { 6329 int i, j; 6330 GSList *list; 6331 GList *names = NULL; 6332 6333 qemu_printf("Available CPUs:\n"); 6334 list = get_sorted_cpu_model_list(); 6335 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6336 g_slist_free(list); 6337 6338 names = NULL; 6339 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6340 FeatureWordInfo *fw = &feature_word_info[i]; 6341 for (j = 0; j < 64; j++) { 6342 if (fw->feat_names[j]) { 6343 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6344 } 6345 } 6346 } 6347 6348 names = g_list_sort_with_data(names, strcmp_wrap, NULL); 6349 6350 qemu_printf("\nRecognized CPUID flags:\n"); 6351 listflags(names); 6352 qemu_printf("\n"); 6353 g_list_free(names); 6354 } 6355 6356 #ifndef CONFIG_USER_ONLY 6357 6358 /* Check for missing features that may prevent the CPU class from 6359 * running using the current machine and accelerator. 6360 */ 6361 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6362 strList **list) 6363 { 6364 strList **tail = list; 6365 X86CPU *xc; 6366 Error *err = NULL; 6367 6368 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6369 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6370 return; 6371 } 6372 6373 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6374 6375 x86_cpu_expand_features(xc, &err); 6376 if (err) { 6377 /* Errors at x86_cpu_expand_features should never happen, 6378 * but in case it does, just report the model as not 6379 * runnable at all using the "type" property. 6380 */ 6381 QAPI_LIST_APPEND(tail, g_strdup("type")); 6382 error_free(err); 6383 } 6384 6385 x86_cpu_filter_features(xc, false); 6386 6387 x86_cpu_list_feature_names(xc->filtered_features, tail); 6388 6389 object_unref(OBJECT(xc)); 6390 } 6391 6392 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6393 { 6394 ObjectClass *oc = data; 6395 X86CPUClass *cc = X86_CPU_CLASS(oc); 6396 CpuDefinitionInfoList **cpu_list = user_data; 6397 CpuDefinitionInfo *info; 6398 6399 info = g_malloc0(sizeof(*info)); 6400 info->name = x86_cpu_class_get_model_name(cc); 6401 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6402 info->has_unavailable_features = true; 6403 info->q_typename = g_strdup(object_class_get_name(oc)); 6404 info->migration_safe = cc->migration_safe; 6405 info->has_migration_safe = true; 6406 info->q_static = cc->static_model; 6407 if (cc->model && cc->model->cpudef->deprecation_note) { 6408 info->deprecated = true; 6409 } else { 6410 info->deprecated = false; 6411 } 6412 /* 6413 * Old machine types won't report aliases, so that alias translation 6414 * doesn't break compatibility with previous QEMU versions. 6415 */ 6416 if (default_cpu_version != CPU_VERSION_LEGACY) { 6417 info->alias_of = x86_cpu_class_get_alias_of(cc); 6418 } 6419 6420 QAPI_LIST_PREPEND(*cpu_list, info); 6421 } 6422 6423 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6424 { 6425 CpuDefinitionInfoList *cpu_list = NULL; 6426 GSList *list = get_sorted_cpu_model_list(); 6427 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6428 g_slist_free(list); 6429 return cpu_list; 6430 } 6431 6432 #endif /* !CONFIG_USER_ONLY */ 6433 6434 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6435 { 6436 FeatureWordInfo *wi = &feature_word_info[w]; 6437 uint64_t r = 0; 6438 uint64_t unavail = 0; 6439 6440 if (kvm_enabled()) { 6441 switch (wi->type) { 6442 case CPUID_FEATURE_WORD: 6443 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6444 wi->cpuid.ecx, 6445 wi->cpuid.reg); 6446 break; 6447 case MSR_FEATURE_WORD: 6448 r = kvm_arch_get_supported_msr_feature(kvm_state, 6449 wi->msr.index); 6450 break; 6451 } 6452 } else if (hvf_enabled()) { 6453 if (wi->type != CPUID_FEATURE_WORD) { 6454 return 0; 6455 } 6456 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6457 wi->cpuid.ecx, 6458 wi->cpuid.reg); 6459 } else if (tcg_enabled()) { 6460 r = wi->tcg_features; 6461 } else { 6462 return ~0; 6463 } 6464 6465 switch (w) { 6466 #ifndef TARGET_X86_64 6467 case FEAT_8000_0001_EDX: 6468 /* 6469 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6470 * way for userspace to get out of its 32-bit jail, we can leave 6471 * the LM bit set. 6472 */ 6473 unavail = tcg_enabled() 6474 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6475 : CPUID_EXT2_LM; 6476 break; 6477 #endif 6478 6479 case FEAT_8000_0007_EBX: 6480 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6481 /* Disable AMD machine check architecture for Intel CPU. */ 6482 unavail = ~0; 6483 } 6484 break; 6485 6486 case FEAT_7_0_EBX: 6487 #ifndef CONFIG_USER_ONLY 6488 if (!check_sgx_support()) { 6489 unavail = CPUID_7_0_EBX_SGX; 6490 } 6491 #endif 6492 break; 6493 case FEAT_7_0_ECX: 6494 #ifndef CONFIG_USER_ONLY 6495 if (!check_sgx_support()) { 6496 unavail = CPUID_7_0_ECX_SGX_LC; 6497 } 6498 #endif 6499 break; 6500 6501 default: 6502 break; 6503 } 6504 6505 r &= ~unavail; 6506 if (cpu && cpu->migratable) { 6507 r &= x86_cpu_get_migratable_flags(cpu, w); 6508 } 6509 return r; 6510 } 6511 6512 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6513 uint32_t *eax, uint32_t *ebx, 6514 uint32_t *ecx, uint32_t *edx) 6515 { 6516 if (kvm_enabled()) { 6517 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6518 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6519 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6520 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6521 } else if (hvf_enabled()) { 6522 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6523 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6524 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6525 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6526 } else { 6527 *eax = 0; 6528 *ebx = 0; 6529 *ecx = 0; 6530 *edx = 0; 6531 } 6532 } 6533 6534 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6535 uint32_t *eax, uint32_t *ebx, 6536 uint32_t *ecx, uint32_t *edx) 6537 { 6538 uint32_t level, unused; 6539 6540 /* Only return valid host leaves. */ 6541 switch (func) { 6542 case 2: 6543 case 4: 6544 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6545 break; 6546 case 0x80000005: 6547 case 0x80000006: 6548 case 0x8000001d: 6549 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6550 break; 6551 default: 6552 return; 6553 } 6554 6555 if (func > level) { 6556 *eax = 0; 6557 *ebx = 0; 6558 *ecx = 0; 6559 *edx = 0; 6560 } else { 6561 host_cpuid(func, index, eax, ebx, ecx, edx); 6562 } 6563 } 6564 6565 /* 6566 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6567 */ 6568 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6569 { 6570 PropValue *pv; 6571 for (pv = props; pv->prop; pv++) { 6572 if (!pv->value) { 6573 continue; 6574 } 6575 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6576 &error_abort); 6577 } 6578 } 6579 6580 /* 6581 * Apply properties for the CPU model version specified in model. 6582 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6583 */ 6584 6585 static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) 6586 { 6587 const X86CPUVersionDefinition *vdef; 6588 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6589 6590 if (version == CPU_VERSION_LEGACY) { 6591 return; 6592 } 6593 6594 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6595 PropValue *p; 6596 6597 for (p = vdef->props; p && p->prop; p++) { 6598 object_property_parse(OBJECT(cpu), p->prop, p->value, 6599 &error_abort); 6600 } 6601 6602 if (vdef->version == version) { 6603 break; 6604 } 6605 } 6606 6607 /* 6608 * If we reached the end of the list, version number was invalid 6609 */ 6610 assert(vdef->version == version); 6611 } 6612 6613 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6614 const X86CPUModel *model) 6615 { 6616 const X86CPUVersionDefinition *vdef; 6617 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6618 const CPUCaches *cache_info = model->cpudef->cache_info; 6619 6620 if (version == CPU_VERSION_LEGACY) { 6621 return cache_info; 6622 } 6623 6624 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6625 if (vdef->cache_info) { 6626 cache_info = vdef->cache_info; 6627 } 6628 6629 if (vdef->version == version) { 6630 break; 6631 } 6632 } 6633 6634 assert(vdef->version == version); 6635 return cache_info; 6636 } 6637 6638 /* 6639 * Load data from X86CPUDefinition into a X86CPU object. 6640 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6641 */ 6642 static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) 6643 { 6644 const X86CPUDefinition *def = model->cpudef; 6645 CPUX86State *env = &cpu->env; 6646 FeatureWord w; 6647 6648 /*NOTE: any property set by this function should be returned by 6649 * x86_cpu_static_props(), so static expansion of 6650 * query-cpu-model-expansion is always complete. 6651 */ 6652 6653 /* CPU models only set _minimum_ values for level/xlevel: */ 6654 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6655 &error_abort); 6656 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6657 &error_abort); 6658 6659 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6660 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6661 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6662 &error_abort); 6663 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6664 &error_abort); 6665 for (w = 0; w < FEATURE_WORDS; w++) { 6666 env->features[w] = def->features[w]; 6667 } 6668 6669 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6670 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6671 6672 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6673 6674 /* sysenter isn't supported in compatibility mode on AMD, 6675 * syscall isn't supported in compatibility mode on Intel. 6676 * Normally we advertise the actual CPU vendor, but you can 6677 * override this using the 'vendor' property if you want to use 6678 * KVM's sysenter/syscall emulation in compatibility mode and 6679 * when doing cross vendor migration 6680 */ 6681 6682 /* 6683 * vendor property is set here but then overloaded with the 6684 * host cpu vendor for KVM and HVF. 6685 */ 6686 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6687 6688 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 6689 &error_abort); 6690 6691 x86_cpu_apply_version_props(cpu, model); 6692 6693 /* 6694 * Properties in versioned CPU model are not user specified features. 6695 * We can simply clear env->user_features here since it will be filled later 6696 * in x86_cpu_expand_features() based on plus_features and minus_features. 6697 */ 6698 memset(&env->user_features, 0, sizeof(env->user_features)); 6699 } 6700 6701 static const gchar *x86_gdb_arch_name(CPUState *cs) 6702 { 6703 #ifdef TARGET_X86_64 6704 return "i386:x86-64"; 6705 #else 6706 return "i386"; 6707 #endif 6708 } 6709 6710 static void x86_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 6711 { 6712 const X86CPUModel *model = data; 6713 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6714 CPUClass *cc = CPU_CLASS(oc); 6715 6716 xcc->model = model; 6717 xcc->migration_safe = true; 6718 cc->deprecation_note = model->cpudef->deprecation_note; 6719 } 6720 6721 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6722 { 6723 g_autofree char *typename = x86_cpu_type_name(name); 6724 TypeInfo ti = { 6725 .name = typename, 6726 .parent = TYPE_X86_CPU, 6727 .class_init = x86_cpu_cpudef_class_init, 6728 .class_data = model, 6729 }; 6730 6731 type_register_static(&ti); 6732 } 6733 6734 6735 /* 6736 * register builtin_x86_defs; 6737 * "max", "base" and subclasses ("host") are not registered here. 6738 * See x86_cpu_register_types for all model registrations. 6739 */ 6740 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6741 { 6742 X86CPUModel *m; 6743 const X86CPUVersionDefinition *vdef; 6744 6745 /* AMD aliases are handled at runtime based on CPUID vendor, so 6746 * they shouldn't be set on the CPU model table. 6747 */ 6748 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6749 /* catch mistakes instead of silently truncating model_id when too long */ 6750 assert(def->model_id && strlen(def->model_id) <= 48); 6751 6752 /* Unversioned model: */ 6753 m = g_new0(X86CPUModel, 1); 6754 m->cpudef = def; 6755 m->version = CPU_VERSION_AUTO; 6756 m->is_alias = true; 6757 x86_register_cpu_model_type(def->name, m); 6758 6759 /* Versioned models: */ 6760 6761 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6762 g_autofree char *name = 6763 x86_cpu_versioned_model_name(def, vdef->version); 6764 6765 m = g_new0(X86CPUModel, 1); 6766 m->cpudef = def; 6767 m->version = vdef->version; 6768 m->note = vdef->note; 6769 x86_register_cpu_model_type(name, m); 6770 6771 if (vdef->alias) { 6772 X86CPUModel *am = g_new0(X86CPUModel, 1); 6773 am->cpudef = def; 6774 am->version = vdef->version; 6775 am->is_alias = true; 6776 x86_register_cpu_model_type(vdef->alias, am); 6777 } 6778 } 6779 6780 } 6781 6782 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6783 { 6784 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6785 return 57; /* 57 bits virtual */ 6786 } else { 6787 return 48; /* 48 bits virtual */ 6788 } 6789 } 6790 6791 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6792 uint32_t *eax, uint32_t *ebx, 6793 uint32_t *ecx, uint32_t *edx) 6794 { 6795 X86CPU *cpu = env_archcpu(env); 6796 CPUState *cs = env_cpu(env); 6797 uint32_t limit; 6798 uint32_t signature[3]; 6799 X86CPUTopoInfo *topo_info = &env->topo_info; 6800 uint32_t threads_per_pkg; 6801 6802 threads_per_pkg = x86_threads_per_pkg(topo_info); 6803 6804 /* Calculate & apply limits for different index ranges */ 6805 if (index >= 0xC0000000) { 6806 limit = env->cpuid_xlevel2; 6807 } else if (index >= 0x80000000) { 6808 limit = env->cpuid_xlevel; 6809 } else if (index >= 0x40000000) { 6810 limit = 0x40000001; 6811 } else { 6812 limit = env->cpuid_level; 6813 } 6814 6815 if (index > limit) { 6816 /* Intel documentation states that invalid EAX input will 6817 * return the same information as EAX=cpuid_level 6818 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6819 */ 6820 index = env->cpuid_level; 6821 } 6822 6823 switch(index) { 6824 case 0: 6825 *eax = env->cpuid_level; 6826 *ebx = env->cpuid_vendor1; 6827 *edx = env->cpuid_vendor2; 6828 *ecx = env->cpuid_vendor3; 6829 break; 6830 case 1: 6831 *eax = env->cpuid_version; 6832 *ebx = (cpu->apic_id << 24) | 6833 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6834 *ecx = env->features[FEAT_1_ECX]; 6835 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6836 *ecx |= CPUID_EXT_OSXSAVE; 6837 } 6838 *edx = env->features[FEAT_1_EDX]; 6839 if (threads_per_pkg > 1) { 6840 *ebx |= threads_per_pkg << 16; 6841 } 6842 if (!cpu->enable_pmu) { 6843 *ecx &= ~CPUID_EXT_PDCM; 6844 } 6845 break; 6846 case 2: 6847 /* cache info: needed for Pentium Pro compatibility */ 6848 if (cpu->cache_info_passthrough) { 6849 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6850 break; 6851 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6852 *eax = *ebx = *ecx = *edx = 0; 6853 break; 6854 } 6855 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6856 *ebx = 0; 6857 if (!cpu->enable_l3_cache) { 6858 *ecx = 0; 6859 } else { 6860 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6861 } 6862 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6863 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6864 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6865 break; 6866 case 4: 6867 /* cache info: needed for Core compatibility */ 6868 if (cpu->cache_info_passthrough) { 6869 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6870 /* 6871 * QEMU has its own number of cores/logical cpus, 6872 * set 24..14, 31..26 bit to configured values 6873 */ 6874 if (*eax & 31) { 6875 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6876 6877 *eax &= ~0xFC000000; 6878 *eax |= max_core_ids_in_package(topo_info) << 26; 6879 if (host_vcpus_per_cache > threads_per_pkg) { 6880 *eax &= ~0x3FFC000; 6881 6882 /* Share the cache at package level. */ 6883 *eax |= max_thread_ids_for_cache(topo_info, 6884 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 6885 } 6886 } 6887 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6888 *eax = *ebx = *ecx = *edx = 0; 6889 } else { 6890 *eax = 0; 6891 6892 switch (count) { 6893 case 0: /* L1 dcache info */ 6894 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6895 topo_info, 6896 eax, ebx, ecx, edx); 6897 if (!cpu->l1_cache_per_core) { 6898 *eax &= ~MAKE_64BIT_MASK(14, 12); 6899 } 6900 break; 6901 case 1: /* L1 icache info */ 6902 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6903 topo_info, 6904 eax, ebx, ecx, edx); 6905 if (!cpu->l1_cache_per_core) { 6906 *eax &= ~MAKE_64BIT_MASK(14, 12); 6907 } 6908 break; 6909 case 2: /* L2 cache info */ 6910 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6911 topo_info, 6912 eax, ebx, ecx, edx); 6913 break; 6914 case 3: /* L3 cache info */ 6915 if (cpu->enable_l3_cache) { 6916 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6917 topo_info, 6918 eax, ebx, ecx, edx); 6919 break; 6920 } 6921 /* fall through */ 6922 default: /* end of info */ 6923 *eax = *ebx = *ecx = *edx = 0; 6924 break; 6925 } 6926 } 6927 break; 6928 case 5: 6929 /* MONITOR/MWAIT Leaf */ 6930 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6931 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6932 *ecx = cpu->mwait.ecx; /* flags */ 6933 *edx = cpu->mwait.edx; /* mwait substates */ 6934 break; 6935 case 6: 6936 /* Thermal and Power Leaf */ 6937 *eax = env->features[FEAT_6_EAX]; 6938 *ebx = 0; 6939 *ecx = 0; 6940 *edx = 0; 6941 break; 6942 case 7: 6943 /* Structured Extended Feature Flags Enumeration Leaf */ 6944 if (count == 0) { 6945 /* Maximum ECX value for sub-leaves */ 6946 *eax = env->cpuid_level_func7; 6947 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6948 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6949 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6950 *ecx |= CPUID_7_0_ECX_OSPKE; 6951 } 6952 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6953 } else if (count == 1) { 6954 *eax = env->features[FEAT_7_1_EAX]; 6955 *edx = env->features[FEAT_7_1_EDX]; 6956 *ebx = 0; 6957 *ecx = 0; 6958 } else if (count == 2) { 6959 *edx = env->features[FEAT_7_2_EDX]; 6960 *eax = 0; 6961 *ebx = 0; 6962 *ecx = 0; 6963 } else { 6964 *eax = 0; 6965 *ebx = 0; 6966 *ecx = 0; 6967 *edx = 0; 6968 } 6969 break; 6970 case 9: 6971 /* Direct Cache Access Information Leaf */ 6972 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6973 *ebx = 0; 6974 *ecx = 0; 6975 *edx = 0; 6976 break; 6977 case 0xA: 6978 /* Architectural Performance Monitoring Leaf */ 6979 if (cpu->enable_pmu) { 6980 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6981 } else { 6982 *eax = 0; 6983 *ebx = 0; 6984 *ecx = 0; 6985 *edx = 0; 6986 } 6987 break; 6988 case 0xB: 6989 /* Extended Topology Enumeration Leaf */ 6990 if (!cpu->enable_cpuid_0xb) { 6991 *eax = *ebx = *ecx = *edx = 0; 6992 break; 6993 } 6994 6995 *ecx = count & 0xff; 6996 *edx = cpu->apic_id; 6997 6998 switch (count) { 6999 case 0: 7000 *eax = apicid_core_offset(topo_info); 7001 *ebx = topo_info->threads_per_core; 7002 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 7003 break; 7004 case 1: 7005 *eax = apicid_pkg_offset(topo_info); 7006 *ebx = threads_per_pkg; 7007 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 7008 break; 7009 default: 7010 *eax = 0; 7011 *ebx = 0; 7012 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 7013 } 7014 7015 assert(!(*eax & ~0x1f)); 7016 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 7017 break; 7018 case 0x1C: 7019 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7020 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 7021 *edx = 0; 7022 } 7023 break; 7024 case 0x1F: 7025 /* V2 Extended Topology Enumeration Leaf */ 7026 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 7027 *eax = *ebx = *ecx = *edx = 0; 7028 break; 7029 } 7030 7031 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 7032 break; 7033 case 0xD: { 7034 /* Processor Extended State */ 7035 *eax = 0; 7036 *ebx = 0; 7037 *ecx = 0; 7038 *edx = 0; 7039 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7040 break; 7041 } 7042 7043 if (count == 0) { 7044 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 7045 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 7046 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 7047 /* 7048 * The initial value of xcr0 and ebx == 0, On host without kvm 7049 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 7050 * even through guest update xcr0, this will crash some legacy guest 7051 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 7052 */ 7053 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 7054 } else if (count == 1) { 7055 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 7056 x86_cpu_xsave_xss_components(cpu); 7057 7058 *eax = env->features[FEAT_XSAVE]; 7059 *ebx = xsave_area_size(xstate, true); 7060 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 7061 *edx = env->features[FEAT_XSAVE_XSS_HI]; 7062 if (kvm_enabled() && cpu->enable_pmu && 7063 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 7064 (*eax & CPUID_XSAVE_XSAVES)) { 7065 *ecx |= XSTATE_ARCH_LBR_MASK; 7066 } else { 7067 *ecx &= ~XSTATE_ARCH_LBR_MASK; 7068 } 7069 } else if (count == 0xf && cpu->enable_pmu 7070 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7071 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 7072 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 7073 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 7074 7075 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 7076 *eax = esa->size; 7077 *ebx = esa->offset; 7078 *ecx = esa->ecx & 7079 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 7080 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 7081 *eax = esa->size; 7082 *ebx = 0; 7083 *ecx = 1; 7084 } 7085 } 7086 break; 7087 } 7088 case 0x12: 7089 #ifndef CONFIG_USER_ONLY 7090 if (!kvm_enabled() || 7091 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 7092 *eax = *ebx = *ecx = *edx = 0; 7093 break; 7094 } 7095 7096 /* 7097 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 7098 * the EPC properties, e.g. confidentiality and integrity, from the 7099 * host's first EPC section, i.e. assume there is one EPC section or 7100 * that all EPC sections have the same security properties. 7101 */ 7102 if (count > 1) { 7103 uint64_t epc_addr, epc_size; 7104 7105 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 7106 *eax = *ebx = *ecx = *edx = 0; 7107 break; 7108 } 7109 host_cpuid(index, 2, eax, ebx, ecx, edx); 7110 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 7111 *ebx = (uint32_t)(epc_addr >> 32); 7112 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 7113 *edx = (uint32_t)(epc_size >> 32); 7114 break; 7115 } 7116 7117 /* 7118 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 7119 * and KVM, i.e. QEMU cannot emulate features to override what KVM 7120 * supports. Features can be further restricted by userspace, but not 7121 * made more permissive. 7122 */ 7123 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 7124 7125 if (count == 0) { 7126 *eax &= env->features[FEAT_SGX_12_0_EAX]; 7127 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 7128 } else { 7129 *eax &= env->features[FEAT_SGX_12_1_EAX]; 7130 *ebx &= 0; /* ebx reserve */ 7131 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 7132 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 7133 7134 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 7135 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 7136 7137 /* Access to PROVISIONKEY requires additional credentials. */ 7138 if ((*eax & (1U << 4)) && 7139 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 7140 *eax &= ~(1U << 4); 7141 } 7142 } 7143 #endif 7144 break; 7145 case 0x14: { 7146 /* Intel Processor Trace Enumeration */ 7147 *eax = 0; 7148 *ebx = 0; 7149 *ecx = 0; 7150 *edx = 0; 7151 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 7152 !kvm_enabled()) { 7153 break; 7154 } 7155 7156 /* 7157 * If these are changed, they should stay in sync with 7158 * x86_cpu_filter_features(). 7159 */ 7160 if (count == 0) { 7161 *eax = INTEL_PT_MAX_SUBLEAF; 7162 *ebx = INTEL_PT_MINIMAL_EBX; 7163 *ecx = INTEL_PT_MINIMAL_ECX; 7164 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 7165 *ecx |= CPUID_14_0_ECX_LIP; 7166 } 7167 } else if (count == 1) { 7168 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 7169 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 7170 } 7171 break; 7172 } 7173 case 0x1D: { 7174 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 7175 *eax = 0; 7176 *ebx = 0; 7177 *ecx = 0; 7178 *edx = 0; 7179 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7180 break; 7181 } 7182 7183 if (count == 0) { 7184 /* Highest numbered palette subleaf */ 7185 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 7186 } else if (count == 1) { 7187 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 7188 (INTEL_AMX_BYTES_PER_TILE << 16); 7189 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 7190 *ecx = INTEL_AMX_TILE_MAX_ROWS; 7191 } 7192 break; 7193 } 7194 case 0x1E: { 7195 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 7196 *eax = 0; 7197 *ebx = 0; 7198 *ecx = 0; 7199 *edx = 0; 7200 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7201 break; 7202 } 7203 7204 if (count == 0) { 7205 /* Highest numbered palette subleaf */ 7206 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 7207 } 7208 break; 7209 } 7210 case 0x24: { 7211 *eax = 0; 7212 *ebx = 0; 7213 *ecx = 0; 7214 *edx = 0; 7215 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 7216 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 7217 } 7218 break; 7219 } 7220 case 0x40000000: 7221 /* 7222 * CPUID code in kvm_arch_init_vcpu() ignores stuff 7223 * set here, but we restrict to TCG none the less. 7224 */ 7225 if (tcg_enabled() && cpu->expose_tcg) { 7226 memcpy(signature, "TCGTCGTCGTCG", 12); 7227 *eax = 0x40000001; 7228 *ebx = signature[0]; 7229 *ecx = signature[1]; 7230 *edx = signature[2]; 7231 } else { 7232 *eax = 0; 7233 *ebx = 0; 7234 *ecx = 0; 7235 *edx = 0; 7236 } 7237 break; 7238 case 0x40000001: 7239 *eax = 0; 7240 *ebx = 0; 7241 *ecx = 0; 7242 *edx = 0; 7243 break; 7244 case 0x80000000: 7245 *eax = env->cpuid_xlevel; 7246 *ebx = env->cpuid_vendor1; 7247 *edx = env->cpuid_vendor2; 7248 *ecx = env->cpuid_vendor3; 7249 break; 7250 case 0x80000001: 7251 *eax = env->cpuid_version; 7252 *ebx = 0; 7253 *ecx = env->features[FEAT_8000_0001_ECX]; 7254 *edx = env->features[FEAT_8000_0001_EDX]; 7255 7256 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 7257 !(env->hflags & HF_LMA_MASK)) { 7258 *edx &= ~CPUID_EXT2_SYSCALL; 7259 } 7260 break; 7261 case 0x80000002: 7262 case 0x80000003: 7263 case 0x80000004: 7264 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 7265 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 7266 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 7267 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 7268 break; 7269 case 0x80000005: 7270 /* cache info (L1 cache) */ 7271 if (cpu->cache_info_passthrough) { 7272 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7273 break; 7274 } 7275 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 7276 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 7277 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 7278 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7279 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7280 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7281 break; 7282 case 0x80000006: 7283 /* cache info (L2 cache) */ 7284 if (cpu->cache_info_passthrough) { 7285 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7286 break; 7287 } 7288 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7289 (L2_DTLB_2M_ENTRIES << 16) | 7290 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7291 (L2_ITLB_2M_ENTRIES); 7292 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7293 (L2_DTLB_4K_ENTRIES << 16) | 7294 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7295 (L2_ITLB_4K_ENTRIES); 7296 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7297 cpu->enable_l3_cache ? 7298 env->cache_info_amd.l3_cache : NULL, 7299 ecx, edx); 7300 break; 7301 case 0x80000007: 7302 *eax = 0; 7303 *ebx = env->features[FEAT_8000_0007_EBX]; 7304 *ecx = 0; 7305 *edx = env->features[FEAT_8000_0007_EDX]; 7306 break; 7307 case 0x80000008: 7308 /* virtual & phys address size in low 2 bytes. */ 7309 *eax = cpu->phys_bits; 7310 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7311 /* 64 bit processor */ 7312 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7313 *eax |= (cpu->guest_phys_bits << 16); 7314 } 7315 *ebx = env->features[FEAT_8000_0008_EBX]; 7316 if (threads_per_pkg > 1) { 7317 /* 7318 * Bits 15:12 is "The number of bits in the initial 7319 * Core::X86::Apic::ApicId[ApicId] value that indicate 7320 * thread ID within a package". 7321 * Bits 7:0 is "The number of threads in the package is NC+1" 7322 */ 7323 *ecx = (apicid_pkg_offset(topo_info) << 12) | 7324 (threads_per_pkg - 1); 7325 } else { 7326 *ecx = 0; 7327 } 7328 *edx = 0; 7329 break; 7330 case 0x8000000A: 7331 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7332 *eax = 0x00000001; /* SVM Revision */ 7333 *ebx = 0x00000010; /* nr of ASIDs */ 7334 *ecx = 0; 7335 *edx = env->features[FEAT_SVM]; /* optional features */ 7336 } else { 7337 *eax = 0; 7338 *ebx = 0; 7339 *ecx = 0; 7340 *edx = 0; 7341 } 7342 break; 7343 case 0x8000001D: 7344 *eax = 0; 7345 if (cpu->cache_info_passthrough) { 7346 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7347 break; 7348 } 7349 switch (count) { 7350 case 0: /* L1 dcache info */ 7351 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7352 topo_info, eax, ebx, ecx, edx); 7353 break; 7354 case 1: /* L1 icache info */ 7355 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7356 topo_info, eax, ebx, ecx, edx); 7357 break; 7358 case 2: /* L2 cache info */ 7359 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7360 topo_info, eax, ebx, ecx, edx); 7361 break; 7362 case 3: /* L3 cache info */ 7363 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7364 topo_info, eax, ebx, ecx, edx); 7365 break; 7366 default: /* end of info */ 7367 *eax = *ebx = *ecx = *edx = 0; 7368 break; 7369 } 7370 if (cpu->amd_topoext_features_only) { 7371 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7372 } 7373 break; 7374 case 0x8000001E: 7375 if (cpu->core_id <= 255) { 7376 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 7377 } else { 7378 *eax = 0; 7379 *ebx = 0; 7380 *ecx = 0; 7381 *edx = 0; 7382 } 7383 break; 7384 case 0x80000022: 7385 *eax = *ebx = *ecx = *edx = 0; 7386 /* AMD Extended Performance Monitoring and Debug */ 7387 if (kvm_enabled() && cpu->enable_pmu && 7388 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7389 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7390 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7391 R_EBX) & 0xf; 7392 } 7393 break; 7394 case 0xC0000000: 7395 *eax = env->cpuid_xlevel2; 7396 *ebx = 0; 7397 *ecx = 0; 7398 *edx = 0; 7399 break; 7400 case 0xC0000001: 7401 /* Support for VIA CPU's CPUID instruction */ 7402 *eax = env->cpuid_version; 7403 *ebx = 0; 7404 *ecx = 0; 7405 *edx = env->features[FEAT_C000_0001_EDX]; 7406 break; 7407 case 0xC0000002: 7408 case 0xC0000003: 7409 case 0xC0000004: 7410 /* Reserved for the future, and now filled with zero */ 7411 *eax = 0; 7412 *ebx = 0; 7413 *ecx = 0; 7414 *edx = 0; 7415 break; 7416 case 0x8000001F: 7417 *eax = *ebx = *ecx = *edx = 0; 7418 if (sev_enabled()) { 7419 *eax = 0x2; 7420 *eax |= sev_es_enabled() ? 0x8 : 0; 7421 *eax |= sev_snp_enabled() ? 0x10 : 0; 7422 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7423 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7424 } 7425 break; 7426 case 0x80000021: 7427 *eax = *ebx = *ecx = *edx = 0; 7428 *eax = env->features[FEAT_8000_0021_EAX]; 7429 *ebx = env->features[FEAT_8000_0021_EBX]; 7430 break; 7431 default: 7432 /* reserved values: zero */ 7433 *eax = 0; 7434 *ebx = 0; 7435 *ecx = 0; 7436 *edx = 0; 7437 break; 7438 } 7439 } 7440 7441 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7442 { 7443 #ifndef CONFIG_USER_ONLY 7444 /* Those default values are defined in Skylake HW */ 7445 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7446 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7447 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7448 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7449 #endif 7450 } 7451 7452 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7453 { 7454 if (!esa->size) { 7455 return false; 7456 } 7457 7458 if (env->features[esa->feature] & esa->bits) { 7459 return true; 7460 } 7461 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7462 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7463 return true; 7464 } 7465 7466 return false; 7467 } 7468 7469 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7470 { 7471 CPUState *cs = CPU(obj); 7472 X86CPU *cpu = X86_CPU(cs); 7473 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7474 CPUX86State *env = &cpu->env; 7475 target_ulong cr4; 7476 uint64_t xcr0; 7477 int i; 7478 7479 if (xcc->parent_phases.hold) { 7480 xcc->parent_phases.hold(obj, type); 7481 } 7482 7483 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7484 7485 if (tcg_enabled()) { 7486 cpu_init_fp_statuses(env); 7487 } 7488 7489 env->old_exception = -1; 7490 7491 /* init to reset state */ 7492 env->int_ctl = 0; 7493 env->hflags2 |= HF2_GIF_MASK; 7494 env->hflags2 |= HF2_VGIF_MASK; 7495 env->hflags &= ~HF_GUEST_MASK; 7496 7497 cpu_x86_update_cr0(env, 0x60000010); 7498 env->a20_mask = ~0x0; 7499 env->smbase = 0x30000; 7500 env->msr_smi_count = 0; 7501 7502 env->idt.limit = 0xffff; 7503 env->gdt.limit = 0xffff; 7504 env->ldt.limit = 0xffff; 7505 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7506 env->tr.limit = 0xffff; 7507 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7508 7509 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7510 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7511 DESC_R_MASK | DESC_A_MASK); 7512 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7513 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7514 DESC_A_MASK); 7515 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7516 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7517 DESC_A_MASK); 7518 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7519 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7520 DESC_A_MASK); 7521 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7522 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7523 DESC_A_MASK); 7524 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7525 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7526 DESC_A_MASK); 7527 7528 env->eip = 0xfff0; 7529 env->regs[R_EDX] = env->cpuid_version; 7530 7531 env->eflags = 0x2; 7532 7533 /* FPU init */ 7534 for (i = 0; i < 8; i++) { 7535 env->fptags[i] = 1; 7536 } 7537 cpu_set_fpuc(env, 0x37f); 7538 7539 env->mxcsr = 0x1f80; 7540 /* All units are in INIT state. */ 7541 env->xstate_bv = 0; 7542 7543 env->pat = 0x0007040600070406ULL; 7544 7545 if (kvm_enabled()) { 7546 /* 7547 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7548 * a new CPU, use 1 instead to force a reset. 7549 */ 7550 if (env->tsc != 0) { 7551 env->tsc = 1; 7552 } 7553 } else { 7554 env->tsc = 0; 7555 } 7556 7557 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7558 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7559 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7560 } 7561 7562 memset(env->dr, 0, sizeof(env->dr)); 7563 env->dr[6] = DR6_FIXED_1; 7564 env->dr[7] = DR7_FIXED_1; 7565 cpu_breakpoint_remove_all(cs, BP_CPU); 7566 cpu_watchpoint_remove_all(cs, BP_CPU); 7567 7568 cr4 = 0; 7569 xcr0 = XSTATE_FP_MASK; 7570 7571 #ifdef CONFIG_USER_ONLY 7572 /* Enable all the features for user-mode. */ 7573 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7574 xcr0 |= XSTATE_SSE_MASK; 7575 } 7576 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7577 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7578 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7579 continue; 7580 } 7581 if (cpuid_has_xsave_feature(env, esa)) { 7582 xcr0 |= 1ull << i; 7583 } 7584 } 7585 7586 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7587 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7588 } 7589 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7590 cr4 |= CR4_FSGSBASE_MASK; 7591 } 7592 #endif 7593 7594 env->xcr0 = xcr0; 7595 cpu_x86_update_cr4(env, cr4); 7596 7597 /* 7598 * SDM 11.11.5 requires: 7599 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7600 * - IA32_MTRR_PHYSMASKn.V = 0 7601 * All other bits are undefined. For simplification, zero it all. 7602 */ 7603 env->mtrr_deftype = 0; 7604 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7605 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7606 7607 env->interrupt_injected = -1; 7608 env->exception_nr = -1; 7609 env->exception_pending = 0; 7610 env->exception_injected = 0; 7611 env->exception_has_payload = false; 7612 env->exception_payload = 0; 7613 env->nmi_injected = false; 7614 env->triple_fault_pending = false; 7615 #if !defined(CONFIG_USER_ONLY) 7616 /* We hard-wire the BSP to the first CPU. */ 7617 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7618 7619 cs->halted = !cpu_is_bsp(cpu); 7620 7621 if (kvm_enabled()) { 7622 kvm_arch_reset_vcpu(cpu); 7623 } 7624 7625 x86_cpu_set_sgxlepubkeyhash(env); 7626 7627 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7628 7629 #endif 7630 } 7631 7632 void x86_cpu_after_reset(X86CPU *cpu) 7633 { 7634 #ifndef CONFIG_USER_ONLY 7635 if (kvm_enabled()) { 7636 kvm_arch_after_reset_vcpu(cpu); 7637 } 7638 7639 if (cpu->apic_state) { 7640 device_cold_reset(cpu->apic_state); 7641 } 7642 #endif 7643 } 7644 7645 static void mce_init(X86CPU *cpu) 7646 { 7647 CPUX86State *cenv = &cpu->env; 7648 unsigned int bank; 7649 7650 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7651 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7652 (CPUID_MCE | CPUID_MCA)) { 7653 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7654 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7655 cenv->mcg_ctl = ~(uint64_t)0; 7656 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7657 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7658 } 7659 } 7660 } 7661 7662 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7663 { 7664 if (*min < value) { 7665 *min = value; 7666 } 7667 } 7668 7669 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7670 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7671 { 7672 CPUX86State *env = &cpu->env; 7673 FeatureWordInfo *fi = &feature_word_info[w]; 7674 uint32_t eax = fi->cpuid.eax; 7675 uint32_t region = eax & 0xF0000000; 7676 7677 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7678 if (!env->features[w]) { 7679 return; 7680 } 7681 7682 switch (region) { 7683 case 0x00000000: 7684 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7685 break; 7686 case 0x80000000: 7687 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7688 break; 7689 case 0xC0000000: 7690 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7691 break; 7692 } 7693 7694 if (eax == 7) { 7695 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7696 fi->cpuid.ecx); 7697 } 7698 } 7699 7700 /* Calculate XSAVE components based on the configured CPU feature flags */ 7701 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7702 { 7703 CPUX86State *env = &cpu->env; 7704 int i; 7705 uint64_t mask; 7706 static bool request_perm; 7707 7708 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7709 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7710 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7711 env->features[FEAT_XSAVE_XSS_LO] = 0; 7712 env->features[FEAT_XSAVE_XSS_HI] = 0; 7713 return; 7714 } 7715 7716 mask = 0; 7717 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7718 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7719 if (cpuid_has_xsave_feature(env, esa)) { 7720 mask |= (1ULL << i); 7721 } 7722 } 7723 7724 /* Only request permission for first vcpu */ 7725 if (kvm_enabled() && !request_perm) { 7726 kvm_request_xsave_components(cpu, mask); 7727 request_perm = true; 7728 } 7729 7730 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7731 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7732 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7733 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7734 } 7735 7736 /***** Steps involved on loading and filtering CPUID data 7737 * 7738 * When initializing and realizing a CPU object, the steps 7739 * involved in setting up CPUID data are: 7740 * 7741 * 1) Loading CPU model definition (X86CPUDefinition). This is 7742 * implemented by x86_cpu_load_model() and should be completely 7743 * transparent, as it is done automatically by instance_init. 7744 * No code should need to look at X86CPUDefinition structs 7745 * outside instance_init. 7746 * 7747 * 2) CPU expansion. This is done by realize before CPUID 7748 * filtering, and will make sure host/accelerator data is 7749 * loaded for CPU models that depend on host capabilities 7750 * (e.g. "host"). Done by x86_cpu_expand_features(). 7751 * 7752 * 3) CPUID filtering. This initializes extra data related to 7753 * CPUID, and checks if the host supports all capabilities 7754 * required by the CPU. Runnability of a CPU model is 7755 * determined at this step. Done by x86_cpu_filter_features(). 7756 * 7757 * Some operations don't require all steps to be performed. 7758 * More precisely: 7759 * 7760 * - CPU instance creation (instance_init) will run only CPU 7761 * model loading. CPU expansion can't run at instance_init-time 7762 * because host/accelerator data may be not available yet. 7763 * - CPU realization will perform both CPU model expansion and CPUID 7764 * filtering, and return an error in case one of them fails. 7765 * - query-cpu-definitions needs to run all 3 steps. It needs 7766 * to run CPUID filtering, as the 'unavailable-features' 7767 * field is set based on the filtering results. 7768 * - The query-cpu-model-expansion QMP command only needs to run 7769 * CPU model loading and CPU expansion. It should not filter 7770 * any CPUID data based on host capabilities. 7771 */ 7772 7773 /* Expand CPU configuration data, based on configured features 7774 * and host/accelerator capabilities when appropriate. 7775 */ 7776 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7777 { 7778 CPUX86State *env = &cpu->env; 7779 FeatureWord w; 7780 int i; 7781 GList *l; 7782 7783 for (l = plus_features; l; l = l->next) { 7784 const char *prop = l->data; 7785 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7786 return; 7787 } 7788 } 7789 7790 for (l = minus_features; l; l = l->next) { 7791 const char *prop = l->data; 7792 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7793 return; 7794 } 7795 } 7796 7797 /*TODO: Now cpu->max_features doesn't overwrite features 7798 * set using QOM properties, and we can convert 7799 * plus_features & minus_features to global properties 7800 * inside x86_cpu_parse_featurestr() too. 7801 */ 7802 if (cpu->max_features) { 7803 for (w = 0; w < FEATURE_WORDS; w++) { 7804 /* Override only features that weren't set explicitly 7805 * by the user. 7806 */ 7807 env->features[w] |= 7808 x86_cpu_get_supported_feature_word(cpu, w) & 7809 ~env->user_features[w] & 7810 ~feature_word_info[w].no_autoenable_flags; 7811 } 7812 7813 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 7814 uint32_t eax, ebx, ecx, edx; 7815 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 7816 env->avx10_version = ebx & 0xff; 7817 } 7818 } 7819 7820 if (x86_threads_per_pkg(&env->topo_info) > 1) { 7821 env->features[FEAT_1_EDX] |= CPUID_HT; 7822 7823 /* 7824 * The Linux kernel checks for the CMPLegacy bit and 7825 * discards multiple thread information if it is set. 7826 * So don't set it here for Intel (and other processors 7827 * following Intel's behavior) to make Linux guests happy. 7828 */ 7829 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 7830 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 7831 } 7832 } 7833 7834 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7835 FeatureDep *d = &feature_dependencies[i]; 7836 if (!(env->features[d->from.index] & d->from.mask)) { 7837 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7838 7839 /* Not an error unless the dependent feature was added explicitly. */ 7840 mark_unavailable_features(cpu, d->to.index, 7841 unavailable_features & env->user_features[d->to.index], 7842 "This feature depends on other features that were not requested"); 7843 7844 env->features[d->to.index] &= ~unavailable_features; 7845 } 7846 } 7847 7848 if (!kvm_enabled() || !cpu->expose_kvm) { 7849 env->features[FEAT_KVM] = 0; 7850 } 7851 7852 x86_cpu_enable_xsave_components(cpu); 7853 7854 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7855 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7856 if (cpu->full_cpuid_auto_level) { 7857 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7858 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7859 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7860 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7861 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7862 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7863 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7864 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7865 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7866 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7867 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7868 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7869 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7870 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7871 7872 /* Intel Processor Trace requires CPUID[0x14] */ 7873 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7874 if (cpu->intel_pt_auto_level) { 7875 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7876 } else if (cpu->env.cpuid_min_level < 0x14) { 7877 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7878 CPUID_7_0_EBX_INTEL_PT, 7879 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7880 } 7881 } 7882 7883 /* 7884 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7885 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7886 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7887 * cpu->vendor_cpuid_only has been unset for compatibility with older 7888 * machine types. 7889 */ 7890 if (x86_has_extended_topo(env->avail_cpu_topo) && 7891 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7892 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7893 } 7894 7895 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 7896 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7897 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 7898 } 7899 7900 /* SVM requires CPUID[0x8000000A] */ 7901 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7902 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7903 } 7904 7905 /* SEV requires CPUID[0x8000001F] */ 7906 if (sev_enabled()) { 7907 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7908 } 7909 7910 if (env->features[FEAT_8000_0021_EAX]) { 7911 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7912 } 7913 7914 /* SGX requires CPUID[0x12] for EPC enumeration */ 7915 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7916 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7917 } 7918 } 7919 7920 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7921 if (env->cpuid_level_func7 == UINT32_MAX) { 7922 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7923 } 7924 if (env->cpuid_level == UINT32_MAX) { 7925 env->cpuid_level = env->cpuid_min_level; 7926 } 7927 if (env->cpuid_xlevel == UINT32_MAX) { 7928 env->cpuid_xlevel = env->cpuid_min_xlevel; 7929 } 7930 if (env->cpuid_xlevel2 == UINT32_MAX) { 7931 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7932 } 7933 7934 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7935 return; 7936 } 7937 } 7938 7939 /* 7940 * Finishes initialization of CPUID data, filters CPU feature 7941 * words based on host availability of each feature. 7942 * 7943 * Returns: true if any flag is not supported by the host, false otherwise. 7944 */ 7945 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7946 { 7947 CPUX86State *env = &cpu->env; 7948 FeatureWord w; 7949 const char *prefix = NULL; 7950 bool have_filtered_features; 7951 7952 uint32_t eax_0, ebx_0, ecx_0, edx_0; 7953 uint32_t eax_1, ebx_1, ecx_1, edx_1; 7954 7955 if (verbose) { 7956 prefix = accel_uses_host_cpuid() 7957 ? "host doesn't support requested feature" 7958 : "TCG doesn't support requested feature"; 7959 } 7960 7961 for (w = 0; w < FEATURE_WORDS; w++) { 7962 uint64_t host_feat = 7963 x86_cpu_get_supported_feature_word(NULL, w); 7964 uint64_t requested_features = env->features[w]; 7965 uint64_t unavailable_features = requested_features & ~host_feat; 7966 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7967 } 7968 7969 /* 7970 * Check that KVM actually allows the processor tracing features that 7971 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7972 */ 7973 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7974 kvm_enabled()) { 7975 x86_cpu_get_supported_cpuid(0x14, 0, 7976 &eax_0, &ebx_0, &ecx_0, &edx_0); 7977 x86_cpu_get_supported_cpuid(0x14, 1, 7978 &eax_1, &ebx_1, &ecx_1, &edx_1); 7979 7980 if (!eax_0 || 7981 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7982 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7983 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7984 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7985 INTEL_PT_ADDR_RANGES_NUM) || 7986 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7987 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7988 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7989 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7990 /* 7991 * Processor Trace capabilities aren't configurable, so if the 7992 * host can't emulate the capabilities we report on 7993 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7994 */ 7995 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7996 } 7997 } 7998 7999 have_filtered_features = x86_cpu_have_filtered_features(cpu); 8000 8001 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 8002 x86_cpu_get_supported_cpuid(0x24, 0, 8003 &eax_0, &ebx_0, &ecx_0, &edx_0); 8004 uint8_t version = ebx_0 & 0xff; 8005 8006 if (version < env->avx10_version) { 8007 if (prefix) { 8008 warn_report("%s: avx10.%d. Adjust to avx10.%d", 8009 prefix, env->avx10_version, version); 8010 } 8011 env->avx10_version = version; 8012 have_filtered_features = true; 8013 } 8014 } else if (env->avx10_version) { 8015 if (prefix) { 8016 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 8017 } 8018 have_filtered_features = true; 8019 } 8020 8021 return have_filtered_features; 8022 } 8023 8024 static void x86_cpu_hyperv_realize(X86CPU *cpu) 8025 { 8026 size_t len; 8027 8028 /* Hyper-V vendor id */ 8029 if (!cpu->hyperv_vendor) { 8030 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 8031 &error_abort); 8032 } 8033 len = strlen(cpu->hyperv_vendor); 8034 if (len > 12) { 8035 warn_report("hv-vendor-id truncated to 12 characters"); 8036 len = 12; 8037 } 8038 memset(cpu->hyperv_vendor_id, 0, 12); 8039 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 8040 8041 /* 'Hv#1' interface identification*/ 8042 cpu->hyperv_interface_id[0] = 0x31237648; 8043 cpu->hyperv_interface_id[1] = 0; 8044 cpu->hyperv_interface_id[2] = 0; 8045 cpu->hyperv_interface_id[3] = 0; 8046 8047 /* Hypervisor implementation limits */ 8048 cpu->hyperv_limits[0] = 64; 8049 cpu->hyperv_limits[1] = 0; 8050 cpu->hyperv_limits[2] = 0; 8051 } 8052 8053 #ifndef CONFIG_USER_ONLY 8054 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 8055 Error **errp) 8056 { 8057 CPUX86State *env = &cpu->env; 8058 CpuTopologyLevel level; 8059 8060 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 8061 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8062 env->cache_info_cpuid4.l1d_cache->share_level = level; 8063 env->cache_info_amd.l1d_cache->share_level = level; 8064 } else { 8065 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8066 env->cache_info_cpuid4.l1d_cache->share_level); 8067 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8068 env->cache_info_amd.l1d_cache->share_level); 8069 } 8070 8071 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 8072 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8073 env->cache_info_cpuid4.l1i_cache->share_level = level; 8074 env->cache_info_amd.l1i_cache->share_level = level; 8075 } else { 8076 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8077 env->cache_info_cpuid4.l1i_cache->share_level); 8078 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8079 env->cache_info_amd.l1i_cache->share_level); 8080 } 8081 8082 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 8083 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8084 env->cache_info_cpuid4.l2_cache->share_level = level; 8085 env->cache_info_amd.l2_cache->share_level = level; 8086 } else { 8087 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8088 env->cache_info_cpuid4.l2_cache->share_level); 8089 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8090 env->cache_info_amd.l2_cache->share_level); 8091 } 8092 8093 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 8094 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8095 env->cache_info_cpuid4.l3_cache->share_level = level; 8096 env->cache_info_amd.l3_cache->share_level = level; 8097 } else { 8098 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8099 env->cache_info_cpuid4.l3_cache->share_level); 8100 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8101 env->cache_info_amd.l3_cache->share_level); 8102 } 8103 8104 if (!machine_check_smp_cache(ms, errp)) { 8105 return false; 8106 } 8107 return true; 8108 } 8109 #endif 8110 8111 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 8112 { 8113 CPUState *cs = CPU(dev); 8114 X86CPU *cpu = X86_CPU(dev); 8115 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8116 CPUX86State *env = &cpu->env; 8117 Error *local_err = NULL; 8118 unsigned requested_lbr_fmt; 8119 8120 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 8121 /* Use pc-relative instructions in system-mode */ 8122 tcg_cflags_set(cs, CF_PCREL); 8123 #endif 8124 8125 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 8126 error_setg(errp, "apic-id property was not initialized properly"); 8127 return; 8128 } 8129 8130 /* 8131 * Process Hyper-V enlightenments. 8132 * Note: this currently has to happen before the expansion of CPU features. 8133 */ 8134 x86_cpu_hyperv_realize(cpu); 8135 8136 x86_cpu_expand_features(cpu, &local_err); 8137 if (local_err) { 8138 goto out; 8139 } 8140 8141 /* 8142 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 8143 * with user-provided setting. 8144 */ 8145 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 8146 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 8147 error_setg(errp, "invalid lbr-fmt"); 8148 return; 8149 } 8150 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 8151 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 8152 } 8153 8154 /* 8155 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 8156 * 3)vPMU LBR format matches that of host setting. 8157 */ 8158 requested_lbr_fmt = 8159 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 8160 if (requested_lbr_fmt && kvm_enabled()) { 8161 uint64_t host_perf_cap = 8162 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 8163 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 8164 8165 if (!cpu->enable_pmu) { 8166 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 8167 return; 8168 } 8169 if (requested_lbr_fmt != host_lbr_fmt) { 8170 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 8171 "the host value (0x%x).", 8172 requested_lbr_fmt, host_lbr_fmt); 8173 return; 8174 } 8175 } 8176 8177 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 8178 if (cpu->enforce_cpuid) { 8179 error_setg(&local_err, 8180 accel_uses_host_cpuid() ? 8181 "Host doesn't support requested features" : 8182 "TCG doesn't support requested features"); 8183 goto out; 8184 } 8185 } 8186 8187 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 8188 * CPUID[1].EDX. 8189 */ 8190 if (IS_AMD_CPU(env)) { 8191 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 8192 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 8193 & CPUID_EXT2_AMD_ALIASES); 8194 } 8195 8196 x86_cpu_set_sgxlepubkeyhash(env); 8197 8198 /* 8199 * note: the call to the framework needs to happen after feature expansion, 8200 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 8201 * These may be set by the accel-specific code, 8202 * and the results are subsequently checked / assumed in this function. 8203 */ 8204 cpu_exec_realizefn(cs, &local_err); 8205 if (local_err != NULL) { 8206 error_propagate(errp, local_err); 8207 return; 8208 } 8209 8210 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 8211 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8212 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 8213 goto out; 8214 } 8215 8216 if (cpu->guest_phys_bits == -1) { 8217 /* 8218 * If it was not set by the user, or by the accelerator via 8219 * cpu_exec_realizefn, clear. 8220 */ 8221 cpu->guest_phys_bits = 0; 8222 } 8223 8224 if (cpu->ucode_rev == 0) { 8225 /* 8226 * The default is the same as KVM's. Note that this check 8227 * needs to happen after the evenual setting of ucode_rev in 8228 * accel-specific code in cpu_exec_realizefn. 8229 */ 8230 if (IS_AMD_CPU(env)) { 8231 cpu->ucode_rev = 0x01000065; 8232 } else { 8233 cpu->ucode_rev = 0x100000000ULL; 8234 } 8235 } 8236 8237 /* 8238 * mwait extended info: needed for Core compatibility 8239 * We always wake on interrupt even if host does not have the capability. 8240 * 8241 * requires the accel-specific code in cpu_exec_realizefn to 8242 * have already acquired the CPUID data into cpu->mwait. 8243 */ 8244 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 8245 8246 /* 8247 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 8248 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8249 * based on inputs (sockets,cores,threads), it is still better to give 8250 * users a warning. 8251 */ 8252 if (IS_AMD_CPU(env) && 8253 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8254 env->topo_info.threads_per_core > 1) { 8255 warn_report_once("This family of AMD CPU doesn't support " 8256 "hyperthreading(%d). Please configure -smp " 8257 "options properly or try enabling topoext " 8258 "feature.", env->topo_info.threads_per_core); 8259 } 8260 8261 /* For 64bit systems think about the number of physical bits to present. 8262 * ideally this should be the same as the host; anything other than matching 8263 * the host can cause incorrect guest behaviour. 8264 * QEMU used to pick the magic value of 40 bits that corresponds to 8265 * consumer AMD devices but nothing else. 8266 * 8267 * Note that this code assumes features expansion has already been done 8268 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 8269 * phys_bits adjustments to match the host have been already done in 8270 * accel-specific code in cpu_exec_realizefn. 8271 */ 8272 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8273 if (cpu->phys_bits && 8274 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 8275 cpu->phys_bits < 32)) { 8276 error_setg(errp, "phys-bits should be between 32 and %u " 8277 " (but is %u)", 8278 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 8279 return; 8280 } 8281 /* 8282 * 0 means it was not explicitly set by the user (or by machine 8283 * compat_props or by the host code in host-cpu.c). 8284 * In this case, the default is the value used by TCG (40). 8285 */ 8286 if (cpu->phys_bits == 0) { 8287 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 8288 } 8289 if (cpu->guest_phys_bits && 8290 (cpu->guest_phys_bits > cpu->phys_bits || 8291 cpu->guest_phys_bits < 32)) { 8292 error_setg(errp, "guest-phys-bits should be between 32 and %u " 8293 " (but is %u)", 8294 cpu->phys_bits, cpu->guest_phys_bits); 8295 return; 8296 } 8297 } else { 8298 /* For 32 bit systems don't use the user set value, but keep 8299 * phys_bits consistent with what we tell the guest. 8300 */ 8301 if (cpu->phys_bits != 0) { 8302 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 8303 return; 8304 } 8305 if (cpu->guest_phys_bits != 0) { 8306 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 8307 return; 8308 } 8309 8310 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 8311 cpu->phys_bits = 36; 8312 } else { 8313 cpu->phys_bits = 32; 8314 } 8315 } 8316 8317 /* Cache information initialization */ 8318 if (!cpu->legacy_cache) { 8319 const CPUCaches *cache_info = 8320 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 8321 8322 if (!xcc->model || !cache_info) { 8323 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8324 error_setg(errp, 8325 "CPU model '%s' doesn't support legacy-cache=off", name); 8326 return; 8327 } 8328 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 8329 *cache_info; 8330 } else { 8331 /* Build legacy cache information */ 8332 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 8333 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 8334 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 8335 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 8336 8337 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 8338 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 8339 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 8340 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 8341 8342 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 8343 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 8344 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 8345 env->cache_info_amd.l3_cache = &legacy_l3_cache; 8346 } 8347 8348 #ifndef CONFIG_USER_ONLY 8349 MachineState *ms = MACHINE(qdev_get_machine()); 8350 MachineClass *mc = MACHINE_GET_CLASS(ms); 8351 8352 if (mc->smp_props.has_caches) { 8353 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 8354 return; 8355 } 8356 } 8357 8358 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 8359 8360 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 8361 x86_cpu_apic_create(cpu, &local_err); 8362 if (local_err != NULL) { 8363 goto out; 8364 } 8365 } 8366 #endif 8367 8368 mce_init(cpu); 8369 8370 x86_cpu_gdb_init(cs); 8371 qemu_init_vcpu(cs); 8372 8373 #ifndef CONFIG_USER_ONLY 8374 x86_cpu_apic_realize(cpu, &local_err); 8375 if (local_err != NULL) { 8376 goto out; 8377 } 8378 #endif /* !CONFIG_USER_ONLY */ 8379 cpu_reset(cs); 8380 8381 xcc->parent_realize(dev, &local_err); 8382 8383 out: 8384 if (local_err != NULL) { 8385 error_propagate(errp, local_err); 8386 return; 8387 } 8388 } 8389 8390 static void x86_cpu_unrealizefn(DeviceState *dev) 8391 { 8392 X86CPU *cpu = X86_CPU(dev); 8393 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8394 8395 #ifndef CONFIG_USER_ONLY 8396 cpu_remove_sync(CPU(dev)); 8397 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8398 #endif 8399 8400 if (cpu->apic_state) { 8401 object_unparent(OBJECT(cpu->apic_state)); 8402 cpu->apic_state = NULL; 8403 } 8404 8405 xcc->parent_unrealize(dev); 8406 } 8407 8408 typedef struct BitProperty { 8409 FeatureWord w; 8410 uint64_t mask; 8411 } BitProperty; 8412 8413 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8414 void *opaque, Error **errp) 8415 { 8416 X86CPU *cpu = X86_CPU(obj); 8417 BitProperty *fp = opaque; 8418 uint64_t f = cpu->env.features[fp->w]; 8419 bool value = (f & fp->mask) == fp->mask; 8420 visit_type_bool(v, name, &value, errp); 8421 } 8422 8423 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8424 void *opaque, Error **errp) 8425 { 8426 DeviceState *dev = DEVICE(obj); 8427 X86CPU *cpu = X86_CPU(obj); 8428 BitProperty *fp = opaque; 8429 bool value; 8430 8431 if (dev->realized) { 8432 qdev_prop_set_after_realize(dev, name, errp); 8433 return; 8434 } 8435 8436 if (!visit_type_bool(v, name, &value, errp)) { 8437 return; 8438 } 8439 8440 if (value) { 8441 cpu->env.features[fp->w] |= fp->mask; 8442 } else { 8443 cpu->env.features[fp->w] &= ~fp->mask; 8444 } 8445 cpu->env.user_features[fp->w] |= fp->mask; 8446 } 8447 8448 /* Register a boolean property to get/set a single bit in a uint32_t field. 8449 * 8450 * The same property name can be registered multiple times to make it affect 8451 * multiple bits in the same FeatureWord. In that case, the getter will return 8452 * true only if all bits are set. 8453 */ 8454 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8455 const char *prop_name, 8456 FeatureWord w, 8457 int bitnr) 8458 { 8459 ObjectClass *oc = OBJECT_CLASS(xcc); 8460 BitProperty *fp; 8461 ObjectProperty *op; 8462 uint64_t mask = (1ULL << bitnr); 8463 8464 op = object_class_property_find(oc, prop_name); 8465 if (op) { 8466 fp = op->opaque; 8467 assert(fp->w == w); 8468 fp->mask |= mask; 8469 } else { 8470 fp = g_new0(BitProperty, 1); 8471 fp->w = w; 8472 fp->mask = mask; 8473 object_class_property_add(oc, prop_name, "bool", 8474 x86_cpu_get_bit_prop, 8475 x86_cpu_set_bit_prop, 8476 NULL, fp); 8477 } 8478 } 8479 8480 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8481 FeatureWord w, 8482 int bitnr) 8483 { 8484 FeatureWordInfo *fi = &feature_word_info[w]; 8485 const char *name = fi->feat_names[bitnr]; 8486 8487 if (!name) { 8488 return; 8489 } 8490 8491 /* Property names should use "-" instead of "_". 8492 * Old names containing underscores are registered as aliases 8493 * using object_property_add_alias() 8494 */ 8495 assert(!strchr(name, '_')); 8496 /* aliases don't use "|" delimiters anymore, they are registered 8497 * manually using object_property_add_alias() */ 8498 assert(!strchr(name, '|')); 8499 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8500 } 8501 8502 static void x86_cpu_post_initfn(Object *obj) 8503 { 8504 static bool first = true; 8505 uint64_t supported_xcr0; 8506 int i; 8507 8508 if (first) { 8509 first = false; 8510 8511 supported_xcr0 = 8512 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 8513 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 8514 8515 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 8516 ExtSaveArea *esa = &x86_ext_save_areas[i]; 8517 8518 if (!(supported_xcr0 & (1 << i))) { 8519 esa->size = 0; 8520 } 8521 } 8522 } 8523 8524 accel_cpu_instance_init(CPU(obj)); 8525 } 8526 8527 static void x86_cpu_init_default_topo(X86CPU *cpu) 8528 { 8529 CPUX86State *env = &cpu->env; 8530 8531 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 8532 8533 /* thread, core and socket levels are set by default. */ 8534 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 8535 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 8536 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 8537 } 8538 8539 static void x86_cpu_initfn(Object *obj) 8540 { 8541 X86CPU *cpu = X86_CPU(obj); 8542 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8543 CPUX86State *env = &cpu->env; 8544 8545 x86_cpu_init_default_topo(cpu); 8546 8547 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8548 x86_cpu_get_feature_words, 8549 NULL, NULL, (void *)env->features); 8550 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8551 x86_cpu_get_feature_words, 8552 NULL, NULL, (void *)cpu->filtered_features); 8553 8554 object_property_add_alias(obj, "sse3", obj, "pni"); 8555 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8556 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8557 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8558 object_property_add_alias(obj, "xd", obj, "nx"); 8559 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8560 object_property_add_alias(obj, "i64", obj, "lm"); 8561 8562 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8563 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8564 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8565 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8566 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8567 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8568 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8569 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8570 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8571 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8572 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8573 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8574 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8575 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8576 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8577 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8578 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8579 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8580 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8581 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8582 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8583 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8584 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8585 8586 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8587 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8588 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8589 8590 if (xcc->model) { 8591 x86_cpu_load_model(cpu, xcc->model); 8592 } 8593 } 8594 8595 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8596 { 8597 X86CPU *cpu = X86_CPU(cs); 8598 8599 return cpu->apic_id; 8600 } 8601 8602 #if !defined(CONFIG_USER_ONLY) 8603 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8604 { 8605 X86CPU *cpu = X86_CPU(cs); 8606 8607 return cpu->env.cr[0] & CR0_PG_MASK; 8608 } 8609 #endif /* !CONFIG_USER_ONLY */ 8610 8611 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8612 { 8613 X86CPU *cpu = X86_CPU(cs); 8614 8615 cpu->env.eip = value; 8616 } 8617 8618 static vaddr x86_cpu_get_pc(CPUState *cs) 8619 { 8620 X86CPU *cpu = X86_CPU(cs); 8621 8622 /* Match cpu_get_tb_cpu_state. */ 8623 return cpu->env.eip + cpu->env.segs[R_CS].base; 8624 } 8625 8626 #if !defined(CONFIG_USER_ONLY) 8627 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8628 { 8629 X86CPU *cpu = X86_CPU(cs); 8630 CPUX86State *env = &cpu->env; 8631 8632 if (interrupt_request & CPU_INTERRUPT_POLL) { 8633 return CPU_INTERRUPT_POLL; 8634 } 8635 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8636 return CPU_INTERRUPT_SIPI; 8637 } 8638 8639 if (env->hflags2 & HF2_GIF_MASK) { 8640 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8641 !(env->hflags & HF_SMM_MASK)) { 8642 return CPU_INTERRUPT_SMI; 8643 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8644 !(env->hflags2 & HF2_NMI_MASK)) { 8645 return CPU_INTERRUPT_NMI; 8646 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8647 return CPU_INTERRUPT_MCE; 8648 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8649 (((env->hflags2 & HF2_VINTR_MASK) && 8650 (env->hflags2 & HF2_HIF_MASK)) || 8651 (!(env->hflags2 & HF2_VINTR_MASK) && 8652 (env->eflags & IF_MASK && 8653 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8654 return CPU_INTERRUPT_HARD; 8655 } else if (env->hflags2 & HF2_VGIF_MASK) { 8656 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8657 (env->eflags & IF_MASK) && 8658 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8659 return CPU_INTERRUPT_VIRQ; 8660 } 8661 } 8662 } 8663 8664 return 0; 8665 } 8666 8667 static bool x86_cpu_has_work(CPUState *cs) 8668 { 8669 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8670 } 8671 #endif /* !CONFIG_USER_ONLY */ 8672 8673 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8674 { 8675 X86CPU *cpu = X86_CPU(cs); 8676 CPUX86State *env = &cpu->env; 8677 8678 info->endian = BFD_ENDIAN_LITTLE; 8679 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8680 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8681 : bfd_mach_i386_i8086); 8682 8683 info->cap_arch = CS_ARCH_X86; 8684 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8685 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8686 : CS_MODE_16); 8687 info->cap_insn_unit = 1; 8688 info->cap_insn_split = 8; 8689 } 8690 8691 void x86_update_hflags(CPUX86State *env) 8692 { 8693 uint32_t hflags; 8694 #define HFLAG_COPY_MASK \ 8695 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8696 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8697 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8698 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8699 8700 hflags = env->hflags & HFLAG_COPY_MASK; 8701 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8702 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8703 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8704 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8705 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8706 8707 if (env->cr[4] & CR4_OSFXSR_MASK) { 8708 hflags |= HF_OSFXSR_MASK; 8709 } 8710 8711 if (env->efer & MSR_EFER_LMA) { 8712 hflags |= HF_LMA_MASK; 8713 } 8714 8715 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8716 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8717 } else { 8718 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8719 (DESC_B_SHIFT - HF_CS32_SHIFT); 8720 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8721 (DESC_B_SHIFT - HF_SS32_SHIFT); 8722 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8723 !(hflags & HF_CS32_MASK)) { 8724 hflags |= HF_ADDSEG_MASK; 8725 } else { 8726 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8727 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8728 } 8729 } 8730 env->hflags = hflags; 8731 } 8732 8733 static const Property x86_cpu_properties[] = { 8734 #ifdef CONFIG_USER_ONLY 8735 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8736 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8737 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8738 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8739 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8740 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8741 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8742 #else 8743 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8744 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8745 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8746 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8747 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8748 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8749 #endif 8750 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8751 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8752 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8753 8754 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8755 HYPERV_SPINLOCK_NEVER_NOTIFY), 8756 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8757 HYPERV_FEAT_RELAXED, 0), 8758 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8759 HYPERV_FEAT_VAPIC, 0), 8760 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8761 HYPERV_FEAT_TIME, 0), 8762 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8763 HYPERV_FEAT_CRASH, 0), 8764 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8765 HYPERV_FEAT_RESET, 0), 8766 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8767 HYPERV_FEAT_VPINDEX, 0), 8768 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8769 HYPERV_FEAT_RUNTIME, 0), 8770 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8771 HYPERV_FEAT_SYNIC, 0), 8772 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8773 HYPERV_FEAT_STIMER, 0), 8774 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8775 HYPERV_FEAT_FREQUENCIES, 0), 8776 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8777 HYPERV_FEAT_REENLIGHTENMENT, 0), 8778 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8779 HYPERV_FEAT_TLBFLUSH, 0), 8780 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8781 HYPERV_FEAT_EVMCS, 0), 8782 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8783 HYPERV_FEAT_IPI, 0), 8784 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8785 HYPERV_FEAT_STIMER_DIRECT, 0), 8786 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8787 HYPERV_FEAT_AVIC, 0), 8788 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8789 HYPERV_FEAT_MSR_BITMAP, 0), 8790 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8791 HYPERV_FEAT_XMM_INPUT, 0), 8792 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8793 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8794 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8795 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8796 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8797 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8798 #ifdef CONFIG_SYNDBG 8799 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8800 HYPERV_FEAT_SYNDBG, 0), 8801 #endif 8802 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8803 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8804 8805 /* WS2008R2 identify by default */ 8806 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8807 0x3839), 8808 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8809 0x000A), 8810 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8811 0x0000), 8812 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8813 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8814 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8815 8816 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8817 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8818 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8819 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8820 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8821 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8822 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8823 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8824 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8825 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8826 UINT32_MAX), 8827 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8828 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8829 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8830 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8831 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8832 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8833 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 8834 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8835 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8836 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8837 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8838 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8839 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8840 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8841 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8842 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8843 false), 8844 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8845 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8846 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8847 true), 8848 /* 8849 * lecacy_cache defaults to true unless the CPU model provides its 8850 * own cache information (see x86_cpu_load_def()). 8851 */ 8852 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8853 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8854 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8855 8856 /* 8857 * From "Requirements for Implementing the Microsoft 8858 * Hypervisor Interface": 8859 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8860 * 8861 * "Starting with Windows Server 2012 and Windows 8, if 8862 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8863 * the hypervisor imposes no specific limit to the number of VPs. 8864 * In this case, Windows Server 2012 guest VMs may use more than 8865 * 64 VPs, up to the maximum supported number of processors applicable 8866 * to the specific Windows version being used." 8867 */ 8868 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8869 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8870 false), 8871 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8872 true), 8873 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8874 }; 8875 8876 #ifndef CONFIG_USER_ONLY 8877 #include "hw/core/sysemu-cpu-ops.h" 8878 8879 static const struct SysemuCPUOps i386_sysemu_ops = { 8880 .has_work = x86_cpu_has_work, 8881 .get_memory_mapping = x86_cpu_get_memory_mapping, 8882 .get_paging_enabled = x86_cpu_get_paging_enabled, 8883 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8884 .asidx_from_attrs = x86_asidx_from_attrs, 8885 .get_crash_info = x86_cpu_get_crash_info, 8886 .write_elf32_note = x86_cpu_write_elf32_note, 8887 .write_elf64_note = x86_cpu_write_elf64_note, 8888 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8889 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8890 .legacy_vmsd = &vmstate_x86_cpu, 8891 }; 8892 #endif 8893 8894 static void x86_cpu_common_class_init(ObjectClass *oc, const void *data) 8895 { 8896 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8897 CPUClass *cc = CPU_CLASS(oc); 8898 DeviceClass *dc = DEVICE_CLASS(oc); 8899 ResettableClass *rc = RESETTABLE_CLASS(oc); 8900 FeatureWord w; 8901 8902 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8903 &xcc->parent_realize); 8904 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8905 &xcc->parent_unrealize); 8906 device_class_set_props(dc, x86_cpu_properties); 8907 8908 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8909 &xcc->parent_phases); 8910 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8911 8912 cc->class_by_name = x86_cpu_class_by_name; 8913 cc->list_cpus = x86_cpu_list; 8914 cc->parse_features = x86_cpu_parse_featurestr; 8915 cc->dump_state = x86_cpu_dump_state; 8916 cc->set_pc = x86_cpu_set_pc; 8917 cc->get_pc = x86_cpu_get_pc; 8918 cc->gdb_read_register = x86_cpu_gdb_read_register; 8919 cc->gdb_write_register = x86_cpu_gdb_write_register; 8920 cc->get_arch_id = x86_cpu_get_arch_id; 8921 8922 #ifndef CONFIG_USER_ONLY 8923 cc->sysemu_ops = &i386_sysemu_ops; 8924 #endif /* !CONFIG_USER_ONLY */ 8925 #ifdef CONFIG_TCG 8926 cc->tcg_ops = &x86_tcg_ops; 8927 #endif /* CONFIG_TCG */ 8928 8929 cc->gdb_arch_name = x86_gdb_arch_name; 8930 #ifdef TARGET_X86_64 8931 cc->gdb_core_xml_file = "i386-64bit.xml"; 8932 #else 8933 cc->gdb_core_xml_file = "i386-32bit.xml"; 8934 #endif 8935 cc->disas_set_info = x86_disas_set_info; 8936 8937 dc->user_creatable = true; 8938 8939 object_class_property_add(oc, "family", "int", 8940 x86_cpuid_version_get_family, 8941 x86_cpuid_version_set_family, NULL, NULL); 8942 object_class_property_add(oc, "model", "int", 8943 x86_cpuid_version_get_model, 8944 x86_cpuid_version_set_model, NULL, NULL); 8945 object_class_property_add(oc, "stepping", "int", 8946 x86_cpuid_version_get_stepping, 8947 x86_cpuid_version_set_stepping, NULL, NULL); 8948 object_class_property_add_str(oc, "vendor", 8949 x86_cpuid_get_vendor, 8950 x86_cpuid_set_vendor); 8951 object_class_property_add_str(oc, "model-id", 8952 x86_cpuid_get_model_id, 8953 x86_cpuid_set_model_id); 8954 object_class_property_add(oc, "tsc-frequency", "int", 8955 x86_cpuid_get_tsc_freq, 8956 x86_cpuid_set_tsc_freq, NULL, NULL); 8957 /* 8958 * The "unavailable-features" property has the same semantics as 8959 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8960 * QMP command: they list the features that would have prevented the 8961 * CPU from running if the "enforce" flag was set. 8962 */ 8963 object_class_property_add(oc, "unavailable-features", "strList", 8964 x86_cpu_get_unavailable_features, 8965 NULL, NULL, NULL); 8966 8967 #if !defined(CONFIG_USER_ONLY) 8968 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8969 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8970 #endif 8971 8972 for (w = 0; w < FEATURE_WORDS; w++) { 8973 int bitnr; 8974 for (bitnr = 0; bitnr < 64; bitnr++) { 8975 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8976 } 8977 } 8978 } 8979 8980 static const TypeInfo x86_cpu_type_info = { 8981 .name = TYPE_X86_CPU, 8982 .parent = TYPE_CPU, 8983 .instance_size = sizeof(X86CPU), 8984 .instance_align = __alignof(X86CPU), 8985 .instance_init = x86_cpu_initfn, 8986 .instance_post_init = x86_cpu_post_initfn, 8987 8988 .abstract = true, 8989 .class_size = sizeof(X86CPUClass), 8990 .class_init = x86_cpu_common_class_init, 8991 }; 8992 8993 /* "base" CPU model, used by query-cpu-model-expansion */ 8994 static void x86_cpu_base_class_init(ObjectClass *oc, const void *data) 8995 { 8996 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8997 8998 xcc->static_model = true; 8999 xcc->migration_safe = true; 9000 xcc->model_description = "base CPU model type with no features enabled"; 9001 xcc->ordering = 8; 9002 } 9003 9004 static const TypeInfo x86_base_cpu_type_info = { 9005 .name = X86_CPU_TYPE_NAME("base"), 9006 .parent = TYPE_X86_CPU, 9007 .class_init = x86_cpu_base_class_init, 9008 }; 9009 9010 static void x86_cpu_register_types(void) 9011 { 9012 int i; 9013 9014 type_register_static(&x86_cpu_type_info); 9015 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 9016 x86_register_cpudef_types(&builtin_x86_defs[i]); 9017 } 9018 type_register_static(&max_x86_cpu_type_info); 9019 type_register_static(&x86_base_cpu_type_info); 9020 } 9021 9022 type_init(x86_cpu_register_types) 9023