1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "sysemu/reset.h" 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 51 /* Helpers for building CPUID[2] descriptors: */ 52 53 struct CPUID2CacheDescriptorInfo { 54 enum CacheType type; 55 int level; 56 int size; 57 int line_size; 58 int associativity; 59 }; 60 61 /* 62 * Known CPUID 2 cache descriptors. 63 * From Intel SDM Volume 2A, CPUID instruction 64 */ 65 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 66 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 67 .associativity = 4, .line_size = 32, }, 68 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 71 .associativity = 4, .line_size = 64, }, 72 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 73 .associativity = 2, .line_size = 32, }, 74 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 75 .associativity = 4, .line_size = 32, }, 76 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 77 .associativity = 4, .line_size = 64, }, 78 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 79 .associativity = 6, .line_size = 64, }, 80 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 81 .associativity = 2, .line_size = 64, }, 82 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 83 .associativity = 8, .line_size = 64, }, 84 /* lines per sector is not supported cpuid2_cache_descriptor(), 85 * so descriptors 0x22, 0x23 are not included 86 */ 87 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 88 .associativity = 16, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x25, 0x20 are not included 91 */ 92 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 93 .associativity = 8, .line_size = 64, }, 94 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 95 .associativity = 8, .line_size = 64, }, 96 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 107 .associativity = 4, .line_size = 64, }, 108 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 109 .associativity = 8, .line_size = 64, }, 110 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 111 .associativity = 12, .line_size = 64, }, 112 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 113 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 116 .associativity = 16, .line_size = 64, }, 117 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 118 .associativity = 12, .line_size = 64, }, 119 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 120 .associativity = 16, .line_size = 64, }, 121 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 122 .associativity = 24, .line_size = 64, }, 123 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 124 .associativity = 8, .line_size = 64, }, 125 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 126 .associativity = 4, .line_size = 64, }, 127 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 128 .associativity = 4, .line_size = 64, }, 129 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 130 .associativity = 4, .line_size = 64, }, 131 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 132 .associativity = 4, .line_size = 64, }, 133 /* lines per sector is not supported cpuid2_cache_descriptor(), 134 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 135 */ 136 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 139 .associativity = 2, .line_size = 64, }, 140 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 141 .associativity = 8, .line_size = 64, }, 142 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 8, .line_size = 32, }, 146 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 147 .associativity = 8, .line_size = 32, }, 148 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 4, .line_size = 64, }, 152 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 8, .line_size = 64, }, 154 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 155 .associativity = 4, .line_size = 64, }, 156 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 157 .associativity = 4, .line_size = 64, }, 158 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 159 .associativity = 4, .line_size = 64, }, 160 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 161 .associativity = 8, .line_size = 64, }, 162 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 163 .associativity = 8, .line_size = 64, }, 164 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 165 .associativity = 8, .line_size = 64, }, 166 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 167 .associativity = 12, .line_size = 64, }, 168 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 169 .associativity = 12, .line_size = 64, }, 170 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 171 .associativity = 12, .line_size = 64, }, 172 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 173 .associativity = 16, .line_size = 64, }, 174 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 175 .associativity = 16, .line_size = 64, }, 176 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 177 .associativity = 16, .line_size = 64, }, 178 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 179 .associativity = 24, .line_size = 64, }, 180 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 181 .associativity = 24, .line_size = 64, }, 182 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 183 .associativity = 24, .line_size = 64, }, 184 }; 185 186 /* 187 * "CPUID leaf 2 does not report cache descriptor information, 188 * use CPUID leaf 4 to query cache parameters" 189 */ 190 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 191 192 /* 193 * Return a CPUID 2 cache descriptor for a given cache. 194 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 195 */ 196 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 197 { 198 int i; 199 200 assert(cache->size > 0); 201 assert(cache->level > 0); 202 assert(cache->line_size > 0); 203 assert(cache->associativity > 0); 204 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 205 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 206 if (d->level == cache->level && d->type == cache->type && 207 d->size == cache->size && d->line_size == cache->line_size && 208 d->associativity == cache->associativity) { 209 return i; 210 } 211 } 212 213 return CACHE_DESCRIPTOR_UNAVAILABLE; 214 } 215 216 /* CPUID Leaf 4 constants: */ 217 218 /* EAX: */ 219 #define CACHE_TYPE_D 1 220 #define CACHE_TYPE_I 2 221 #define CACHE_TYPE_UNIFIED 3 222 223 #define CACHE_LEVEL(l) (l << 5) 224 225 #define CACHE_SELF_INIT_LEVEL (1 << 8) 226 227 /* EDX: */ 228 #define CACHE_NO_INVD_SHARING (1 << 0) 229 #define CACHE_INCLUSIVE (1 << 1) 230 #define CACHE_COMPLEX_IDX (1 << 2) 231 232 /* Encode CacheType for CPUID[4].EAX */ 233 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 234 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 235 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 236 0 /* Invalid value */) 237 238 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 239 enum CPUTopoLevel share_level) 240 { 241 uint32_t num_ids = 0; 242 243 switch (share_level) { 244 case CPU_TOPO_LEVEL_CORE: 245 num_ids = 1 << apicid_core_offset(topo_info); 246 break; 247 case CPU_TOPO_LEVEL_DIE: 248 num_ids = 1 << apicid_die_offset(topo_info); 249 break; 250 case CPU_TOPO_LEVEL_PACKAGE: 251 num_ids = 1 << apicid_pkg_offset(topo_info); 252 break; 253 default: 254 /* 255 * Currently there is no use case for SMT and MODULE, so use 256 * assert directly to facilitate debugging. 257 */ 258 g_assert_not_reached(); 259 } 260 261 return num_ids - 1; 262 } 263 264 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 265 { 266 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 267 apicid_core_offset(topo_info)); 268 return num_cores - 1; 269 } 270 271 /* Encode cache info for CPUID[4] */ 272 static void encode_cache_cpuid4(CPUCacheInfo *cache, 273 X86CPUTopoInfo *topo_info, 274 uint32_t *eax, uint32_t *ebx, 275 uint32_t *ecx, uint32_t *edx) 276 { 277 assert(cache->size == cache->line_size * cache->associativity * 278 cache->partitions * cache->sets); 279 280 *eax = CACHE_TYPE(cache->type) | 281 CACHE_LEVEL(cache->level) | 282 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 283 (max_core_ids_in_package(topo_info) << 26) | 284 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 285 286 assert(cache->line_size > 0); 287 assert(cache->partitions > 0); 288 assert(cache->associativity > 0); 289 /* We don't implement fully-associative caches */ 290 assert(cache->associativity < cache->sets); 291 *ebx = (cache->line_size - 1) | 292 ((cache->partitions - 1) << 12) | 293 ((cache->associativity - 1) << 22); 294 295 assert(cache->sets > 0); 296 *ecx = cache->sets - 1; 297 298 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 299 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 300 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 301 } 302 303 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 304 enum CPUTopoLevel topo_level) 305 { 306 switch (topo_level) { 307 case CPU_TOPO_LEVEL_SMT: 308 return 1; 309 case CPU_TOPO_LEVEL_CORE: 310 return topo_info->threads_per_core; 311 case CPU_TOPO_LEVEL_MODULE: 312 return topo_info->threads_per_core * topo_info->cores_per_module; 313 case CPU_TOPO_LEVEL_DIE: 314 return topo_info->threads_per_core * topo_info->cores_per_module * 315 topo_info->modules_per_die; 316 case CPU_TOPO_LEVEL_PACKAGE: 317 return topo_info->threads_per_core * topo_info->cores_per_module * 318 topo_info->modules_per_die * topo_info->dies_per_pkg; 319 default: 320 g_assert_not_reached(); 321 } 322 return 0; 323 } 324 325 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 326 enum CPUTopoLevel topo_level) 327 { 328 switch (topo_level) { 329 case CPU_TOPO_LEVEL_SMT: 330 return 0; 331 case CPU_TOPO_LEVEL_CORE: 332 return apicid_core_offset(topo_info); 333 case CPU_TOPO_LEVEL_MODULE: 334 return apicid_module_offset(topo_info); 335 case CPU_TOPO_LEVEL_DIE: 336 return apicid_die_offset(topo_info); 337 case CPU_TOPO_LEVEL_PACKAGE: 338 return apicid_pkg_offset(topo_info); 339 default: 340 g_assert_not_reached(); 341 } 342 return 0; 343 } 344 345 static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) 346 { 347 switch (topo_level) { 348 case CPU_TOPO_LEVEL_INVALID: 349 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 350 case CPU_TOPO_LEVEL_SMT: 351 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 352 case CPU_TOPO_LEVEL_CORE: 353 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 354 case CPU_TOPO_LEVEL_MODULE: 355 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 356 case CPU_TOPO_LEVEL_DIE: 357 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 358 default: 359 /* Other types are not supported in QEMU. */ 360 g_assert_not_reached(); 361 } 362 return 0; 363 } 364 365 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 366 X86CPUTopoInfo *topo_info, 367 uint32_t *eax, uint32_t *ebx, 368 uint32_t *ecx, uint32_t *edx) 369 { 370 X86CPU *cpu = env_archcpu(env); 371 unsigned long level, next_level; 372 uint32_t num_threads_next_level, offset_next_level; 373 374 assert(count + 1 < CPU_TOPO_LEVEL_MAX); 375 376 /* 377 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 378 * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). 379 */ 380 level = CPU_TOPO_LEVEL_INVALID; 381 for (int i = 0; i <= count; i++) { 382 level = find_next_bit(env->avail_cpu_topo, 383 CPU_TOPO_LEVEL_PACKAGE, 384 level + 1); 385 386 /* 387 * CPUID[0x1f] doesn't explicitly encode the package level, 388 * and it just encodes the invalid level (all fields are 0) 389 * into the last subleaf of 0x1f. 390 */ 391 if (level == CPU_TOPO_LEVEL_PACKAGE) { 392 level = CPU_TOPO_LEVEL_INVALID; 393 break; 394 } 395 } 396 397 if (level == CPU_TOPO_LEVEL_INVALID) { 398 num_threads_next_level = 0; 399 offset_next_level = 0; 400 } else { 401 next_level = find_next_bit(env->avail_cpu_topo, 402 CPU_TOPO_LEVEL_PACKAGE, 403 level + 1); 404 num_threads_next_level = num_threads_by_topo_level(topo_info, 405 next_level); 406 offset_next_level = apicid_offset_by_topo_level(topo_info, 407 next_level); 408 } 409 410 *eax = offset_next_level; 411 /* The count (bits 15-00) doesn't need to be reliable. */ 412 *ebx = num_threads_next_level & 0xffff; 413 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 414 *edx = cpu->apic_id; 415 416 assert(!(*eax & ~0x1f)); 417 } 418 419 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 420 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 421 { 422 assert(cache->size % 1024 == 0); 423 assert(cache->lines_per_tag > 0); 424 assert(cache->associativity > 0); 425 assert(cache->line_size > 0); 426 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 427 (cache->lines_per_tag << 8) | (cache->line_size); 428 } 429 430 #define ASSOC_FULL 0xFF 431 432 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 433 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 434 a == 2 ? 0x2 : \ 435 a == 4 ? 0x4 : \ 436 a == 8 ? 0x6 : \ 437 a == 16 ? 0x8 : \ 438 a == 32 ? 0xA : \ 439 a == 48 ? 0xB : \ 440 a == 64 ? 0xC : \ 441 a == 96 ? 0xD : \ 442 a == 128 ? 0xE : \ 443 a == ASSOC_FULL ? 0xF : \ 444 0 /* invalid value */) 445 446 /* 447 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 448 * @l3 can be NULL. 449 */ 450 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 451 CPUCacheInfo *l3, 452 uint32_t *ecx, uint32_t *edx) 453 { 454 assert(l2->size % 1024 == 0); 455 assert(l2->associativity > 0); 456 assert(l2->lines_per_tag > 0); 457 assert(l2->line_size > 0); 458 *ecx = ((l2->size / 1024) << 16) | 459 (AMD_ENC_ASSOC(l2->associativity) << 12) | 460 (l2->lines_per_tag << 8) | (l2->line_size); 461 462 if (l3) { 463 assert(l3->size % (512 * 1024) == 0); 464 assert(l3->associativity > 0); 465 assert(l3->lines_per_tag > 0); 466 assert(l3->line_size > 0); 467 *edx = ((l3->size / (512 * 1024)) << 18) | 468 (AMD_ENC_ASSOC(l3->associativity) << 12) | 469 (l3->lines_per_tag << 8) | (l3->line_size); 470 } else { 471 *edx = 0; 472 } 473 } 474 475 /* Encode cache info for CPUID[8000001D] */ 476 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 477 X86CPUTopoInfo *topo_info, 478 uint32_t *eax, uint32_t *ebx, 479 uint32_t *ecx, uint32_t *edx) 480 { 481 assert(cache->size == cache->line_size * cache->associativity * 482 cache->partitions * cache->sets); 483 484 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 485 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 486 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 487 488 assert(cache->line_size > 0); 489 assert(cache->partitions > 0); 490 assert(cache->associativity > 0); 491 /* We don't implement fully-associative caches */ 492 assert(cache->associativity < cache->sets); 493 *ebx = (cache->line_size - 1) | 494 ((cache->partitions - 1) << 12) | 495 ((cache->associativity - 1) << 22); 496 497 assert(cache->sets > 0); 498 *ecx = cache->sets - 1; 499 500 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 501 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 502 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 503 } 504 505 /* Encode cache info for CPUID[8000001E] */ 506 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 507 uint32_t *eax, uint32_t *ebx, 508 uint32_t *ecx, uint32_t *edx) 509 { 510 X86CPUTopoIDs topo_ids; 511 512 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 513 514 *eax = cpu->apic_id; 515 516 /* 517 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 518 * Read-only. Reset: 0000_XXXXh. 519 * See Core::X86::Cpuid::ExtApicId. 520 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 521 * Bits Description 522 * 31:16 Reserved. 523 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 524 * The number of threads per core is ThreadsPerCore+1. 525 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 526 * 527 * NOTE: CoreId is already part of apic_id. Just use it. We can 528 * use all the 8 bits to represent the core_id here. 529 */ 530 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 531 532 /* 533 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 534 * Read-only. Reset: 0000_0XXXh. 535 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 536 * Bits Description 537 * 31:11 Reserved. 538 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 539 * ValidValues: 540 * Value Description 541 * 0h 1 node per processor. 542 * 7h-1h Reserved. 543 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 544 * 545 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 546 * But users can create more nodes than the actual hardware can 547 * support. To genaralize we can use all the upper 8 bits for nodes. 548 * NodeId is combination of node and socket_id which is already decoded 549 * in apic_id. Just use it by shifting. 550 */ 551 if (cpu->legacy_multi_node) { 552 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 553 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 554 } else { 555 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 556 } 557 558 *edx = 0; 559 } 560 561 /* 562 * Definitions of the hardcoded cache entries we expose: 563 * These are legacy cache values. If there is a need to change any 564 * of these values please use builtin_x86_defs 565 */ 566 567 /* L1 data cache: */ 568 static CPUCacheInfo legacy_l1d_cache = { 569 .type = DATA_CACHE, 570 .level = 1, 571 .size = 32 * KiB, 572 .self_init = 1, 573 .line_size = 64, 574 .associativity = 8, 575 .sets = 64, 576 .partitions = 1, 577 .no_invd_sharing = true, 578 .share_level = CPU_TOPO_LEVEL_CORE, 579 }; 580 581 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 582 static CPUCacheInfo legacy_l1d_cache_amd = { 583 .type = DATA_CACHE, 584 .level = 1, 585 .size = 64 * KiB, 586 .self_init = 1, 587 .line_size = 64, 588 .associativity = 2, 589 .sets = 512, 590 .partitions = 1, 591 .lines_per_tag = 1, 592 .no_invd_sharing = true, 593 .share_level = CPU_TOPO_LEVEL_CORE, 594 }; 595 596 /* L1 instruction cache: */ 597 static CPUCacheInfo legacy_l1i_cache = { 598 .type = INSTRUCTION_CACHE, 599 .level = 1, 600 .size = 32 * KiB, 601 .self_init = 1, 602 .line_size = 64, 603 .associativity = 8, 604 .sets = 64, 605 .partitions = 1, 606 .no_invd_sharing = true, 607 .share_level = CPU_TOPO_LEVEL_CORE, 608 }; 609 610 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 611 static CPUCacheInfo legacy_l1i_cache_amd = { 612 .type = INSTRUCTION_CACHE, 613 .level = 1, 614 .size = 64 * KiB, 615 .self_init = 1, 616 .line_size = 64, 617 .associativity = 2, 618 .sets = 512, 619 .partitions = 1, 620 .lines_per_tag = 1, 621 .no_invd_sharing = true, 622 .share_level = CPU_TOPO_LEVEL_CORE, 623 }; 624 625 /* Level 2 unified cache: */ 626 static CPUCacheInfo legacy_l2_cache = { 627 .type = UNIFIED_CACHE, 628 .level = 2, 629 .size = 4 * MiB, 630 .self_init = 1, 631 .line_size = 64, 632 .associativity = 16, 633 .sets = 4096, 634 .partitions = 1, 635 .no_invd_sharing = true, 636 .share_level = CPU_TOPO_LEVEL_CORE, 637 }; 638 639 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 640 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 641 .type = UNIFIED_CACHE, 642 .level = 2, 643 .size = 2 * MiB, 644 .line_size = 64, 645 .associativity = 8, 646 .share_level = CPU_TOPO_LEVEL_INVALID, 647 }; 648 649 650 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 651 static CPUCacheInfo legacy_l2_cache_amd = { 652 .type = UNIFIED_CACHE, 653 .level = 2, 654 .size = 512 * KiB, 655 .line_size = 64, 656 .lines_per_tag = 1, 657 .associativity = 16, 658 .sets = 512, 659 .partitions = 1, 660 .share_level = CPU_TOPO_LEVEL_CORE, 661 }; 662 663 /* Level 3 unified cache: */ 664 static CPUCacheInfo legacy_l3_cache = { 665 .type = UNIFIED_CACHE, 666 .level = 3, 667 .size = 16 * MiB, 668 .line_size = 64, 669 .associativity = 16, 670 .sets = 16384, 671 .partitions = 1, 672 .lines_per_tag = 1, 673 .self_init = true, 674 .inclusive = true, 675 .complex_indexing = true, 676 .share_level = CPU_TOPO_LEVEL_DIE, 677 }; 678 679 /* TLB definitions: */ 680 681 #define L1_DTLB_2M_ASSOC 1 682 #define L1_DTLB_2M_ENTRIES 255 683 #define L1_DTLB_4K_ASSOC 1 684 #define L1_DTLB_4K_ENTRIES 255 685 686 #define L1_ITLB_2M_ASSOC 1 687 #define L1_ITLB_2M_ENTRIES 255 688 #define L1_ITLB_4K_ASSOC 1 689 #define L1_ITLB_4K_ENTRIES 255 690 691 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 692 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 693 #define L2_DTLB_4K_ASSOC 4 694 #define L2_DTLB_4K_ENTRIES 512 695 696 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 697 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 698 #define L2_ITLB_4K_ASSOC 4 699 #define L2_ITLB_4K_ENTRIES 512 700 701 /* CPUID Leaf 0x14 constants: */ 702 #define INTEL_PT_MAX_SUBLEAF 0x1 703 /* 704 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 705 * MSR can be accessed; 706 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 707 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 708 * of Intel PT MSRs across warm reset; 709 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 710 */ 711 #define INTEL_PT_MINIMAL_EBX 0xf 712 /* 713 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 714 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 715 * accessed; 716 * bit[01]: ToPA tables can hold any number of output entries, up to the 717 * maximum allowed by the MaskOrTableOffset field of 718 * IA32_RTIT_OUTPUT_MASK_PTRS; 719 * bit[02]: Support Single-Range Output scheme; 720 */ 721 #define INTEL_PT_MINIMAL_ECX 0x7 722 /* generated packets which contain IP payloads have LIP values */ 723 #define INTEL_PT_IP_LIP (1 << 31) 724 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 725 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 726 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 727 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 728 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 729 730 /* CPUID Leaf 0x1D constants: */ 731 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 732 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 733 #define INTEL_AMX_BYTES_PER_TILE 0x400 734 #define INTEL_AMX_BYTES_PER_ROW 0x40 735 #define INTEL_AMX_TILE_MAX_NAMES 0x8 736 #define INTEL_AMX_TILE_MAX_ROWS 0x10 737 738 /* CPUID Leaf 0x1E constants: */ 739 #define INTEL_AMX_TMUL_MAX_K 0x10 740 #define INTEL_AMX_TMUL_MAX_N 0x40 741 742 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 743 uint32_t vendor2, uint32_t vendor3) 744 { 745 int i; 746 for (i = 0; i < 4; i++) { 747 dst[i] = vendor1 >> (8 * i); 748 dst[i + 4] = vendor2 >> (8 * i); 749 dst[i + 8] = vendor3 >> (8 * i); 750 } 751 dst[CPUID_VENDOR_SZ] = '\0'; 752 } 753 754 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 755 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 756 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 757 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 758 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 759 CPUID_PSE36 | CPUID_FXSR) 760 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 761 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 762 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 763 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 764 CPUID_PAE | CPUID_SEP | CPUID_APIC) 765 766 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 767 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 768 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 769 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 770 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 771 /* partly implemented: 772 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 773 /* missing: 774 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 775 776 /* 777 * Kernel-only features that can be shown to usermode programs even if 778 * they aren't actually supported by TCG, because qemu-user only runs 779 * in CPL=3; remove them if they are ever implemented for system emulation. 780 */ 781 #if defined CONFIG_USER_ONLY 782 #define CPUID_EXT_KERNEL_FEATURES \ 783 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 784 #else 785 #define CPUID_EXT_KERNEL_FEATURES 0 786 #endif 787 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 788 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 789 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 790 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 791 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 792 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 793 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 794 /* missing: 795 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 796 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 797 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 798 CPUID_EXT_TSC_DEADLINE_TIMER 799 */ 800 801 #ifdef TARGET_X86_64 802 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 803 #else 804 #define TCG_EXT2_X86_64_FEATURES 0 805 #endif 806 807 /* 808 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 809 * in usermode or by 32-bit programs. Those are added to supported 810 * TCG features unconditionally in user-mode emulation mode. This may 811 * indeed seem strange or incorrect, but it works because code running 812 * under usermode emulation cannot access them. 813 * 814 * Even for long mode, qemu-i386 is not running "a userspace program on a 815 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 816 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 817 * but again the difference is only visible in kernel mode. 818 */ 819 #if defined CONFIG_LINUX_USER 820 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 821 #elif defined CONFIG_USER_ONLY 822 /* FIXME: Long mode not yet supported for i386 bsd-user */ 823 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 824 #else 825 #define CPUID_EXT2_KERNEL_FEATURES 0 826 #endif 827 828 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 829 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 830 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 831 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 832 CPUID_EXT2_KERNEL_FEATURES) 833 834 #if defined CONFIG_USER_ONLY 835 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 836 #else 837 #define CPUID_EXT3_KERNEL_FEATURES 0 838 #endif 839 840 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 841 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 842 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 843 844 #define TCG_EXT4_FEATURES 0 845 846 #if defined CONFIG_USER_ONLY 847 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 848 #else 849 #define CPUID_SVM_KERNEL_FEATURES 0 850 #endif 851 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 852 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 853 854 #define TCG_KVM_FEATURES 0 855 856 #if defined CONFIG_USER_ONLY 857 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 858 #else 859 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 860 #endif 861 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 862 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 863 CPUID_7_0_EBX_CLFLUSHOPT | \ 864 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 865 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 866 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 867 /* missing: 868 CPUID_7_0_EBX_HLE 869 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 870 871 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 872 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 873 #else 874 #define TCG_7_0_ECX_RDPID 0 875 #endif 876 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 877 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 878 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 879 TCG_7_0_ECX_RDPID) 880 881 #if defined CONFIG_USER_ONLY 882 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 883 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 884 #else 885 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 886 #endif 887 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 888 889 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 890 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 891 #define TCG_7_1_EDX_FEATURES 0 892 #define TCG_7_2_EDX_FEATURES 0 893 #define TCG_APM_FEATURES 0 894 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 895 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 896 /* missing: 897 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 898 #define TCG_14_0_ECX_FEATURES 0 899 #define TCG_SGX_12_0_EAX_FEATURES 0 900 #define TCG_SGX_12_0_EBX_FEATURES 0 901 #define TCG_SGX_12_1_EAX_FEATURES 0 902 903 #if defined CONFIG_USER_ONLY 904 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 905 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 906 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 907 CPUID_8000_0008_EBX_AMD_PSFD) 908 #else 909 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 910 #endif 911 912 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 913 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 914 915 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 916 [FEAT_1_EDX] = { 917 .type = CPUID_FEATURE_WORD, 918 .feat_names = { 919 "fpu", "vme", "de", "pse", 920 "tsc", "msr", "pae", "mce", 921 "cx8", "apic", NULL, "sep", 922 "mtrr", "pge", "mca", "cmov", 923 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 924 NULL, "ds" /* Intel dts */, "acpi", "mmx", 925 "fxsr", "sse", "sse2", "ss", 926 "ht" /* Intel htt */, "tm", "ia64", "pbe", 927 }, 928 .cpuid = {.eax = 1, .reg = R_EDX, }, 929 .tcg_features = TCG_FEATURES, 930 .no_autoenable_flags = CPUID_HT, 931 }, 932 [FEAT_1_ECX] = { 933 .type = CPUID_FEATURE_WORD, 934 .feat_names = { 935 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 936 "ds-cpl", "vmx", "smx", "est", 937 "tm2", "ssse3", "cid", NULL, 938 "fma", "cx16", "xtpr", "pdcm", 939 NULL, "pcid", "dca", "sse4.1", 940 "sse4.2", "x2apic", "movbe", "popcnt", 941 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 942 "avx", "f16c", "rdrand", "hypervisor", 943 }, 944 .cpuid = { .eax = 1, .reg = R_ECX, }, 945 .tcg_features = TCG_EXT_FEATURES, 946 }, 947 /* Feature names that are already defined on feature_name[] but 948 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 949 * names on feat_names below. They are copied automatically 950 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 951 */ 952 [FEAT_8000_0001_EDX] = { 953 .type = CPUID_FEATURE_WORD, 954 .feat_names = { 955 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 956 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 957 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 958 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 959 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 960 "nx", NULL, "mmxext", NULL /* mmx */, 961 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 962 NULL, "lm", "3dnowext", "3dnow", 963 }, 964 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 965 .tcg_features = TCG_EXT2_FEATURES, 966 }, 967 [FEAT_8000_0001_ECX] = { 968 .type = CPUID_FEATURE_WORD, 969 .feat_names = { 970 "lahf-lm", "cmp-legacy", "svm", "extapic", 971 "cr8legacy", "abm", "sse4a", "misalignsse", 972 "3dnowprefetch", "osvw", "ibs", "xop", 973 "skinit", "wdt", NULL, "lwp", 974 "fma4", "tce", NULL, "nodeid-msr", 975 NULL, "tbm", "topoext", "perfctr-core", 976 "perfctr-nb", NULL, NULL, NULL, 977 NULL, NULL, NULL, NULL, 978 }, 979 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 980 .tcg_features = TCG_EXT3_FEATURES, 981 /* 982 * TOPOEXT is always allowed but can't be enabled blindly by 983 * "-cpu host", as it requires consistent cache topology info 984 * to be provided so it doesn't confuse guests. 985 */ 986 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 987 }, 988 [FEAT_C000_0001_EDX] = { 989 .type = CPUID_FEATURE_WORD, 990 .feat_names = { 991 NULL, NULL, "xstore", "xstore-en", 992 NULL, NULL, "xcrypt", "xcrypt-en", 993 "ace2", "ace2-en", "phe", "phe-en", 994 "pmm", "pmm-en", NULL, NULL, 995 NULL, NULL, NULL, NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 }, 1000 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1001 .tcg_features = TCG_EXT4_FEATURES, 1002 }, 1003 [FEAT_KVM] = { 1004 .type = CPUID_FEATURE_WORD, 1005 .feat_names = { 1006 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1007 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1008 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1009 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1010 NULL, NULL, NULL, NULL, 1011 NULL, NULL, NULL, NULL, 1012 "kvmclock-stable-bit", NULL, NULL, NULL, 1013 NULL, NULL, NULL, NULL, 1014 }, 1015 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1016 .tcg_features = TCG_KVM_FEATURES, 1017 }, 1018 [FEAT_KVM_HINTS] = { 1019 .type = CPUID_FEATURE_WORD, 1020 .feat_names = { 1021 "kvm-hint-dedicated", NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 NULL, NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 }, 1030 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1031 .tcg_features = TCG_KVM_FEATURES, 1032 /* 1033 * KVM hints aren't auto-enabled by -cpu host, they need to be 1034 * explicitly enabled in the command-line. 1035 */ 1036 .no_autoenable_flags = ~0U, 1037 }, 1038 [FEAT_SVM] = { 1039 .type = CPUID_FEATURE_WORD, 1040 .feat_names = { 1041 "npt", "lbrv", "svm-lock", "nrip-save", 1042 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1043 NULL, NULL, "pause-filter", NULL, 1044 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1045 "vgif", NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, "vnmi", NULL, NULL, 1048 "svme-addr-chk", NULL, NULL, NULL, 1049 }, 1050 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1051 .tcg_features = TCG_SVM_FEATURES, 1052 }, 1053 [FEAT_7_0_EBX] = { 1054 .type = CPUID_FEATURE_WORD, 1055 .feat_names = { 1056 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1057 "hle", "avx2", "fdp-excptn-only", "smep", 1058 "bmi2", "erms", "invpcid", "rtm", 1059 NULL, "zero-fcs-fds", "mpx", NULL, 1060 "avx512f", "avx512dq", "rdseed", "adx", 1061 "smap", "avx512ifma", "pcommit", "clflushopt", 1062 "clwb", "intel-pt", "avx512pf", "avx512er", 1063 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1064 }, 1065 .cpuid = { 1066 .eax = 7, 1067 .needs_ecx = true, .ecx = 0, 1068 .reg = R_EBX, 1069 }, 1070 .tcg_features = TCG_7_0_EBX_FEATURES, 1071 }, 1072 [FEAT_7_0_ECX] = { 1073 .type = CPUID_FEATURE_WORD, 1074 .feat_names = { 1075 NULL, "avx512vbmi", "umip", "pku", 1076 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1077 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1078 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1079 "la57", NULL, NULL, NULL, 1080 NULL, NULL, "rdpid", NULL, 1081 "bus-lock-detect", "cldemote", NULL, "movdiri", 1082 "movdir64b", NULL, "sgxlc", "pks", 1083 }, 1084 .cpuid = { 1085 .eax = 7, 1086 .needs_ecx = true, .ecx = 0, 1087 .reg = R_ECX, 1088 }, 1089 .tcg_features = TCG_7_0_ECX_FEATURES, 1090 }, 1091 [FEAT_7_0_EDX] = { 1092 .type = CPUID_FEATURE_WORD, 1093 .feat_names = { 1094 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1095 "fsrm", NULL, NULL, NULL, 1096 "avx512-vp2intersect", NULL, "md-clear", NULL, 1097 NULL, NULL, "serialize", NULL, 1098 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1099 NULL, NULL, "amx-bf16", "avx512-fp16", 1100 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1101 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1102 }, 1103 .cpuid = { 1104 .eax = 7, 1105 .needs_ecx = true, .ecx = 0, 1106 .reg = R_EDX, 1107 }, 1108 .tcg_features = TCG_7_0_EDX_FEATURES, 1109 }, 1110 [FEAT_7_1_EAX] = { 1111 .type = CPUID_FEATURE_WORD, 1112 .feat_names = { 1113 NULL, NULL, NULL, NULL, 1114 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1115 NULL, NULL, "fzrm", "fsrs", 1116 "fsrc", NULL, NULL, NULL, 1117 NULL, "fred", "lkgs", "wrmsrns", 1118 NULL, "amx-fp16", NULL, "avx-ifma", 1119 NULL, NULL, "lam", NULL, 1120 NULL, NULL, NULL, NULL, 1121 }, 1122 .cpuid = { 1123 .eax = 7, 1124 .needs_ecx = true, .ecx = 1, 1125 .reg = R_EAX, 1126 }, 1127 .tcg_features = TCG_7_1_EAX_FEATURES, 1128 }, 1129 [FEAT_7_1_EDX] = { 1130 .type = CPUID_FEATURE_WORD, 1131 .feat_names = { 1132 NULL, NULL, NULL, NULL, 1133 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1134 "amx-complex", NULL, "avx-vnni-int16", NULL, 1135 NULL, NULL, "prefetchiti", NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 }, 1141 .cpuid = { 1142 .eax = 7, 1143 .needs_ecx = true, .ecx = 1, 1144 .reg = R_EDX, 1145 }, 1146 .tcg_features = TCG_7_1_EDX_FEATURES, 1147 }, 1148 [FEAT_7_2_EDX] = { 1149 .type = CPUID_FEATURE_WORD, 1150 .feat_names = { 1151 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1152 "bhi-ctrl", "mcdt-no", NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL, NULL, NULL, 1156 NULL, NULL, NULL, NULL, 1157 NULL, NULL, NULL, NULL, 1158 NULL, NULL, NULL, NULL, 1159 }, 1160 .cpuid = { 1161 .eax = 7, 1162 .needs_ecx = true, .ecx = 2, 1163 .reg = R_EDX, 1164 }, 1165 .tcg_features = TCG_7_2_EDX_FEATURES, 1166 }, 1167 [FEAT_8000_0007_EDX] = { 1168 .type = CPUID_FEATURE_WORD, 1169 .feat_names = { 1170 NULL, NULL, NULL, NULL, 1171 NULL, NULL, NULL, NULL, 1172 "invtsc", NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 }, 1179 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1180 .tcg_features = TCG_APM_FEATURES, 1181 .unmigratable_flags = CPUID_APM_INVTSC, 1182 }, 1183 [FEAT_8000_0007_EBX] = { 1184 .type = CPUID_FEATURE_WORD, 1185 .feat_names = { 1186 "overflow-recov", "succor", NULL, NULL, 1187 NULL, NULL, NULL, NULL, 1188 NULL, NULL, NULL, NULL, 1189 NULL, NULL, NULL, NULL, 1190 NULL, NULL, NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 NULL, NULL, NULL, NULL, 1194 }, 1195 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1196 .tcg_features = 0, 1197 .unmigratable_flags = 0, 1198 }, 1199 [FEAT_8000_0008_EBX] = { 1200 .type = CPUID_FEATURE_WORD, 1201 .feat_names = { 1202 "clzero", NULL, "xsaveerptr", NULL, 1203 NULL, NULL, NULL, NULL, 1204 NULL, "wbnoinvd", NULL, NULL, 1205 "ibpb", NULL, "ibrs", "amd-stibp", 1206 NULL, "stibp-always-on", NULL, NULL, 1207 NULL, NULL, NULL, NULL, 1208 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1209 "amd-psfd", NULL, NULL, NULL, 1210 }, 1211 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1212 .tcg_features = TCG_8000_0008_EBX, 1213 .unmigratable_flags = 0, 1214 }, 1215 [FEAT_8000_0021_EAX] = { 1216 .type = CPUID_FEATURE_WORD, 1217 .feat_names = { 1218 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1219 NULL, NULL, "null-sel-clr-base", NULL, 1220 "auto-ibrs", NULL, NULL, NULL, 1221 NULL, NULL, NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, NULL, NULL, NULL, 1224 NULL, NULL, NULL, "sbpb", 1225 "ibpb-brtype", NULL, NULL, NULL, 1226 }, 1227 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1228 .tcg_features = 0, 1229 .unmigratable_flags = 0, 1230 }, 1231 [FEAT_XSAVE] = { 1232 .type = CPUID_FEATURE_WORD, 1233 .feat_names = { 1234 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1235 "xfd", NULL, NULL, NULL, 1236 NULL, NULL, NULL, NULL, 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 }, 1243 .cpuid = { 1244 .eax = 0xd, 1245 .needs_ecx = true, .ecx = 1, 1246 .reg = R_EAX, 1247 }, 1248 .tcg_features = TCG_XSAVE_FEATURES, 1249 }, 1250 [FEAT_XSAVE_XSS_LO] = { 1251 .type = CPUID_FEATURE_WORD, 1252 .feat_names = { 1253 NULL, NULL, NULL, NULL, 1254 NULL, NULL, NULL, NULL, 1255 NULL, NULL, NULL, NULL, 1256 NULL, NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 NULL, NULL, NULL, NULL, 1261 }, 1262 .cpuid = { 1263 .eax = 0xD, 1264 .needs_ecx = true, 1265 .ecx = 1, 1266 .reg = R_ECX, 1267 }, 1268 }, 1269 [FEAT_XSAVE_XSS_HI] = { 1270 .type = CPUID_FEATURE_WORD, 1271 .cpuid = { 1272 .eax = 0xD, 1273 .needs_ecx = true, 1274 .ecx = 1, 1275 .reg = R_EDX 1276 }, 1277 }, 1278 [FEAT_6_EAX] = { 1279 .type = CPUID_FEATURE_WORD, 1280 .feat_names = { 1281 NULL, NULL, "arat", NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 NULL, NULL, NULL, NULL, 1287 NULL, NULL, NULL, NULL, 1288 NULL, NULL, NULL, NULL, 1289 }, 1290 .cpuid = { .eax = 6, .reg = R_EAX, }, 1291 .tcg_features = TCG_6_EAX_FEATURES, 1292 }, 1293 [FEAT_XSAVE_XCR0_LO] = { 1294 .type = CPUID_FEATURE_WORD, 1295 .cpuid = { 1296 .eax = 0xD, 1297 .needs_ecx = true, .ecx = 0, 1298 .reg = R_EAX, 1299 }, 1300 .tcg_features = ~0U, 1301 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1302 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1303 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1304 XSTATE_PKRU_MASK, 1305 }, 1306 [FEAT_XSAVE_XCR0_HI] = { 1307 .type = CPUID_FEATURE_WORD, 1308 .cpuid = { 1309 .eax = 0xD, 1310 .needs_ecx = true, .ecx = 0, 1311 .reg = R_EDX, 1312 }, 1313 .tcg_features = ~0U, 1314 }, 1315 /*Below are MSR exposed features*/ 1316 [FEAT_ARCH_CAPABILITIES] = { 1317 .type = MSR_FEATURE_WORD, 1318 .feat_names = { 1319 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1320 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1321 "taa-no", NULL, NULL, NULL, 1322 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1323 NULL, "fb-clear", NULL, NULL, 1324 NULL, NULL, NULL, NULL, 1325 "pbrsb-no", NULL, "gds-no", "rfds-no", 1326 "rfds-clear", NULL, NULL, NULL, 1327 }, 1328 .msr = { 1329 .index = MSR_IA32_ARCH_CAPABILITIES, 1330 }, 1331 /* 1332 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1333 * cannot be read from user mode. Therefore, it has no impact 1334 > on any user-mode operation, and warnings about unsupported 1335 * features do not matter. 1336 */ 1337 .tcg_features = ~0U, 1338 }, 1339 [FEAT_CORE_CAPABILITY] = { 1340 .type = MSR_FEATURE_WORD, 1341 .feat_names = { 1342 NULL, NULL, NULL, NULL, 1343 NULL, "split-lock-detect", NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 NULL, NULL, NULL, NULL, 1349 NULL, NULL, NULL, NULL, 1350 }, 1351 .msr = { 1352 .index = MSR_IA32_CORE_CAPABILITY, 1353 }, 1354 }, 1355 [FEAT_PERF_CAPABILITIES] = { 1356 .type = MSR_FEATURE_WORD, 1357 .feat_names = { 1358 NULL, NULL, NULL, NULL, 1359 NULL, NULL, NULL, NULL, 1360 NULL, NULL, NULL, NULL, 1361 NULL, "full-width-write", NULL, NULL, 1362 NULL, NULL, NULL, NULL, 1363 NULL, NULL, NULL, NULL, 1364 NULL, NULL, NULL, NULL, 1365 NULL, NULL, NULL, NULL, 1366 }, 1367 .msr = { 1368 .index = MSR_IA32_PERF_CAPABILITIES, 1369 }, 1370 }, 1371 1372 [FEAT_VMX_PROCBASED_CTLS] = { 1373 .type = MSR_FEATURE_WORD, 1374 .feat_names = { 1375 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1376 NULL, NULL, NULL, "vmx-hlt-exit", 1377 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1378 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1379 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1380 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1381 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1382 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1383 }, 1384 .msr = { 1385 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1386 } 1387 }, 1388 1389 [FEAT_VMX_SECONDARY_CTLS] = { 1390 .type = MSR_FEATURE_WORD, 1391 .feat_names = { 1392 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1393 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1394 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1395 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1396 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1397 "vmx-xsaves", NULL, NULL, NULL, 1398 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1399 NULL, NULL, NULL, NULL, 1400 }, 1401 .msr = { 1402 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1403 } 1404 }, 1405 1406 [FEAT_VMX_PINBASED_CTLS] = { 1407 .type = MSR_FEATURE_WORD, 1408 .feat_names = { 1409 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1410 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 NULL, NULL, NULL, NULL, 1417 }, 1418 .msr = { 1419 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1420 } 1421 }, 1422 1423 [FEAT_VMX_EXIT_CTLS] = { 1424 .type = MSR_FEATURE_WORD, 1425 /* 1426 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1427 * the LM CPUID bit. 1428 */ 1429 .feat_names = { 1430 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1431 NULL, NULL, NULL, NULL, 1432 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1433 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1434 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1435 "vmx-exit-save-efer", "vmx-exit-load-efer", 1436 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1437 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1438 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1439 }, 1440 .msr = { 1441 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1442 } 1443 }, 1444 1445 [FEAT_VMX_ENTRY_CTLS] = { 1446 .type = MSR_FEATURE_WORD, 1447 .feat_names = { 1448 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1449 NULL, NULL, NULL, NULL, 1450 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1451 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1452 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1453 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1454 NULL, NULL, NULL, NULL, 1455 NULL, NULL, NULL, NULL, 1456 }, 1457 .msr = { 1458 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1459 } 1460 }, 1461 1462 [FEAT_VMX_MISC] = { 1463 .type = MSR_FEATURE_WORD, 1464 .feat_names = { 1465 NULL, NULL, NULL, NULL, 1466 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1467 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1468 NULL, NULL, NULL, NULL, 1469 NULL, NULL, NULL, NULL, 1470 NULL, NULL, NULL, NULL, 1471 NULL, NULL, NULL, NULL, 1472 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1473 }, 1474 .msr = { 1475 .index = MSR_IA32_VMX_MISC, 1476 } 1477 }, 1478 1479 [FEAT_VMX_EPT_VPID_CAPS] = { 1480 .type = MSR_FEATURE_WORD, 1481 .feat_names = { 1482 "vmx-ept-execonly", NULL, NULL, NULL, 1483 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1484 NULL, NULL, NULL, NULL, 1485 NULL, NULL, NULL, NULL, 1486 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1487 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1488 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1489 NULL, NULL, NULL, NULL, 1490 "vmx-invvpid", NULL, NULL, NULL, 1491 NULL, NULL, NULL, NULL, 1492 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1493 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1494 NULL, NULL, NULL, NULL, 1495 NULL, NULL, NULL, NULL, 1496 NULL, NULL, NULL, NULL, 1497 NULL, NULL, NULL, NULL, 1498 NULL, NULL, NULL, NULL, 1499 }, 1500 .msr = { 1501 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1502 } 1503 }, 1504 1505 [FEAT_VMX_BASIC] = { 1506 .type = MSR_FEATURE_WORD, 1507 .feat_names = { 1508 [54] = "vmx-ins-outs", 1509 [55] = "vmx-true-ctls", 1510 [56] = "vmx-any-errcode", 1511 [58] = "vmx-nested-exception", 1512 }, 1513 .msr = { 1514 .index = MSR_IA32_VMX_BASIC, 1515 }, 1516 /* Just to be safe - we don't support setting the MSEG version field. */ 1517 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1518 }, 1519 1520 [FEAT_VMX_VMFUNC] = { 1521 .type = MSR_FEATURE_WORD, 1522 .feat_names = { 1523 [0] = "vmx-eptp-switching", 1524 }, 1525 .msr = { 1526 .index = MSR_IA32_VMX_VMFUNC, 1527 } 1528 }, 1529 1530 [FEAT_14_0_ECX] = { 1531 .type = CPUID_FEATURE_WORD, 1532 .feat_names = { 1533 NULL, NULL, NULL, NULL, 1534 NULL, NULL, NULL, NULL, 1535 NULL, NULL, NULL, NULL, 1536 NULL, NULL, NULL, NULL, 1537 NULL, NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, NULL, NULL, 1540 NULL, NULL, NULL, "intel-pt-lip", 1541 }, 1542 .cpuid = { 1543 .eax = 0x14, 1544 .needs_ecx = true, .ecx = 0, 1545 .reg = R_ECX, 1546 }, 1547 .tcg_features = TCG_14_0_ECX_FEATURES, 1548 }, 1549 1550 [FEAT_SGX_12_0_EAX] = { 1551 .type = CPUID_FEATURE_WORD, 1552 .feat_names = { 1553 "sgx1", "sgx2", NULL, NULL, 1554 NULL, NULL, NULL, NULL, 1555 NULL, NULL, NULL, "sgx-edeccssa", 1556 NULL, NULL, NULL, NULL, 1557 NULL, NULL, NULL, NULL, 1558 NULL, NULL, NULL, NULL, 1559 NULL, NULL, NULL, NULL, 1560 NULL, NULL, NULL, NULL, 1561 }, 1562 .cpuid = { 1563 .eax = 0x12, 1564 .needs_ecx = true, .ecx = 0, 1565 .reg = R_EAX, 1566 }, 1567 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1568 }, 1569 1570 [FEAT_SGX_12_0_EBX] = { 1571 .type = CPUID_FEATURE_WORD, 1572 .feat_names = { 1573 "sgx-exinfo" , NULL, NULL, NULL, 1574 NULL, NULL, NULL, NULL, 1575 NULL, NULL, NULL, NULL, 1576 NULL, NULL, NULL, NULL, 1577 NULL, NULL, NULL, NULL, 1578 NULL, NULL, NULL, NULL, 1579 NULL, NULL, NULL, NULL, 1580 NULL, NULL, NULL, NULL, 1581 }, 1582 .cpuid = { 1583 .eax = 0x12, 1584 .needs_ecx = true, .ecx = 0, 1585 .reg = R_EBX, 1586 }, 1587 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1588 }, 1589 1590 [FEAT_SGX_12_1_EAX] = { 1591 .type = CPUID_FEATURE_WORD, 1592 .feat_names = { 1593 NULL, "sgx-debug", "sgx-mode64", NULL, 1594 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1595 NULL, NULL, "sgx-aex-notify", NULL, 1596 NULL, NULL, NULL, NULL, 1597 NULL, NULL, NULL, NULL, 1598 NULL, NULL, NULL, NULL, 1599 NULL, NULL, NULL, NULL, 1600 NULL, NULL, NULL, NULL, 1601 }, 1602 .cpuid = { 1603 .eax = 0x12, 1604 .needs_ecx = true, .ecx = 1, 1605 .reg = R_EAX, 1606 }, 1607 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1608 }, 1609 }; 1610 1611 typedef struct FeatureMask { 1612 FeatureWord index; 1613 uint64_t mask; 1614 } FeatureMask; 1615 1616 typedef struct FeatureDep { 1617 FeatureMask from, to; 1618 } FeatureDep; 1619 1620 static FeatureDep feature_dependencies[] = { 1621 { 1622 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1623 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1624 }, 1625 { 1626 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1627 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1628 }, 1629 { 1630 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1631 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1632 }, 1633 { 1634 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1635 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1636 }, 1637 { 1638 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1639 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1640 }, 1641 { 1642 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1643 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1644 }, 1645 { 1646 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1647 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1648 }, 1649 { 1650 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1651 .to = { FEAT_VMX_MISC, ~0ull }, 1652 }, 1653 { 1654 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1655 .to = { FEAT_VMX_BASIC, ~0ull }, 1656 }, 1657 { 1658 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1659 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1660 }, 1661 { 1662 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1663 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1664 }, 1665 { 1666 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1667 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1668 }, 1669 { 1670 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1671 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1672 }, 1673 { 1674 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1675 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1676 }, 1677 { 1678 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1679 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1680 }, 1681 { 1682 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1683 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1684 }, 1685 { 1686 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1687 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1688 }, 1689 { 1690 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1691 .to = { FEAT_14_0_ECX, ~0ull }, 1692 }, 1693 { 1694 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1695 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1696 }, 1697 { 1698 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1699 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1700 }, 1701 { 1702 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1703 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1704 }, 1705 { 1706 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1707 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1708 }, 1709 { 1710 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1711 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1712 }, 1713 { 1714 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1715 .to = { FEAT_SVM, ~0ull }, 1716 }, 1717 { 1718 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1719 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1720 }, 1721 { 1722 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1723 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1724 }, 1725 { 1726 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1727 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1728 }, 1729 { 1730 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1731 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1732 }, 1733 { 1734 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1735 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1736 }, 1737 { 1738 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1739 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1740 }, 1741 { 1742 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1743 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1744 }, 1745 { 1746 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1747 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1748 }, 1749 }; 1750 1751 typedef struct X86RegisterInfo32 { 1752 /* Name of register */ 1753 const char *name; 1754 /* QAPI enum value register */ 1755 X86CPURegister32 qapi_enum; 1756 } X86RegisterInfo32; 1757 1758 #define REGISTER(reg) \ 1759 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1760 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1761 REGISTER(EAX), 1762 REGISTER(ECX), 1763 REGISTER(EDX), 1764 REGISTER(EBX), 1765 REGISTER(ESP), 1766 REGISTER(EBP), 1767 REGISTER(ESI), 1768 REGISTER(EDI), 1769 }; 1770 #undef REGISTER 1771 1772 /* CPUID feature bits available in XSS */ 1773 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1774 1775 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1776 [XSTATE_FP_BIT] = { 1777 /* x87 FP state component is always enabled if XSAVE is supported */ 1778 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1779 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1780 }, 1781 [XSTATE_SSE_BIT] = { 1782 /* SSE state component is always enabled if XSAVE is supported */ 1783 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1784 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1785 }, 1786 [XSTATE_YMM_BIT] = 1787 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1788 .size = sizeof(XSaveAVX) }, 1789 [XSTATE_BNDREGS_BIT] = 1790 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1791 .size = sizeof(XSaveBNDREG) }, 1792 [XSTATE_BNDCSR_BIT] = 1793 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1794 .size = sizeof(XSaveBNDCSR) }, 1795 [XSTATE_OPMASK_BIT] = 1796 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1797 .size = sizeof(XSaveOpmask) }, 1798 [XSTATE_ZMM_Hi256_BIT] = 1799 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1800 .size = sizeof(XSaveZMM_Hi256) }, 1801 [XSTATE_Hi16_ZMM_BIT] = 1802 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1803 .size = sizeof(XSaveHi16_ZMM) }, 1804 [XSTATE_PKRU_BIT] = 1805 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1806 .size = sizeof(XSavePKRU) }, 1807 [XSTATE_ARCH_LBR_BIT] = { 1808 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1809 .offset = 0 /*supervisor mode component, offset = 0 */, 1810 .size = sizeof(XSavesArchLBR) }, 1811 [XSTATE_XTILE_CFG_BIT] = { 1812 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1813 .size = sizeof(XSaveXTILECFG), 1814 }, 1815 [XSTATE_XTILE_DATA_BIT] = { 1816 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1817 .size = sizeof(XSaveXTILEDATA) 1818 }, 1819 }; 1820 1821 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1822 { 1823 uint64_t ret = x86_ext_save_areas[0].size; 1824 const ExtSaveArea *esa; 1825 uint32_t offset = 0; 1826 int i; 1827 1828 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1829 esa = &x86_ext_save_areas[i]; 1830 if ((mask >> i) & 1) { 1831 offset = compacted ? ret : esa->offset; 1832 ret = MAX(ret, offset + esa->size); 1833 } 1834 } 1835 return ret; 1836 } 1837 1838 static inline bool accel_uses_host_cpuid(void) 1839 { 1840 return kvm_enabled() || hvf_enabled(); 1841 } 1842 1843 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1844 { 1845 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1846 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1847 } 1848 1849 /* Return name of 32-bit register, from a R_* constant */ 1850 static const char *get_register_name_32(unsigned int reg) 1851 { 1852 if (reg >= CPU_NB_REGS32) { 1853 return NULL; 1854 } 1855 return x86_reg_info_32[reg].name; 1856 } 1857 1858 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1859 { 1860 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1861 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1862 } 1863 1864 /* 1865 * Returns the set of feature flags that are supported and migratable by 1866 * QEMU, for a given FeatureWord. 1867 */ 1868 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1869 { 1870 FeatureWordInfo *wi = &feature_word_info[w]; 1871 CPUX86State *env = &cpu->env; 1872 uint64_t r = 0; 1873 int i; 1874 1875 for (i = 0; i < 64; i++) { 1876 uint64_t f = 1ULL << i; 1877 1878 /* If the feature name is known, it is implicitly considered migratable, 1879 * unless it is explicitly set in unmigratable_flags */ 1880 if ((wi->migratable_flags & f) || 1881 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1882 r |= f; 1883 } 1884 } 1885 1886 /* when tsc-khz is set explicitly, invtsc is migratable */ 1887 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1888 r |= CPUID_APM_INVTSC; 1889 } 1890 1891 return r; 1892 } 1893 1894 void host_cpuid(uint32_t function, uint32_t count, 1895 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1896 { 1897 uint32_t vec[4]; 1898 1899 #ifdef __x86_64__ 1900 asm volatile("cpuid" 1901 : "=a"(vec[0]), "=b"(vec[1]), 1902 "=c"(vec[2]), "=d"(vec[3]) 1903 : "0"(function), "c"(count) : "cc"); 1904 #elif defined(__i386__) 1905 asm volatile("pusha \n\t" 1906 "cpuid \n\t" 1907 "mov %%eax, 0(%2) \n\t" 1908 "mov %%ebx, 4(%2) \n\t" 1909 "mov %%ecx, 8(%2) \n\t" 1910 "mov %%edx, 12(%2) \n\t" 1911 "popa" 1912 : : "a"(function), "c"(count), "S"(vec) 1913 : "memory", "cc"); 1914 #else 1915 abort(); 1916 #endif 1917 1918 if (eax) 1919 *eax = vec[0]; 1920 if (ebx) 1921 *ebx = vec[1]; 1922 if (ecx) 1923 *ecx = vec[2]; 1924 if (edx) 1925 *edx = vec[3]; 1926 } 1927 1928 /* CPU class name definitions: */ 1929 1930 /* Return type name for a given CPU model name 1931 * Caller is responsible for freeing the returned string. 1932 */ 1933 static char *x86_cpu_type_name(const char *model_name) 1934 { 1935 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1936 } 1937 1938 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1939 { 1940 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1941 return object_class_by_name(typename); 1942 } 1943 1944 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1945 { 1946 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1947 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1948 return cpu_model_from_type(class_name); 1949 } 1950 1951 typedef struct X86CPUVersionDefinition { 1952 X86CPUVersion version; 1953 const char *alias; 1954 const char *note; 1955 PropValue *props; 1956 const CPUCaches *const cache_info; 1957 } X86CPUVersionDefinition; 1958 1959 /* Base definition for a CPU model */ 1960 typedef struct X86CPUDefinition { 1961 const char *name; 1962 uint32_t level; 1963 uint32_t xlevel; 1964 /* vendor is zero-terminated, 12 character ASCII string */ 1965 char vendor[CPUID_VENDOR_SZ + 1]; 1966 int family; 1967 int model; 1968 int stepping; 1969 FeatureWordArray features; 1970 const char *model_id; 1971 const CPUCaches *const cache_info; 1972 /* 1973 * Definitions for alternative versions of CPU model. 1974 * List is terminated by item with version == 0. 1975 * If NULL, version 1 will be registered automatically. 1976 */ 1977 const X86CPUVersionDefinition *versions; 1978 const char *deprecation_note; 1979 } X86CPUDefinition; 1980 1981 /* Reference to a specific CPU model version */ 1982 struct X86CPUModel { 1983 /* Base CPU definition */ 1984 const X86CPUDefinition *cpudef; 1985 /* CPU model version */ 1986 X86CPUVersion version; 1987 const char *note; 1988 /* 1989 * If true, this is an alias CPU model. 1990 * This matters only for "-cpu help" and query-cpu-definitions 1991 */ 1992 bool is_alias; 1993 }; 1994 1995 /* Get full model name for CPU version */ 1996 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1997 X86CPUVersion version) 1998 { 1999 assert(version > 0); 2000 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2001 } 2002 2003 static const X86CPUVersionDefinition * 2004 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2005 { 2006 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2007 static const X86CPUVersionDefinition default_version_list[] = { 2008 { 1 }, 2009 { /* end of list */ } 2010 }; 2011 2012 return def->versions ?: default_version_list; 2013 } 2014 2015 static const CPUCaches epyc_cache_info = { 2016 .l1d_cache = &(CPUCacheInfo) { 2017 .type = DATA_CACHE, 2018 .level = 1, 2019 .size = 32 * KiB, 2020 .line_size = 64, 2021 .associativity = 8, 2022 .partitions = 1, 2023 .sets = 64, 2024 .lines_per_tag = 1, 2025 .self_init = 1, 2026 .no_invd_sharing = true, 2027 .share_level = CPU_TOPO_LEVEL_CORE, 2028 }, 2029 .l1i_cache = &(CPUCacheInfo) { 2030 .type = INSTRUCTION_CACHE, 2031 .level = 1, 2032 .size = 64 * KiB, 2033 .line_size = 64, 2034 .associativity = 4, 2035 .partitions = 1, 2036 .sets = 256, 2037 .lines_per_tag = 1, 2038 .self_init = 1, 2039 .no_invd_sharing = true, 2040 .share_level = CPU_TOPO_LEVEL_CORE, 2041 }, 2042 .l2_cache = &(CPUCacheInfo) { 2043 .type = UNIFIED_CACHE, 2044 .level = 2, 2045 .size = 512 * KiB, 2046 .line_size = 64, 2047 .associativity = 8, 2048 .partitions = 1, 2049 .sets = 1024, 2050 .lines_per_tag = 1, 2051 .share_level = CPU_TOPO_LEVEL_CORE, 2052 }, 2053 .l3_cache = &(CPUCacheInfo) { 2054 .type = UNIFIED_CACHE, 2055 .level = 3, 2056 .size = 8 * MiB, 2057 .line_size = 64, 2058 .associativity = 16, 2059 .partitions = 1, 2060 .sets = 8192, 2061 .lines_per_tag = 1, 2062 .self_init = true, 2063 .inclusive = true, 2064 .complex_indexing = true, 2065 .share_level = CPU_TOPO_LEVEL_DIE, 2066 }, 2067 }; 2068 2069 static CPUCaches epyc_v4_cache_info = { 2070 .l1d_cache = &(CPUCacheInfo) { 2071 .type = DATA_CACHE, 2072 .level = 1, 2073 .size = 32 * KiB, 2074 .line_size = 64, 2075 .associativity = 8, 2076 .partitions = 1, 2077 .sets = 64, 2078 .lines_per_tag = 1, 2079 .self_init = 1, 2080 .no_invd_sharing = true, 2081 .share_level = CPU_TOPO_LEVEL_CORE, 2082 }, 2083 .l1i_cache = &(CPUCacheInfo) { 2084 .type = INSTRUCTION_CACHE, 2085 .level = 1, 2086 .size = 64 * KiB, 2087 .line_size = 64, 2088 .associativity = 4, 2089 .partitions = 1, 2090 .sets = 256, 2091 .lines_per_tag = 1, 2092 .self_init = 1, 2093 .no_invd_sharing = true, 2094 .share_level = CPU_TOPO_LEVEL_CORE, 2095 }, 2096 .l2_cache = &(CPUCacheInfo) { 2097 .type = UNIFIED_CACHE, 2098 .level = 2, 2099 .size = 512 * KiB, 2100 .line_size = 64, 2101 .associativity = 8, 2102 .partitions = 1, 2103 .sets = 1024, 2104 .lines_per_tag = 1, 2105 .share_level = CPU_TOPO_LEVEL_CORE, 2106 }, 2107 .l3_cache = &(CPUCacheInfo) { 2108 .type = UNIFIED_CACHE, 2109 .level = 3, 2110 .size = 8 * MiB, 2111 .line_size = 64, 2112 .associativity = 16, 2113 .partitions = 1, 2114 .sets = 8192, 2115 .lines_per_tag = 1, 2116 .self_init = true, 2117 .inclusive = true, 2118 .complex_indexing = false, 2119 .share_level = CPU_TOPO_LEVEL_DIE, 2120 }, 2121 }; 2122 2123 static const CPUCaches epyc_rome_cache_info = { 2124 .l1d_cache = &(CPUCacheInfo) { 2125 .type = DATA_CACHE, 2126 .level = 1, 2127 .size = 32 * KiB, 2128 .line_size = 64, 2129 .associativity = 8, 2130 .partitions = 1, 2131 .sets = 64, 2132 .lines_per_tag = 1, 2133 .self_init = 1, 2134 .no_invd_sharing = true, 2135 .share_level = CPU_TOPO_LEVEL_CORE, 2136 }, 2137 .l1i_cache = &(CPUCacheInfo) { 2138 .type = INSTRUCTION_CACHE, 2139 .level = 1, 2140 .size = 32 * KiB, 2141 .line_size = 64, 2142 .associativity = 8, 2143 .partitions = 1, 2144 .sets = 64, 2145 .lines_per_tag = 1, 2146 .self_init = 1, 2147 .no_invd_sharing = true, 2148 .share_level = CPU_TOPO_LEVEL_CORE, 2149 }, 2150 .l2_cache = &(CPUCacheInfo) { 2151 .type = UNIFIED_CACHE, 2152 .level = 2, 2153 .size = 512 * KiB, 2154 .line_size = 64, 2155 .associativity = 8, 2156 .partitions = 1, 2157 .sets = 1024, 2158 .lines_per_tag = 1, 2159 .share_level = CPU_TOPO_LEVEL_CORE, 2160 }, 2161 .l3_cache = &(CPUCacheInfo) { 2162 .type = UNIFIED_CACHE, 2163 .level = 3, 2164 .size = 16 * MiB, 2165 .line_size = 64, 2166 .associativity = 16, 2167 .partitions = 1, 2168 .sets = 16384, 2169 .lines_per_tag = 1, 2170 .self_init = true, 2171 .inclusive = true, 2172 .complex_indexing = true, 2173 .share_level = CPU_TOPO_LEVEL_DIE, 2174 }, 2175 }; 2176 2177 static const CPUCaches epyc_rome_v3_cache_info = { 2178 .l1d_cache = &(CPUCacheInfo) { 2179 .type = DATA_CACHE, 2180 .level = 1, 2181 .size = 32 * KiB, 2182 .line_size = 64, 2183 .associativity = 8, 2184 .partitions = 1, 2185 .sets = 64, 2186 .lines_per_tag = 1, 2187 .self_init = 1, 2188 .no_invd_sharing = true, 2189 .share_level = CPU_TOPO_LEVEL_CORE, 2190 }, 2191 .l1i_cache = &(CPUCacheInfo) { 2192 .type = INSTRUCTION_CACHE, 2193 .level = 1, 2194 .size = 32 * KiB, 2195 .line_size = 64, 2196 .associativity = 8, 2197 .partitions = 1, 2198 .sets = 64, 2199 .lines_per_tag = 1, 2200 .self_init = 1, 2201 .no_invd_sharing = true, 2202 .share_level = CPU_TOPO_LEVEL_CORE, 2203 }, 2204 .l2_cache = &(CPUCacheInfo) { 2205 .type = UNIFIED_CACHE, 2206 .level = 2, 2207 .size = 512 * KiB, 2208 .line_size = 64, 2209 .associativity = 8, 2210 .partitions = 1, 2211 .sets = 1024, 2212 .lines_per_tag = 1, 2213 .share_level = CPU_TOPO_LEVEL_CORE, 2214 }, 2215 .l3_cache = &(CPUCacheInfo) { 2216 .type = UNIFIED_CACHE, 2217 .level = 3, 2218 .size = 16 * MiB, 2219 .line_size = 64, 2220 .associativity = 16, 2221 .partitions = 1, 2222 .sets = 16384, 2223 .lines_per_tag = 1, 2224 .self_init = true, 2225 .inclusive = true, 2226 .complex_indexing = false, 2227 .share_level = CPU_TOPO_LEVEL_DIE, 2228 }, 2229 }; 2230 2231 static const CPUCaches epyc_milan_cache_info = { 2232 .l1d_cache = &(CPUCacheInfo) { 2233 .type = DATA_CACHE, 2234 .level = 1, 2235 .size = 32 * KiB, 2236 .line_size = 64, 2237 .associativity = 8, 2238 .partitions = 1, 2239 .sets = 64, 2240 .lines_per_tag = 1, 2241 .self_init = 1, 2242 .no_invd_sharing = true, 2243 .share_level = CPU_TOPO_LEVEL_CORE, 2244 }, 2245 .l1i_cache = &(CPUCacheInfo) { 2246 .type = INSTRUCTION_CACHE, 2247 .level = 1, 2248 .size = 32 * KiB, 2249 .line_size = 64, 2250 .associativity = 8, 2251 .partitions = 1, 2252 .sets = 64, 2253 .lines_per_tag = 1, 2254 .self_init = 1, 2255 .no_invd_sharing = true, 2256 .share_level = CPU_TOPO_LEVEL_CORE, 2257 }, 2258 .l2_cache = &(CPUCacheInfo) { 2259 .type = UNIFIED_CACHE, 2260 .level = 2, 2261 .size = 512 * KiB, 2262 .line_size = 64, 2263 .associativity = 8, 2264 .partitions = 1, 2265 .sets = 1024, 2266 .lines_per_tag = 1, 2267 .share_level = CPU_TOPO_LEVEL_CORE, 2268 }, 2269 .l3_cache = &(CPUCacheInfo) { 2270 .type = UNIFIED_CACHE, 2271 .level = 3, 2272 .size = 32 * MiB, 2273 .line_size = 64, 2274 .associativity = 16, 2275 .partitions = 1, 2276 .sets = 32768, 2277 .lines_per_tag = 1, 2278 .self_init = true, 2279 .inclusive = true, 2280 .complex_indexing = true, 2281 .share_level = CPU_TOPO_LEVEL_DIE, 2282 }, 2283 }; 2284 2285 static const CPUCaches epyc_milan_v2_cache_info = { 2286 .l1d_cache = &(CPUCacheInfo) { 2287 .type = DATA_CACHE, 2288 .level = 1, 2289 .size = 32 * KiB, 2290 .line_size = 64, 2291 .associativity = 8, 2292 .partitions = 1, 2293 .sets = 64, 2294 .lines_per_tag = 1, 2295 .self_init = 1, 2296 .no_invd_sharing = true, 2297 .share_level = CPU_TOPO_LEVEL_CORE, 2298 }, 2299 .l1i_cache = &(CPUCacheInfo) { 2300 .type = INSTRUCTION_CACHE, 2301 .level = 1, 2302 .size = 32 * KiB, 2303 .line_size = 64, 2304 .associativity = 8, 2305 .partitions = 1, 2306 .sets = 64, 2307 .lines_per_tag = 1, 2308 .self_init = 1, 2309 .no_invd_sharing = true, 2310 .share_level = CPU_TOPO_LEVEL_CORE, 2311 }, 2312 .l2_cache = &(CPUCacheInfo) { 2313 .type = UNIFIED_CACHE, 2314 .level = 2, 2315 .size = 512 * KiB, 2316 .line_size = 64, 2317 .associativity = 8, 2318 .partitions = 1, 2319 .sets = 1024, 2320 .lines_per_tag = 1, 2321 .share_level = CPU_TOPO_LEVEL_CORE, 2322 }, 2323 .l3_cache = &(CPUCacheInfo) { 2324 .type = UNIFIED_CACHE, 2325 .level = 3, 2326 .size = 32 * MiB, 2327 .line_size = 64, 2328 .associativity = 16, 2329 .partitions = 1, 2330 .sets = 32768, 2331 .lines_per_tag = 1, 2332 .self_init = true, 2333 .inclusive = true, 2334 .complex_indexing = false, 2335 .share_level = CPU_TOPO_LEVEL_DIE, 2336 }, 2337 }; 2338 2339 static const CPUCaches epyc_genoa_cache_info = { 2340 .l1d_cache = &(CPUCacheInfo) { 2341 .type = DATA_CACHE, 2342 .level = 1, 2343 .size = 32 * KiB, 2344 .line_size = 64, 2345 .associativity = 8, 2346 .partitions = 1, 2347 .sets = 64, 2348 .lines_per_tag = 1, 2349 .self_init = 1, 2350 .no_invd_sharing = true, 2351 .share_level = CPU_TOPO_LEVEL_CORE, 2352 }, 2353 .l1i_cache = &(CPUCacheInfo) { 2354 .type = INSTRUCTION_CACHE, 2355 .level = 1, 2356 .size = 32 * KiB, 2357 .line_size = 64, 2358 .associativity = 8, 2359 .partitions = 1, 2360 .sets = 64, 2361 .lines_per_tag = 1, 2362 .self_init = 1, 2363 .no_invd_sharing = true, 2364 .share_level = CPU_TOPO_LEVEL_CORE, 2365 }, 2366 .l2_cache = &(CPUCacheInfo) { 2367 .type = UNIFIED_CACHE, 2368 .level = 2, 2369 .size = 1 * MiB, 2370 .line_size = 64, 2371 .associativity = 8, 2372 .partitions = 1, 2373 .sets = 2048, 2374 .lines_per_tag = 1, 2375 .share_level = CPU_TOPO_LEVEL_CORE, 2376 }, 2377 .l3_cache = &(CPUCacheInfo) { 2378 .type = UNIFIED_CACHE, 2379 .level = 3, 2380 .size = 32 * MiB, 2381 .line_size = 64, 2382 .associativity = 16, 2383 .partitions = 1, 2384 .sets = 32768, 2385 .lines_per_tag = 1, 2386 .self_init = true, 2387 .inclusive = true, 2388 .complex_indexing = false, 2389 .share_level = CPU_TOPO_LEVEL_DIE, 2390 }, 2391 }; 2392 2393 /* The following VMX features are not supported by KVM and are left out in the 2394 * CPU definitions: 2395 * 2396 * Dual-monitor support (all processors) 2397 * Entry to SMM 2398 * Deactivate dual-monitor treatment 2399 * Number of CR3-target values 2400 * Shutdown activity state 2401 * Wait-for-SIPI activity state 2402 * PAUSE-loop exiting (Westmere and newer) 2403 * EPT-violation #VE (Broadwell and newer) 2404 * Inject event with insn length=0 (Skylake and newer) 2405 * Conceal non-root operation from PT 2406 * Conceal VM exits from PT 2407 * Conceal VM entries from PT 2408 * Enable ENCLS exiting 2409 * Mode-based execute control (XS/XU) 2410 * TSC scaling (Skylake Server and newer) 2411 * GPA translation for PT (IceLake and newer) 2412 * User wait and pause 2413 * ENCLV exiting 2414 * Load IA32_RTIT_CTL 2415 * Clear IA32_RTIT_CTL 2416 * Advanced VM-exit information for EPT violations 2417 * Sub-page write permissions 2418 * PT in VMX operation 2419 */ 2420 2421 static const X86CPUDefinition builtin_x86_defs[] = { 2422 { 2423 .name = "qemu64", 2424 .level = 0xd, 2425 .vendor = CPUID_VENDOR_AMD, 2426 .family = 15, 2427 .model = 107, 2428 .stepping = 1, 2429 .features[FEAT_1_EDX] = 2430 PPRO_FEATURES | 2431 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2432 CPUID_PSE36, 2433 .features[FEAT_1_ECX] = 2434 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2435 .features[FEAT_8000_0001_EDX] = 2436 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2437 .features[FEAT_8000_0001_ECX] = 2438 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2439 .xlevel = 0x8000000A, 2440 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2441 }, 2442 { 2443 .name = "phenom", 2444 .level = 5, 2445 .vendor = CPUID_VENDOR_AMD, 2446 .family = 16, 2447 .model = 2, 2448 .stepping = 3, 2449 /* Missing: CPUID_HT */ 2450 .features[FEAT_1_EDX] = 2451 PPRO_FEATURES | 2452 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2453 CPUID_PSE36 | CPUID_VME, 2454 .features[FEAT_1_ECX] = 2455 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2456 CPUID_EXT_POPCNT, 2457 .features[FEAT_8000_0001_EDX] = 2458 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2459 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2460 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2461 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2462 CPUID_EXT3_CR8LEG, 2463 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2464 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2465 .features[FEAT_8000_0001_ECX] = 2466 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2467 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2468 /* Missing: CPUID_SVM_LBRV */ 2469 .features[FEAT_SVM] = 2470 CPUID_SVM_NPT, 2471 .xlevel = 0x8000001A, 2472 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2473 }, 2474 { 2475 .name = "core2duo", 2476 .level = 10, 2477 .vendor = CPUID_VENDOR_INTEL, 2478 .family = 6, 2479 .model = 15, 2480 .stepping = 11, 2481 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2482 .features[FEAT_1_EDX] = 2483 PPRO_FEATURES | 2484 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2485 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2486 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2487 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2488 .features[FEAT_1_ECX] = 2489 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2490 CPUID_EXT_CX16, 2491 .features[FEAT_8000_0001_EDX] = 2492 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2493 .features[FEAT_8000_0001_ECX] = 2494 CPUID_EXT3_LAHF_LM, 2495 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2496 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2497 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2498 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2499 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2500 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2501 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2502 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2503 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2504 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2505 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2506 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2507 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2508 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2509 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2510 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2511 .features[FEAT_VMX_SECONDARY_CTLS] = 2512 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2513 .xlevel = 0x80000008, 2514 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2515 }, 2516 { 2517 .name = "kvm64", 2518 .level = 0xd, 2519 .vendor = CPUID_VENDOR_INTEL, 2520 .family = 15, 2521 .model = 6, 2522 .stepping = 1, 2523 /* Missing: CPUID_HT */ 2524 .features[FEAT_1_EDX] = 2525 PPRO_FEATURES | CPUID_VME | 2526 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2527 CPUID_PSE36, 2528 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2529 .features[FEAT_1_ECX] = 2530 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2531 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2532 .features[FEAT_8000_0001_EDX] = 2533 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2534 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2535 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2536 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2537 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2538 .features[FEAT_8000_0001_ECX] = 2539 0, 2540 /* VMX features from Cedar Mill/Prescott */ 2541 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2542 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2543 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2544 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2545 VMX_PIN_BASED_NMI_EXITING, 2546 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2547 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2548 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2549 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2550 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2551 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2552 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2553 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2554 .xlevel = 0x80000008, 2555 .model_id = "Common KVM processor" 2556 }, 2557 { 2558 .name = "qemu32", 2559 .level = 4, 2560 .vendor = CPUID_VENDOR_INTEL, 2561 .family = 6, 2562 .model = 6, 2563 .stepping = 3, 2564 .features[FEAT_1_EDX] = 2565 PPRO_FEATURES, 2566 .features[FEAT_1_ECX] = 2567 CPUID_EXT_SSE3, 2568 .xlevel = 0x80000004, 2569 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2570 }, 2571 { 2572 .name = "kvm32", 2573 .level = 5, 2574 .vendor = CPUID_VENDOR_INTEL, 2575 .family = 15, 2576 .model = 6, 2577 .stepping = 1, 2578 .features[FEAT_1_EDX] = 2579 PPRO_FEATURES | CPUID_VME | 2580 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2581 .features[FEAT_1_ECX] = 2582 CPUID_EXT_SSE3, 2583 .features[FEAT_8000_0001_ECX] = 2584 0, 2585 /* VMX features from Yonah */ 2586 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2587 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2588 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2589 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2590 VMX_PIN_BASED_NMI_EXITING, 2591 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2592 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2593 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2594 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2595 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2596 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2597 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2598 .xlevel = 0x80000008, 2599 .model_id = "Common 32-bit KVM processor" 2600 }, 2601 { 2602 .name = "coreduo", 2603 .level = 10, 2604 .vendor = CPUID_VENDOR_INTEL, 2605 .family = 6, 2606 .model = 14, 2607 .stepping = 8, 2608 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2609 .features[FEAT_1_EDX] = 2610 PPRO_FEATURES | CPUID_VME | 2611 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2612 CPUID_SS, 2613 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2614 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2615 .features[FEAT_1_ECX] = 2616 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2617 .features[FEAT_8000_0001_EDX] = 2618 CPUID_EXT2_NX, 2619 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2620 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2621 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2622 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2623 VMX_PIN_BASED_NMI_EXITING, 2624 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2625 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2626 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2627 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2628 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2629 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2630 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2631 .xlevel = 0x80000008, 2632 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2633 }, 2634 { 2635 .name = "486", 2636 .level = 1, 2637 .vendor = CPUID_VENDOR_INTEL, 2638 .family = 4, 2639 .model = 8, 2640 .stepping = 0, 2641 .features[FEAT_1_EDX] = 2642 I486_FEATURES, 2643 .xlevel = 0, 2644 .model_id = "", 2645 }, 2646 { 2647 .name = "pentium", 2648 .level = 1, 2649 .vendor = CPUID_VENDOR_INTEL, 2650 .family = 5, 2651 .model = 4, 2652 .stepping = 3, 2653 .features[FEAT_1_EDX] = 2654 PENTIUM_FEATURES, 2655 .xlevel = 0, 2656 .model_id = "", 2657 }, 2658 { 2659 .name = "pentium2", 2660 .level = 2, 2661 .vendor = CPUID_VENDOR_INTEL, 2662 .family = 6, 2663 .model = 5, 2664 .stepping = 2, 2665 .features[FEAT_1_EDX] = 2666 PENTIUM2_FEATURES, 2667 .xlevel = 0, 2668 .model_id = "", 2669 }, 2670 { 2671 .name = "pentium3", 2672 .level = 3, 2673 .vendor = CPUID_VENDOR_INTEL, 2674 .family = 6, 2675 .model = 7, 2676 .stepping = 3, 2677 .features[FEAT_1_EDX] = 2678 PENTIUM3_FEATURES, 2679 .xlevel = 0, 2680 .model_id = "", 2681 }, 2682 { 2683 .name = "athlon", 2684 .level = 2, 2685 .vendor = CPUID_VENDOR_AMD, 2686 .family = 6, 2687 .model = 2, 2688 .stepping = 3, 2689 .features[FEAT_1_EDX] = 2690 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2691 CPUID_MCA, 2692 .features[FEAT_8000_0001_EDX] = 2693 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2694 .xlevel = 0x80000008, 2695 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2696 }, 2697 { 2698 .name = "n270", 2699 .level = 10, 2700 .vendor = CPUID_VENDOR_INTEL, 2701 .family = 6, 2702 .model = 28, 2703 .stepping = 2, 2704 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2705 .features[FEAT_1_EDX] = 2706 PPRO_FEATURES | 2707 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2708 CPUID_ACPI | CPUID_SS, 2709 /* Some CPUs got no CPUID_SEP */ 2710 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2711 * CPUID_EXT_XTPR */ 2712 .features[FEAT_1_ECX] = 2713 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2714 CPUID_EXT_MOVBE, 2715 .features[FEAT_8000_0001_EDX] = 2716 CPUID_EXT2_NX, 2717 .features[FEAT_8000_0001_ECX] = 2718 CPUID_EXT3_LAHF_LM, 2719 .xlevel = 0x80000008, 2720 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2721 }, 2722 { 2723 .name = "Conroe", 2724 .level = 10, 2725 .vendor = CPUID_VENDOR_INTEL, 2726 .family = 6, 2727 .model = 15, 2728 .stepping = 3, 2729 .features[FEAT_1_EDX] = 2730 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2731 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2732 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2733 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2734 CPUID_DE | CPUID_FP87, 2735 .features[FEAT_1_ECX] = 2736 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2737 .features[FEAT_8000_0001_EDX] = 2738 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2739 .features[FEAT_8000_0001_ECX] = 2740 CPUID_EXT3_LAHF_LM, 2741 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2742 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2743 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2744 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2745 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2746 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2747 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2748 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2749 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2750 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2751 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2752 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2753 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2754 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2755 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2756 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2757 .features[FEAT_VMX_SECONDARY_CTLS] = 2758 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2759 .xlevel = 0x80000008, 2760 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2761 }, 2762 { 2763 .name = "Penryn", 2764 .level = 10, 2765 .vendor = CPUID_VENDOR_INTEL, 2766 .family = 6, 2767 .model = 23, 2768 .stepping = 3, 2769 .features[FEAT_1_EDX] = 2770 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2771 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2772 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2773 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2774 CPUID_DE | CPUID_FP87, 2775 .features[FEAT_1_ECX] = 2776 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2777 CPUID_EXT_SSE3, 2778 .features[FEAT_8000_0001_EDX] = 2779 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2780 .features[FEAT_8000_0001_ECX] = 2781 CPUID_EXT3_LAHF_LM, 2782 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2783 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2784 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2785 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2786 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2787 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2788 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2789 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2790 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2791 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2792 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2793 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2794 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2795 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2796 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2797 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2798 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2799 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2800 .features[FEAT_VMX_SECONDARY_CTLS] = 2801 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2802 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2803 .xlevel = 0x80000008, 2804 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2805 }, 2806 { 2807 .name = "Nehalem", 2808 .level = 11, 2809 .vendor = CPUID_VENDOR_INTEL, 2810 .family = 6, 2811 .model = 26, 2812 .stepping = 3, 2813 .features[FEAT_1_EDX] = 2814 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2815 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2816 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2817 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2818 CPUID_DE | CPUID_FP87, 2819 .features[FEAT_1_ECX] = 2820 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2821 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2822 .features[FEAT_8000_0001_EDX] = 2823 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2824 .features[FEAT_8000_0001_ECX] = 2825 CPUID_EXT3_LAHF_LM, 2826 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2827 MSR_VMX_BASIC_TRUE_CTLS, 2828 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2829 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2830 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2831 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2832 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2833 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2834 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2835 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2836 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2837 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2838 .features[FEAT_VMX_EXIT_CTLS] = 2839 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2840 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2841 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2842 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2843 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2844 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2845 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2846 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2847 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2848 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2849 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2850 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2851 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2852 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2853 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2854 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2855 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2856 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2857 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2858 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2859 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2860 .features[FEAT_VMX_SECONDARY_CTLS] = 2861 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2862 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2863 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2864 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2865 VMX_SECONDARY_EXEC_ENABLE_VPID, 2866 .xlevel = 0x80000008, 2867 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2868 .versions = (X86CPUVersionDefinition[]) { 2869 { .version = 1 }, 2870 { 2871 .version = 2, 2872 .alias = "Nehalem-IBRS", 2873 .props = (PropValue[]) { 2874 { "spec-ctrl", "on" }, 2875 { "model-id", 2876 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2877 { /* end of list */ } 2878 } 2879 }, 2880 { /* end of list */ } 2881 } 2882 }, 2883 { 2884 .name = "Westmere", 2885 .level = 11, 2886 .vendor = CPUID_VENDOR_INTEL, 2887 .family = 6, 2888 .model = 44, 2889 .stepping = 1, 2890 .features[FEAT_1_EDX] = 2891 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2892 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2893 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2894 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2895 CPUID_DE | CPUID_FP87, 2896 .features[FEAT_1_ECX] = 2897 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2898 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2899 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2900 .features[FEAT_8000_0001_EDX] = 2901 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2902 .features[FEAT_8000_0001_ECX] = 2903 CPUID_EXT3_LAHF_LM, 2904 .features[FEAT_6_EAX] = 2905 CPUID_6_EAX_ARAT, 2906 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2907 MSR_VMX_BASIC_TRUE_CTLS, 2908 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2909 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2910 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2911 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2912 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2913 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2914 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2915 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2916 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2917 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2918 .features[FEAT_VMX_EXIT_CTLS] = 2919 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2920 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2921 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2922 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2923 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2924 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2925 MSR_VMX_MISC_STORE_LMA, 2926 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2927 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2928 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2929 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2930 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2931 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2932 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2933 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2934 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2935 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2936 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2937 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2938 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2939 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2940 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2941 .features[FEAT_VMX_SECONDARY_CTLS] = 2942 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2943 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2944 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2945 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2946 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2947 .xlevel = 0x80000008, 2948 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2949 .versions = (X86CPUVersionDefinition[]) { 2950 { .version = 1 }, 2951 { 2952 .version = 2, 2953 .alias = "Westmere-IBRS", 2954 .props = (PropValue[]) { 2955 { "spec-ctrl", "on" }, 2956 { "model-id", 2957 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2958 { /* end of list */ } 2959 } 2960 }, 2961 { /* end of list */ } 2962 } 2963 }, 2964 { 2965 .name = "SandyBridge", 2966 .level = 0xd, 2967 .vendor = CPUID_VENDOR_INTEL, 2968 .family = 6, 2969 .model = 42, 2970 .stepping = 1, 2971 .features[FEAT_1_EDX] = 2972 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2973 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2974 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2975 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2976 CPUID_DE | CPUID_FP87, 2977 .features[FEAT_1_ECX] = 2978 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2979 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2980 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2981 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2982 CPUID_EXT_SSE3, 2983 .features[FEAT_8000_0001_EDX] = 2984 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2985 CPUID_EXT2_SYSCALL, 2986 .features[FEAT_8000_0001_ECX] = 2987 CPUID_EXT3_LAHF_LM, 2988 .features[FEAT_XSAVE] = 2989 CPUID_XSAVE_XSAVEOPT, 2990 .features[FEAT_6_EAX] = 2991 CPUID_6_EAX_ARAT, 2992 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2993 MSR_VMX_BASIC_TRUE_CTLS, 2994 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2995 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2996 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2997 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2998 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2999 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3000 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3001 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3002 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3003 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3004 .features[FEAT_VMX_EXIT_CTLS] = 3005 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3006 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3007 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3008 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3009 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3010 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3011 MSR_VMX_MISC_STORE_LMA, 3012 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3013 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3014 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3015 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3016 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3017 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3018 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3019 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3020 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3021 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3022 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3023 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3024 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3025 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3026 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3027 .features[FEAT_VMX_SECONDARY_CTLS] = 3028 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3029 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3030 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3031 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3032 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3033 .xlevel = 0x80000008, 3034 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3035 .versions = (X86CPUVersionDefinition[]) { 3036 { .version = 1 }, 3037 { 3038 .version = 2, 3039 .alias = "SandyBridge-IBRS", 3040 .props = (PropValue[]) { 3041 { "spec-ctrl", "on" }, 3042 { "model-id", 3043 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3044 { /* end of list */ } 3045 } 3046 }, 3047 { /* end of list */ } 3048 } 3049 }, 3050 { 3051 .name = "IvyBridge", 3052 .level = 0xd, 3053 .vendor = CPUID_VENDOR_INTEL, 3054 .family = 6, 3055 .model = 58, 3056 .stepping = 9, 3057 .features[FEAT_1_EDX] = 3058 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3059 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3060 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3061 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3062 CPUID_DE | CPUID_FP87, 3063 .features[FEAT_1_ECX] = 3064 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3065 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3066 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3067 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3068 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3069 .features[FEAT_7_0_EBX] = 3070 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3071 CPUID_7_0_EBX_ERMS, 3072 .features[FEAT_8000_0001_EDX] = 3073 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3074 CPUID_EXT2_SYSCALL, 3075 .features[FEAT_8000_0001_ECX] = 3076 CPUID_EXT3_LAHF_LM, 3077 .features[FEAT_XSAVE] = 3078 CPUID_XSAVE_XSAVEOPT, 3079 .features[FEAT_6_EAX] = 3080 CPUID_6_EAX_ARAT, 3081 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3082 MSR_VMX_BASIC_TRUE_CTLS, 3083 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3084 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3085 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3086 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3087 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3088 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3089 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3090 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3091 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3092 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3093 .features[FEAT_VMX_EXIT_CTLS] = 3094 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3095 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3096 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3097 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3098 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3099 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3100 MSR_VMX_MISC_STORE_LMA, 3101 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3102 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3103 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3104 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3105 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3106 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3107 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3108 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3109 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3110 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3111 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3112 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3113 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3114 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3115 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3116 .features[FEAT_VMX_SECONDARY_CTLS] = 3117 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3118 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3119 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3120 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3121 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3122 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3123 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3124 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3125 .xlevel = 0x80000008, 3126 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3127 .versions = (X86CPUVersionDefinition[]) { 3128 { .version = 1 }, 3129 { 3130 .version = 2, 3131 .alias = "IvyBridge-IBRS", 3132 .props = (PropValue[]) { 3133 { "spec-ctrl", "on" }, 3134 { "model-id", 3135 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3136 { /* end of list */ } 3137 } 3138 }, 3139 { /* end of list */ } 3140 } 3141 }, 3142 { 3143 .name = "Haswell", 3144 .level = 0xd, 3145 .vendor = CPUID_VENDOR_INTEL, 3146 .family = 6, 3147 .model = 60, 3148 .stepping = 4, 3149 .features[FEAT_1_EDX] = 3150 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3151 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3152 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3153 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3154 CPUID_DE | CPUID_FP87, 3155 .features[FEAT_1_ECX] = 3156 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3157 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3158 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3159 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3160 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3161 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3162 .features[FEAT_8000_0001_EDX] = 3163 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3164 CPUID_EXT2_SYSCALL, 3165 .features[FEAT_8000_0001_ECX] = 3166 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3167 .features[FEAT_7_0_EBX] = 3168 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3169 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3170 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3171 CPUID_7_0_EBX_RTM, 3172 .features[FEAT_XSAVE] = 3173 CPUID_XSAVE_XSAVEOPT, 3174 .features[FEAT_6_EAX] = 3175 CPUID_6_EAX_ARAT, 3176 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3177 MSR_VMX_BASIC_TRUE_CTLS, 3178 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3179 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3180 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3181 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3182 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3183 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3184 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3185 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3186 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3187 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3188 .features[FEAT_VMX_EXIT_CTLS] = 3189 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3190 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3191 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3192 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3193 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3194 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3195 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3196 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3197 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3198 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3199 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3200 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3201 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3202 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3203 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3204 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3205 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3206 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3207 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3208 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3209 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3210 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3211 .features[FEAT_VMX_SECONDARY_CTLS] = 3212 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3213 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3214 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3215 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3216 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3217 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3218 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3219 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3220 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3221 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3222 .xlevel = 0x80000008, 3223 .model_id = "Intel Core Processor (Haswell)", 3224 .versions = (X86CPUVersionDefinition[]) { 3225 { .version = 1 }, 3226 { 3227 .version = 2, 3228 .alias = "Haswell-noTSX", 3229 .props = (PropValue[]) { 3230 { "hle", "off" }, 3231 { "rtm", "off" }, 3232 { "stepping", "1" }, 3233 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3234 { /* end of list */ } 3235 }, 3236 }, 3237 { 3238 .version = 3, 3239 .alias = "Haswell-IBRS", 3240 .props = (PropValue[]) { 3241 /* Restore TSX features removed by -v2 above */ 3242 { "hle", "on" }, 3243 { "rtm", "on" }, 3244 /* 3245 * Haswell and Haswell-IBRS had stepping=4 in 3246 * QEMU 4.0 and older 3247 */ 3248 { "stepping", "4" }, 3249 { "spec-ctrl", "on" }, 3250 { "model-id", 3251 "Intel Core Processor (Haswell, IBRS)" }, 3252 { /* end of list */ } 3253 } 3254 }, 3255 { 3256 .version = 4, 3257 .alias = "Haswell-noTSX-IBRS", 3258 .props = (PropValue[]) { 3259 { "hle", "off" }, 3260 { "rtm", "off" }, 3261 /* spec-ctrl was already enabled by -v3 above */ 3262 { "stepping", "1" }, 3263 { "model-id", 3264 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3265 { /* end of list */ } 3266 } 3267 }, 3268 { /* end of list */ } 3269 } 3270 }, 3271 { 3272 .name = "Broadwell", 3273 .level = 0xd, 3274 .vendor = CPUID_VENDOR_INTEL, 3275 .family = 6, 3276 .model = 61, 3277 .stepping = 2, 3278 .features[FEAT_1_EDX] = 3279 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3280 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3281 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3282 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3283 CPUID_DE | CPUID_FP87, 3284 .features[FEAT_1_ECX] = 3285 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3286 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3287 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3288 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3289 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3290 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3291 .features[FEAT_8000_0001_EDX] = 3292 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3293 CPUID_EXT2_SYSCALL, 3294 .features[FEAT_8000_0001_ECX] = 3295 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3296 .features[FEAT_7_0_EBX] = 3297 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3298 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3299 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3300 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3301 CPUID_7_0_EBX_SMAP, 3302 .features[FEAT_XSAVE] = 3303 CPUID_XSAVE_XSAVEOPT, 3304 .features[FEAT_6_EAX] = 3305 CPUID_6_EAX_ARAT, 3306 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3307 MSR_VMX_BASIC_TRUE_CTLS, 3308 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3309 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3310 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3311 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3312 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3313 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3314 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3315 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3316 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3317 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3318 .features[FEAT_VMX_EXIT_CTLS] = 3319 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3320 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3321 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3322 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3323 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3324 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3325 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3326 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3327 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3328 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3329 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3330 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3331 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3332 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3333 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3334 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3335 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3336 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3337 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3338 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3339 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3340 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3341 .features[FEAT_VMX_SECONDARY_CTLS] = 3342 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3343 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3344 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3345 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3346 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3347 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3348 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3349 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3350 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3351 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3352 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3353 .xlevel = 0x80000008, 3354 .model_id = "Intel Core Processor (Broadwell)", 3355 .versions = (X86CPUVersionDefinition[]) { 3356 { .version = 1 }, 3357 { 3358 .version = 2, 3359 .alias = "Broadwell-noTSX", 3360 .props = (PropValue[]) { 3361 { "hle", "off" }, 3362 { "rtm", "off" }, 3363 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3364 { /* end of list */ } 3365 }, 3366 }, 3367 { 3368 .version = 3, 3369 .alias = "Broadwell-IBRS", 3370 .props = (PropValue[]) { 3371 /* Restore TSX features removed by -v2 above */ 3372 { "hle", "on" }, 3373 { "rtm", "on" }, 3374 { "spec-ctrl", "on" }, 3375 { "model-id", 3376 "Intel Core Processor (Broadwell, IBRS)" }, 3377 { /* end of list */ } 3378 } 3379 }, 3380 { 3381 .version = 4, 3382 .alias = "Broadwell-noTSX-IBRS", 3383 .props = (PropValue[]) { 3384 { "hle", "off" }, 3385 { "rtm", "off" }, 3386 /* spec-ctrl was already enabled by -v3 above */ 3387 { "model-id", 3388 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3389 { /* end of list */ } 3390 } 3391 }, 3392 { /* end of list */ } 3393 } 3394 }, 3395 { 3396 .name = "Skylake-Client", 3397 .level = 0xd, 3398 .vendor = CPUID_VENDOR_INTEL, 3399 .family = 6, 3400 .model = 94, 3401 .stepping = 3, 3402 .features[FEAT_1_EDX] = 3403 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3404 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3405 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3406 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3407 CPUID_DE | CPUID_FP87, 3408 .features[FEAT_1_ECX] = 3409 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3410 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3411 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3412 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3413 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3414 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3415 .features[FEAT_8000_0001_EDX] = 3416 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3417 CPUID_EXT2_SYSCALL, 3418 .features[FEAT_8000_0001_ECX] = 3419 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3420 .features[FEAT_7_0_EBX] = 3421 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3422 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3423 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3424 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3425 CPUID_7_0_EBX_SMAP, 3426 /* XSAVES is added in version 4 */ 3427 .features[FEAT_XSAVE] = 3428 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3429 CPUID_XSAVE_XGETBV1, 3430 .features[FEAT_6_EAX] = 3431 CPUID_6_EAX_ARAT, 3432 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3433 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3434 MSR_VMX_BASIC_TRUE_CTLS, 3435 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3436 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3437 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3438 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3439 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3440 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3441 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3442 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3443 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3444 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3445 .features[FEAT_VMX_EXIT_CTLS] = 3446 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3447 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3448 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3449 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3450 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3451 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3452 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3453 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3454 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3455 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3456 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3457 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3458 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3459 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3460 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3461 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3462 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3463 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3464 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3465 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3466 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3467 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3468 .features[FEAT_VMX_SECONDARY_CTLS] = 3469 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3470 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3471 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3472 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3473 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3474 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3475 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3476 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3477 .xlevel = 0x80000008, 3478 .model_id = "Intel Core Processor (Skylake)", 3479 .versions = (X86CPUVersionDefinition[]) { 3480 { .version = 1 }, 3481 { 3482 .version = 2, 3483 .alias = "Skylake-Client-IBRS", 3484 .props = (PropValue[]) { 3485 { "spec-ctrl", "on" }, 3486 { "model-id", 3487 "Intel Core Processor (Skylake, IBRS)" }, 3488 { /* end of list */ } 3489 } 3490 }, 3491 { 3492 .version = 3, 3493 .alias = "Skylake-Client-noTSX-IBRS", 3494 .props = (PropValue[]) { 3495 { "hle", "off" }, 3496 { "rtm", "off" }, 3497 { "model-id", 3498 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3499 { /* end of list */ } 3500 } 3501 }, 3502 { 3503 .version = 4, 3504 .note = "IBRS, XSAVES, no TSX", 3505 .props = (PropValue[]) { 3506 { "xsaves", "on" }, 3507 { "vmx-xsaves", "on" }, 3508 { /* end of list */ } 3509 } 3510 }, 3511 { /* end of list */ } 3512 } 3513 }, 3514 { 3515 .name = "Skylake-Server", 3516 .level = 0xd, 3517 .vendor = CPUID_VENDOR_INTEL, 3518 .family = 6, 3519 .model = 85, 3520 .stepping = 4, 3521 .features[FEAT_1_EDX] = 3522 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3523 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3524 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3525 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3526 CPUID_DE | CPUID_FP87, 3527 .features[FEAT_1_ECX] = 3528 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3529 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3530 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3531 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3532 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3533 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3534 .features[FEAT_8000_0001_EDX] = 3535 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3536 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3537 .features[FEAT_8000_0001_ECX] = 3538 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3539 .features[FEAT_7_0_EBX] = 3540 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3541 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3542 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3543 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3544 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3545 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3546 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3547 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3548 .features[FEAT_7_0_ECX] = 3549 CPUID_7_0_ECX_PKU, 3550 /* XSAVES is added in version 5 */ 3551 .features[FEAT_XSAVE] = 3552 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3553 CPUID_XSAVE_XGETBV1, 3554 .features[FEAT_6_EAX] = 3555 CPUID_6_EAX_ARAT, 3556 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3557 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3558 MSR_VMX_BASIC_TRUE_CTLS, 3559 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3560 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3561 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3562 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3563 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3564 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3565 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3566 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3567 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3568 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3569 .features[FEAT_VMX_EXIT_CTLS] = 3570 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3571 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3572 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3573 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3574 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3575 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3576 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3577 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3578 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3579 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3580 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3581 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3582 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3583 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3584 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3585 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3586 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3587 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3588 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3589 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3590 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3591 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3592 .features[FEAT_VMX_SECONDARY_CTLS] = 3593 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3594 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3595 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3596 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3597 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3598 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3599 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3600 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3601 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3602 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3603 .xlevel = 0x80000008, 3604 .model_id = "Intel Xeon Processor (Skylake)", 3605 .versions = (X86CPUVersionDefinition[]) { 3606 { .version = 1 }, 3607 { 3608 .version = 2, 3609 .alias = "Skylake-Server-IBRS", 3610 .props = (PropValue[]) { 3611 /* clflushopt was not added to Skylake-Server-IBRS */ 3612 /* TODO: add -v3 including clflushopt */ 3613 { "clflushopt", "off" }, 3614 { "spec-ctrl", "on" }, 3615 { "model-id", 3616 "Intel Xeon Processor (Skylake, IBRS)" }, 3617 { /* end of list */ } 3618 } 3619 }, 3620 { 3621 .version = 3, 3622 .alias = "Skylake-Server-noTSX-IBRS", 3623 .props = (PropValue[]) { 3624 { "hle", "off" }, 3625 { "rtm", "off" }, 3626 { "model-id", 3627 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3628 { /* end of list */ } 3629 } 3630 }, 3631 { 3632 .version = 4, 3633 .props = (PropValue[]) { 3634 { "vmx-eptp-switching", "on" }, 3635 { /* end of list */ } 3636 } 3637 }, 3638 { 3639 .version = 5, 3640 .note = "IBRS, XSAVES, EPT switching, no TSX", 3641 .props = (PropValue[]) { 3642 { "xsaves", "on" }, 3643 { "vmx-xsaves", "on" }, 3644 { /* end of list */ } 3645 } 3646 }, 3647 { /* end of list */ } 3648 } 3649 }, 3650 { 3651 .name = "Cascadelake-Server", 3652 .level = 0xd, 3653 .vendor = CPUID_VENDOR_INTEL, 3654 .family = 6, 3655 .model = 85, 3656 .stepping = 6, 3657 .features[FEAT_1_EDX] = 3658 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3660 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3662 CPUID_DE | CPUID_FP87, 3663 .features[FEAT_1_ECX] = 3664 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3665 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3666 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3667 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3668 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3669 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3670 .features[FEAT_8000_0001_EDX] = 3671 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3672 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3673 .features[FEAT_8000_0001_ECX] = 3674 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3675 .features[FEAT_7_0_EBX] = 3676 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3677 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3678 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3679 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3680 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3681 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3682 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3683 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3684 .features[FEAT_7_0_ECX] = 3685 CPUID_7_0_ECX_PKU | 3686 CPUID_7_0_ECX_AVX512VNNI, 3687 .features[FEAT_7_0_EDX] = 3688 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3689 /* XSAVES is added in version 5 */ 3690 .features[FEAT_XSAVE] = 3691 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3692 CPUID_XSAVE_XGETBV1, 3693 .features[FEAT_6_EAX] = 3694 CPUID_6_EAX_ARAT, 3695 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3696 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3697 MSR_VMX_BASIC_TRUE_CTLS, 3698 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3699 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3700 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3701 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3702 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3703 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3704 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3705 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3706 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3707 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3708 .features[FEAT_VMX_EXIT_CTLS] = 3709 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3710 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3711 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3712 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3713 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3714 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3715 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3716 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3717 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3718 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3719 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3720 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3721 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3722 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3723 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3724 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3725 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3726 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3727 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3728 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3729 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3730 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3731 .features[FEAT_VMX_SECONDARY_CTLS] = 3732 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3733 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3734 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3735 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3736 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3737 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3738 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3739 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3740 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3741 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3742 .xlevel = 0x80000008, 3743 .model_id = "Intel Xeon Processor (Cascadelake)", 3744 .versions = (X86CPUVersionDefinition[]) { 3745 { .version = 1 }, 3746 { .version = 2, 3747 .note = "ARCH_CAPABILITIES", 3748 .props = (PropValue[]) { 3749 { "arch-capabilities", "on" }, 3750 { "rdctl-no", "on" }, 3751 { "ibrs-all", "on" }, 3752 { "skip-l1dfl-vmentry", "on" }, 3753 { "mds-no", "on" }, 3754 { /* end of list */ } 3755 }, 3756 }, 3757 { .version = 3, 3758 .alias = "Cascadelake-Server-noTSX", 3759 .note = "ARCH_CAPABILITIES, no TSX", 3760 .props = (PropValue[]) { 3761 { "hle", "off" }, 3762 { "rtm", "off" }, 3763 { /* end of list */ } 3764 }, 3765 }, 3766 { .version = 4, 3767 .note = "ARCH_CAPABILITIES, no TSX", 3768 .props = (PropValue[]) { 3769 { "vmx-eptp-switching", "on" }, 3770 { /* end of list */ } 3771 }, 3772 }, 3773 { .version = 5, 3774 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3775 .props = (PropValue[]) { 3776 { "xsaves", "on" }, 3777 { "vmx-xsaves", "on" }, 3778 { /* end of list */ } 3779 }, 3780 }, 3781 { /* end of list */ } 3782 } 3783 }, 3784 { 3785 .name = "Cooperlake", 3786 .level = 0xd, 3787 .vendor = CPUID_VENDOR_INTEL, 3788 .family = 6, 3789 .model = 85, 3790 .stepping = 10, 3791 .features[FEAT_1_EDX] = 3792 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3793 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3794 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3795 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3796 CPUID_DE | CPUID_FP87, 3797 .features[FEAT_1_ECX] = 3798 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3799 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3800 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3801 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3802 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3803 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3804 .features[FEAT_8000_0001_EDX] = 3805 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3806 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3807 .features[FEAT_8000_0001_ECX] = 3808 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3809 .features[FEAT_7_0_EBX] = 3810 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3811 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3812 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3813 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3814 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3815 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3816 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3817 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3818 .features[FEAT_7_0_ECX] = 3819 CPUID_7_0_ECX_PKU | 3820 CPUID_7_0_ECX_AVX512VNNI, 3821 .features[FEAT_7_0_EDX] = 3822 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3823 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3824 .features[FEAT_ARCH_CAPABILITIES] = 3825 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3826 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3827 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3828 .features[FEAT_7_1_EAX] = 3829 CPUID_7_1_EAX_AVX512_BF16, 3830 /* XSAVES is added in version 2 */ 3831 .features[FEAT_XSAVE] = 3832 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3833 CPUID_XSAVE_XGETBV1, 3834 .features[FEAT_6_EAX] = 3835 CPUID_6_EAX_ARAT, 3836 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3837 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3838 MSR_VMX_BASIC_TRUE_CTLS, 3839 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3840 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3841 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3842 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3843 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3844 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3845 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3846 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3847 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3848 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3849 .features[FEAT_VMX_EXIT_CTLS] = 3850 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3851 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3852 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3853 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3854 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3855 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3856 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3857 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3858 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3859 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3860 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3861 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3862 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3863 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3864 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3865 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3866 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3867 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3868 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3869 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3870 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3871 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3872 .features[FEAT_VMX_SECONDARY_CTLS] = 3873 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3874 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3875 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3876 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3877 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3878 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3879 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3880 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3881 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3882 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3883 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3884 .xlevel = 0x80000008, 3885 .model_id = "Intel Xeon Processor (Cooperlake)", 3886 .versions = (X86CPUVersionDefinition[]) { 3887 { .version = 1 }, 3888 { .version = 2, 3889 .note = "XSAVES", 3890 .props = (PropValue[]) { 3891 { "xsaves", "on" }, 3892 { "vmx-xsaves", "on" }, 3893 { /* end of list */ } 3894 }, 3895 }, 3896 { /* end of list */ } 3897 } 3898 }, 3899 { 3900 .name = "Icelake-Server", 3901 .level = 0xd, 3902 .vendor = CPUID_VENDOR_INTEL, 3903 .family = 6, 3904 .model = 134, 3905 .stepping = 0, 3906 .features[FEAT_1_EDX] = 3907 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3908 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3909 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3910 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3911 CPUID_DE | CPUID_FP87, 3912 .features[FEAT_1_ECX] = 3913 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3914 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3915 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3916 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3917 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3918 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3919 .features[FEAT_8000_0001_EDX] = 3920 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3921 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3922 .features[FEAT_8000_0001_ECX] = 3923 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3924 .features[FEAT_8000_0008_EBX] = 3925 CPUID_8000_0008_EBX_WBNOINVD, 3926 .features[FEAT_7_0_EBX] = 3927 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3928 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3929 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3930 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3931 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3932 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3933 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3934 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3935 .features[FEAT_7_0_ECX] = 3936 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3937 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3938 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3939 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3940 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3941 .features[FEAT_7_0_EDX] = 3942 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3943 /* XSAVES is added in version 5 */ 3944 .features[FEAT_XSAVE] = 3945 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3946 CPUID_XSAVE_XGETBV1, 3947 .features[FEAT_6_EAX] = 3948 CPUID_6_EAX_ARAT, 3949 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3950 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3951 MSR_VMX_BASIC_TRUE_CTLS, 3952 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3953 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3954 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3955 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3956 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3957 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3958 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3959 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3960 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3961 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3962 .features[FEAT_VMX_EXIT_CTLS] = 3963 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3964 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3965 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3966 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3967 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3968 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3969 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3970 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3971 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3972 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3973 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3974 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3975 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3976 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3977 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3978 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3979 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3980 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3981 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3982 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3983 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3984 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3985 .features[FEAT_VMX_SECONDARY_CTLS] = 3986 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3987 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3988 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3989 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3990 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3991 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3992 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3993 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3994 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3995 .xlevel = 0x80000008, 3996 .model_id = "Intel Xeon Processor (Icelake)", 3997 .versions = (X86CPUVersionDefinition[]) { 3998 { .version = 1 }, 3999 { 4000 .version = 2, 4001 .note = "no TSX", 4002 .alias = "Icelake-Server-noTSX", 4003 .props = (PropValue[]) { 4004 { "hle", "off" }, 4005 { "rtm", "off" }, 4006 { /* end of list */ } 4007 }, 4008 }, 4009 { 4010 .version = 3, 4011 .props = (PropValue[]) { 4012 { "arch-capabilities", "on" }, 4013 { "rdctl-no", "on" }, 4014 { "ibrs-all", "on" }, 4015 { "skip-l1dfl-vmentry", "on" }, 4016 { "mds-no", "on" }, 4017 { "pschange-mc-no", "on" }, 4018 { "taa-no", "on" }, 4019 { /* end of list */ } 4020 }, 4021 }, 4022 { 4023 .version = 4, 4024 .props = (PropValue[]) { 4025 { "sha-ni", "on" }, 4026 { "avx512ifma", "on" }, 4027 { "rdpid", "on" }, 4028 { "fsrm", "on" }, 4029 { "vmx-rdseed-exit", "on" }, 4030 { "vmx-pml", "on" }, 4031 { "vmx-eptp-switching", "on" }, 4032 { "model", "106" }, 4033 { /* end of list */ } 4034 }, 4035 }, 4036 { 4037 .version = 5, 4038 .note = "XSAVES", 4039 .props = (PropValue[]) { 4040 { "xsaves", "on" }, 4041 { "vmx-xsaves", "on" }, 4042 { /* end of list */ } 4043 }, 4044 }, 4045 { 4046 .version = 6, 4047 .note = "5-level EPT", 4048 .props = (PropValue[]) { 4049 { "vmx-page-walk-5", "on" }, 4050 { /* end of list */ } 4051 }, 4052 }, 4053 { 4054 .version = 7, 4055 .note = "TSX, taa-no", 4056 .props = (PropValue[]) { 4057 /* Restore TSX features removed by -v2 above */ 4058 { "hle", "on" }, 4059 { "rtm", "on" }, 4060 { /* end of list */ } 4061 }, 4062 }, 4063 { /* end of list */ } 4064 } 4065 }, 4066 { 4067 .name = "SapphireRapids", 4068 .level = 0x20, 4069 .vendor = CPUID_VENDOR_INTEL, 4070 .family = 6, 4071 .model = 143, 4072 .stepping = 4, 4073 /* 4074 * please keep the ascending order so that we can have a clear view of 4075 * bit position of each feature. 4076 */ 4077 .features[FEAT_1_EDX] = 4078 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4079 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4080 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4081 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4082 CPUID_SSE | CPUID_SSE2, 4083 .features[FEAT_1_ECX] = 4084 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4085 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4086 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4087 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4088 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4089 .features[FEAT_8000_0001_EDX] = 4090 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4091 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4092 .features[FEAT_8000_0001_ECX] = 4093 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4094 .features[FEAT_8000_0008_EBX] = 4095 CPUID_8000_0008_EBX_WBNOINVD, 4096 .features[FEAT_7_0_EBX] = 4097 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4098 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4099 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4100 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4101 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4102 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4103 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4104 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4105 .features[FEAT_7_0_ECX] = 4106 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4107 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4108 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4109 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4110 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4111 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4112 .features[FEAT_7_0_EDX] = 4113 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4114 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4115 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4116 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4117 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4118 .features[FEAT_ARCH_CAPABILITIES] = 4119 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4120 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4121 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4122 .features[FEAT_XSAVE] = 4123 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4124 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4125 .features[FEAT_6_EAX] = 4126 CPUID_6_EAX_ARAT, 4127 .features[FEAT_7_1_EAX] = 4128 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4129 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4130 .features[FEAT_VMX_BASIC] = 4131 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4132 .features[FEAT_VMX_ENTRY_CTLS] = 4133 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4134 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4135 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4136 .features[FEAT_VMX_EPT_VPID_CAPS] = 4137 MSR_VMX_EPT_EXECONLY | 4138 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4139 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4140 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4141 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4142 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4143 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4144 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4145 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4146 .features[FEAT_VMX_EXIT_CTLS] = 4147 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4148 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4149 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4150 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4151 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4152 .features[FEAT_VMX_MISC] = 4153 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4154 MSR_VMX_MISC_VMWRITE_VMEXIT, 4155 .features[FEAT_VMX_PINBASED_CTLS] = 4156 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4157 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4158 VMX_PIN_BASED_POSTED_INTR, 4159 .features[FEAT_VMX_PROCBASED_CTLS] = 4160 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4161 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4162 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4163 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4164 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4165 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4166 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4167 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4168 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4169 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4170 VMX_CPU_BASED_PAUSE_EXITING | 4171 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4172 .features[FEAT_VMX_SECONDARY_CTLS] = 4173 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4174 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4175 VMX_SECONDARY_EXEC_RDTSCP | 4176 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4177 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4178 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4179 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4180 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4181 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4182 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4183 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4184 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4185 VMX_SECONDARY_EXEC_XSAVES, 4186 .features[FEAT_VMX_VMFUNC] = 4187 MSR_VMX_VMFUNC_EPT_SWITCHING, 4188 .xlevel = 0x80000008, 4189 .model_id = "Intel Xeon Processor (SapphireRapids)", 4190 .versions = (X86CPUVersionDefinition[]) { 4191 { .version = 1 }, 4192 { 4193 .version = 2, 4194 .props = (PropValue[]) { 4195 { "sbdr-ssdp-no", "on" }, 4196 { "fbsdp-no", "on" }, 4197 { "psdp-no", "on" }, 4198 { /* end of list */ } 4199 } 4200 }, 4201 { 4202 .version = 3, 4203 .props = (PropValue[]) { 4204 { "ss", "on" }, 4205 { "tsc-adjust", "on" }, 4206 { "cldemote", "on" }, 4207 { "movdiri", "on" }, 4208 { "movdir64b", "on" }, 4209 { /* end of list */ } 4210 } 4211 }, 4212 { /* end of list */ } 4213 } 4214 }, 4215 { 4216 .name = "GraniteRapids", 4217 .level = 0x20, 4218 .vendor = CPUID_VENDOR_INTEL, 4219 .family = 6, 4220 .model = 173, 4221 .stepping = 0, 4222 /* 4223 * please keep the ascending order so that we can have a clear view of 4224 * bit position of each feature. 4225 */ 4226 .features[FEAT_1_EDX] = 4227 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4228 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4229 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4230 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4231 CPUID_SSE | CPUID_SSE2, 4232 .features[FEAT_1_ECX] = 4233 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4234 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4235 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4236 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4237 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4238 .features[FEAT_8000_0001_EDX] = 4239 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4240 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4241 .features[FEAT_8000_0001_ECX] = 4242 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4243 .features[FEAT_8000_0008_EBX] = 4244 CPUID_8000_0008_EBX_WBNOINVD, 4245 .features[FEAT_7_0_EBX] = 4246 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4247 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4248 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4249 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4250 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4251 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4252 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4253 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4254 .features[FEAT_7_0_ECX] = 4255 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4256 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4257 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4258 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4259 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4260 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4261 .features[FEAT_7_0_EDX] = 4262 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4263 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4264 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4265 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4266 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4267 .features[FEAT_ARCH_CAPABILITIES] = 4268 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4269 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4270 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4271 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4272 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4273 .features[FEAT_XSAVE] = 4274 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4275 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4276 .features[FEAT_6_EAX] = 4277 CPUID_6_EAX_ARAT, 4278 .features[FEAT_7_1_EAX] = 4279 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4280 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4281 CPUID_7_1_EAX_AMX_FP16, 4282 .features[FEAT_7_1_EDX] = 4283 CPUID_7_1_EDX_PREFETCHITI, 4284 .features[FEAT_7_2_EDX] = 4285 CPUID_7_2_EDX_MCDT_NO, 4286 .features[FEAT_VMX_BASIC] = 4287 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4288 .features[FEAT_VMX_ENTRY_CTLS] = 4289 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4290 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4291 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4292 .features[FEAT_VMX_EPT_VPID_CAPS] = 4293 MSR_VMX_EPT_EXECONLY | 4294 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4295 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4296 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4297 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4298 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4299 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4300 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4301 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4302 .features[FEAT_VMX_EXIT_CTLS] = 4303 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4304 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4305 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4306 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4307 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4308 .features[FEAT_VMX_MISC] = 4309 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4310 MSR_VMX_MISC_VMWRITE_VMEXIT, 4311 .features[FEAT_VMX_PINBASED_CTLS] = 4312 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4313 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4314 VMX_PIN_BASED_POSTED_INTR, 4315 .features[FEAT_VMX_PROCBASED_CTLS] = 4316 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4317 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4318 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4319 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4320 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4321 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4322 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4323 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4324 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4325 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4326 VMX_CPU_BASED_PAUSE_EXITING | 4327 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4328 .features[FEAT_VMX_SECONDARY_CTLS] = 4329 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4330 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4331 VMX_SECONDARY_EXEC_RDTSCP | 4332 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4333 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4334 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4335 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4336 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4337 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4338 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4339 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4340 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4341 VMX_SECONDARY_EXEC_XSAVES, 4342 .features[FEAT_VMX_VMFUNC] = 4343 MSR_VMX_VMFUNC_EPT_SWITCHING, 4344 .xlevel = 0x80000008, 4345 .model_id = "Intel Xeon Processor (GraniteRapids)", 4346 .versions = (X86CPUVersionDefinition[]) { 4347 { .version = 1 }, 4348 { /* end of list */ }, 4349 }, 4350 }, 4351 { 4352 .name = "SierraForest", 4353 .level = 0x23, 4354 .vendor = CPUID_VENDOR_INTEL, 4355 .family = 6, 4356 .model = 175, 4357 .stepping = 0, 4358 /* 4359 * please keep the ascending order so that we can have a clear view of 4360 * bit position of each feature. 4361 */ 4362 .features[FEAT_1_EDX] = 4363 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4364 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4365 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4366 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4367 CPUID_SSE | CPUID_SSE2, 4368 .features[FEAT_1_ECX] = 4369 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4370 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4371 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4372 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4373 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4374 .features[FEAT_8000_0001_EDX] = 4375 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4376 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4377 .features[FEAT_8000_0001_ECX] = 4378 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4379 .features[FEAT_8000_0008_EBX] = 4380 CPUID_8000_0008_EBX_WBNOINVD, 4381 .features[FEAT_7_0_EBX] = 4382 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4383 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4384 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4385 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4386 CPUID_7_0_EBX_SHA_NI, 4387 .features[FEAT_7_0_ECX] = 4388 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4389 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4390 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4391 .features[FEAT_7_0_EDX] = 4392 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4393 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4394 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4395 .features[FEAT_ARCH_CAPABILITIES] = 4396 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4397 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4398 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4399 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4400 MSR_ARCH_CAP_PBRSB_NO, 4401 .features[FEAT_XSAVE] = 4402 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4403 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4404 .features[FEAT_6_EAX] = 4405 CPUID_6_EAX_ARAT, 4406 .features[FEAT_7_1_EAX] = 4407 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4408 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4409 .features[FEAT_7_1_EDX] = 4410 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4411 .features[FEAT_7_2_EDX] = 4412 CPUID_7_2_EDX_MCDT_NO, 4413 .features[FEAT_VMX_BASIC] = 4414 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4415 .features[FEAT_VMX_ENTRY_CTLS] = 4416 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4417 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4418 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4419 .features[FEAT_VMX_EPT_VPID_CAPS] = 4420 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4421 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4422 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4423 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4424 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4425 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4426 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4427 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4428 .features[FEAT_VMX_EXIT_CTLS] = 4429 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4430 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4431 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4432 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4433 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4434 .features[FEAT_VMX_MISC] = 4435 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4436 MSR_VMX_MISC_VMWRITE_VMEXIT, 4437 .features[FEAT_VMX_PINBASED_CTLS] = 4438 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4439 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4440 VMX_PIN_BASED_POSTED_INTR, 4441 .features[FEAT_VMX_PROCBASED_CTLS] = 4442 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4443 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4444 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4445 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4446 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4447 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4448 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4449 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4450 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4451 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4452 VMX_CPU_BASED_PAUSE_EXITING | 4453 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4454 .features[FEAT_VMX_SECONDARY_CTLS] = 4455 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4456 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4457 VMX_SECONDARY_EXEC_RDTSCP | 4458 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4459 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4460 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4461 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4462 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4463 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4464 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4465 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4466 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4467 VMX_SECONDARY_EXEC_XSAVES, 4468 .features[FEAT_VMX_VMFUNC] = 4469 MSR_VMX_VMFUNC_EPT_SWITCHING, 4470 .xlevel = 0x80000008, 4471 .model_id = "Intel Xeon Processor (SierraForest)", 4472 .versions = (X86CPUVersionDefinition[]) { 4473 { .version = 1 }, 4474 { /* end of list */ }, 4475 }, 4476 }, 4477 { 4478 .name = "Denverton", 4479 .level = 21, 4480 .vendor = CPUID_VENDOR_INTEL, 4481 .family = 6, 4482 .model = 95, 4483 .stepping = 1, 4484 .features[FEAT_1_EDX] = 4485 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4486 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4487 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4488 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4489 CPUID_SSE | CPUID_SSE2, 4490 .features[FEAT_1_ECX] = 4491 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4492 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4493 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4494 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4495 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4496 .features[FEAT_8000_0001_EDX] = 4497 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4498 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4499 .features[FEAT_8000_0001_ECX] = 4500 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4501 .features[FEAT_7_0_EBX] = 4502 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4503 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4504 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4505 .features[FEAT_7_0_EDX] = 4506 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4507 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4508 /* XSAVES is added in version 3 */ 4509 .features[FEAT_XSAVE] = 4510 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4511 .features[FEAT_6_EAX] = 4512 CPUID_6_EAX_ARAT, 4513 .features[FEAT_ARCH_CAPABILITIES] = 4514 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4515 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4516 MSR_VMX_BASIC_TRUE_CTLS, 4517 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4518 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4519 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4520 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4521 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4522 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4523 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4524 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4525 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4526 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4527 .features[FEAT_VMX_EXIT_CTLS] = 4528 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4529 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4530 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4531 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4532 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4533 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4534 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4535 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4536 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4537 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4538 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4539 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4540 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4541 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4542 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4543 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4544 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4545 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4546 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4547 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4548 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4549 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4550 .features[FEAT_VMX_SECONDARY_CTLS] = 4551 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4552 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4553 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4554 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4555 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4556 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4557 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4558 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4559 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4560 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4561 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4562 .xlevel = 0x80000008, 4563 .model_id = "Intel Atom Processor (Denverton)", 4564 .versions = (X86CPUVersionDefinition[]) { 4565 { .version = 1 }, 4566 { 4567 .version = 2, 4568 .note = "no MPX, no MONITOR", 4569 .props = (PropValue[]) { 4570 { "monitor", "off" }, 4571 { "mpx", "off" }, 4572 { /* end of list */ }, 4573 }, 4574 }, 4575 { 4576 .version = 3, 4577 .note = "XSAVES, no MPX, no MONITOR", 4578 .props = (PropValue[]) { 4579 { "xsaves", "on" }, 4580 { "vmx-xsaves", "on" }, 4581 { /* end of list */ }, 4582 }, 4583 }, 4584 { /* end of list */ }, 4585 }, 4586 }, 4587 { 4588 .name = "Snowridge", 4589 .level = 27, 4590 .vendor = CPUID_VENDOR_INTEL, 4591 .family = 6, 4592 .model = 134, 4593 .stepping = 1, 4594 .features[FEAT_1_EDX] = 4595 /* missing: CPUID_PN CPUID_IA64 */ 4596 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4597 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4598 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4599 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4600 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4601 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4602 CPUID_MMX | 4603 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4604 .features[FEAT_1_ECX] = 4605 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4606 CPUID_EXT_SSSE3 | 4607 CPUID_EXT_CX16 | 4608 CPUID_EXT_SSE41 | 4609 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4610 CPUID_EXT_POPCNT | 4611 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4612 CPUID_EXT_RDRAND, 4613 .features[FEAT_8000_0001_EDX] = 4614 CPUID_EXT2_SYSCALL | 4615 CPUID_EXT2_NX | 4616 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4617 CPUID_EXT2_LM, 4618 .features[FEAT_8000_0001_ECX] = 4619 CPUID_EXT3_LAHF_LM | 4620 CPUID_EXT3_3DNOWPREFETCH, 4621 .features[FEAT_7_0_EBX] = 4622 CPUID_7_0_EBX_FSGSBASE | 4623 CPUID_7_0_EBX_SMEP | 4624 CPUID_7_0_EBX_ERMS | 4625 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4626 CPUID_7_0_EBX_RDSEED | 4627 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4628 CPUID_7_0_EBX_CLWB | 4629 CPUID_7_0_EBX_SHA_NI, 4630 .features[FEAT_7_0_ECX] = 4631 CPUID_7_0_ECX_UMIP | 4632 /* missing bit 5 */ 4633 CPUID_7_0_ECX_GFNI | 4634 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4635 CPUID_7_0_ECX_MOVDIR64B, 4636 .features[FEAT_7_0_EDX] = 4637 CPUID_7_0_EDX_SPEC_CTRL | 4638 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4639 CPUID_7_0_EDX_CORE_CAPABILITY, 4640 .features[FEAT_CORE_CAPABILITY] = 4641 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4642 /* XSAVES is added in version 3 */ 4643 .features[FEAT_XSAVE] = 4644 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4645 CPUID_XSAVE_XGETBV1, 4646 .features[FEAT_6_EAX] = 4647 CPUID_6_EAX_ARAT, 4648 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4649 MSR_VMX_BASIC_TRUE_CTLS, 4650 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4651 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4652 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4653 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4654 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4655 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4656 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4657 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4658 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4659 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4660 .features[FEAT_VMX_EXIT_CTLS] = 4661 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4662 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4663 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4664 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4665 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4666 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4667 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4668 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4669 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4670 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4671 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4672 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4673 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4674 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4675 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4676 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4677 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4678 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4679 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4680 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4681 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4682 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4683 .features[FEAT_VMX_SECONDARY_CTLS] = 4684 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4685 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4686 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4687 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4688 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4689 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4690 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4691 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4692 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4693 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4694 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4695 .xlevel = 0x80000008, 4696 .model_id = "Intel Atom Processor (SnowRidge)", 4697 .versions = (X86CPUVersionDefinition[]) { 4698 { .version = 1 }, 4699 { 4700 .version = 2, 4701 .props = (PropValue[]) { 4702 { "mpx", "off" }, 4703 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4704 { /* end of list */ }, 4705 }, 4706 }, 4707 { 4708 .version = 3, 4709 .note = "XSAVES, no MPX", 4710 .props = (PropValue[]) { 4711 { "xsaves", "on" }, 4712 { "vmx-xsaves", "on" }, 4713 { /* end of list */ }, 4714 }, 4715 }, 4716 { 4717 .version = 4, 4718 .note = "no split lock detect, no core-capability", 4719 .props = (PropValue[]) { 4720 { "split-lock-detect", "off" }, 4721 { "core-capability", "off" }, 4722 { /* end of list */ }, 4723 }, 4724 }, 4725 { /* end of list */ }, 4726 }, 4727 }, 4728 { 4729 .name = "KnightsMill", 4730 .level = 0xd, 4731 .vendor = CPUID_VENDOR_INTEL, 4732 .family = 6, 4733 .model = 133, 4734 .stepping = 0, 4735 .features[FEAT_1_EDX] = 4736 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4737 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4738 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4739 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4740 CPUID_PSE | CPUID_DE | CPUID_FP87, 4741 .features[FEAT_1_ECX] = 4742 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4743 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4744 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4745 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4746 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4747 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4748 .features[FEAT_8000_0001_EDX] = 4749 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4750 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4751 .features[FEAT_8000_0001_ECX] = 4752 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4753 .features[FEAT_7_0_EBX] = 4754 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4755 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4756 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4757 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4758 CPUID_7_0_EBX_AVX512ER, 4759 .features[FEAT_7_0_ECX] = 4760 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4761 .features[FEAT_7_0_EDX] = 4762 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4763 .features[FEAT_XSAVE] = 4764 CPUID_XSAVE_XSAVEOPT, 4765 .features[FEAT_6_EAX] = 4766 CPUID_6_EAX_ARAT, 4767 .xlevel = 0x80000008, 4768 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4769 }, 4770 { 4771 .name = "Opteron_G1", 4772 .level = 5, 4773 .vendor = CPUID_VENDOR_AMD, 4774 .family = 15, 4775 .model = 6, 4776 .stepping = 1, 4777 .features[FEAT_1_EDX] = 4778 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4779 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4780 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4781 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4782 CPUID_DE | CPUID_FP87, 4783 .features[FEAT_1_ECX] = 4784 CPUID_EXT_SSE3, 4785 .features[FEAT_8000_0001_EDX] = 4786 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4787 .xlevel = 0x80000008, 4788 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4789 }, 4790 { 4791 .name = "Opteron_G2", 4792 .level = 5, 4793 .vendor = CPUID_VENDOR_AMD, 4794 .family = 15, 4795 .model = 6, 4796 .stepping = 1, 4797 .features[FEAT_1_EDX] = 4798 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4799 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4800 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4801 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4802 CPUID_DE | CPUID_FP87, 4803 .features[FEAT_1_ECX] = 4804 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4805 .features[FEAT_8000_0001_EDX] = 4806 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4807 .features[FEAT_8000_0001_ECX] = 4808 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4809 .xlevel = 0x80000008, 4810 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4811 }, 4812 { 4813 .name = "Opteron_G3", 4814 .level = 5, 4815 .vendor = CPUID_VENDOR_AMD, 4816 .family = 16, 4817 .model = 2, 4818 .stepping = 3, 4819 .features[FEAT_1_EDX] = 4820 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4821 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4822 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4823 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4824 CPUID_DE | CPUID_FP87, 4825 .features[FEAT_1_ECX] = 4826 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4827 CPUID_EXT_SSE3, 4828 .features[FEAT_8000_0001_EDX] = 4829 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4830 CPUID_EXT2_RDTSCP, 4831 .features[FEAT_8000_0001_ECX] = 4832 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4833 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4834 .xlevel = 0x80000008, 4835 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4836 }, 4837 { 4838 .name = "Opteron_G4", 4839 .level = 0xd, 4840 .vendor = CPUID_VENDOR_AMD, 4841 .family = 21, 4842 .model = 1, 4843 .stepping = 2, 4844 .features[FEAT_1_EDX] = 4845 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4846 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4847 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4848 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4849 CPUID_DE | CPUID_FP87, 4850 .features[FEAT_1_ECX] = 4851 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4852 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4853 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4854 CPUID_EXT_SSE3, 4855 .features[FEAT_8000_0001_EDX] = 4856 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4857 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4858 .features[FEAT_8000_0001_ECX] = 4859 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4860 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4861 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4862 CPUID_EXT3_LAHF_LM, 4863 .features[FEAT_SVM] = 4864 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4865 /* no xsaveopt! */ 4866 .xlevel = 0x8000001A, 4867 .model_id = "AMD Opteron 62xx class CPU", 4868 }, 4869 { 4870 .name = "Opteron_G5", 4871 .level = 0xd, 4872 .vendor = CPUID_VENDOR_AMD, 4873 .family = 21, 4874 .model = 2, 4875 .stepping = 0, 4876 .features[FEAT_1_EDX] = 4877 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4878 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4879 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4880 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4881 CPUID_DE | CPUID_FP87, 4882 .features[FEAT_1_ECX] = 4883 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4884 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4885 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4886 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4887 .features[FEAT_8000_0001_EDX] = 4888 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4889 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4890 .features[FEAT_8000_0001_ECX] = 4891 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4892 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4893 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4894 CPUID_EXT3_LAHF_LM, 4895 .features[FEAT_SVM] = 4896 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4897 /* no xsaveopt! */ 4898 .xlevel = 0x8000001A, 4899 .model_id = "AMD Opteron 63xx class CPU", 4900 }, 4901 { 4902 .name = "EPYC", 4903 .level = 0xd, 4904 .vendor = CPUID_VENDOR_AMD, 4905 .family = 23, 4906 .model = 1, 4907 .stepping = 2, 4908 .features[FEAT_1_EDX] = 4909 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4910 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4911 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4912 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4913 CPUID_VME | CPUID_FP87, 4914 .features[FEAT_1_ECX] = 4915 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4916 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4917 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4918 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4919 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4920 .features[FEAT_8000_0001_EDX] = 4921 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4922 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4923 CPUID_EXT2_SYSCALL, 4924 .features[FEAT_8000_0001_ECX] = 4925 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4926 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4927 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4928 CPUID_EXT3_TOPOEXT, 4929 .features[FEAT_7_0_EBX] = 4930 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4931 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4932 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4933 CPUID_7_0_EBX_SHA_NI, 4934 .features[FEAT_XSAVE] = 4935 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4936 CPUID_XSAVE_XGETBV1, 4937 .features[FEAT_6_EAX] = 4938 CPUID_6_EAX_ARAT, 4939 .features[FEAT_SVM] = 4940 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4941 .xlevel = 0x8000001E, 4942 .model_id = "AMD EPYC Processor", 4943 .cache_info = &epyc_cache_info, 4944 .versions = (X86CPUVersionDefinition[]) { 4945 { .version = 1 }, 4946 { 4947 .version = 2, 4948 .alias = "EPYC-IBPB", 4949 .props = (PropValue[]) { 4950 { "ibpb", "on" }, 4951 { "model-id", 4952 "AMD EPYC Processor (with IBPB)" }, 4953 { /* end of list */ } 4954 } 4955 }, 4956 { 4957 .version = 3, 4958 .props = (PropValue[]) { 4959 { "ibpb", "on" }, 4960 { "perfctr-core", "on" }, 4961 { "clzero", "on" }, 4962 { "xsaveerptr", "on" }, 4963 { "xsaves", "on" }, 4964 { "model-id", 4965 "AMD EPYC Processor" }, 4966 { /* end of list */ } 4967 } 4968 }, 4969 { 4970 .version = 4, 4971 .props = (PropValue[]) { 4972 { "model-id", 4973 "AMD EPYC-v4 Processor" }, 4974 { /* end of list */ } 4975 }, 4976 .cache_info = &epyc_v4_cache_info 4977 }, 4978 { /* end of list */ } 4979 } 4980 }, 4981 { 4982 .name = "Dhyana", 4983 .level = 0xd, 4984 .vendor = CPUID_VENDOR_HYGON, 4985 .family = 24, 4986 .model = 0, 4987 .stepping = 1, 4988 .features[FEAT_1_EDX] = 4989 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4990 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4991 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4992 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4993 CPUID_VME | CPUID_FP87, 4994 .features[FEAT_1_ECX] = 4995 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4996 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4997 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4998 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4999 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5000 .features[FEAT_8000_0001_EDX] = 5001 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5002 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5003 CPUID_EXT2_SYSCALL, 5004 .features[FEAT_8000_0001_ECX] = 5005 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5006 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5007 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5008 CPUID_EXT3_TOPOEXT, 5009 .features[FEAT_8000_0008_EBX] = 5010 CPUID_8000_0008_EBX_IBPB, 5011 .features[FEAT_7_0_EBX] = 5012 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5013 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5014 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5015 /* XSAVES is added in version 2 */ 5016 .features[FEAT_XSAVE] = 5017 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5018 CPUID_XSAVE_XGETBV1, 5019 .features[FEAT_6_EAX] = 5020 CPUID_6_EAX_ARAT, 5021 .features[FEAT_SVM] = 5022 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5023 .xlevel = 0x8000001E, 5024 .model_id = "Hygon Dhyana Processor", 5025 .cache_info = &epyc_cache_info, 5026 .versions = (X86CPUVersionDefinition[]) { 5027 { .version = 1 }, 5028 { .version = 2, 5029 .note = "XSAVES", 5030 .props = (PropValue[]) { 5031 { "xsaves", "on" }, 5032 { /* end of list */ } 5033 }, 5034 }, 5035 { /* end of list */ } 5036 } 5037 }, 5038 { 5039 .name = "EPYC-Rome", 5040 .level = 0xd, 5041 .vendor = CPUID_VENDOR_AMD, 5042 .family = 23, 5043 .model = 49, 5044 .stepping = 0, 5045 .features[FEAT_1_EDX] = 5046 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5047 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5048 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5049 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5050 CPUID_VME | CPUID_FP87, 5051 .features[FEAT_1_ECX] = 5052 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5053 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5054 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5055 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5056 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5057 .features[FEAT_8000_0001_EDX] = 5058 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5059 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5060 CPUID_EXT2_SYSCALL, 5061 .features[FEAT_8000_0001_ECX] = 5062 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5063 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5064 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5065 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5066 .features[FEAT_8000_0008_EBX] = 5067 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5068 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5069 CPUID_8000_0008_EBX_STIBP, 5070 .features[FEAT_7_0_EBX] = 5071 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5072 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5073 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5074 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5075 .features[FEAT_7_0_ECX] = 5076 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5077 .features[FEAT_XSAVE] = 5078 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5079 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5080 .features[FEAT_6_EAX] = 5081 CPUID_6_EAX_ARAT, 5082 .features[FEAT_SVM] = 5083 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5084 .xlevel = 0x8000001E, 5085 .model_id = "AMD EPYC-Rome Processor", 5086 .cache_info = &epyc_rome_cache_info, 5087 .versions = (X86CPUVersionDefinition[]) { 5088 { .version = 1 }, 5089 { 5090 .version = 2, 5091 .props = (PropValue[]) { 5092 { "ibrs", "on" }, 5093 { "amd-ssbd", "on" }, 5094 { /* end of list */ } 5095 } 5096 }, 5097 { 5098 .version = 3, 5099 .props = (PropValue[]) { 5100 { "model-id", 5101 "AMD EPYC-Rome-v3 Processor" }, 5102 { /* end of list */ } 5103 }, 5104 .cache_info = &epyc_rome_v3_cache_info 5105 }, 5106 { 5107 .version = 4, 5108 .props = (PropValue[]) { 5109 /* Erratum 1386 */ 5110 { "model-id", 5111 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5112 { "xsaves", "off" }, 5113 { /* end of list */ } 5114 }, 5115 }, 5116 { /* end of list */ } 5117 } 5118 }, 5119 { 5120 .name = "EPYC-Milan", 5121 .level = 0xd, 5122 .vendor = CPUID_VENDOR_AMD, 5123 .family = 25, 5124 .model = 1, 5125 .stepping = 1, 5126 .features[FEAT_1_EDX] = 5127 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5128 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5129 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5130 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5131 CPUID_VME | CPUID_FP87, 5132 .features[FEAT_1_ECX] = 5133 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5134 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5135 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5136 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5137 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5138 CPUID_EXT_PCID, 5139 .features[FEAT_8000_0001_EDX] = 5140 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5141 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5142 CPUID_EXT2_SYSCALL, 5143 .features[FEAT_8000_0001_ECX] = 5144 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5145 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5146 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5147 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5148 .features[FEAT_8000_0008_EBX] = 5149 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5150 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5151 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5152 CPUID_8000_0008_EBX_AMD_SSBD, 5153 .features[FEAT_7_0_EBX] = 5154 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5155 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5156 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5157 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5158 CPUID_7_0_EBX_INVPCID, 5159 .features[FEAT_7_0_ECX] = 5160 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5161 .features[FEAT_7_0_EDX] = 5162 CPUID_7_0_EDX_FSRM, 5163 .features[FEAT_XSAVE] = 5164 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5165 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5166 .features[FEAT_6_EAX] = 5167 CPUID_6_EAX_ARAT, 5168 .features[FEAT_SVM] = 5169 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5170 .xlevel = 0x8000001E, 5171 .model_id = "AMD EPYC-Milan Processor", 5172 .cache_info = &epyc_milan_cache_info, 5173 .versions = (X86CPUVersionDefinition[]) { 5174 { .version = 1 }, 5175 { 5176 .version = 2, 5177 .props = (PropValue[]) { 5178 { "model-id", 5179 "AMD EPYC-Milan-v2 Processor" }, 5180 { "vaes", "on" }, 5181 { "vpclmulqdq", "on" }, 5182 { "stibp-always-on", "on" }, 5183 { "amd-psfd", "on" }, 5184 { "no-nested-data-bp", "on" }, 5185 { "lfence-always-serializing", "on" }, 5186 { "null-sel-clr-base", "on" }, 5187 { /* end of list */ } 5188 }, 5189 .cache_info = &epyc_milan_v2_cache_info 5190 }, 5191 { /* end of list */ } 5192 } 5193 }, 5194 { 5195 .name = "EPYC-Genoa", 5196 .level = 0xd, 5197 .vendor = CPUID_VENDOR_AMD, 5198 .family = 25, 5199 .model = 17, 5200 .stepping = 0, 5201 .features[FEAT_1_EDX] = 5202 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5203 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5204 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5205 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5206 CPUID_VME | CPUID_FP87, 5207 .features[FEAT_1_ECX] = 5208 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5209 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5210 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5211 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5212 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5213 CPUID_EXT_SSE3, 5214 .features[FEAT_8000_0001_EDX] = 5215 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5216 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5217 CPUID_EXT2_SYSCALL, 5218 .features[FEAT_8000_0001_ECX] = 5219 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5220 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5221 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5222 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5223 .features[FEAT_8000_0008_EBX] = 5224 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5225 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5226 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5227 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5228 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5229 .features[FEAT_8000_0021_EAX] = 5230 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 5231 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5232 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5233 CPUID_8000_0021_EAX_AUTO_IBRS, 5234 .features[FEAT_7_0_EBX] = 5235 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5236 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5237 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5238 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5239 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5240 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5241 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5242 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5243 .features[FEAT_7_0_ECX] = 5244 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5245 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5246 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5247 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5248 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5249 CPUID_7_0_ECX_RDPID, 5250 .features[FEAT_7_0_EDX] = 5251 CPUID_7_0_EDX_FSRM, 5252 .features[FEAT_7_1_EAX] = 5253 CPUID_7_1_EAX_AVX512_BF16, 5254 .features[FEAT_XSAVE] = 5255 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5256 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5257 .features[FEAT_6_EAX] = 5258 CPUID_6_EAX_ARAT, 5259 .features[FEAT_SVM] = 5260 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5261 CPUID_SVM_SVME_ADDR_CHK, 5262 .xlevel = 0x80000022, 5263 .model_id = "AMD EPYC-Genoa Processor", 5264 .cache_info = &epyc_genoa_cache_info, 5265 }, 5266 }; 5267 5268 /* 5269 * We resolve CPU model aliases using -v1 when using "-machine 5270 * none", but this is just for compatibility while libvirt isn't 5271 * adapted to resolve CPU model versions before creating VMs. 5272 * See "Runnability guarantee of CPU models" at 5273 * docs/about/deprecated.rst. 5274 */ 5275 X86CPUVersion default_cpu_version = 1; 5276 5277 void x86_cpu_set_default_version(X86CPUVersion version) 5278 { 5279 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5280 assert(version != CPU_VERSION_AUTO); 5281 default_cpu_version = version; 5282 } 5283 5284 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5285 { 5286 int v = 0; 5287 const X86CPUVersionDefinition *vdef = 5288 x86_cpu_def_get_versions(model->cpudef); 5289 while (vdef->version) { 5290 v = vdef->version; 5291 vdef++; 5292 } 5293 return v; 5294 } 5295 5296 /* Return the actual version being used for a specific CPU model */ 5297 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5298 { 5299 X86CPUVersion v = model->version; 5300 if (v == CPU_VERSION_AUTO) { 5301 v = default_cpu_version; 5302 } 5303 if (v == CPU_VERSION_LATEST) { 5304 return x86_cpu_model_last_version(model); 5305 } 5306 return v; 5307 } 5308 5309 static Property max_x86_cpu_properties[] = { 5310 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5311 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5312 DEFINE_PROP_END_OF_LIST() 5313 }; 5314 5315 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5316 { 5317 Object *obj = OBJECT(dev); 5318 5319 if (!object_property_get_int(obj, "family", &error_abort)) { 5320 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5321 object_property_set_int(obj, "family", 15, &error_abort); 5322 object_property_set_int(obj, "model", 107, &error_abort); 5323 object_property_set_int(obj, "stepping", 1, &error_abort); 5324 } else { 5325 object_property_set_int(obj, "family", 6, &error_abort); 5326 object_property_set_int(obj, "model", 6, &error_abort); 5327 object_property_set_int(obj, "stepping", 3, &error_abort); 5328 } 5329 } 5330 5331 x86_cpu_realizefn(dev, errp); 5332 } 5333 5334 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5335 { 5336 DeviceClass *dc = DEVICE_CLASS(oc); 5337 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5338 5339 xcc->ordering = 9; 5340 5341 xcc->model_description = 5342 "Enables all features supported by the accelerator in the current host"; 5343 5344 device_class_set_props(dc, max_x86_cpu_properties); 5345 dc->realize = max_x86_cpu_realize; 5346 } 5347 5348 static void max_x86_cpu_initfn(Object *obj) 5349 { 5350 X86CPU *cpu = X86_CPU(obj); 5351 5352 /* We can't fill the features array here because we don't know yet if 5353 * "migratable" is true or false. 5354 */ 5355 cpu->max_features = true; 5356 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5357 5358 /* 5359 * these defaults are used for TCG and all other accelerators 5360 * besides KVM and HVF, which overwrite these values 5361 */ 5362 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5363 &error_abort); 5364 object_property_set_str(OBJECT(cpu), "model-id", 5365 "QEMU TCG CPU version " QEMU_HW_VERSION, 5366 &error_abort); 5367 } 5368 5369 static const TypeInfo max_x86_cpu_type_info = { 5370 .name = X86_CPU_TYPE_NAME("max"), 5371 .parent = TYPE_X86_CPU, 5372 .instance_init = max_x86_cpu_initfn, 5373 .class_init = max_x86_cpu_class_init, 5374 }; 5375 5376 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5377 { 5378 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5379 5380 switch (f->type) { 5381 case CPUID_FEATURE_WORD: 5382 { 5383 const char *reg = get_register_name_32(f->cpuid.reg); 5384 assert(reg); 5385 return g_strdup_printf("CPUID.%02XH:%s", 5386 f->cpuid.eax, reg); 5387 } 5388 case MSR_FEATURE_WORD: 5389 return g_strdup_printf("MSR(%02XH)", 5390 f->msr.index); 5391 } 5392 5393 return NULL; 5394 } 5395 5396 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5397 { 5398 FeatureWord w; 5399 5400 for (w = 0; w < FEATURE_WORDS; w++) { 5401 if (cpu->filtered_features[w]) { 5402 return true; 5403 } 5404 } 5405 5406 return false; 5407 } 5408 5409 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5410 const char *verbose_prefix) 5411 { 5412 CPUX86State *env = &cpu->env; 5413 FeatureWordInfo *f = &feature_word_info[w]; 5414 int i; 5415 5416 if (!cpu->force_features) { 5417 env->features[w] &= ~mask; 5418 } 5419 cpu->filtered_features[w] |= mask; 5420 5421 if (!verbose_prefix) { 5422 return; 5423 } 5424 5425 for (i = 0; i < 64; ++i) { 5426 if ((1ULL << i) & mask) { 5427 g_autofree char *feat_word_str = feature_word_description(f, i); 5428 warn_report("%s: %s%s%s [bit %d]", 5429 verbose_prefix, 5430 feat_word_str, 5431 f->feat_names[i] ? "." : "", 5432 f->feat_names[i] ? f->feat_names[i] : "", i); 5433 } 5434 } 5435 } 5436 5437 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5438 const char *name, void *opaque, 5439 Error **errp) 5440 { 5441 X86CPU *cpu = X86_CPU(obj); 5442 CPUX86State *env = &cpu->env; 5443 int64_t value; 5444 5445 value = (env->cpuid_version >> 8) & 0xf; 5446 if (value == 0xf) { 5447 value += (env->cpuid_version >> 20) & 0xff; 5448 } 5449 visit_type_int(v, name, &value, errp); 5450 } 5451 5452 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5453 const char *name, void *opaque, 5454 Error **errp) 5455 { 5456 X86CPU *cpu = X86_CPU(obj); 5457 CPUX86State *env = &cpu->env; 5458 const int64_t min = 0; 5459 const int64_t max = 0xff + 0xf; 5460 int64_t value; 5461 5462 if (!visit_type_int(v, name, &value, errp)) { 5463 return; 5464 } 5465 if (value < min || value > max) { 5466 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5467 name ? name : "null", value, min, max); 5468 return; 5469 } 5470 5471 env->cpuid_version &= ~0xff00f00; 5472 if (value > 0x0f) { 5473 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5474 } else { 5475 env->cpuid_version |= value << 8; 5476 } 5477 } 5478 5479 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5480 const char *name, void *opaque, 5481 Error **errp) 5482 { 5483 X86CPU *cpu = X86_CPU(obj); 5484 CPUX86State *env = &cpu->env; 5485 int64_t value; 5486 5487 value = (env->cpuid_version >> 4) & 0xf; 5488 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5489 visit_type_int(v, name, &value, errp); 5490 } 5491 5492 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5493 const char *name, void *opaque, 5494 Error **errp) 5495 { 5496 X86CPU *cpu = X86_CPU(obj); 5497 CPUX86State *env = &cpu->env; 5498 const int64_t min = 0; 5499 const int64_t max = 0xff; 5500 int64_t value; 5501 5502 if (!visit_type_int(v, name, &value, errp)) { 5503 return; 5504 } 5505 if (value < min || value > max) { 5506 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5507 name ? name : "null", value, min, max); 5508 return; 5509 } 5510 5511 env->cpuid_version &= ~0xf00f0; 5512 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5513 } 5514 5515 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5516 const char *name, void *opaque, 5517 Error **errp) 5518 { 5519 X86CPU *cpu = X86_CPU(obj); 5520 CPUX86State *env = &cpu->env; 5521 int64_t value; 5522 5523 value = env->cpuid_version & 0xf; 5524 visit_type_int(v, name, &value, errp); 5525 } 5526 5527 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5528 const char *name, void *opaque, 5529 Error **errp) 5530 { 5531 X86CPU *cpu = X86_CPU(obj); 5532 CPUX86State *env = &cpu->env; 5533 const int64_t min = 0; 5534 const int64_t max = 0xf; 5535 int64_t value; 5536 5537 if (!visit_type_int(v, name, &value, errp)) { 5538 return; 5539 } 5540 if (value < min || value > max) { 5541 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5542 name ? name : "null", value, min, max); 5543 return; 5544 } 5545 5546 env->cpuid_version &= ~0xf; 5547 env->cpuid_version |= value & 0xf; 5548 } 5549 5550 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5551 { 5552 X86CPU *cpu = X86_CPU(obj); 5553 CPUX86State *env = &cpu->env; 5554 char *value; 5555 5556 value = g_malloc(CPUID_VENDOR_SZ + 1); 5557 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5558 env->cpuid_vendor3); 5559 return value; 5560 } 5561 5562 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5563 Error **errp) 5564 { 5565 X86CPU *cpu = X86_CPU(obj); 5566 CPUX86State *env = &cpu->env; 5567 int i; 5568 5569 if (strlen(value) != CPUID_VENDOR_SZ) { 5570 error_setg(errp, "value of property 'vendor' must consist of" 5571 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5572 return; 5573 } 5574 5575 env->cpuid_vendor1 = 0; 5576 env->cpuid_vendor2 = 0; 5577 env->cpuid_vendor3 = 0; 5578 for (i = 0; i < 4; i++) { 5579 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5580 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5581 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5582 } 5583 } 5584 5585 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5586 { 5587 X86CPU *cpu = X86_CPU(obj); 5588 CPUX86State *env = &cpu->env; 5589 char *value; 5590 int i; 5591 5592 value = g_malloc(48 + 1); 5593 for (i = 0; i < 48; i++) { 5594 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5595 } 5596 value[48] = '\0'; 5597 return value; 5598 } 5599 5600 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5601 Error **errp) 5602 { 5603 X86CPU *cpu = X86_CPU(obj); 5604 CPUX86State *env = &cpu->env; 5605 int c, len, i; 5606 5607 if (model_id == NULL) { 5608 model_id = ""; 5609 } 5610 len = strlen(model_id); 5611 memset(env->cpuid_model, 0, 48); 5612 for (i = 0; i < 48; i++) { 5613 if (i >= len) { 5614 c = '\0'; 5615 } else { 5616 c = (uint8_t)model_id[i]; 5617 } 5618 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5619 } 5620 } 5621 5622 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5623 void *opaque, Error **errp) 5624 { 5625 X86CPU *cpu = X86_CPU(obj); 5626 int64_t value; 5627 5628 value = cpu->env.tsc_khz * 1000; 5629 visit_type_int(v, name, &value, errp); 5630 } 5631 5632 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5633 void *opaque, Error **errp) 5634 { 5635 X86CPU *cpu = X86_CPU(obj); 5636 const int64_t min = 0; 5637 const int64_t max = INT64_MAX; 5638 int64_t value; 5639 5640 if (!visit_type_int(v, name, &value, errp)) { 5641 return; 5642 } 5643 if (value < min || value > max) { 5644 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5645 name ? name : "null", value, min, max); 5646 return; 5647 } 5648 5649 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5650 } 5651 5652 /* Generic getter for "feature-words" and "filtered-features" properties */ 5653 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5654 const char *name, void *opaque, 5655 Error **errp) 5656 { 5657 uint64_t *array = (uint64_t *)opaque; 5658 FeatureWord w; 5659 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5660 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5661 X86CPUFeatureWordInfoList *list = NULL; 5662 5663 for (w = 0; w < FEATURE_WORDS; w++) { 5664 FeatureWordInfo *wi = &feature_word_info[w]; 5665 /* 5666 * We didn't have MSR features when "feature-words" was 5667 * introduced. Therefore skipped other type entries. 5668 */ 5669 if (wi->type != CPUID_FEATURE_WORD) { 5670 continue; 5671 } 5672 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5673 qwi->cpuid_input_eax = wi->cpuid.eax; 5674 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5675 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5676 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5677 qwi->features = array[w]; 5678 5679 /* List will be in reverse order, but order shouldn't matter */ 5680 list_entries[w].next = list; 5681 list_entries[w].value = &word_infos[w]; 5682 list = &list_entries[w]; 5683 } 5684 5685 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5686 } 5687 5688 /* Convert all '_' in a feature string option name to '-', to make feature 5689 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5690 */ 5691 static inline void feat2prop(char *s) 5692 { 5693 while ((s = strchr(s, '_'))) { 5694 *s = '-'; 5695 } 5696 } 5697 5698 /* Return the feature property name for a feature flag bit */ 5699 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5700 { 5701 const char *name; 5702 /* XSAVE components are automatically enabled by other features, 5703 * so return the original feature name instead 5704 */ 5705 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5706 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5707 5708 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5709 x86_ext_save_areas[comp].bits) { 5710 w = x86_ext_save_areas[comp].feature; 5711 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5712 } 5713 } 5714 5715 assert(bitnr < 64); 5716 assert(w < FEATURE_WORDS); 5717 name = feature_word_info[w].feat_names[bitnr]; 5718 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5719 return name; 5720 } 5721 5722 /* Compatibility hack to maintain legacy +-feat semantic, 5723 * where +-feat overwrites any feature set by 5724 * feat=on|feat even if the later is parsed after +-feat 5725 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5726 */ 5727 static GList *plus_features, *minus_features; 5728 5729 static gint compare_string(gconstpointer a, gconstpointer b) 5730 { 5731 return g_strcmp0(a, b); 5732 } 5733 5734 /* Parse "+feature,-feature,feature=foo" CPU feature string 5735 */ 5736 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5737 Error **errp) 5738 { 5739 char *featurestr; /* Single 'key=value" string being parsed */ 5740 static bool cpu_globals_initialized; 5741 bool ambiguous = false; 5742 5743 if (cpu_globals_initialized) { 5744 return; 5745 } 5746 cpu_globals_initialized = true; 5747 5748 if (!features) { 5749 return; 5750 } 5751 5752 for (featurestr = strtok(features, ","); 5753 featurestr; 5754 featurestr = strtok(NULL, ",")) { 5755 const char *name; 5756 const char *val = NULL; 5757 char *eq = NULL; 5758 char num[32]; 5759 GlobalProperty *prop; 5760 5761 /* Compatibility syntax: */ 5762 if (featurestr[0] == '+') { 5763 plus_features = g_list_append(plus_features, 5764 g_strdup(featurestr + 1)); 5765 continue; 5766 } else if (featurestr[0] == '-') { 5767 minus_features = g_list_append(minus_features, 5768 g_strdup(featurestr + 1)); 5769 continue; 5770 } 5771 5772 eq = strchr(featurestr, '='); 5773 if (eq) { 5774 *eq++ = 0; 5775 val = eq; 5776 } else { 5777 val = "on"; 5778 } 5779 5780 feat2prop(featurestr); 5781 name = featurestr; 5782 5783 if (g_list_find_custom(plus_features, name, compare_string)) { 5784 warn_report("Ambiguous CPU model string. " 5785 "Don't mix both \"+%s\" and \"%s=%s\"", 5786 name, name, val); 5787 ambiguous = true; 5788 } 5789 if (g_list_find_custom(minus_features, name, compare_string)) { 5790 warn_report("Ambiguous CPU model string. " 5791 "Don't mix both \"-%s\" and \"%s=%s\"", 5792 name, name, val); 5793 ambiguous = true; 5794 } 5795 5796 /* Special case: */ 5797 if (!strcmp(name, "tsc-freq")) { 5798 int ret; 5799 uint64_t tsc_freq; 5800 5801 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5802 if (ret < 0 || tsc_freq > INT64_MAX) { 5803 error_setg(errp, "bad numerical value %s", val); 5804 return; 5805 } 5806 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5807 val = num; 5808 name = "tsc-frequency"; 5809 } 5810 5811 prop = g_new0(typeof(*prop), 1); 5812 prop->driver = typename; 5813 prop->property = g_strdup(name); 5814 prop->value = g_strdup(val); 5815 qdev_prop_register_global(prop); 5816 } 5817 5818 if (ambiguous) { 5819 warn_report("Compatibility of ambiguous CPU model " 5820 "strings won't be kept on future QEMU versions"); 5821 } 5822 } 5823 5824 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5825 5826 /* Build a list with the name of all features on a feature word array */ 5827 static void x86_cpu_list_feature_names(FeatureWordArray features, 5828 strList **list) 5829 { 5830 strList **tail = list; 5831 FeatureWord w; 5832 5833 for (w = 0; w < FEATURE_WORDS; w++) { 5834 uint64_t filtered = features[w]; 5835 int i; 5836 for (i = 0; i < 64; i++) { 5837 if (filtered & (1ULL << i)) { 5838 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5839 } 5840 } 5841 } 5842 } 5843 5844 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5845 const char *name, void *opaque, 5846 Error **errp) 5847 { 5848 X86CPU *xc = X86_CPU(obj); 5849 strList *result = NULL; 5850 5851 x86_cpu_list_feature_names(xc->filtered_features, &result); 5852 visit_type_strList(v, "unavailable-features", &result, errp); 5853 } 5854 5855 /* Print all cpuid feature names in featureset 5856 */ 5857 static void listflags(GList *features) 5858 { 5859 size_t len = 0; 5860 GList *tmp; 5861 5862 for (tmp = features; tmp; tmp = tmp->next) { 5863 const char *name = tmp->data; 5864 if ((len + strlen(name) + 1) >= 75) { 5865 qemu_printf("\n"); 5866 len = 0; 5867 } 5868 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5869 len += strlen(name) + 1; 5870 } 5871 qemu_printf("\n"); 5872 } 5873 5874 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5875 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5876 { 5877 ObjectClass *class_a = (ObjectClass *)a; 5878 ObjectClass *class_b = (ObjectClass *)b; 5879 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5880 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5881 int ret; 5882 5883 if (cc_a->ordering != cc_b->ordering) { 5884 ret = cc_a->ordering - cc_b->ordering; 5885 } else { 5886 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5887 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5888 ret = strcmp(name_a, name_b); 5889 } 5890 return ret; 5891 } 5892 5893 static GSList *get_sorted_cpu_model_list(void) 5894 { 5895 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5896 list = g_slist_sort(list, x86_cpu_list_compare); 5897 return list; 5898 } 5899 5900 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5901 { 5902 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5903 char *r = object_property_get_str(obj, "model-id", &error_abort); 5904 object_unref(obj); 5905 return r; 5906 } 5907 5908 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5909 { 5910 X86CPUVersion version; 5911 5912 if (!cc->model || !cc->model->is_alias) { 5913 return NULL; 5914 } 5915 version = x86_cpu_model_resolve_version(cc->model); 5916 if (version <= 0) { 5917 return NULL; 5918 } 5919 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5920 } 5921 5922 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5923 { 5924 ObjectClass *oc = data; 5925 X86CPUClass *cc = X86_CPU_CLASS(oc); 5926 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5927 g_autofree char *desc = g_strdup(cc->model_description); 5928 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5929 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5930 5931 if (!desc && alias_of) { 5932 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5933 desc = g_strdup("(alias configured by machine type)"); 5934 } else { 5935 desc = g_strdup_printf("(alias of %s)", alias_of); 5936 } 5937 } 5938 if (!desc && cc->model && cc->model->note) { 5939 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5940 } 5941 if (!desc) { 5942 desc = g_strdup_printf("%s", model_id); 5943 } 5944 5945 if (cc->model && cc->model->cpudef->deprecation_note) { 5946 g_autofree char *olddesc = desc; 5947 desc = g_strdup_printf("%s (deprecated)", olddesc); 5948 } 5949 5950 qemu_printf(" %-20s %s\n", name, desc); 5951 } 5952 5953 /* list available CPU models and flags */ 5954 void x86_cpu_list(void) 5955 { 5956 int i, j; 5957 GSList *list; 5958 GList *names = NULL; 5959 5960 qemu_printf("Available CPUs:\n"); 5961 list = get_sorted_cpu_model_list(); 5962 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5963 g_slist_free(list); 5964 5965 names = NULL; 5966 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5967 FeatureWordInfo *fw = &feature_word_info[i]; 5968 for (j = 0; j < 64; j++) { 5969 if (fw->feat_names[j]) { 5970 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5971 } 5972 } 5973 } 5974 5975 names = g_list_sort(names, (GCompareFunc)strcmp); 5976 5977 qemu_printf("\nRecognized CPUID flags:\n"); 5978 listflags(names); 5979 qemu_printf("\n"); 5980 g_list_free(names); 5981 } 5982 5983 #ifndef CONFIG_USER_ONLY 5984 5985 /* Check for missing features that may prevent the CPU class from 5986 * running using the current machine and accelerator. 5987 */ 5988 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5989 strList **list) 5990 { 5991 strList **tail = list; 5992 X86CPU *xc; 5993 Error *err = NULL; 5994 5995 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5996 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5997 return; 5998 } 5999 6000 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6001 6002 x86_cpu_expand_features(xc, &err); 6003 if (err) { 6004 /* Errors at x86_cpu_expand_features should never happen, 6005 * but in case it does, just report the model as not 6006 * runnable at all using the "type" property. 6007 */ 6008 QAPI_LIST_APPEND(tail, g_strdup("type")); 6009 error_free(err); 6010 } 6011 6012 x86_cpu_filter_features(xc, false); 6013 6014 x86_cpu_list_feature_names(xc->filtered_features, tail); 6015 6016 object_unref(OBJECT(xc)); 6017 } 6018 6019 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6020 { 6021 ObjectClass *oc = data; 6022 X86CPUClass *cc = X86_CPU_CLASS(oc); 6023 CpuDefinitionInfoList **cpu_list = user_data; 6024 CpuDefinitionInfo *info; 6025 6026 info = g_malloc0(sizeof(*info)); 6027 info->name = x86_cpu_class_get_model_name(cc); 6028 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6029 info->has_unavailable_features = true; 6030 info->q_typename = g_strdup(object_class_get_name(oc)); 6031 info->migration_safe = cc->migration_safe; 6032 info->has_migration_safe = true; 6033 info->q_static = cc->static_model; 6034 if (cc->model && cc->model->cpudef->deprecation_note) { 6035 info->deprecated = true; 6036 } else { 6037 info->deprecated = false; 6038 } 6039 /* 6040 * Old machine types won't report aliases, so that alias translation 6041 * doesn't break compatibility with previous QEMU versions. 6042 */ 6043 if (default_cpu_version != CPU_VERSION_LEGACY) { 6044 info->alias_of = x86_cpu_class_get_alias_of(cc); 6045 } 6046 6047 QAPI_LIST_PREPEND(*cpu_list, info); 6048 } 6049 6050 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6051 { 6052 CpuDefinitionInfoList *cpu_list = NULL; 6053 GSList *list = get_sorted_cpu_model_list(); 6054 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6055 g_slist_free(list); 6056 return cpu_list; 6057 } 6058 6059 #endif /* !CONFIG_USER_ONLY */ 6060 6061 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6062 { 6063 FeatureWordInfo *wi = &feature_word_info[w]; 6064 uint64_t r = 0; 6065 uint64_t unavail = 0; 6066 6067 if (kvm_enabled()) { 6068 switch (wi->type) { 6069 case CPUID_FEATURE_WORD: 6070 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6071 wi->cpuid.ecx, 6072 wi->cpuid.reg); 6073 break; 6074 case MSR_FEATURE_WORD: 6075 r = kvm_arch_get_supported_msr_feature(kvm_state, 6076 wi->msr.index); 6077 break; 6078 } 6079 } else if (hvf_enabled()) { 6080 if (wi->type != CPUID_FEATURE_WORD) { 6081 return 0; 6082 } 6083 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6084 wi->cpuid.ecx, 6085 wi->cpuid.reg); 6086 } else if (tcg_enabled()) { 6087 r = wi->tcg_features; 6088 } else { 6089 return ~0; 6090 } 6091 6092 switch (w) { 6093 #ifndef TARGET_X86_64 6094 case FEAT_8000_0001_EDX: 6095 /* 6096 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6097 * way for userspace to get out of its 32-bit jail, we can leave 6098 * the LM bit set. 6099 */ 6100 unavail = tcg_enabled() 6101 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6102 : CPUID_EXT2_LM; 6103 break; 6104 #endif 6105 6106 case FEAT_8000_0007_EBX: 6107 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6108 /* Disable AMD machine check architecture for Intel CPU. */ 6109 unavail = ~0; 6110 } 6111 break; 6112 6113 case FEAT_7_0_EBX: 6114 #ifndef CONFIG_USER_ONLY 6115 if (!check_sgx_support()) { 6116 unavail = CPUID_7_0_EBX_SGX; 6117 } 6118 #endif 6119 break; 6120 case FEAT_7_0_ECX: 6121 #ifndef CONFIG_USER_ONLY 6122 if (!check_sgx_support()) { 6123 unavail = CPUID_7_0_ECX_SGX_LC; 6124 } 6125 #endif 6126 break; 6127 6128 default: 6129 break; 6130 } 6131 6132 r &= ~unavail; 6133 if (cpu && cpu->migratable) { 6134 r &= x86_cpu_get_migratable_flags(cpu, w); 6135 } 6136 return r; 6137 } 6138 6139 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6140 uint32_t *eax, uint32_t *ebx, 6141 uint32_t *ecx, uint32_t *edx) 6142 { 6143 if (kvm_enabled()) { 6144 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6145 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6146 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6147 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6148 } else if (hvf_enabled()) { 6149 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6150 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6151 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6152 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6153 } else { 6154 *eax = 0; 6155 *ebx = 0; 6156 *ecx = 0; 6157 *edx = 0; 6158 } 6159 } 6160 6161 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6162 uint32_t *eax, uint32_t *ebx, 6163 uint32_t *ecx, uint32_t *edx) 6164 { 6165 uint32_t level, unused; 6166 6167 /* Only return valid host leaves. */ 6168 switch (func) { 6169 case 2: 6170 case 4: 6171 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6172 break; 6173 case 0x80000005: 6174 case 0x80000006: 6175 case 0x8000001d: 6176 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6177 break; 6178 default: 6179 return; 6180 } 6181 6182 if (func > level) { 6183 *eax = 0; 6184 *ebx = 0; 6185 *ecx = 0; 6186 *edx = 0; 6187 } else { 6188 host_cpuid(func, index, eax, ebx, ecx, edx); 6189 } 6190 } 6191 6192 /* 6193 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6194 */ 6195 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6196 { 6197 PropValue *pv; 6198 for (pv = props; pv->prop; pv++) { 6199 if (!pv->value) { 6200 continue; 6201 } 6202 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6203 &error_abort); 6204 } 6205 } 6206 6207 /* 6208 * Apply properties for the CPU model version specified in model. 6209 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6210 */ 6211 6212 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6213 { 6214 const X86CPUVersionDefinition *vdef; 6215 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6216 6217 if (version == CPU_VERSION_LEGACY) { 6218 return; 6219 } 6220 6221 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6222 PropValue *p; 6223 6224 for (p = vdef->props; p && p->prop; p++) { 6225 object_property_parse(OBJECT(cpu), p->prop, p->value, 6226 &error_abort); 6227 } 6228 6229 if (vdef->version == version) { 6230 break; 6231 } 6232 } 6233 6234 /* 6235 * If we reached the end of the list, version number was invalid 6236 */ 6237 assert(vdef->version == version); 6238 } 6239 6240 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6241 X86CPUModel *model) 6242 { 6243 const X86CPUVersionDefinition *vdef; 6244 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6245 const CPUCaches *cache_info = model->cpudef->cache_info; 6246 6247 if (version == CPU_VERSION_LEGACY) { 6248 return cache_info; 6249 } 6250 6251 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6252 if (vdef->cache_info) { 6253 cache_info = vdef->cache_info; 6254 } 6255 6256 if (vdef->version == version) { 6257 break; 6258 } 6259 } 6260 6261 assert(vdef->version == version); 6262 return cache_info; 6263 } 6264 6265 /* 6266 * Load data from X86CPUDefinition into a X86CPU object. 6267 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6268 */ 6269 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6270 { 6271 const X86CPUDefinition *def = model->cpudef; 6272 CPUX86State *env = &cpu->env; 6273 FeatureWord w; 6274 6275 /*NOTE: any property set by this function should be returned by 6276 * x86_cpu_static_props(), so static expansion of 6277 * query-cpu-model-expansion is always complete. 6278 */ 6279 6280 /* CPU models only set _minimum_ values for level/xlevel: */ 6281 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6282 &error_abort); 6283 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6284 &error_abort); 6285 6286 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6287 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6288 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6289 &error_abort); 6290 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6291 &error_abort); 6292 for (w = 0; w < FEATURE_WORDS; w++) { 6293 env->features[w] = def->features[w]; 6294 } 6295 6296 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6297 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6298 6299 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6300 6301 /* sysenter isn't supported in compatibility mode on AMD, 6302 * syscall isn't supported in compatibility mode on Intel. 6303 * Normally we advertise the actual CPU vendor, but you can 6304 * override this using the 'vendor' property if you want to use 6305 * KVM's sysenter/syscall emulation in compatibility mode and 6306 * when doing cross vendor migration 6307 */ 6308 6309 /* 6310 * vendor property is set here but then overloaded with the 6311 * host cpu vendor for KVM and HVF. 6312 */ 6313 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6314 6315 x86_cpu_apply_version_props(cpu, model); 6316 6317 /* 6318 * Properties in versioned CPU model are not user specified features. 6319 * We can simply clear env->user_features here since it will be filled later 6320 * in x86_cpu_expand_features() based on plus_features and minus_features. 6321 */ 6322 memset(&env->user_features, 0, sizeof(env->user_features)); 6323 } 6324 6325 static const gchar *x86_gdb_arch_name(CPUState *cs) 6326 { 6327 #ifdef TARGET_X86_64 6328 return "i386:x86-64"; 6329 #else 6330 return "i386"; 6331 #endif 6332 } 6333 6334 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6335 { 6336 X86CPUModel *model = data; 6337 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6338 CPUClass *cc = CPU_CLASS(oc); 6339 6340 xcc->model = model; 6341 xcc->migration_safe = true; 6342 cc->deprecation_note = model->cpudef->deprecation_note; 6343 } 6344 6345 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6346 { 6347 g_autofree char *typename = x86_cpu_type_name(name); 6348 TypeInfo ti = { 6349 .name = typename, 6350 .parent = TYPE_X86_CPU, 6351 .class_init = x86_cpu_cpudef_class_init, 6352 .class_data = model, 6353 }; 6354 6355 type_register(&ti); 6356 } 6357 6358 6359 /* 6360 * register builtin_x86_defs; 6361 * "max", "base" and subclasses ("host") are not registered here. 6362 * See x86_cpu_register_types for all model registrations. 6363 */ 6364 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6365 { 6366 X86CPUModel *m; 6367 const X86CPUVersionDefinition *vdef; 6368 6369 /* AMD aliases are handled at runtime based on CPUID vendor, so 6370 * they shouldn't be set on the CPU model table. 6371 */ 6372 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6373 /* catch mistakes instead of silently truncating model_id when too long */ 6374 assert(def->model_id && strlen(def->model_id) <= 48); 6375 6376 /* Unversioned model: */ 6377 m = g_new0(X86CPUModel, 1); 6378 m->cpudef = def; 6379 m->version = CPU_VERSION_AUTO; 6380 m->is_alias = true; 6381 x86_register_cpu_model_type(def->name, m); 6382 6383 /* Versioned models: */ 6384 6385 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6386 g_autofree char *name = 6387 x86_cpu_versioned_model_name(def, vdef->version); 6388 6389 m = g_new0(X86CPUModel, 1); 6390 m->cpudef = def; 6391 m->version = vdef->version; 6392 m->note = vdef->note; 6393 x86_register_cpu_model_type(name, m); 6394 6395 if (vdef->alias) { 6396 X86CPUModel *am = g_new0(X86CPUModel, 1); 6397 am->cpudef = def; 6398 am->version = vdef->version; 6399 am->is_alias = true; 6400 x86_register_cpu_model_type(vdef->alias, am); 6401 } 6402 } 6403 6404 } 6405 6406 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6407 { 6408 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6409 return 57; /* 57 bits virtual */ 6410 } else { 6411 return 48; /* 48 bits virtual */ 6412 } 6413 } 6414 6415 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6416 uint32_t *eax, uint32_t *ebx, 6417 uint32_t *ecx, uint32_t *edx) 6418 { 6419 X86CPU *cpu = env_archcpu(env); 6420 CPUState *cs = env_cpu(env); 6421 uint32_t limit; 6422 uint32_t signature[3]; 6423 X86CPUTopoInfo topo_info; 6424 uint32_t cores_per_pkg; 6425 uint32_t threads_per_pkg; 6426 6427 topo_info.dies_per_pkg = env->nr_dies; 6428 topo_info.modules_per_die = env->nr_modules; 6429 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; 6430 topo_info.threads_per_core = cs->nr_threads; 6431 6432 cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * 6433 topo_info.dies_per_pkg; 6434 threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; 6435 6436 /* Calculate & apply limits for different index ranges */ 6437 if (index >= 0xC0000000) { 6438 limit = env->cpuid_xlevel2; 6439 } else if (index >= 0x80000000) { 6440 limit = env->cpuid_xlevel; 6441 } else if (index >= 0x40000000) { 6442 limit = 0x40000001; 6443 } else { 6444 limit = env->cpuid_level; 6445 } 6446 6447 if (index > limit) { 6448 /* Intel documentation states that invalid EAX input will 6449 * return the same information as EAX=cpuid_level 6450 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6451 */ 6452 index = env->cpuid_level; 6453 } 6454 6455 switch(index) { 6456 case 0: 6457 *eax = env->cpuid_level; 6458 *ebx = env->cpuid_vendor1; 6459 *edx = env->cpuid_vendor2; 6460 *ecx = env->cpuid_vendor3; 6461 break; 6462 case 1: 6463 *eax = env->cpuid_version; 6464 *ebx = (cpu->apic_id << 24) | 6465 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6466 *ecx = env->features[FEAT_1_ECX]; 6467 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6468 *ecx |= CPUID_EXT_OSXSAVE; 6469 } 6470 *edx = env->features[FEAT_1_EDX]; 6471 if (threads_per_pkg > 1) { 6472 *ebx |= threads_per_pkg << 16; 6473 *edx |= CPUID_HT; 6474 } 6475 if (!cpu->enable_pmu) { 6476 *ecx &= ~CPUID_EXT_PDCM; 6477 } 6478 break; 6479 case 2: 6480 /* cache info: needed for Pentium Pro compatibility */ 6481 if (cpu->cache_info_passthrough) { 6482 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6483 break; 6484 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6485 *eax = *ebx = *ecx = *edx = 0; 6486 break; 6487 } 6488 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6489 *ebx = 0; 6490 if (!cpu->enable_l3_cache) { 6491 *ecx = 0; 6492 } else { 6493 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6494 } 6495 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6496 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6497 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6498 break; 6499 case 4: 6500 /* cache info: needed for Core compatibility */ 6501 if (cpu->cache_info_passthrough) { 6502 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6503 /* 6504 * QEMU has its own number of cores/logical cpus, 6505 * set 24..14, 31..26 bit to configured values 6506 */ 6507 if (*eax & 31) { 6508 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6509 6510 *eax &= ~0xFC000000; 6511 *eax |= max_core_ids_in_package(&topo_info) << 26; 6512 if (host_vcpus_per_cache > threads_per_pkg) { 6513 *eax &= ~0x3FFC000; 6514 6515 /* Share the cache at package level. */ 6516 *eax |= max_thread_ids_for_cache(&topo_info, 6517 CPU_TOPO_LEVEL_PACKAGE) << 14; 6518 } 6519 } 6520 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6521 *eax = *ebx = *ecx = *edx = 0; 6522 } else { 6523 *eax = 0; 6524 6525 switch (count) { 6526 case 0: /* L1 dcache info */ 6527 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6528 &topo_info, 6529 eax, ebx, ecx, edx); 6530 if (!cpu->l1_cache_per_core) { 6531 *eax &= ~MAKE_64BIT_MASK(14, 12); 6532 } 6533 break; 6534 case 1: /* L1 icache info */ 6535 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6536 &topo_info, 6537 eax, ebx, ecx, edx); 6538 if (!cpu->l1_cache_per_core) { 6539 *eax &= ~MAKE_64BIT_MASK(14, 12); 6540 } 6541 break; 6542 case 2: /* L2 cache info */ 6543 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6544 &topo_info, 6545 eax, ebx, ecx, edx); 6546 break; 6547 case 3: /* L3 cache info */ 6548 if (cpu->enable_l3_cache) { 6549 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6550 &topo_info, 6551 eax, ebx, ecx, edx); 6552 break; 6553 } 6554 /* fall through */ 6555 default: /* end of info */ 6556 *eax = *ebx = *ecx = *edx = 0; 6557 break; 6558 } 6559 } 6560 break; 6561 case 5: 6562 /* MONITOR/MWAIT Leaf */ 6563 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6564 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6565 *ecx = cpu->mwait.ecx; /* flags */ 6566 *edx = cpu->mwait.edx; /* mwait substates */ 6567 break; 6568 case 6: 6569 /* Thermal and Power Leaf */ 6570 *eax = env->features[FEAT_6_EAX]; 6571 *ebx = 0; 6572 *ecx = 0; 6573 *edx = 0; 6574 break; 6575 case 7: 6576 /* Structured Extended Feature Flags Enumeration Leaf */ 6577 if (count == 0) { 6578 /* Maximum ECX value for sub-leaves */ 6579 *eax = env->cpuid_level_func7; 6580 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6581 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6582 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6583 *ecx |= CPUID_7_0_ECX_OSPKE; 6584 } 6585 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6586 } else if (count == 1) { 6587 *eax = env->features[FEAT_7_1_EAX]; 6588 *edx = env->features[FEAT_7_1_EDX]; 6589 *ebx = 0; 6590 *ecx = 0; 6591 } else if (count == 2) { 6592 *edx = env->features[FEAT_7_2_EDX]; 6593 *eax = 0; 6594 *ebx = 0; 6595 *ecx = 0; 6596 } else { 6597 *eax = 0; 6598 *ebx = 0; 6599 *ecx = 0; 6600 *edx = 0; 6601 } 6602 break; 6603 case 9: 6604 /* Direct Cache Access Information Leaf */ 6605 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6606 *ebx = 0; 6607 *ecx = 0; 6608 *edx = 0; 6609 break; 6610 case 0xA: 6611 /* Architectural Performance Monitoring Leaf */ 6612 if (cpu->enable_pmu) { 6613 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6614 } else { 6615 *eax = 0; 6616 *ebx = 0; 6617 *ecx = 0; 6618 *edx = 0; 6619 } 6620 break; 6621 case 0xB: 6622 /* Extended Topology Enumeration Leaf */ 6623 if (!cpu->enable_cpuid_0xb) { 6624 *eax = *ebx = *ecx = *edx = 0; 6625 break; 6626 } 6627 6628 *ecx = count & 0xff; 6629 *edx = cpu->apic_id; 6630 6631 switch (count) { 6632 case 0: 6633 *eax = apicid_core_offset(&topo_info); 6634 *ebx = topo_info.threads_per_core; 6635 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6636 break; 6637 case 1: 6638 *eax = apicid_pkg_offset(&topo_info); 6639 *ebx = threads_per_pkg; 6640 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6641 break; 6642 default: 6643 *eax = 0; 6644 *ebx = 0; 6645 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6646 } 6647 6648 assert(!(*eax & ~0x1f)); 6649 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6650 break; 6651 case 0x1C: 6652 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6653 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6654 *edx = 0; 6655 } 6656 break; 6657 case 0x1F: 6658 /* V2 Extended Topology Enumeration Leaf */ 6659 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6660 *eax = *ebx = *ecx = *edx = 0; 6661 break; 6662 } 6663 6664 encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); 6665 break; 6666 case 0xD: { 6667 /* Processor Extended State */ 6668 *eax = 0; 6669 *ebx = 0; 6670 *ecx = 0; 6671 *edx = 0; 6672 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6673 break; 6674 } 6675 6676 if (count == 0) { 6677 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6678 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6679 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6680 /* 6681 * The initial value of xcr0 and ebx == 0, On host without kvm 6682 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6683 * even through guest update xcr0, this will crash some legacy guest 6684 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6685 */ 6686 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6687 } else if (count == 1) { 6688 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6689 x86_cpu_xsave_xss_components(cpu); 6690 6691 *eax = env->features[FEAT_XSAVE]; 6692 *ebx = xsave_area_size(xstate, true); 6693 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6694 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6695 if (kvm_enabled() && cpu->enable_pmu && 6696 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6697 (*eax & CPUID_XSAVE_XSAVES)) { 6698 *ecx |= XSTATE_ARCH_LBR_MASK; 6699 } else { 6700 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6701 } 6702 } else if (count == 0xf && cpu->enable_pmu 6703 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6704 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6705 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6706 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6707 6708 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6709 *eax = esa->size; 6710 *ebx = esa->offset; 6711 *ecx = esa->ecx & 6712 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6713 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6714 *eax = esa->size; 6715 *ebx = 0; 6716 *ecx = 1; 6717 } 6718 } 6719 break; 6720 } 6721 case 0x12: 6722 #ifndef CONFIG_USER_ONLY 6723 if (!kvm_enabled() || 6724 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6725 *eax = *ebx = *ecx = *edx = 0; 6726 break; 6727 } 6728 6729 /* 6730 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6731 * the EPC properties, e.g. confidentiality and integrity, from the 6732 * host's first EPC section, i.e. assume there is one EPC section or 6733 * that all EPC sections have the same security properties. 6734 */ 6735 if (count > 1) { 6736 uint64_t epc_addr, epc_size; 6737 6738 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6739 *eax = *ebx = *ecx = *edx = 0; 6740 break; 6741 } 6742 host_cpuid(index, 2, eax, ebx, ecx, edx); 6743 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6744 *ebx = (uint32_t)(epc_addr >> 32); 6745 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6746 *edx = (uint32_t)(epc_size >> 32); 6747 break; 6748 } 6749 6750 /* 6751 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6752 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6753 * supports. Features can be further restricted by userspace, but not 6754 * made more permissive. 6755 */ 6756 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6757 6758 if (count == 0) { 6759 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6760 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6761 } else { 6762 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6763 *ebx &= 0; /* ebx reserve */ 6764 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6765 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6766 6767 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6768 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6769 6770 /* Access to PROVISIONKEY requires additional credentials. */ 6771 if ((*eax & (1U << 4)) && 6772 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6773 *eax &= ~(1U << 4); 6774 } 6775 } 6776 #endif 6777 break; 6778 case 0x14: { 6779 /* Intel Processor Trace Enumeration */ 6780 *eax = 0; 6781 *ebx = 0; 6782 *ecx = 0; 6783 *edx = 0; 6784 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6785 !kvm_enabled()) { 6786 break; 6787 } 6788 6789 /* 6790 * If these are changed, they should stay in sync with 6791 * x86_cpu_filter_features(). 6792 */ 6793 if (count == 0) { 6794 *eax = INTEL_PT_MAX_SUBLEAF; 6795 *ebx = INTEL_PT_MINIMAL_EBX; 6796 *ecx = INTEL_PT_MINIMAL_ECX; 6797 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6798 *ecx |= CPUID_14_0_ECX_LIP; 6799 } 6800 } else if (count == 1) { 6801 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6802 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6803 } 6804 break; 6805 } 6806 case 0x1D: { 6807 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6808 *eax = 0; 6809 *ebx = 0; 6810 *ecx = 0; 6811 *edx = 0; 6812 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6813 break; 6814 } 6815 6816 if (count == 0) { 6817 /* Highest numbered palette subleaf */ 6818 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6819 } else if (count == 1) { 6820 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6821 (INTEL_AMX_BYTES_PER_TILE << 16); 6822 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6823 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6824 } 6825 break; 6826 } 6827 case 0x1E: { 6828 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6829 *eax = 0; 6830 *ebx = 0; 6831 *ecx = 0; 6832 *edx = 0; 6833 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6834 break; 6835 } 6836 6837 if (count == 0) { 6838 /* Highest numbered palette subleaf */ 6839 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6840 } 6841 break; 6842 } 6843 case 0x40000000: 6844 /* 6845 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6846 * set here, but we restrict to TCG none the less. 6847 */ 6848 if (tcg_enabled() && cpu->expose_tcg) { 6849 memcpy(signature, "TCGTCGTCGTCG", 12); 6850 *eax = 0x40000001; 6851 *ebx = signature[0]; 6852 *ecx = signature[1]; 6853 *edx = signature[2]; 6854 } else { 6855 *eax = 0; 6856 *ebx = 0; 6857 *ecx = 0; 6858 *edx = 0; 6859 } 6860 break; 6861 case 0x40000001: 6862 *eax = 0; 6863 *ebx = 0; 6864 *ecx = 0; 6865 *edx = 0; 6866 break; 6867 case 0x80000000: 6868 *eax = env->cpuid_xlevel; 6869 *ebx = env->cpuid_vendor1; 6870 *edx = env->cpuid_vendor2; 6871 *ecx = env->cpuid_vendor3; 6872 break; 6873 case 0x80000001: 6874 *eax = env->cpuid_version; 6875 *ebx = 0; 6876 *ecx = env->features[FEAT_8000_0001_ECX]; 6877 *edx = env->features[FEAT_8000_0001_EDX]; 6878 6879 /* The Linux kernel checks for the CMPLegacy bit and 6880 * discards multiple thread information if it is set. 6881 * So don't set it here for Intel to make Linux guests happy. 6882 */ 6883 if (threads_per_pkg > 1) { 6884 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6885 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6886 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6887 *ecx |= 1 << 1; /* CmpLegacy bit */ 6888 } 6889 } 6890 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6891 !(env->hflags & HF_LMA_MASK)) { 6892 *edx &= ~CPUID_EXT2_SYSCALL; 6893 } 6894 break; 6895 case 0x80000002: 6896 case 0x80000003: 6897 case 0x80000004: 6898 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6899 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6900 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6901 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6902 break; 6903 case 0x80000005: 6904 /* cache info (L1 cache) */ 6905 if (cpu->cache_info_passthrough) { 6906 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6907 break; 6908 } 6909 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6910 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6911 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6912 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6913 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6914 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6915 break; 6916 case 0x80000006: 6917 /* cache info (L2 cache) */ 6918 if (cpu->cache_info_passthrough) { 6919 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6920 break; 6921 } 6922 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6923 (L2_DTLB_2M_ENTRIES << 16) | 6924 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6925 (L2_ITLB_2M_ENTRIES); 6926 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6927 (L2_DTLB_4K_ENTRIES << 16) | 6928 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6929 (L2_ITLB_4K_ENTRIES); 6930 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6931 cpu->enable_l3_cache ? 6932 env->cache_info_amd.l3_cache : NULL, 6933 ecx, edx); 6934 break; 6935 case 0x80000007: 6936 *eax = 0; 6937 *ebx = env->features[FEAT_8000_0007_EBX]; 6938 *ecx = 0; 6939 *edx = env->features[FEAT_8000_0007_EDX]; 6940 break; 6941 case 0x80000008: 6942 /* virtual & phys address size in low 2 bytes. */ 6943 *eax = cpu->phys_bits; 6944 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6945 /* 64 bit processor */ 6946 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6947 *eax |= (cpu->guest_phys_bits << 16); 6948 } 6949 *ebx = env->features[FEAT_8000_0008_EBX]; 6950 if (threads_per_pkg > 1) { 6951 /* 6952 * Bits 15:12 is "The number of bits in the initial 6953 * Core::X86::Apic::ApicId[ApicId] value that indicate 6954 * thread ID within a package". 6955 * Bits 7:0 is "The number of threads in the package is NC+1" 6956 */ 6957 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6958 (threads_per_pkg - 1); 6959 } else { 6960 *ecx = 0; 6961 } 6962 *edx = 0; 6963 break; 6964 case 0x8000000A: 6965 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6966 *eax = 0x00000001; /* SVM Revision */ 6967 *ebx = 0x00000010; /* nr of ASIDs */ 6968 *ecx = 0; 6969 *edx = env->features[FEAT_SVM]; /* optional features */ 6970 } else { 6971 *eax = 0; 6972 *ebx = 0; 6973 *ecx = 0; 6974 *edx = 0; 6975 } 6976 break; 6977 case 0x8000001D: 6978 *eax = 0; 6979 if (cpu->cache_info_passthrough) { 6980 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6981 break; 6982 } 6983 switch (count) { 6984 case 0: /* L1 dcache info */ 6985 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6986 &topo_info, eax, ebx, ecx, edx); 6987 break; 6988 case 1: /* L1 icache info */ 6989 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6990 &topo_info, eax, ebx, ecx, edx); 6991 break; 6992 case 2: /* L2 cache info */ 6993 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6994 &topo_info, eax, ebx, ecx, edx); 6995 break; 6996 case 3: /* L3 cache info */ 6997 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6998 &topo_info, eax, ebx, ecx, edx); 6999 break; 7000 default: /* end of info */ 7001 *eax = *ebx = *ecx = *edx = 0; 7002 break; 7003 } 7004 if (cpu->amd_topoext_features_only) { 7005 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7006 } 7007 break; 7008 case 0x8000001E: 7009 if (cpu->core_id <= 255) { 7010 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 7011 } else { 7012 *eax = 0; 7013 *ebx = 0; 7014 *ecx = 0; 7015 *edx = 0; 7016 } 7017 break; 7018 case 0xC0000000: 7019 *eax = env->cpuid_xlevel2; 7020 *ebx = 0; 7021 *ecx = 0; 7022 *edx = 0; 7023 break; 7024 case 0xC0000001: 7025 /* Support for VIA CPU's CPUID instruction */ 7026 *eax = env->cpuid_version; 7027 *ebx = 0; 7028 *ecx = 0; 7029 *edx = env->features[FEAT_C000_0001_EDX]; 7030 break; 7031 case 0xC0000002: 7032 case 0xC0000003: 7033 case 0xC0000004: 7034 /* Reserved for the future, and now filled with zero */ 7035 *eax = 0; 7036 *ebx = 0; 7037 *ecx = 0; 7038 *edx = 0; 7039 break; 7040 case 0x8000001F: 7041 *eax = *ebx = *ecx = *edx = 0; 7042 if (sev_enabled()) { 7043 *eax = 0x2; 7044 *eax |= sev_es_enabled() ? 0x8 : 0; 7045 *eax |= sev_snp_enabled() ? 0x10 : 0; 7046 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7047 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7048 } 7049 break; 7050 case 0x80000021: 7051 *eax = env->features[FEAT_8000_0021_EAX]; 7052 *ebx = *ecx = *edx = 0; 7053 break; 7054 default: 7055 /* reserved values: zero */ 7056 *eax = 0; 7057 *ebx = 0; 7058 *ecx = 0; 7059 *edx = 0; 7060 break; 7061 } 7062 } 7063 7064 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7065 { 7066 #ifndef CONFIG_USER_ONLY 7067 /* Those default values are defined in Skylake HW */ 7068 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7069 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7070 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7071 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7072 #endif 7073 } 7074 7075 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7076 { 7077 CPUState *cs = CPU(obj); 7078 X86CPU *cpu = X86_CPU(cs); 7079 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7080 CPUX86State *env = &cpu->env; 7081 target_ulong cr4; 7082 uint64_t xcr0; 7083 int i; 7084 7085 if (xcc->parent_phases.hold) { 7086 xcc->parent_phases.hold(obj, type); 7087 } 7088 7089 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7090 7091 env->old_exception = -1; 7092 7093 /* init to reset state */ 7094 env->int_ctl = 0; 7095 env->hflags2 |= HF2_GIF_MASK; 7096 env->hflags2 |= HF2_VGIF_MASK; 7097 env->hflags &= ~HF_GUEST_MASK; 7098 7099 cpu_x86_update_cr0(env, 0x60000010); 7100 env->a20_mask = ~0x0; 7101 env->smbase = 0x30000; 7102 env->msr_smi_count = 0; 7103 7104 env->idt.limit = 0xffff; 7105 env->gdt.limit = 0xffff; 7106 env->ldt.limit = 0xffff; 7107 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7108 env->tr.limit = 0xffff; 7109 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7110 7111 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7112 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7113 DESC_R_MASK | DESC_A_MASK); 7114 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7115 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7116 DESC_A_MASK); 7117 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7118 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7119 DESC_A_MASK); 7120 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7121 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7122 DESC_A_MASK); 7123 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7124 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7125 DESC_A_MASK); 7126 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7127 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7128 DESC_A_MASK); 7129 7130 env->eip = 0xfff0; 7131 env->regs[R_EDX] = env->cpuid_version; 7132 7133 env->eflags = 0x2; 7134 7135 /* FPU init */ 7136 for (i = 0; i < 8; i++) { 7137 env->fptags[i] = 1; 7138 } 7139 cpu_set_fpuc(env, 0x37f); 7140 7141 env->mxcsr = 0x1f80; 7142 /* All units are in INIT state. */ 7143 env->xstate_bv = 0; 7144 7145 env->pat = 0x0007040600070406ULL; 7146 7147 if (kvm_enabled()) { 7148 /* 7149 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7150 * a new CPU, use 1 instead to force a reset. 7151 */ 7152 if (env->tsc != 0) { 7153 env->tsc = 1; 7154 } 7155 } else { 7156 env->tsc = 0; 7157 } 7158 7159 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7160 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7161 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7162 } 7163 7164 memset(env->dr, 0, sizeof(env->dr)); 7165 env->dr[6] = DR6_FIXED_1; 7166 env->dr[7] = DR7_FIXED_1; 7167 cpu_breakpoint_remove_all(cs, BP_CPU); 7168 cpu_watchpoint_remove_all(cs, BP_CPU); 7169 7170 cr4 = 0; 7171 xcr0 = XSTATE_FP_MASK; 7172 7173 #ifdef CONFIG_USER_ONLY 7174 /* Enable all the features for user-mode. */ 7175 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7176 xcr0 |= XSTATE_SSE_MASK; 7177 } 7178 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7179 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7180 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7181 continue; 7182 } 7183 if (env->features[esa->feature] & esa->bits) { 7184 xcr0 |= 1ull << i; 7185 } 7186 } 7187 7188 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7189 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7190 } 7191 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7192 cr4 |= CR4_FSGSBASE_MASK; 7193 } 7194 #endif 7195 7196 env->xcr0 = xcr0; 7197 cpu_x86_update_cr4(env, cr4); 7198 7199 /* 7200 * SDM 11.11.5 requires: 7201 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7202 * - IA32_MTRR_PHYSMASKn.V = 0 7203 * All other bits are undefined. For simplification, zero it all. 7204 */ 7205 env->mtrr_deftype = 0; 7206 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7207 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7208 7209 env->interrupt_injected = -1; 7210 env->exception_nr = -1; 7211 env->exception_pending = 0; 7212 env->exception_injected = 0; 7213 env->exception_has_payload = false; 7214 env->exception_payload = 0; 7215 env->nmi_injected = false; 7216 env->triple_fault_pending = false; 7217 #if !defined(CONFIG_USER_ONLY) 7218 /* We hard-wire the BSP to the first CPU. */ 7219 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7220 7221 cs->halted = !cpu_is_bsp(cpu); 7222 7223 if (kvm_enabled()) { 7224 kvm_arch_reset_vcpu(cpu); 7225 } 7226 7227 x86_cpu_set_sgxlepubkeyhash(env); 7228 7229 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7230 7231 #endif 7232 } 7233 7234 void x86_cpu_after_reset(X86CPU *cpu) 7235 { 7236 #ifndef CONFIG_USER_ONLY 7237 if (kvm_enabled()) { 7238 kvm_arch_after_reset_vcpu(cpu); 7239 } 7240 7241 if (cpu->apic_state) { 7242 device_cold_reset(cpu->apic_state); 7243 } 7244 #endif 7245 } 7246 7247 static void mce_init(X86CPU *cpu) 7248 { 7249 CPUX86State *cenv = &cpu->env; 7250 unsigned int bank; 7251 7252 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7253 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7254 (CPUID_MCE | CPUID_MCA)) { 7255 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7256 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7257 cenv->mcg_ctl = ~(uint64_t)0; 7258 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7259 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7260 } 7261 } 7262 } 7263 7264 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7265 { 7266 if (*min < value) { 7267 *min = value; 7268 } 7269 } 7270 7271 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7272 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7273 { 7274 CPUX86State *env = &cpu->env; 7275 FeatureWordInfo *fi = &feature_word_info[w]; 7276 uint32_t eax = fi->cpuid.eax; 7277 uint32_t region = eax & 0xF0000000; 7278 7279 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7280 if (!env->features[w]) { 7281 return; 7282 } 7283 7284 switch (region) { 7285 case 0x00000000: 7286 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7287 break; 7288 case 0x80000000: 7289 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7290 break; 7291 case 0xC0000000: 7292 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7293 break; 7294 } 7295 7296 if (eax == 7) { 7297 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7298 fi->cpuid.ecx); 7299 } 7300 } 7301 7302 /* Calculate XSAVE components based on the configured CPU feature flags */ 7303 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7304 { 7305 CPUX86State *env = &cpu->env; 7306 int i; 7307 uint64_t mask; 7308 static bool request_perm; 7309 7310 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7311 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7312 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7313 env->features[FEAT_XSAVE_XSS_LO] = 0; 7314 env->features[FEAT_XSAVE_XSS_HI] = 0; 7315 return; 7316 } 7317 7318 mask = 0; 7319 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7320 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7321 if (env->features[esa->feature] & esa->bits) { 7322 mask |= (1ULL << i); 7323 } 7324 } 7325 7326 /* Only request permission for first vcpu */ 7327 if (kvm_enabled() && !request_perm) { 7328 kvm_request_xsave_components(cpu, mask); 7329 request_perm = true; 7330 } 7331 7332 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7333 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7334 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7335 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7336 } 7337 7338 /***** Steps involved on loading and filtering CPUID data 7339 * 7340 * When initializing and realizing a CPU object, the steps 7341 * involved in setting up CPUID data are: 7342 * 7343 * 1) Loading CPU model definition (X86CPUDefinition). This is 7344 * implemented by x86_cpu_load_model() and should be completely 7345 * transparent, as it is done automatically by instance_init. 7346 * No code should need to look at X86CPUDefinition structs 7347 * outside instance_init. 7348 * 7349 * 2) CPU expansion. This is done by realize before CPUID 7350 * filtering, and will make sure host/accelerator data is 7351 * loaded for CPU models that depend on host capabilities 7352 * (e.g. "host"). Done by x86_cpu_expand_features(). 7353 * 7354 * 3) CPUID filtering. This initializes extra data related to 7355 * CPUID, and checks if the host supports all capabilities 7356 * required by the CPU. Runnability of a CPU model is 7357 * determined at this step. Done by x86_cpu_filter_features(). 7358 * 7359 * Some operations don't require all steps to be performed. 7360 * More precisely: 7361 * 7362 * - CPU instance creation (instance_init) will run only CPU 7363 * model loading. CPU expansion can't run at instance_init-time 7364 * because host/accelerator data may be not available yet. 7365 * - CPU realization will perform both CPU model expansion and CPUID 7366 * filtering, and return an error in case one of them fails. 7367 * - query-cpu-definitions needs to run all 3 steps. It needs 7368 * to run CPUID filtering, as the 'unavailable-features' 7369 * field is set based on the filtering results. 7370 * - The query-cpu-model-expansion QMP command only needs to run 7371 * CPU model loading and CPU expansion. It should not filter 7372 * any CPUID data based on host capabilities. 7373 */ 7374 7375 /* Expand CPU configuration data, based on configured features 7376 * and host/accelerator capabilities when appropriate. 7377 */ 7378 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7379 { 7380 CPUX86State *env = &cpu->env; 7381 FeatureWord w; 7382 int i; 7383 GList *l; 7384 7385 for (l = plus_features; l; l = l->next) { 7386 const char *prop = l->data; 7387 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7388 return; 7389 } 7390 } 7391 7392 for (l = minus_features; l; l = l->next) { 7393 const char *prop = l->data; 7394 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7395 return; 7396 } 7397 } 7398 7399 /*TODO: Now cpu->max_features doesn't overwrite features 7400 * set using QOM properties, and we can convert 7401 * plus_features & minus_features to global properties 7402 * inside x86_cpu_parse_featurestr() too. 7403 */ 7404 if (cpu->max_features) { 7405 for (w = 0; w < FEATURE_WORDS; w++) { 7406 /* Override only features that weren't set explicitly 7407 * by the user. 7408 */ 7409 env->features[w] |= 7410 x86_cpu_get_supported_feature_word(cpu, w) & 7411 ~env->user_features[w] & 7412 ~feature_word_info[w].no_autoenable_flags; 7413 } 7414 } 7415 7416 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7417 FeatureDep *d = &feature_dependencies[i]; 7418 if (!(env->features[d->from.index] & d->from.mask)) { 7419 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7420 7421 /* Not an error unless the dependent feature was added explicitly. */ 7422 mark_unavailable_features(cpu, d->to.index, 7423 unavailable_features & env->user_features[d->to.index], 7424 "This feature depends on other features that were not requested"); 7425 7426 env->features[d->to.index] &= ~unavailable_features; 7427 } 7428 } 7429 7430 if (!kvm_enabled() || !cpu->expose_kvm) { 7431 env->features[FEAT_KVM] = 0; 7432 } 7433 7434 x86_cpu_enable_xsave_components(cpu); 7435 7436 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7437 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7438 if (cpu->full_cpuid_auto_level) { 7439 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7440 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7441 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7442 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7443 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7444 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7445 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7446 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7447 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7448 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7449 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7450 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7451 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7452 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7453 7454 /* Intel Processor Trace requires CPUID[0x14] */ 7455 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7456 if (cpu->intel_pt_auto_level) { 7457 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7458 } else if (cpu->env.cpuid_min_level < 0x14) { 7459 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7460 CPUID_7_0_EBX_INTEL_PT, 7461 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7462 } 7463 } 7464 7465 /* 7466 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7467 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7468 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7469 * cpu->vendor_cpuid_only has been unset for compatibility with older 7470 * machine types. 7471 */ 7472 if (x86_has_extended_topo(env->avail_cpu_topo) && 7473 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7474 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7475 } 7476 7477 /* SVM requires CPUID[0x8000000A] */ 7478 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7479 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7480 } 7481 7482 /* SEV requires CPUID[0x8000001F] */ 7483 if (sev_enabled()) { 7484 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7485 } 7486 7487 if (env->features[FEAT_8000_0021_EAX]) { 7488 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7489 } 7490 7491 /* SGX requires CPUID[0x12] for EPC enumeration */ 7492 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7493 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7494 } 7495 } 7496 7497 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7498 if (env->cpuid_level_func7 == UINT32_MAX) { 7499 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7500 } 7501 if (env->cpuid_level == UINT32_MAX) { 7502 env->cpuid_level = env->cpuid_min_level; 7503 } 7504 if (env->cpuid_xlevel == UINT32_MAX) { 7505 env->cpuid_xlevel = env->cpuid_min_xlevel; 7506 } 7507 if (env->cpuid_xlevel2 == UINT32_MAX) { 7508 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7509 } 7510 7511 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7512 return; 7513 } 7514 } 7515 7516 /* 7517 * Finishes initialization of CPUID data, filters CPU feature 7518 * words based on host availability of each feature. 7519 * 7520 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7521 */ 7522 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7523 { 7524 CPUX86State *env = &cpu->env; 7525 FeatureWord w; 7526 const char *prefix = NULL; 7527 7528 if (verbose) { 7529 prefix = accel_uses_host_cpuid() 7530 ? "host doesn't support requested feature" 7531 : "TCG doesn't support requested feature"; 7532 } 7533 7534 for (w = 0; w < FEATURE_WORDS; w++) { 7535 uint64_t host_feat = 7536 x86_cpu_get_supported_feature_word(NULL, w); 7537 uint64_t requested_features = env->features[w]; 7538 uint64_t unavailable_features = requested_features & ~host_feat; 7539 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7540 } 7541 7542 /* 7543 * Check that KVM actually allows the processor tracing features that 7544 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7545 */ 7546 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7547 kvm_enabled()) { 7548 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7549 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7550 7551 x86_cpu_get_supported_cpuid(0x14, 0, 7552 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7553 x86_cpu_get_supported_cpuid(0x14, 1, 7554 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7555 7556 if (!eax_0 || 7557 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7558 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7559 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7560 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7561 INTEL_PT_ADDR_RANGES_NUM) || 7562 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7563 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7564 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7565 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7566 /* 7567 * Processor Trace capabilities aren't configurable, so if the 7568 * host can't emulate the capabilities we report on 7569 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7570 */ 7571 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7572 } 7573 } 7574 } 7575 7576 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7577 { 7578 size_t len; 7579 7580 /* Hyper-V vendor id */ 7581 if (!cpu->hyperv_vendor) { 7582 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7583 &error_abort); 7584 } 7585 len = strlen(cpu->hyperv_vendor); 7586 if (len > 12) { 7587 warn_report("hv-vendor-id truncated to 12 characters"); 7588 len = 12; 7589 } 7590 memset(cpu->hyperv_vendor_id, 0, 12); 7591 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7592 7593 /* 'Hv#1' interface identification*/ 7594 cpu->hyperv_interface_id[0] = 0x31237648; 7595 cpu->hyperv_interface_id[1] = 0; 7596 cpu->hyperv_interface_id[2] = 0; 7597 cpu->hyperv_interface_id[3] = 0; 7598 7599 /* Hypervisor implementation limits */ 7600 cpu->hyperv_limits[0] = 64; 7601 cpu->hyperv_limits[1] = 0; 7602 cpu->hyperv_limits[2] = 0; 7603 } 7604 7605 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7606 { 7607 CPUState *cs = CPU(dev); 7608 X86CPU *cpu = X86_CPU(dev); 7609 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7610 CPUX86State *env = &cpu->env; 7611 Error *local_err = NULL; 7612 unsigned requested_lbr_fmt; 7613 7614 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7615 /* Use pc-relative instructions in system-mode */ 7616 tcg_cflags_set(cs, CF_PCREL); 7617 #endif 7618 7619 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7620 error_setg(errp, "apic-id property was not initialized properly"); 7621 return; 7622 } 7623 7624 /* 7625 * Process Hyper-V enlightenments. 7626 * Note: this currently has to happen before the expansion of CPU features. 7627 */ 7628 x86_cpu_hyperv_realize(cpu); 7629 7630 x86_cpu_expand_features(cpu, &local_err); 7631 if (local_err) { 7632 goto out; 7633 } 7634 7635 /* 7636 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7637 * with user-provided setting. 7638 */ 7639 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7640 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7641 error_setg(errp, "invalid lbr-fmt"); 7642 return; 7643 } 7644 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7645 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7646 } 7647 7648 /* 7649 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7650 * 3)vPMU LBR format matches that of host setting. 7651 */ 7652 requested_lbr_fmt = 7653 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7654 if (requested_lbr_fmt && kvm_enabled()) { 7655 uint64_t host_perf_cap = 7656 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 7657 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7658 7659 if (!cpu->enable_pmu) { 7660 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7661 return; 7662 } 7663 if (requested_lbr_fmt != host_lbr_fmt) { 7664 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7665 "the host value (0x%x).", 7666 requested_lbr_fmt, host_lbr_fmt); 7667 return; 7668 } 7669 } 7670 7671 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7672 7673 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7674 error_setg(&local_err, 7675 accel_uses_host_cpuid() ? 7676 "Host doesn't support requested features" : 7677 "TCG doesn't support requested features"); 7678 goto out; 7679 } 7680 7681 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7682 * CPUID[1].EDX. 7683 */ 7684 if (IS_AMD_CPU(env)) { 7685 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7686 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7687 & CPUID_EXT2_AMD_ALIASES); 7688 } 7689 7690 x86_cpu_set_sgxlepubkeyhash(env); 7691 7692 /* 7693 * note: the call to the framework needs to happen after feature expansion, 7694 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7695 * These may be set by the accel-specific code, 7696 * and the results are subsequently checked / assumed in this function. 7697 */ 7698 cpu_exec_realizefn(cs, &local_err); 7699 if (local_err != NULL) { 7700 error_propagate(errp, local_err); 7701 return; 7702 } 7703 7704 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7705 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7706 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7707 goto out; 7708 } 7709 7710 if (cpu->guest_phys_bits == -1) { 7711 /* 7712 * If it was not set by the user, or by the accelerator via 7713 * cpu_exec_realizefn, clear. 7714 */ 7715 cpu->guest_phys_bits = 0; 7716 } 7717 7718 if (cpu->ucode_rev == 0) { 7719 /* 7720 * The default is the same as KVM's. Note that this check 7721 * needs to happen after the evenual setting of ucode_rev in 7722 * accel-specific code in cpu_exec_realizefn. 7723 */ 7724 if (IS_AMD_CPU(env)) { 7725 cpu->ucode_rev = 0x01000065; 7726 } else { 7727 cpu->ucode_rev = 0x100000000ULL; 7728 } 7729 } 7730 7731 /* 7732 * mwait extended info: needed for Core compatibility 7733 * We always wake on interrupt even if host does not have the capability. 7734 * 7735 * requires the accel-specific code in cpu_exec_realizefn to 7736 * have already acquired the CPUID data into cpu->mwait. 7737 */ 7738 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7739 7740 /* For 64bit systems think about the number of physical bits to present. 7741 * ideally this should be the same as the host; anything other than matching 7742 * the host can cause incorrect guest behaviour. 7743 * QEMU used to pick the magic value of 40 bits that corresponds to 7744 * consumer AMD devices but nothing else. 7745 * 7746 * Note that this code assumes features expansion has already been done 7747 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7748 * phys_bits adjustments to match the host have been already done in 7749 * accel-specific code in cpu_exec_realizefn. 7750 */ 7751 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7752 if (cpu->phys_bits && 7753 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7754 cpu->phys_bits < 32)) { 7755 error_setg(errp, "phys-bits should be between 32 and %u " 7756 " (but is %u)", 7757 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7758 return; 7759 } 7760 /* 7761 * 0 means it was not explicitly set by the user (or by machine 7762 * compat_props or by the host code in host-cpu.c). 7763 * In this case, the default is the value used by TCG (40). 7764 */ 7765 if (cpu->phys_bits == 0) { 7766 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7767 } 7768 if (cpu->guest_phys_bits && 7769 (cpu->guest_phys_bits > cpu->phys_bits || 7770 cpu->guest_phys_bits < 32)) { 7771 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7772 " (but is %u)", 7773 cpu->phys_bits, cpu->guest_phys_bits); 7774 return; 7775 } 7776 } else { 7777 /* For 32 bit systems don't use the user set value, but keep 7778 * phys_bits consistent with what we tell the guest. 7779 */ 7780 if (cpu->phys_bits != 0) { 7781 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7782 return; 7783 } 7784 if (cpu->guest_phys_bits != 0) { 7785 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7786 return; 7787 } 7788 7789 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7790 cpu->phys_bits = 36; 7791 } else { 7792 cpu->phys_bits = 32; 7793 } 7794 } 7795 7796 /* Cache information initialization */ 7797 if (!cpu->legacy_cache) { 7798 const CPUCaches *cache_info = 7799 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7800 7801 if (!xcc->model || !cache_info) { 7802 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7803 error_setg(errp, 7804 "CPU model '%s' doesn't support legacy-cache=off", name); 7805 return; 7806 } 7807 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7808 *cache_info; 7809 } else { 7810 /* Build legacy cache information */ 7811 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7812 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7813 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7814 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7815 7816 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7817 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7818 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7819 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7820 7821 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7822 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7823 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7824 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7825 } 7826 7827 #ifndef CONFIG_USER_ONLY 7828 MachineState *ms = MACHINE(qdev_get_machine()); 7829 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7830 7831 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7832 x86_cpu_apic_create(cpu, &local_err); 7833 if (local_err != NULL) { 7834 goto out; 7835 } 7836 } 7837 #endif 7838 7839 mce_init(cpu); 7840 7841 x86_cpu_gdb_init(cs); 7842 qemu_init_vcpu(cs); 7843 7844 /* 7845 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7846 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7847 * based on inputs (sockets,cores,threads), it is still better to give 7848 * users a warning. 7849 * 7850 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7851 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7852 */ 7853 if (IS_AMD_CPU(env) && 7854 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7855 cs->nr_threads > 1) { 7856 warn_report_once("This family of AMD CPU doesn't support " 7857 "hyperthreading(%d). Please configure -smp " 7858 "options properly or try enabling topoext " 7859 "feature.", cs->nr_threads); 7860 } 7861 7862 #ifndef CONFIG_USER_ONLY 7863 x86_cpu_apic_realize(cpu, &local_err); 7864 if (local_err != NULL) { 7865 goto out; 7866 } 7867 #endif /* !CONFIG_USER_ONLY */ 7868 cpu_reset(cs); 7869 7870 xcc->parent_realize(dev, &local_err); 7871 7872 out: 7873 if (local_err != NULL) { 7874 error_propagate(errp, local_err); 7875 return; 7876 } 7877 } 7878 7879 static void x86_cpu_unrealizefn(DeviceState *dev) 7880 { 7881 X86CPU *cpu = X86_CPU(dev); 7882 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7883 7884 #ifndef CONFIG_USER_ONLY 7885 cpu_remove_sync(CPU(dev)); 7886 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7887 #endif 7888 7889 if (cpu->apic_state) { 7890 object_unparent(OBJECT(cpu->apic_state)); 7891 cpu->apic_state = NULL; 7892 } 7893 7894 xcc->parent_unrealize(dev); 7895 } 7896 7897 typedef struct BitProperty { 7898 FeatureWord w; 7899 uint64_t mask; 7900 } BitProperty; 7901 7902 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7903 void *opaque, Error **errp) 7904 { 7905 X86CPU *cpu = X86_CPU(obj); 7906 BitProperty *fp = opaque; 7907 uint64_t f = cpu->env.features[fp->w]; 7908 bool value = (f & fp->mask) == fp->mask; 7909 visit_type_bool(v, name, &value, errp); 7910 } 7911 7912 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7913 void *opaque, Error **errp) 7914 { 7915 DeviceState *dev = DEVICE(obj); 7916 X86CPU *cpu = X86_CPU(obj); 7917 BitProperty *fp = opaque; 7918 bool value; 7919 7920 if (dev->realized) { 7921 qdev_prop_set_after_realize(dev, name, errp); 7922 return; 7923 } 7924 7925 if (!visit_type_bool(v, name, &value, errp)) { 7926 return; 7927 } 7928 7929 if (value) { 7930 cpu->env.features[fp->w] |= fp->mask; 7931 } else { 7932 cpu->env.features[fp->w] &= ~fp->mask; 7933 } 7934 cpu->env.user_features[fp->w] |= fp->mask; 7935 } 7936 7937 /* Register a boolean property to get/set a single bit in a uint32_t field. 7938 * 7939 * The same property name can be registered multiple times to make it affect 7940 * multiple bits in the same FeatureWord. In that case, the getter will return 7941 * true only if all bits are set. 7942 */ 7943 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7944 const char *prop_name, 7945 FeatureWord w, 7946 int bitnr) 7947 { 7948 ObjectClass *oc = OBJECT_CLASS(xcc); 7949 BitProperty *fp; 7950 ObjectProperty *op; 7951 uint64_t mask = (1ULL << bitnr); 7952 7953 op = object_class_property_find(oc, prop_name); 7954 if (op) { 7955 fp = op->opaque; 7956 assert(fp->w == w); 7957 fp->mask |= mask; 7958 } else { 7959 fp = g_new0(BitProperty, 1); 7960 fp->w = w; 7961 fp->mask = mask; 7962 object_class_property_add(oc, prop_name, "bool", 7963 x86_cpu_get_bit_prop, 7964 x86_cpu_set_bit_prop, 7965 NULL, fp); 7966 } 7967 } 7968 7969 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7970 FeatureWord w, 7971 int bitnr) 7972 { 7973 FeatureWordInfo *fi = &feature_word_info[w]; 7974 const char *name = fi->feat_names[bitnr]; 7975 7976 if (!name) { 7977 return; 7978 } 7979 7980 /* Property names should use "-" instead of "_". 7981 * Old names containing underscores are registered as aliases 7982 * using object_property_add_alias() 7983 */ 7984 assert(!strchr(name, '_')); 7985 /* aliases don't use "|" delimiters anymore, they are registered 7986 * manually using object_property_add_alias() */ 7987 assert(!strchr(name, '|')); 7988 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7989 } 7990 7991 static void x86_cpu_post_initfn(Object *obj) 7992 { 7993 accel_cpu_instance_init(CPU(obj)); 7994 } 7995 7996 static void x86_cpu_init_default_topo(X86CPU *cpu) 7997 { 7998 CPUX86State *env = &cpu->env; 7999 8000 env->nr_modules = 1; 8001 env->nr_dies = 1; 8002 8003 /* SMT, core and package levels are set by default. */ 8004 set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); 8005 set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); 8006 set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); 8007 } 8008 8009 static void x86_cpu_initfn(Object *obj) 8010 { 8011 X86CPU *cpu = X86_CPU(obj); 8012 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8013 CPUX86State *env = &cpu->env; 8014 8015 x86_cpu_init_default_topo(cpu); 8016 8017 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8018 x86_cpu_get_feature_words, 8019 NULL, NULL, (void *)env->features); 8020 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8021 x86_cpu_get_feature_words, 8022 NULL, NULL, (void *)cpu->filtered_features); 8023 8024 object_property_add_alias(obj, "sse3", obj, "pni"); 8025 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8026 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8027 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8028 object_property_add_alias(obj, "xd", obj, "nx"); 8029 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8030 object_property_add_alias(obj, "i64", obj, "lm"); 8031 8032 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8033 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8034 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8035 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8036 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8037 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8038 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8039 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8040 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8041 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8042 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8043 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8044 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8045 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8046 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8047 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8048 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8049 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8050 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8051 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8052 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8053 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8054 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8055 8056 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8057 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8058 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8059 8060 if (xcc->model) { 8061 x86_cpu_load_model(cpu, xcc->model); 8062 } 8063 } 8064 8065 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8066 { 8067 X86CPU *cpu = X86_CPU(cs); 8068 8069 return cpu->apic_id; 8070 } 8071 8072 #if !defined(CONFIG_USER_ONLY) 8073 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8074 { 8075 X86CPU *cpu = X86_CPU(cs); 8076 8077 return cpu->env.cr[0] & CR0_PG_MASK; 8078 } 8079 #endif /* !CONFIG_USER_ONLY */ 8080 8081 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8082 { 8083 X86CPU *cpu = X86_CPU(cs); 8084 8085 cpu->env.eip = value; 8086 } 8087 8088 static vaddr x86_cpu_get_pc(CPUState *cs) 8089 { 8090 X86CPU *cpu = X86_CPU(cs); 8091 8092 /* Match cpu_get_tb_cpu_state. */ 8093 return cpu->env.eip + cpu->env.segs[R_CS].base; 8094 } 8095 8096 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8097 { 8098 X86CPU *cpu = X86_CPU(cs); 8099 CPUX86State *env = &cpu->env; 8100 8101 #if !defined(CONFIG_USER_ONLY) 8102 if (interrupt_request & CPU_INTERRUPT_POLL) { 8103 return CPU_INTERRUPT_POLL; 8104 } 8105 #endif 8106 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8107 return CPU_INTERRUPT_SIPI; 8108 } 8109 8110 if (env->hflags2 & HF2_GIF_MASK) { 8111 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8112 !(env->hflags & HF_SMM_MASK)) { 8113 return CPU_INTERRUPT_SMI; 8114 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8115 !(env->hflags2 & HF2_NMI_MASK)) { 8116 return CPU_INTERRUPT_NMI; 8117 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8118 return CPU_INTERRUPT_MCE; 8119 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8120 (((env->hflags2 & HF2_VINTR_MASK) && 8121 (env->hflags2 & HF2_HIF_MASK)) || 8122 (!(env->hflags2 & HF2_VINTR_MASK) && 8123 (env->eflags & IF_MASK && 8124 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8125 return CPU_INTERRUPT_HARD; 8126 #if !defined(CONFIG_USER_ONLY) 8127 } else if (env->hflags2 & HF2_VGIF_MASK) { 8128 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8129 (env->eflags & IF_MASK) && 8130 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8131 return CPU_INTERRUPT_VIRQ; 8132 } 8133 #endif 8134 } 8135 } 8136 8137 return 0; 8138 } 8139 8140 static bool x86_cpu_has_work(CPUState *cs) 8141 { 8142 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8143 } 8144 8145 int x86_mmu_index_pl(CPUX86State *env, unsigned pl) 8146 { 8147 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8148 int mmu_index_base = 8149 pl == 3 ? MMU_USER64_IDX : 8150 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8151 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8152 8153 return mmu_index_base + mmu_index_32; 8154 } 8155 8156 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8157 { 8158 CPUX86State *env = cpu_env(cs); 8159 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); 8160 } 8161 8162 static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) 8163 { 8164 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; 8165 int mmu_index_base = 8166 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8167 (pl < 3 && (env->eflags & AC_MASK) 8168 ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); 8169 8170 return mmu_index_base + mmu_index_32; 8171 } 8172 8173 int cpu_mmu_index_kernel(CPUX86State *env) 8174 { 8175 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); 8176 } 8177 8178 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8179 { 8180 X86CPU *cpu = X86_CPU(cs); 8181 CPUX86State *env = &cpu->env; 8182 8183 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8184 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8185 : bfd_mach_i386_i8086); 8186 8187 info->cap_arch = CS_ARCH_X86; 8188 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8189 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8190 : CS_MODE_16); 8191 info->cap_insn_unit = 1; 8192 info->cap_insn_split = 8; 8193 } 8194 8195 void x86_update_hflags(CPUX86State *env) 8196 { 8197 uint32_t hflags; 8198 #define HFLAG_COPY_MASK \ 8199 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8200 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8201 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8202 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8203 8204 hflags = env->hflags & HFLAG_COPY_MASK; 8205 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8206 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8207 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8208 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8209 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8210 8211 if (env->cr[4] & CR4_OSFXSR_MASK) { 8212 hflags |= HF_OSFXSR_MASK; 8213 } 8214 8215 if (env->efer & MSR_EFER_LMA) { 8216 hflags |= HF_LMA_MASK; 8217 } 8218 8219 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8220 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8221 } else { 8222 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8223 (DESC_B_SHIFT - HF_CS32_SHIFT); 8224 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8225 (DESC_B_SHIFT - HF_SS32_SHIFT); 8226 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8227 !(hflags & HF_CS32_MASK)) { 8228 hflags |= HF_ADDSEG_MASK; 8229 } else { 8230 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8231 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8232 } 8233 } 8234 env->hflags = hflags; 8235 } 8236 8237 static Property x86_cpu_properties[] = { 8238 #ifdef CONFIG_USER_ONLY 8239 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8240 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8241 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8242 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8243 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8244 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8245 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8246 #else 8247 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8248 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8249 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8250 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8251 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8252 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8253 #endif 8254 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8255 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8256 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8257 8258 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8259 HYPERV_SPINLOCK_NEVER_NOTIFY), 8260 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8261 HYPERV_FEAT_RELAXED, 0), 8262 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8263 HYPERV_FEAT_VAPIC, 0), 8264 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8265 HYPERV_FEAT_TIME, 0), 8266 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8267 HYPERV_FEAT_CRASH, 0), 8268 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8269 HYPERV_FEAT_RESET, 0), 8270 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8271 HYPERV_FEAT_VPINDEX, 0), 8272 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8273 HYPERV_FEAT_RUNTIME, 0), 8274 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8275 HYPERV_FEAT_SYNIC, 0), 8276 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8277 HYPERV_FEAT_STIMER, 0), 8278 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8279 HYPERV_FEAT_FREQUENCIES, 0), 8280 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8281 HYPERV_FEAT_REENLIGHTENMENT, 0), 8282 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8283 HYPERV_FEAT_TLBFLUSH, 0), 8284 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8285 HYPERV_FEAT_EVMCS, 0), 8286 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8287 HYPERV_FEAT_IPI, 0), 8288 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8289 HYPERV_FEAT_STIMER_DIRECT, 0), 8290 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8291 HYPERV_FEAT_AVIC, 0), 8292 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8293 HYPERV_FEAT_MSR_BITMAP, 0), 8294 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8295 HYPERV_FEAT_XMM_INPUT, 0), 8296 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8297 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8298 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8299 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8300 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8301 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8302 #ifdef CONFIG_SYNDBG 8303 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8304 HYPERV_FEAT_SYNDBG, 0), 8305 #endif 8306 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8307 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8308 8309 /* WS2008R2 identify by default */ 8310 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8311 0x3839), 8312 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8313 0x000A), 8314 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8315 0x0000), 8316 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8317 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8318 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8319 8320 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8321 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8322 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8323 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8324 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8325 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8326 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8327 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8328 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8329 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8330 UINT32_MAX), 8331 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8332 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8333 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8334 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8335 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8336 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8337 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8338 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8339 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8340 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8341 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8342 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8343 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8344 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8345 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8346 false), 8347 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8348 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8349 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8350 true), 8351 /* 8352 * lecacy_cache defaults to true unless the CPU model provides its 8353 * own cache information (see x86_cpu_load_def()). 8354 */ 8355 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8356 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8357 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8358 8359 /* 8360 * From "Requirements for Implementing the Microsoft 8361 * Hypervisor Interface": 8362 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8363 * 8364 * "Starting with Windows Server 2012 and Windows 8, if 8365 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8366 * the hypervisor imposes no specific limit to the number of VPs. 8367 * In this case, Windows Server 2012 guest VMs may use more than 8368 * 64 VPs, up to the maximum supported number of processors applicable 8369 * to the specific Windows version being used." 8370 */ 8371 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8372 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8373 false), 8374 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8375 true), 8376 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8377 DEFINE_PROP_END_OF_LIST() 8378 }; 8379 8380 #ifndef CONFIG_USER_ONLY 8381 #include "hw/core/sysemu-cpu-ops.h" 8382 8383 static const struct SysemuCPUOps i386_sysemu_ops = { 8384 .get_memory_mapping = x86_cpu_get_memory_mapping, 8385 .get_paging_enabled = x86_cpu_get_paging_enabled, 8386 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8387 .asidx_from_attrs = x86_asidx_from_attrs, 8388 .get_crash_info = x86_cpu_get_crash_info, 8389 .write_elf32_note = x86_cpu_write_elf32_note, 8390 .write_elf64_note = x86_cpu_write_elf64_note, 8391 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8392 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8393 .legacy_vmsd = &vmstate_x86_cpu, 8394 }; 8395 #endif 8396 8397 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8398 { 8399 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8400 CPUClass *cc = CPU_CLASS(oc); 8401 DeviceClass *dc = DEVICE_CLASS(oc); 8402 ResettableClass *rc = RESETTABLE_CLASS(oc); 8403 FeatureWord w; 8404 8405 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8406 &xcc->parent_realize); 8407 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8408 &xcc->parent_unrealize); 8409 device_class_set_props(dc, x86_cpu_properties); 8410 8411 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8412 &xcc->parent_phases); 8413 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8414 8415 cc->class_by_name = x86_cpu_class_by_name; 8416 cc->parse_features = x86_cpu_parse_featurestr; 8417 cc->has_work = x86_cpu_has_work; 8418 cc->mmu_index = x86_cpu_mmu_index; 8419 cc->dump_state = x86_cpu_dump_state; 8420 cc->set_pc = x86_cpu_set_pc; 8421 cc->get_pc = x86_cpu_get_pc; 8422 cc->gdb_read_register = x86_cpu_gdb_read_register; 8423 cc->gdb_write_register = x86_cpu_gdb_write_register; 8424 cc->get_arch_id = x86_cpu_get_arch_id; 8425 8426 #ifndef CONFIG_USER_ONLY 8427 cc->sysemu_ops = &i386_sysemu_ops; 8428 #endif /* !CONFIG_USER_ONLY */ 8429 8430 cc->gdb_arch_name = x86_gdb_arch_name; 8431 #ifdef TARGET_X86_64 8432 cc->gdb_core_xml_file = "i386-64bit.xml"; 8433 #else 8434 cc->gdb_core_xml_file = "i386-32bit.xml"; 8435 #endif 8436 cc->disas_set_info = x86_disas_set_info; 8437 8438 dc->user_creatable = true; 8439 8440 object_class_property_add(oc, "family", "int", 8441 x86_cpuid_version_get_family, 8442 x86_cpuid_version_set_family, NULL, NULL); 8443 object_class_property_add(oc, "model", "int", 8444 x86_cpuid_version_get_model, 8445 x86_cpuid_version_set_model, NULL, NULL); 8446 object_class_property_add(oc, "stepping", "int", 8447 x86_cpuid_version_get_stepping, 8448 x86_cpuid_version_set_stepping, NULL, NULL); 8449 object_class_property_add_str(oc, "vendor", 8450 x86_cpuid_get_vendor, 8451 x86_cpuid_set_vendor); 8452 object_class_property_add_str(oc, "model-id", 8453 x86_cpuid_get_model_id, 8454 x86_cpuid_set_model_id); 8455 object_class_property_add(oc, "tsc-frequency", "int", 8456 x86_cpuid_get_tsc_freq, 8457 x86_cpuid_set_tsc_freq, NULL, NULL); 8458 /* 8459 * The "unavailable-features" property has the same semantics as 8460 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8461 * QMP command: they list the features that would have prevented the 8462 * CPU from running if the "enforce" flag was set. 8463 */ 8464 object_class_property_add(oc, "unavailable-features", "strList", 8465 x86_cpu_get_unavailable_features, 8466 NULL, NULL, NULL); 8467 8468 #if !defined(CONFIG_USER_ONLY) 8469 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8470 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8471 #endif 8472 8473 for (w = 0; w < FEATURE_WORDS; w++) { 8474 int bitnr; 8475 for (bitnr = 0; bitnr < 64; bitnr++) { 8476 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8477 } 8478 } 8479 } 8480 8481 static const TypeInfo x86_cpu_type_info = { 8482 .name = TYPE_X86_CPU, 8483 .parent = TYPE_CPU, 8484 .instance_size = sizeof(X86CPU), 8485 .instance_align = __alignof(X86CPU), 8486 .instance_init = x86_cpu_initfn, 8487 .instance_post_init = x86_cpu_post_initfn, 8488 8489 .abstract = true, 8490 .class_size = sizeof(X86CPUClass), 8491 .class_init = x86_cpu_common_class_init, 8492 }; 8493 8494 /* "base" CPU model, used by query-cpu-model-expansion */ 8495 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8496 { 8497 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8498 8499 xcc->static_model = true; 8500 xcc->migration_safe = true; 8501 xcc->model_description = "base CPU model type with no features enabled"; 8502 xcc->ordering = 8; 8503 } 8504 8505 static const TypeInfo x86_base_cpu_type_info = { 8506 .name = X86_CPU_TYPE_NAME("base"), 8507 .parent = TYPE_X86_CPU, 8508 .class_init = x86_cpu_base_class_init, 8509 }; 8510 8511 static void x86_cpu_register_types(void) 8512 { 8513 int i; 8514 8515 type_register_static(&x86_cpu_type_info); 8516 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8517 x86_register_cpudef_types(&builtin_x86_defs[i]); 8518 } 8519 type_register_static(&max_x86_cpu_type_info); 8520 type_register_static(&x86_base_cpu_type_info); 8521 } 8522 8523 type_init(x86_cpu_register_types) 8524