1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #include "exec/watchpoint.h" 39 #ifndef CONFIG_USER_ONLY 40 #include "system/reset.h" 41 #include "qapi/qapi-commands-machine-target.h" 42 #include "system/address-spaces.h" 43 #include "hw/boards.h" 44 #include "hw/i386/sgx-epc.h" 45 #endif 46 47 #include "disas/capstone.h" 48 #include "cpu-internal.h" 49 50 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 51 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 52 uint32_t *eax, uint32_t *ebx, 53 uint32_t *ecx, uint32_t *edx); 54 55 /* Helpers for building CPUID[2] descriptors: */ 56 57 struct CPUID2CacheDescriptorInfo { 58 enum CacheType type; 59 int level; 60 int size; 61 int line_size; 62 int associativity; 63 }; 64 65 /* 66 * Known CPUID 2 cache descriptors. 67 * From Intel SDM Volume 2A, CPUID instruction 68 */ 69 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 70 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 71 .associativity = 4, .line_size = 32, }, 72 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 73 .associativity = 4, .line_size = 32, }, 74 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 75 .associativity = 4, .line_size = 64, }, 76 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 77 .associativity = 2, .line_size = 32, }, 78 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 79 .associativity = 4, .line_size = 32, }, 80 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 81 .associativity = 4, .line_size = 64, }, 82 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 83 .associativity = 6, .line_size = 64, }, 84 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 85 .associativity = 2, .line_size = 64, }, 86 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 87 .associativity = 8, .line_size = 64, }, 88 /* lines per sector is not supported cpuid2_cache_descriptor(), 89 * so descriptors 0x22, 0x23 are not included 90 */ 91 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 92 .associativity = 16, .line_size = 64, }, 93 /* lines per sector is not supported cpuid2_cache_descriptor(), 94 * so descriptors 0x25, 0x20 are not included 95 */ 96 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 97 .associativity = 8, .line_size = 64, }, 98 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 99 .associativity = 8, .line_size = 64, }, 100 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 107 .associativity = 4, .line_size = 32, }, 108 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 109 .associativity = 4, .line_size = 32, }, 110 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 111 .associativity = 4, .line_size = 64, }, 112 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 113 .associativity = 8, .line_size = 64, }, 114 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 115 .associativity = 12, .line_size = 64, }, 116 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 117 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 118 .associativity = 12, .line_size = 64, }, 119 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 120 .associativity = 16, .line_size = 64, }, 121 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 122 .associativity = 12, .line_size = 64, }, 123 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 124 .associativity = 16, .line_size = 64, }, 125 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 126 .associativity = 24, .line_size = 64, }, 127 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 128 .associativity = 8, .line_size = 64, }, 129 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 130 .associativity = 4, .line_size = 64, }, 131 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 132 .associativity = 4, .line_size = 64, }, 133 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 134 .associativity = 4, .line_size = 64, }, 135 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 136 .associativity = 4, .line_size = 64, }, 137 /* lines per sector is not supported cpuid2_cache_descriptor(), 138 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 139 */ 140 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 141 .associativity = 8, .line_size = 64, }, 142 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 143 .associativity = 2, .line_size = 64, }, 144 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 8, .line_size = 64, }, 146 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 147 .associativity = 8, .line_size = 32, }, 148 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 151 .associativity = 8, .line_size = 32, }, 152 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 153 .associativity = 8, .line_size = 32, }, 154 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 155 .associativity = 4, .line_size = 64, }, 156 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 157 .associativity = 8, .line_size = 64, }, 158 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 159 .associativity = 4, .line_size = 64, }, 160 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 161 .associativity = 4, .line_size = 64, }, 162 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 163 .associativity = 4, .line_size = 64, }, 164 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 165 .associativity = 8, .line_size = 64, }, 166 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 167 .associativity = 8, .line_size = 64, }, 168 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 169 .associativity = 8, .line_size = 64, }, 170 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 171 .associativity = 12, .line_size = 64, }, 172 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 173 .associativity = 12, .line_size = 64, }, 174 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 175 .associativity = 12, .line_size = 64, }, 176 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 177 .associativity = 16, .line_size = 64, }, 178 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 179 .associativity = 16, .line_size = 64, }, 180 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 181 .associativity = 16, .line_size = 64, }, 182 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 183 .associativity = 24, .line_size = 64, }, 184 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 185 .associativity = 24, .line_size = 64, }, 186 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 187 .associativity = 24, .line_size = 64, }, 188 }; 189 190 /* 191 * "CPUID leaf 2 does not report cache descriptor information, 192 * use CPUID leaf 4 to query cache parameters" 193 */ 194 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 195 196 /* 197 * Return a CPUID 2 cache descriptor for a given cache. 198 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 199 */ 200 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 201 { 202 int i; 203 204 assert(cache->size > 0); 205 assert(cache->level > 0); 206 assert(cache->line_size > 0); 207 assert(cache->associativity > 0); 208 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 209 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 210 if (d->level == cache->level && d->type == cache->type && 211 d->size == cache->size && d->line_size == cache->line_size && 212 d->associativity == cache->associativity) { 213 return i; 214 } 215 } 216 217 return CACHE_DESCRIPTOR_UNAVAILABLE; 218 } 219 220 /* CPUID Leaf 4 constants: */ 221 222 /* EAX: */ 223 #define CACHE_TYPE_D 1 224 #define CACHE_TYPE_I 2 225 #define CACHE_TYPE_UNIFIED 3 226 227 #define CACHE_LEVEL(l) (l << 5) 228 229 #define CACHE_SELF_INIT_LEVEL (1 << 8) 230 231 /* EDX: */ 232 #define CACHE_NO_INVD_SHARING (1 << 0) 233 #define CACHE_INCLUSIVE (1 << 1) 234 #define CACHE_COMPLEX_IDX (1 << 2) 235 236 /* Encode CacheType for CPUID[4].EAX */ 237 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 238 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 239 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 240 0 /* Invalid value */) 241 242 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 243 enum CpuTopologyLevel share_level) 244 { 245 uint32_t num_ids = 0; 246 247 switch (share_level) { 248 case CPU_TOPOLOGY_LEVEL_CORE: 249 num_ids = 1 << apicid_core_offset(topo_info); 250 break; 251 case CPU_TOPOLOGY_LEVEL_MODULE: 252 num_ids = 1 << apicid_module_offset(topo_info); 253 break; 254 case CPU_TOPOLOGY_LEVEL_DIE: 255 num_ids = 1 << apicid_die_offset(topo_info); 256 break; 257 case CPU_TOPOLOGY_LEVEL_SOCKET: 258 num_ids = 1 << apicid_pkg_offset(topo_info); 259 break; 260 default: 261 /* 262 * Currently there is no use case for THREAD, so use 263 * assert directly to facilitate debugging. 264 */ 265 g_assert_not_reached(); 266 } 267 268 return num_ids - 1; 269 } 270 271 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 272 { 273 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 274 apicid_core_offset(topo_info)); 275 return num_cores - 1; 276 } 277 278 /* Encode cache info for CPUID[4] */ 279 static void encode_cache_cpuid4(CPUCacheInfo *cache, 280 X86CPUTopoInfo *topo_info, 281 uint32_t *eax, uint32_t *ebx, 282 uint32_t *ecx, uint32_t *edx) 283 { 284 assert(cache->size == cache->line_size * cache->associativity * 285 cache->partitions * cache->sets); 286 287 *eax = CACHE_TYPE(cache->type) | 288 CACHE_LEVEL(cache->level) | 289 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 290 (max_core_ids_in_package(topo_info) << 26) | 291 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 292 293 assert(cache->line_size > 0); 294 assert(cache->partitions > 0); 295 assert(cache->associativity > 0); 296 /* We don't implement fully-associative caches */ 297 assert(cache->associativity < cache->sets); 298 *ebx = (cache->line_size - 1) | 299 ((cache->partitions - 1) << 12) | 300 ((cache->associativity - 1) << 22); 301 302 assert(cache->sets > 0); 303 *ecx = cache->sets - 1; 304 305 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 306 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 307 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 308 } 309 310 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 311 enum CpuTopologyLevel topo_level) 312 { 313 switch (topo_level) { 314 case CPU_TOPOLOGY_LEVEL_THREAD: 315 return 1; 316 case CPU_TOPOLOGY_LEVEL_CORE: 317 return topo_info->threads_per_core; 318 case CPU_TOPOLOGY_LEVEL_MODULE: 319 return x86_threads_per_module(topo_info); 320 case CPU_TOPOLOGY_LEVEL_DIE: 321 return x86_threads_per_die(topo_info); 322 case CPU_TOPOLOGY_LEVEL_SOCKET: 323 return x86_threads_per_pkg(topo_info); 324 default: 325 g_assert_not_reached(); 326 } 327 return 0; 328 } 329 330 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 331 enum CpuTopologyLevel topo_level) 332 { 333 switch (topo_level) { 334 case CPU_TOPOLOGY_LEVEL_THREAD: 335 return 0; 336 case CPU_TOPOLOGY_LEVEL_CORE: 337 return apicid_core_offset(topo_info); 338 case CPU_TOPOLOGY_LEVEL_MODULE: 339 return apicid_module_offset(topo_info); 340 case CPU_TOPOLOGY_LEVEL_DIE: 341 return apicid_die_offset(topo_info); 342 case CPU_TOPOLOGY_LEVEL_SOCKET: 343 return apicid_pkg_offset(topo_info); 344 default: 345 g_assert_not_reached(); 346 } 347 return 0; 348 } 349 350 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 351 { 352 switch (topo_level) { 353 case CPU_TOPOLOGY_LEVEL_INVALID: 354 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 355 case CPU_TOPOLOGY_LEVEL_THREAD: 356 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 357 case CPU_TOPOLOGY_LEVEL_CORE: 358 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 359 case CPU_TOPOLOGY_LEVEL_MODULE: 360 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 361 case CPU_TOPOLOGY_LEVEL_DIE: 362 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 363 default: 364 /* Other types are not supported in QEMU. */ 365 g_assert_not_reached(); 366 } 367 return 0; 368 } 369 370 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 371 X86CPUTopoInfo *topo_info, 372 uint32_t *eax, uint32_t *ebx, 373 uint32_t *ecx, uint32_t *edx) 374 { 375 X86CPU *cpu = env_archcpu(env); 376 unsigned long level, base_level, next_level; 377 uint32_t num_threads_next_level, offset_next_level; 378 379 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 380 381 /* 382 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 383 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 384 */ 385 level = CPU_TOPOLOGY_LEVEL_THREAD; 386 base_level = level; 387 for (int i = 0; i <= count; i++) { 388 level = find_next_bit(env->avail_cpu_topo, 389 CPU_TOPOLOGY_LEVEL_SOCKET, 390 base_level); 391 392 /* 393 * CPUID[0x1f] doesn't explicitly encode the package level, 394 * and it just encodes the invalid level (all fields are 0) 395 * into the last subleaf of 0x1f. 396 */ 397 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 398 level = CPU_TOPOLOGY_LEVEL_INVALID; 399 break; 400 } 401 /* Search the next level. */ 402 base_level = level + 1; 403 } 404 405 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 406 num_threads_next_level = 0; 407 offset_next_level = 0; 408 } else { 409 next_level = find_next_bit(env->avail_cpu_topo, 410 CPU_TOPOLOGY_LEVEL_SOCKET, 411 level + 1); 412 num_threads_next_level = num_threads_by_topo_level(topo_info, 413 next_level); 414 offset_next_level = apicid_offset_by_topo_level(topo_info, 415 next_level); 416 } 417 418 *eax = offset_next_level; 419 /* The count (bits 15-00) doesn't need to be reliable. */ 420 *ebx = num_threads_next_level & 0xffff; 421 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 422 *edx = cpu->apic_id; 423 424 assert(!(*eax & ~0x1f)); 425 } 426 427 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 428 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 429 { 430 assert(cache->size % 1024 == 0); 431 assert(cache->lines_per_tag > 0); 432 assert(cache->associativity > 0); 433 assert(cache->line_size > 0); 434 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 435 (cache->lines_per_tag << 8) | (cache->line_size); 436 } 437 438 #define ASSOC_FULL 0xFF 439 440 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 441 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 442 a == 2 ? 0x2 : \ 443 a == 4 ? 0x4 : \ 444 a == 8 ? 0x6 : \ 445 a == 16 ? 0x8 : \ 446 a == 32 ? 0xA : \ 447 a == 48 ? 0xB : \ 448 a == 64 ? 0xC : \ 449 a == 96 ? 0xD : \ 450 a == 128 ? 0xE : \ 451 a == ASSOC_FULL ? 0xF : \ 452 0 /* invalid value */) 453 454 /* 455 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 456 * @l3 can be NULL. 457 */ 458 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 459 CPUCacheInfo *l3, 460 uint32_t *ecx, uint32_t *edx) 461 { 462 assert(l2->size % 1024 == 0); 463 assert(l2->associativity > 0); 464 assert(l2->lines_per_tag > 0); 465 assert(l2->line_size > 0); 466 *ecx = ((l2->size / 1024) << 16) | 467 (AMD_ENC_ASSOC(l2->associativity) << 12) | 468 (l2->lines_per_tag << 8) | (l2->line_size); 469 470 if (l3) { 471 assert(l3->size % (512 * 1024) == 0); 472 assert(l3->associativity > 0); 473 assert(l3->lines_per_tag > 0); 474 assert(l3->line_size > 0); 475 *edx = ((l3->size / (512 * 1024)) << 18) | 476 (AMD_ENC_ASSOC(l3->associativity) << 12) | 477 (l3->lines_per_tag << 8) | (l3->line_size); 478 } else { 479 *edx = 0; 480 } 481 } 482 483 /* Encode cache info for CPUID[8000001D] */ 484 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 485 X86CPUTopoInfo *topo_info, 486 uint32_t *eax, uint32_t *ebx, 487 uint32_t *ecx, uint32_t *edx) 488 { 489 assert(cache->size == cache->line_size * cache->associativity * 490 cache->partitions * cache->sets); 491 492 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 493 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 494 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 495 496 assert(cache->line_size > 0); 497 assert(cache->partitions > 0); 498 assert(cache->associativity > 0); 499 /* We don't implement fully-associative caches */ 500 assert(cache->associativity < cache->sets); 501 *ebx = (cache->line_size - 1) | 502 ((cache->partitions - 1) << 12) | 503 ((cache->associativity - 1) << 22); 504 505 assert(cache->sets > 0); 506 *ecx = cache->sets - 1; 507 508 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 509 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 510 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 511 } 512 513 /* Encode cache info for CPUID[8000001E] */ 514 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 515 uint32_t *eax, uint32_t *ebx, 516 uint32_t *ecx, uint32_t *edx) 517 { 518 X86CPUTopoIDs topo_ids; 519 520 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 521 522 *eax = cpu->apic_id; 523 524 /* 525 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 526 * Read-only. Reset: 0000_XXXXh. 527 * See Core::X86::Cpuid::ExtApicId. 528 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 529 * Bits Description 530 * 31:16 Reserved. 531 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 532 * The number of threads per core is ThreadsPerCore+1. 533 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 534 * 535 * NOTE: CoreId is already part of apic_id. Just use it. We can 536 * use all the 8 bits to represent the core_id here. 537 */ 538 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 539 540 /* 541 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 542 * Read-only. Reset: 0000_0XXXh. 543 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 544 * Bits Description 545 * 31:11 Reserved. 546 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 547 * ValidValues: 548 * Value Description 549 * 0h 1 node per processor. 550 * 7h-1h Reserved. 551 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 552 * 553 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 554 * But users can create more nodes than the actual hardware can 555 * support. To genaralize we can use all the upper 8 bits for nodes. 556 * NodeId is combination of node and socket_id which is already decoded 557 * in apic_id. Just use it by shifting. 558 */ 559 if (cpu->legacy_multi_node) { 560 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 561 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 562 } else { 563 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 564 } 565 566 *edx = 0; 567 } 568 569 /* 570 * Definitions of the hardcoded cache entries we expose: 571 * These are legacy cache values. If there is a need to change any 572 * of these values please use builtin_x86_defs 573 */ 574 575 /* L1 data cache: */ 576 static CPUCacheInfo legacy_l1d_cache = { 577 .type = DATA_CACHE, 578 .level = 1, 579 .size = 32 * KiB, 580 .self_init = 1, 581 .line_size = 64, 582 .associativity = 8, 583 .sets = 64, 584 .partitions = 1, 585 .no_invd_sharing = true, 586 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 587 }; 588 589 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 590 static CPUCacheInfo legacy_l1d_cache_amd = { 591 .type = DATA_CACHE, 592 .level = 1, 593 .size = 64 * KiB, 594 .self_init = 1, 595 .line_size = 64, 596 .associativity = 2, 597 .sets = 512, 598 .partitions = 1, 599 .lines_per_tag = 1, 600 .no_invd_sharing = true, 601 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 602 }; 603 604 /* L1 instruction cache: */ 605 static CPUCacheInfo legacy_l1i_cache = { 606 .type = INSTRUCTION_CACHE, 607 .level = 1, 608 .size = 32 * KiB, 609 .self_init = 1, 610 .line_size = 64, 611 .associativity = 8, 612 .sets = 64, 613 .partitions = 1, 614 .no_invd_sharing = true, 615 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 616 }; 617 618 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 619 static CPUCacheInfo legacy_l1i_cache_amd = { 620 .type = INSTRUCTION_CACHE, 621 .level = 1, 622 .size = 64 * KiB, 623 .self_init = 1, 624 .line_size = 64, 625 .associativity = 2, 626 .sets = 512, 627 .partitions = 1, 628 .lines_per_tag = 1, 629 .no_invd_sharing = true, 630 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 631 }; 632 633 /* Level 2 unified cache: */ 634 static CPUCacheInfo legacy_l2_cache = { 635 .type = UNIFIED_CACHE, 636 .level = 2, 637 .size = 4 * MiB, 638 .self_init = 1, 639 .line_size = 64, 640 .associativity = 16, 641 .sets = 4096, 642 .partitions = 1, 643 .no_invd_sharing = true, 644 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 645 }; 646 647 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 648 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 649 .type = UNIFIED_CACHE, 650 .level = 2, 651 .size = 2 * MiB, 652 .line_size = 64, 653 .associativity = 8, 654 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 655 }; 656 657 658 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 659 static CPUCacheInfo legacy_l2_cache_amd = { 660 .type = UNIFIED_CACHE, 661 .level = 2, 662 .size = 512 * KiB, 663 .line_size = 64, 664 .lines_per_tag = 1, 665 .associativity = 16, 666 .sets = 512, 667 .partitions = 1, 668 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 669 }; 670 671 /* Level 3 unified cache: */ 672 static CPUCacheInfo legacy_l3_cache = { 673 .type = UNIFIED_CACHE, 674 .level = 3, 675 .size = 16 * MiB, 676 .line_size = 64, 677 .associativity = 16, 678 .sets = 16384, 679 .partitions = 1, 680 .lines_per_tag = 1, 681 .self_init = true, 682 .inclusive = true, 683 .complex_indexing = true, 684 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 685 }; 686 687 /* TLB definitions: */ 688 689 #define L1_DTLB_2M_ASSOC 1 690 #define L1_DTLB_2M_ENTRIES 255 691 #define L1_DTLB_4K_ASSOC 1 692 #define L1_DTLB_4K_ENTRIES 255 693 694 #define L1_ITLB_2M_ASSOC 1 695 #define L1_ITLB_2M_ENTRIES 255 696 #define L1_ITLB_4K_ASSOC 1 697 #define L1_ITLB_4K_ENTRIES 255 698 699 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 700 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 701 #define L2_DTLB_4K_ASSOC 4 702 #define L2_DTLB_4K_ENTRIES 512 703 704 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 705 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 706 #define L2_ITLB_4K_ASSOC 4 707 #define L2_ITLB_4K_ENTRIES 512 708 709 /* CPUID Leaf 0x14 constants: */ 710 #define INTEL_PT_MAX_SUBLEAF 0x1 711 /* 712 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 713 * MSR can be accessed; 714 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 715 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 716 * of Intel PT MSRs across warm reset; 717 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 718 */ 719 #define INTEL_PT_MINIMAL_EBX 0xf 720 /* 721 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 722 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 723 * accessed; 724 * bit[01]: ToPA tables can hold any number of output entries, up to the 725 * maximum allowed by the MaskOrTableOffset field of 726 * IA32_RTIT_OUTPUT_MASK_PTRS; 727 * bit[02]: Support Single-Range Output scheme; 728 */ 729 #define INTEL_PT_MINIMAL_ECX 0x7 730 /* generated packets which contain IP payloads have LIP values */ 731 #define INTEL_PT_IP_LIP (1 << 31) 732 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 733 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 734 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 735 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 736 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 737 738 /* CPUID Leaf 0x1D constants: */ 739 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 740 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 741 #define INTEL_AMX_BYTES_PER_TILE 0x400 742 #define INTEL_AMX_BYTES_PER_ROW 0x40 743 #define INTEL_AMX_TILE_MAX_NAMES 0x8 744 #define INTEL_AMX_TILE_MAX_ROWS 0x10 745 746 /* CPUID Leaf 0x1E constants: */ 747 #define INTEL_AMX_TMUL_MAX_K 0x10 748 #define INTEL_AMX_TMUL_MAX_N 0x40 749 750 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 751 uint32_t vendor2, uint32_t vendor3) 752 { 753 int i; 754 for (i = 0; i < 4; i++) { 755 dst[i] = vendor1 >> (8 * i); 756 dst[i + 4] = vendor2 >> (8 * i); 757 dst[i + 8] = vendor3 >> (8 * i); 758 } 759 dst[CPUID_VENDOR_SZ] = '\0'; 760 } 761 762 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 763 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 764 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 765 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 766 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 767 CPUID_PSE36 | CPUID_FXSR) 768 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 769 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 770 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 771 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 772 CPUID_PAE | CPUID_SEP | CPUID_APIC) 773 774 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 775 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 776 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 777 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 778 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 779 /* partly implemented: 780 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 781 /* missing: 782 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 783 784 /* 785 * Kernel-only features that can be shown to usermode programs even if 786 * they aren't actually supported by TCG, because qemu-user only runs 787 * in CPL=3; remove them if they are ever implemented for system emulation. 788 */ 789 #if defined CONFIG_USER_ONLY 790 #define CPUID_EXT_KERNEL_FEATURES \ 791 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 792 #else 793 #define CPUID_EXT_KERNEL_FEATURES 0 794 #endif 795 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 796 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 797 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 798 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 799 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 800 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 801 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 802 /* missing: 803 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 804 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 805 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 806 CPUID_EXT_TSC_DEADLINE_TIMER 807 */ 808 809 #ifdef TARGET_X86_64 810 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 811 #else 812 #define TCG_EXT2_X86_64_FEATURES 0 813 #endif 814 815 /* 816 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 817 * in usermode or by 32-bit programs. Those are added to supported 818 * TCG features unconditionally in user-mode emulation mode. This may 819 * indeed seem strange or incorrect, but it works because code running 820 * under usermode emulation cannot access them. 821 * 822 * Even for long mode, qemu-i386 is not running "a userspace program on a 823 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 824 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 825 * but again the difference is only visible in kernel mode. 826 */ 827 #if defined CONFIG_LINUX_USER 828 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 829 #elif defined CONFIG_USER_ONLY 830 /* FIXME: Long mode not yet supported for i386 bsd-user */ 831 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 832 #else 833 #define CPUID_EXT2_KERNEL_FEATURES 0 834 #endif 835 836 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 837 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 838 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 839 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 840 CPUID_EXT2_KERNEL_FEATURES) 841 842 #if defined CONFIG_USER_ONLY 843 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 844 #else 845 #define CPUID_EXT3_KERNEL_FEATURES 0 846 #endif 847 848 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 849 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 850 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 851 852 #define TCG_EXT4_FEATURES 0 853 854 #if defined CONFIG_USER_ONLY 855 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 856 #else 857 #define CPUID_SVM_KERNEL_FEATURES 0 858 #endif 859 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 860 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 861 862 #define TCG_KVM_FEATURES 0 863 864 #if defined CONFIG_USER_ONLY 865 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 866 #else 867 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 868 #endif 869 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 870 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 871 CPUID_7_0_EBX_CLFLUSHOPT | \ 872 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 873 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 874 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 875 /* missing: 876 CPUID_7_0_EBX_HLE 877 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 878 879 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 880 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 881 #else 882 #define TCG_7_0_ECX_RDPID 0 883 #endif 884 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 885 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 886 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 887 TCG_7_0_ECX_RDPID) 888 889 #if defined CONFIG_USER_ONLY 890 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 891 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 892 #else 893 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 894 #endif 895 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 896 897 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 898 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 899 #define TCG_7_1_EDX_FEATURES 0 900 #define TCG_7_2_EDX_FEATURES 0 901 #define TCG_APM_FEATURES 0 902 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 903 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 904 /* missing: 905 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 906 #define TCG_14_0_ECX_FEATURES 0 907 #define TCG_SGX_12_0_EAX_FEATURES 0 908 #define TCG_SGX_12_0_EBX_FEATURES 0 909 #define TCG_SGX_12_1_EAX_FEATURES 0 910 #define TCG_24_0_EBX_FEATURES 0 911 912 #if defined CONFIG_USER_ONLY 913 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 914 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 915 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 916 CPUID_8000_0008_EBX_AMD_PSFD) 917 #else 918 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 919 #endif 920 921 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 922 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 923 924 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 925 [FEAT_1_EDX] = { 926 .type = CPUID_FEATURE_WORD, 927 .feat_names = { 928 "fpu", "vme", "de", "pse", 929 "tsc", "msr", "pae", "mce", 930 "cx8", "apic", NULL, "sep", 931 "mtrr", "pge", "mca", "cmov", 932 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 933 NULL, "ds" /* Intel dts */, "acpi", "mmx", 934 "fxsr", "sse", "sse2", "ss", 935 "ht" /* Intel htt */, "tm", "ia64", "pbe", 936 }, 937 .cpuid = {.eax = 1, .reg = R_EDX, }, 938 .tcg_features = TCG_FEATURES, 939 .no_autoenable_flags = CPUID_HT, 940 }, 941 [FEAT_1_ECX] = { 942 .type = CPUID_FEATURE_WORD, 943 .feat_names = { 944 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 945 "ds-cpl", "vmx", "smx", "est", 946 "tm2", "ssse3", "cid", NULL, 947 "fma", "cx16", "xtpr", "pdcm", 948 NULL, "pcid", "dca", "sse4.1", 949 "sse4.2", "x2apic", "movbe", "popcnt", 950 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 951 "avx", "f16c", "rdrand", "hypervisor", 952 }, 953 .cpuid = { .eax = 1, .reg = R_ECX, }, 954 .tcg_features = TCG_EXT_FEATURES, 955 }, 956 /* Feature names that are already defined on feature_name[] but 957 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 958 * names on feat_names below. They are copied automatically 959 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 960 */ 961 [FEAT_8000_0001_EDX] = { 962 .type = CPUID_FEATURE_WORD, 963 .feat_names = { 964 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 965 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 966 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 967 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 968 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 969 "nx", NULL, "mmxext", NULL /* mmx */, 970 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 971 NULL, "lm", "3dnowext", "3dnow", 972 }, 973 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 974 .tcg_features = TCG_EXT2_FEATURES, 975 }, 976 [FEAT_8000_0001_ECX] = { 977 .type = CPUID_FEATURE_WORD, 978 .feat_names = { 979 "lahf-lm", "cmp-legacy", "svm", "extapic", 980 "cr8legacy", "abm", "sse4a", "misalignsse", 981 "3dnowprefetch", "osvw", "ibs", "xop", 982 "skinit", "wdt", NULL, "lwp", 983 "fma4", "tce", NULL, "nodeid-msr", 984 NULL, "tbm", "topoext", "perfctr-core", 985 "perfctr-nb", NULL, NULL, NULL, 986 NULL, NULL, NULL, NULL, 987 }, 988 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 989 .tcg_features = TCG_EXT3_FEATURES, 990 /* 991 * TOPOEXT is always allowed but can't be enabled blindly by 992 * "-cpu host", as it requires consistent cache topology info 993 * to be provided so it doesn't confuse guests. 994 */ 995 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 996 }, 997 [FEAT_C000_0001_EDX] = { 998 .type = CPUID_FEATURE_WORD, 999 .feat_names = { 1000 NULL, NULL, "xstore", "xstore-en", 1001 NULL, NULL, "xcrypt", "xcrypt-en", 1002 "ace2", "ace2-en", "phe", "phe-en", 1003 "pmm", "pmm-en", NULL, NULL, 1004 NULL, NULL, NULL, NULL, 1005 NULL, NULL, NULL, NULL, 1006 NULL, NULL, NULL, NULL, 1007 NULL, NULL, NULL, NULL, 1008 }, 1009 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1010 .tcg_features = TCG_EXT4_FEATURES, 1011 }, 1012 [FEAT_KVM] = { 1013 .type = CPUID_FEATURE_WORD, 1014 .feat_names = { 1015 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1016 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1017 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1018 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1019 NULL, NULL, NULL, NULL, 1020 NULL, NULL, NULL, NULL, 1021 "kvmclock-stable-bit", NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 }, 1024 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1025 .tcg_features = TCG_KVM_FEATURES, 1026 }, 1027 [FEAT_KVM_HINTS] = { 1028 .type = CPUID_FEATURE_WORD, 1029 .feat_names = { 1030 "kvm-hint-dedicated", NULL, NULL, NULL, 1031 NULL, NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 NULL, NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 NULL, NULL, NULL, NULL, 1036 NULL, NULL, NULL, NULL, 1037 NULL, NULL, NULL, NULL, 1038 }, 1039 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1040 .tcg_features = TCG_KVM_FEATURES, 1041 /* 1042 * KVM hints aren't auto-enabled by -cpu host, they need to be 1043 * explicitly enabled in the command-line. 1044 */ 1045 .no_autoenable_flags = ~0U, 1046 }, 1047 [FEAT_SVM] = { 1048 .type = CPUID_FEATURE_WORD, 1049 .feat_names = { 1050 "npt", "lbrv", "svm-lock", "nrip-save", 1051 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1052 NULL, NULL, "pause-filter", NULL, 1053 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1054 "vgif", NULL, NULL, NULL, 1055 NULL, NULL, NULL, NULL, 1056 NULL, "vnmi", NULL, NULL, 1057 "svme-addr-chk", NULL, NULL, NULL, 1058 }, 1059 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1060 .tcg_features = TCG_SVM_FEATURES, 1061 }, 1062 [FEAT_7_0_EBX] = { 1063 .type = CPUID_FEATURE_WORD, 1064 .feat_names = { 1065 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1066 "hle", "avx2", "fdp-excptn-only", "smep", 1067 "bmi2", "erms", "invpcid", "rtm", 1068 NULL, "zero-fcs-fds", "mpx", NULL, 1069 "avx512f", "avx512dq", "rdseed", "adx", 1070 "smap", "avx512ifma", "pcommit", "clflushopt", 1071 "clwb", "intel-pt", "avx512pf", "avx512er", 1072 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1073 }, 1074 .cpuid = { 1075 .eax = 7, 1076 .needs_ecx = true, .ecx = 0, 1077 .reg = R_EBX, 1078 }, 1079 .tcg_features = TCG_7_0_EBX_FEATURES, 1080 }, 1081 [FEAT_7_0_ECX] = { 1082 .type = CPUID_FEATURE_WORD, 1083 .feat_names = { 1084 NULL, "avx512vbmi", "umip", "pku", 1085 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1086 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1087 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1088 "la57", NULL, NULL, NULL, 1089 NULL, NULL, "rdpid", NULL, 1090 "bus-lock-detect", "cldemote", NULL, "movdiri", 1091 "movdir64b", NULL, "sgxlc", "pks", 1092 }, 1093 .cpuid = { 1094 .eax = 7, 1095 .needs_ecx = true, .ecx = 0, 1096 .reg = R_ECX, 1097 }, 1098 .tcg_features = TCG_7_0_ECX_FEATURES, 1099 }, 1100 [FEAT_7_0_EDX] = { 1101 .type = CPUID_FEATURE_WORD, 1102 .feat_names = { 1103 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1104 "fsrm", NULL, NULL, NULL, 1105 "avx512-vp2intersect", NULL, "md-clear", NULL, 1106 NULL, NULL, "serialize", NULL, 1107 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1108 NULL, NULL, "amx-bf16", "avx512-fp16", 1109 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1110 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1111 }, 1112 .cpuid = { 1113 .eax = 7, 1114 .needs_ecx = true, .ecx = 0, 1115 .reg = R_EDX, 1116 }, 1117 .tcg_features = TCG_7_0_EDX_FEATURES, 1118 }, 1119 [FEAT_7_1_EAX] = { 1120 .type = CPUID_FEATURE_WORD, 1121 .feat_names = { 1122 "sha512", "sm3", "sm4", NULL, 1123 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1124 NULL, NULL, "fzrm", "fsrs", 1125 "fsrc", NULL, NULL, NULL, 1126 NULL, "fred", "lkgs", "wrmsrns", 1127 NULL, "amx-fp16", NULL, "avx-ifma", 1128 NULL, NULL, "lam", NULL, 1129 NULL, NULL, NULL, NULL, 1130 }, 1131 .cpuid = { 1132 .eax = 7, 1133 .needs_ecx = true, .ecx = 1, 1134 .reg = R_EAX, 1135 }, 1136 .tcg_features = TCG_7_1_EAX_FEATURES, 1137 }, 1138 [FEAT_7_1_EDX] = { 1139 .type = CPUID_FEATURE_WORD, 1140 .feat_names = { 1141 NULL, NULL, NULL, NULL, 1142 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1143 "amx-complex", NULL, "avx-vnni-int16", NULL, 1144 NULL, NULL, "prefetchiti", NULL, 1145 NULL, NULL, NULL, "avx10", 1146 NULL, NULL, NULL, NULL, 1147 NULL, NULL, NULL, NULL, 1148 NULL, NULL, NULL, NULL, 1149 }, 1150 .cpuid = { 1151 .eax = 7, 1152 .needs_ecx = true, .ecx = 1, 1153 .reg = R_EDX, 1154 }, 1155 .tcg_features = TCG_7_1_EDX_FEATURES, 1156 }, 1157 [FEAT_7_2_EDX] = { 1158 .type = CPUID_FEATURE_WORD, 1159 .feat_names = { 1160 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1161 "bhi-ctrl", "mcdt-no", NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 NULL, NULL, NULL, NULL, 1164 NULL, NULL, NULL, NULL, 1165 NULL, NULL, NULL, NULL, 1166 NULL, NULL, NULL, NULL, 1167 NULL, NULL, NULL, NULL, 1168 }, 1169 .cpuid = { 1170 .eax = 7, 1171 .needs_ecx = true, .ecx = 2, 1172 .reg = R_EDX, 1173 }, 1174 .tcg_features = TCG_7_2_EDX_FEATURES, 1175 }, 1176 [FEAT_24_0_EBX] = { 1177 .type = CPUID_FEATURE_WORD, 1178 .feat_names = { 1179 [16] = "avx10-128", 1180 [17] = "avx10-256", 1181 [18] = "avx10-512", 1182 }, 1183 .cpuid = { 1184 .eax = 0x24, 1185 .needs_ecx = true, .ecx = 0, 1186 .reg = R_EBX, 1187 }, 1188 .tcg_features = TCG_24_0_EBX_FEATURES, 1189 }, 1190 [FEAT_8000_0007_EDX] = { 1191 .type = CPUID_FEATURE_WORD, 1192 .feat_names = { 1193 NULL, NULL, NULL, NULL, 1194 NULL, NULL, NULL, NULL, 1195 "invtsc", NULL, NULL, NULL, 1196 NULL, NULL, NULL, NULL, 1197 NULL, NULL, NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 NULL, NULL, NULL, NULL, 1200 NULL, NULL, NULL, NULL, 1201 }, 1202 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1203 .tcg_features = TCG_APM_FEATURES, 1204 .unmigratable_flags = CPUID_APM_INVTSC, 1205 }, 1206 [FEAT_8000_0007_EBX] = { 1207 .type = CPUID_FEATURE_WORD, 1208 .feat_names = { 1209 "overflow-recov", "succor", NULL, NULL, 1210 NULL, NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 NULL, NULL, NULL, NULL, 1216 NULL, NULL, NULL, NULL, 1217 }, 1218 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1219 .tcg_features = 0, 1220 .unmigratable_flags = 0, 1221 }, 1222 [FEAT_8000_0008_EBX] = { 1223 .type = CPUID_FEATURE_WORD, 1224 .feat_names = { 1225 "clzero", NULL, "xsaveerptr", NULL, 1226 NULL, NULL, NULL, NULL, 1227 NULL, "wbnoinvd", NULL, NULL, 1228 "ibpb", NULL, "ibrs", "amd-stibp", 1229 NULL, "stibp-always-on", NULL, NULL, 1230 NULL, NULL, NULL, NULL, 1231 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1232 "amd-psfd", NULL, NULL, NULL, 1233 }, 1234 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1235 .tcg_features = TCG_8000_0008_EBX, 1236 .unmigratable_flags = 0, 1237 }, 1238 [FEAT_8000_0021_EAX] = { 1239 .type = CPUID_FEATURE_WORD, 1240 .feat_names = { 1241 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1242 NULL, NULL, "null-sel-clr-base", NULL, 1243 "auto-ibrs", NULL, NULL, NULL, 1244 NULL, NULL, NULL, NULL, 1245 NULL, NULL, NULL, NULL, 1246 NULL, NULL, NULL, NULL, 1247 "eraps", NULL, NULL, "sbpb", 1248 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1249 }, 1250 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1251 .tcg_features = 0, 1252 .unmigratable_flags = 0, 1253 }, 1254 [FEAT_8000_0021_EBX] = { 1255 .type = CPUID_FEATURE_WORD, 1256 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1257 .tcg_features = 0, 1258 .unmigratable_flags = 0, 1259 }, 1260 [FEAT_8000_0022_EAX] = { 1261 .type = CPUID_FEATURE_WORD, 1262 .feat_names = { 1263 "perfmon-v2", NULL, NULL, NULL, 1264 NULL, NULL, NULL, NULL, 1265 NULL, NULL, NULL, NULL, 1266 NULL, NULL, NULL, NULL, 1267 NULL, NULL, NULL, NULL, 1268 NULL, NULL, NULL, NULL, 1269 NULL, NULL, NULL, NULL, 1270 NULL, NULL, NULL, NULL, 1271 }, 1272 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1273 .tcg_features = 0, 1274 .unmigratable_flags = 0, 1275 }, 1276 [FEAT_XSAVE] = { 1277 .type = CPUID_FEATURE_WORD, 1278 .feat_names = { 1279 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1280 "xfd", NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 NULL, NULL, NULL, NULL, 1287 }, 1288 .cpuid = { 1289 .eax = 0xd, 1290 .needs_ecx = true, .ecx = 1, 1291 .reg = R_EAX, 1292 }, 1293 .tcg_features = TCG_XSAVE_FEATURES, 1294 }, 1295 [FEAT_XSAVE_XSS_LO] = { 1296 .type = CPUID_FEATURE_WORD, 1297 .feat_names = { 1298 NULL, NULL, NULL, NULL, 1299 NULL, NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 NULL, NULL, NULL, NULL, 1302 NULL, NULL, NULL, NULL, 1303 NULL, NULL, NULL, NULL, 1304 NULL, NULL, NULL, NULL, 1305 NULL, NULL, NULL, NULL, 1306 }, 1307 .cpuid = { 1308 .eax = 0xD, 1309 .needs_ecx = true, 1310 .ecx = 1, 1311 .reg = R_ECX, 1312 }, 1313 }, 1314 [FEAT_XSAVE_XSS_HI] = { 1315 .type = CPUID_FEATURE_WORD, 1316 .cpuid = { 1317 .eax = 0xD, 1318 .needs_ecx = true, 1319 .ecx = 1, 1320 .reg = R_EDX 1321 }, 1322 }, 1323 [FEAT_6_EAX] = { 1324 .type = CPUID_FEATURE_WORD, 1325 .feat_names = { 1326 NULL, NULL, "arat", NULL, 1327 NULL, NULL, NULL, NULL, 1328 NULL, NULL, NULL, NULL, 1329 NULL, NULL, NULL, NULL, 1330 NULL, NULL, NULL, NULL, 1331 NULL, NULL, NULL, NULL, 1332 NULL, NULL, NULL, NULL, 1333 NULL, NULL, NULL, NULL, 1334 }, 1335 .cpuid = { .eax = 6, .reg = R_EAX, }, 1336 .tcg_features = TCG_6_EAX_FEATURES, 1337 }, 1338 [FEAT_XSAVE_XCR0_LO] = { 1339 .type = CPUID_FEATURE_WORD, 1340 .cpuid = { 1341 .eax = 0xD, 1342 .needs_ecx = true, .ecx = 0, 1343 .reg = R_EAX, 1344 }, 1345 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1346 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1347 XSTATE_PKRU_MASK, 1348 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1349 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1350 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1351 XSTATE_PKRU_MASK, 1352 }, 1353 [FEAT_XSAVE_XCR0_HI] = { 1354 .type = CPUID_FEATURE_WORD, 1355 .cpuid = { 1356 .eax = 0xD, 1357 .needs_ecx = true, .ecx = 0, 1358 .reg = R_EDX, 1359 }, 1360 .tcg_features = 0U, 1361 }, 1362 /*Below are MSR exposed features*/ 1363 [FEAT_ARCH_CAPABILITIES] = { 1364 .type = MSR_FEATURE_WORD, 1365 .feat_names = { 1366 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1367 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1368 "taa-no", NULL, NULL, NULL, 1369 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1370 NULL, "fb-clear", NULL, NULL, 1371 "bhi-no", NULL, NULL, NULL, 1372 "pbrsb-no", NULL, "gds-no", "rfds-no", 1373 "rfds-clear", NULL, NULL, NULL, 1374 }, 1375 .msr = { 1376 .index = MSR_IA32_ARCH_CAPABILITIES, 1377 }, 1378 /* 1379 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1380 * cannot be read from user mode. Therefore, it has no impact 1381 > on any user-mode operation, and warnings about unsupported 1382 * features do not matter. 1383 */ 1384 .tcg_features = ~0U, 1385 }, 1386 [FEAT_CORE_CAPABILITY] = { 1387 .type = MSR_FEATURE_WORD, 1388 .feat_names = { 1389 NULL, NULL, NULL, NULL, 1390 NULL, "split-lock-detect", NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 NULL, NULL, NULL, NULL, 1395 NULL, NULL, NULL, NULL, 1396 NULL, NULL, NULL, NULL, 1397 }, 1398 .msr = { 1399 .index = MSR_IA32_CORE_CAPABILITY, 1400 }, 1401 }, 1402 [FEAT_PERF_CAPABILITIES] = { 1403 .type = MSR_FEATURE_WORD, 1404 .feat_names = { 1405 NULL, NULL, NULL, NULL, 1406 NULL, NULL, NULL, NULL, 1407 NULL, NULL, NULL, NULL, 1408 NULL, "full-width-write", NULL, NULL, 1409 NULL, NULL, NULL, NULL, 1410 NULL, NULL, NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 }, 1414 .msr = { 1415 .index = MSR_IA32_PERF_CAPABILITIES, 1416 }, 1417 }, 1418 1419 [FEAT_VMX_PROCBASED_CTLS] = { 1420 .type = MSR_FEATURE_WORD, 1421 .feat_names = { 1422 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1423 NULL, NULL, NULL, "vmx-hlt-exit", 1424 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1425 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1426 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1427 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1428 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1429 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1430 }, 1431 .msr = { 1432 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1433 } 1434 }, 1435 1436 [FEAT_VMX_SECONDARY_CTLS] = { 1437 .type = MSR_FEATURE_WORD, 1438 .feat_names = { 1439 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1440 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1441 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1442 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1443 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1444 "vmx-xsaves", NULL, NULL, NULL, 1445 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1446 NULL, NULL, NULL, NULL, 1447 }, 1448 .msr = { 1449 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1450 } 1451 }, 1452 1453 [FEAT_VMX_PINBASED_CTLS] = { 1454 .type = MSR_FEATURE_WORD, 1455 .feat_names = { 1456 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1457 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1458 NULL, NULL, NULL, NULL, 1459 NULL, NULL, NULL, NULL, 1460 NULL, NULL, NULL, NULL, 1461 NULL, NULL, NULL, NULL, 1462 NULL, NULL, NULL, NULL, 1463 NULL, NULL, NULL, NULL, 1464 }, 1465 .msr = { 1466 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1467 } 1468 }, 1469 1470 [FEAT_VMX_EXIT_CTLS] = { 1471 .type = MSR_FEATURE_WORD, 1472 /* 1473 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1474 * the LM CPUID bit. 1475 */ 1476 .feat_names = { 1477 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1478 NULL, NULL, NULL, NULL, 1479 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1480 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1481 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1482 "vmx-exit-save-efer", "vmx-exit-load-efer", 1483 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1484 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1485 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1486 }, 1487 .msr = { 1488 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1489 } 1490 }, 1491 1492 [FEAT_VMX_ENTRY_CTLS] = { 1493 .type = MSR_FEATURE_WORD, 1494 .feat_names = { 1495 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1496 NULL, NULL, NULL, NULL, 1497 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1498 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1499 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1500 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1501 NULL, NULL, NULL, NULL, 1502 NULL, NULL, NULL, NULL, 1503 }, 1504 .msr = { 1505 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1506 } 1507 }, 1508 1509 [FEAT_VMX_MISC] = { 1510 .type = MSR_FEATURE_WORD, 1511 .feat_names = { 1512 NULL, NULL, NULL, NULL, 1513 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1514 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1515 NULL, NULL, NULL, NULL, 1516 NULL, NULL, NULL, NULL, 1517 NULL, NULL, NULL, NULL, 1518 NULL, NULL, NULL, NULL, 1519 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1520 }, 1521 .msr = { 1522 .index = MSR_IA32_VMX_MISC, 1523 } 1524 }, 1525 1526 [FEAT_VMX_EPT_VPID_CAPS] = { 1527 .type = MSR_FEATURE_WORD, 1528 .feat_names = { 1529 "vmx-ept-execonly", NULL, NULL, NULL, 1530 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1531 NULL, NULL, NULL, NULL, 1532 NULL, NULL, NULL, NULL, 1533 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1534 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1535 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1536 NULL, NULL, NULL, NULL, 1537 "vmx-invvpid", NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1540 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1541 NULL, NULL, NULL, NULL, 1542 NULL, NULL, NULL, NULL, 1543 NULL, NULL, NULL, NULL, 1544 NULL, NULL, NULL, NULL, 1545 NULL, NULL, NULL, NULL, 1546 }, 1547 .msr = { 1548 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1549 } 1550 }, 1551 1552 [FEAT_VMX_BASIC] = { 1553 .type = MSR_FEATURE_WORD, 1554 .feat_names = { 1555 [54] = "vmx-ins-outs", 1556 [55] = "vmx-true-ctls", 1557 [56] = "vmx-any-errcode", 1558 [58] = "vmx-nested-exception", 1559 }, 1560 .msr = { 1561 .index = MSR_IA32_VMX_BASIC, 1562 }, 1563 /* Just to be safe - we don't support setting the MSEG version field. */ 1564 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1565 }, 1566 1567 [FEAT_VMX_VMFUNC] = { 1568 .type = MSR_FEATURE_WORD, 1569 .feat_names = { 1570 [0] = "vmx-eptp-switching", 1571 }, 1572 .msr = { 1573 .index = MSR_IA32_VMX_VMFUNC, 1574 } 1575 }, 1576 1577 [FEAT_14_0_ECX] = { 1578 .type = CPUID_FEATURE_WORD, 1579 .feat_names = { 1580 NULL, NULL, NULL, NULL, 1581 NULL, NULL, NULL, NULL, 1582 NULL, NULL, NULL, NULL, 1583 NULL, NULL, NULL, NULL, 1584 NULL, NULL, NULL, NULL, 1585 NULL, NULL, NULL, NULL, 1586 NULL, NULL, NULL, NULL, 1587 NULL, NULL, NULL, "intel-pt-lip", 1588 }, 1589 .cpuid = { 1590 .eax = 0x14, 1591 .needs_ecx = true, .ecx = 0, 1592 .reg = R_ECX, 1593 }, 1594 .tcg_features = TCG_14_0_ECX_FEATURES, 1595 }, 1596 1597 [FEAT_SGX_12_0_EAX] = { 1598 .type = CPUID_FEATURE_WORD, 1599 .feat_names = { 1600 "sgx1", "sgx2", NULL, NULL, 1601 NULL, NULL, NULL, NULL, 1602 NULL, NULL, NULL, "sgx-edeccssa", 1603 NULL, NULL, NULL, NULL, 1604 NULL, NULL, NULL, NULL, 1605 NULL, NULL, NULL, NULL, 1606 NULL, NULL, NULL, NULL, 1607 NULL, NULL, NULL, NULL, 1608 }, 1609 .cpuid = { 1610 .eax = 0x12, 1611 .needs_ecx = true, .ecx = 0, 1612 .reg = R_EAX, 1613 }, 1614 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1615 }, 1616 1617 [FEAT_SGX_12_0_EBX] = { 1618 .type = CPUID_FEATURE_WORD, 1619 .feat_names = { 1620 "sgx-exinfo" , NULL, NULL, NULL, 1621 NULL, NULL, NULL, NULL, 1622 NULL, NULL, NULL, NULL, 1623 NULL, NULL, NULL, NULL, 1624 NULL, NULL, NULL, NULL, 1625 NULL, NULL, NULL, NULL, 1626 NULL, NULL, NULL, NULL, 1627 NULL, NULL, NULL, NULL, 1628 }, 1629 .cpuid = { 1630 .eax = 0x12, 1631 .needs_ecx = true, .ecx = 0, 1632 .reg = R_EBX, 1633 }, 1634 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1635 }, 1636 1637 [FEAT_SGX_12_1_EAX] = { 1638 .type = CPUID_FEATURE_WORD, 1639 .feat_names = { 1640 NULL, "sgx-debug", "sgx-mode64", NULL, 1641 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1642 NULL, NULL, "sgx-aex-notify", NULL, 1643 NULL, NULL, NULL, NULL, 1644 NULL, NULL, NULL, NULL, 1645 NULL, NULL, NULL, NULL, 1646 NULL, NULL, NULL, NULL, 1647 NULL, NULL, NULL, NULL, 1648 }, 1649 .cpuid = { 1650 .eax = 0x12, 1651 .needs_ecx = true, .ecx = 1, 1652 .reg = R_EAX, 1653 }, 1654 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1655 }, 1656 }; 1657 1658 typedef struct FeatureMask { 1659 FeatureWord index; 1660 uint64_t mask; 1661 } FeatureMask; 1662 1663 typedef struct FeatureDep { 1664 FeatureMask from, to; 1665 } FeatureDep; 1666 1667 static FeatureDep feature_dependencies[] = { 1668 { 1669 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1670 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1671 }, 1672 { 1673 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1674 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1675 }, 1676 { 1677 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1678 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1679 }, 1680 { 1681 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1682 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1683 }, 1684 { 1685 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1686 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1687 }, 1688 { 1689 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1690 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1691 }, 1692 { 1693 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1694 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1695 }, 1696 { 1697 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1698 .to = { FEAT_VMX_MISC, ~0ull }, 1699 }, 1700 { 1701 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1702 .to = { FEAT_VMX_BASIC, ~0ull }, 1703 }, 1704 { 1705 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1706 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1707 }, 1708 { 1709 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1710 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1711 }, 1712 { 1713 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1714 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1715 }, 1716 { 1717 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1718 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1719 }, 1720 { 1721 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1722 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1723 }, 1724 { 1725 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1726 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1727 }, 1728 { 1729 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1730 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1731 }, 1732 { 1733 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1734 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1735 }, 1736 { 1737 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1738 .to = { FEAT_14_0_ECX, ~0ull }, 1739 }, 1740 { 1741 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1742 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1743 }, 1744 { 1745 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1746 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1747 }, 1748 { 1749 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1750 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1751 }, 1752 { 1753 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1754 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1755 }, 1756 { 1757 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1758 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1759 }, 1760 { 1761 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1762 .to = { FEAT_SVM, ~0ull }, 1763 }, 1764 { 1765 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1766 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1767 }, 1768 { 1769 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1770 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1771 }, 1772 { 1773 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1774 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1775 }, 1776 { 1777 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1778 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1779 }, 1780 { 1781 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1782 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1783 }, 1784 { 1785 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1786 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1787 }, 1788 { 1789 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1790 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1791 }, 1792 { 1793 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1794 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1795 }, 1796 { 1797 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1798 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1799 }, 1800 { 1801 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1802 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1803 }, 1804 { 1805 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1806 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1807 }, 1808 { 1809 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1810 .to = { FEAT_24_0_EBX, ~0ull }, 1811 }, 1812 }; 1813 1814 typedef struct X86RegisterInfo32 { 1815 /* Name of register */ 1816 const char *name; 1817 /* QAPI enum value register */ 1818 X86CPURegister32 qapi_enum; 1819 } X86RegisterInfo32; 1820 1821 #define REGISTER(reg) \ 1822 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1823 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1824 REGISTER(EAX), 1825 REGISTER(ECX), 1826 REGISTER(EDX), 1827 REGISTER(EBX), 1828 REGISTER(ESP), 1829 REGISTER(EBP), 1830 REGISTER(ESI), 1831 REGISTER(EDI), 1832 }; 1833 #undef REGISTER 1834 1835 /* CPUID feature bits available in XSS */ 1836 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1837 1838 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1839 [XSTATE_FP_BIT] = { 1840 /* x87 FP state component is always enabled if XSAVE is supported */ 1841 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1842 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1843 }, 1844 [XSTATE_SSE_BIT] = { 1845 /* SSE state component is always enabled if XSAVE is supported */ 1846 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1847 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1848 }, 1849 [XSTATE_YMM_BIT] = 1850 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1851 .size = sizeof(XSaveAVX) }, 1852 [XSTATE_BNDREGS_BIT] = 1853 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1854 .size = sizeof(XSaveBNDREG) }, 1855 [XSTATE_BNDCSR_BIT] = 1856 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1857 .size = sizeof(XSaveBNDCSR) }, 1858 [XSTATE_OPMASK_BIT] = 1859 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1860 .size = sizeof(XSaveOpmask) }, 1861 [XSTATE_ZMM_Hi256_BIT] = 1862 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1863 .size = sizeof(XSaveZMM_Hi256) }, 1864 [XSTATE_Hi16_ZMM_BIT] = 1865 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1866 .size = sizeof(XSaveHi16_ZMM) }, 1867 [XSTATE_PKRU_BIT] = 1868 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1869 .size = sizeof(XSavePKRU) }, 1870 [XSTATE_ARCH_LBR_BIT] = { 1871 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1872 .offset = 0 /*supervisor mode component, offset = 0 */, 1873 .size = sizeof(XSavesArchLBR) }, 1874 [XSTATE_XTILE_CFG_BIT] = { 1875 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1876 .size = sizeof(XSaveXTILECFG), 1877 }, 1878 [XSTATE_XTILE_DATA_BIT] = { 1879 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1880 .size = sizeof(XSaveXTILEDATA) 1881 }, 1882 }; 1883 1884 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1885 { 1886 uint64_t ret = x86_ext_save_areas[0].size; 1887 const ExtSaveArea *esa; 1888 uint32_t offset = 0; 1889 int i; 1890 1891 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1892 esa = &x86_ext_save_areas[i]; 1893 if ((mask >> i) & 1) { 1894 offset = compacted ? ret : esa->offset; 1895 ret = MAX(ret, offset + esa->size); 1896 } 1897 } 1898 return ret; 1899 } 1900 1901 static inline bool accel_uses_host_cpuid(void) 1902 { 1903 return kvm_enabled() || hvf_enabled(); 1904 } 1905 1906 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1907 { 1908 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1909 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1910 } 1911 1912 /* Return name of 32-bit register, from a R_* constant */ 1913 static const char *get_register_name_32(unsigned int reg) 1914 { 1915 if (reg >= CPU_NB_REGS32) { 1916 return NULL; 1917 } 1918 return x86_reg_info_32[reg].name; 1919 } 1920 1921 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1922 { 1923 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1924 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1925 } 1926 1927 /* 1928 * Returns the set of feature flags that are supported and migratable by 1929 * QEMU, for a given FeatureWord. 1930 */ 1931 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1932 { 1933 FeatureWordInfo *wi = &feature_word_info[w]; 1934 CPUX86State *env = &cpu->env; 1935 uint64_t r = 0; 1936 int i; 1937 1938 for (i = 0; i < 64; i++) { 1939 uint64_t f = 1ULL << i; 1940 1941 /* If the feature name is known, it is implicitly considered migratable, 1942 * unless it is explicitly set in unmigratable_flags */ 1943 if ((wi->migratable_flags & f) || 1944 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1945 r |= f; 1946 } 1947 } 1948 1949 /* when tsc-khz is set explicitly, invtsc is migratable */ 1950 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1951 r |= CPUID_APM_INVTSC; 1952 } 1953 1954 return r; 1955 } 1956 1957 void host_cpuid(uint32_t function, uint32_t count, 1958 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1959 { 1960 uint32_t vec[4]; 1961 1962 #ifdef __x86_64__ 1963 asm volatile("cpuid" 1964 : "=a"(vec[0]), "=b"(vec[1]), 1965 "=c"(vec[2]), "=d"(vec[3]) 1966 : "0"(function), "c"(count) : "cc"); 1967 #elif defined(__i386__) 1968 asm volatile("pusha \n\t" 1969 "cpuid \n\t" 1970 "mov %%eax, 0(%2) \n\t" 1971 "mov %%ebx, 4(%2) \n\t" 1972 "mov %%ecx, 8(%2) \n\t" 1973 "mov %%edx, 12(%2) \n\t" 1974 "popa" 1975 : : "a"(function), "c"(count), "S"(vec) 1976 : "memory", "cc"); 1977 #else 1978 abort(); 1979 #endif 1980 1981 if (eax) 1982 *eax = vec[0]; 1983 if (ebx) 1984 *ebx = vec[1]; 1985 if (ecx) 1986 *ecx = vec[2]; 1987 if (edx) 1988 *edx = vec[3]; 1989 } 1990 1991 /* CPU class name definitions: */ 1992 1993 /* Return type name for a given CPU model name 1994 * Caller is responsible for freeing the returned string. 1995 */ 1996 static char *x86_cpu_type_name(const char *model_name) 1997 { 1998 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1999 } 2000 2001 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2002 { 2003 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2004 return object_class_by_name(typename); 2005 } 2006 2007 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2008 { 2009 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2010 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2011 return cpu_model_from_type(class_name); 2012 } 2013 2014 typedef struct X86CPUVersionDefinition { 2015 X86CPUVersion version; 2016 const char *alias; 2017 const char *note; 2018 PropValue *props; 2019 const CPUCaches *const cache_info; 2020 } X86CPUVersionDefinition; 2021 2022 /* Base definition for a CPU model */ 2023 typedef struct X86CPUDefinition { 2024 const char *name; 2025 uint32_t level; 2026 uint32_t xlevel; 2027 /* vendor is zero-terminated, 12 character ASCII string */ 2028 char vendor[CPUID_VENDOR_SZ + 1]; 2029 int family; 2030 int model; 2031 int stepping; 2032 uint8_t avx10_version; 2033 FeatureWordArray features; 2034 const char *model_id; 2035 const CPUCaches *const cache_info; 2036 /* 2037 * Definitions for alternative versions of CPU model. 2038 * List is terminated by item with version == 0. 2039 * If NULL, version 1 will be registered automatically. 2040 */ 2041 const X86CPUVersionDefinition *versions; 2042 const char *deprecation_note; 2043 } X86CPUDefinition; 2044 2045 /* Reference to a specific CPU model version */ 2046 struct X86CPUModel { 2047 /* Base CPU definition */ 2048 const X86CPUDefinition *cpudef; 2049 /* CPU model version */ 2050 X86CPUVersion version; 2051 const char *note; 2052 /* 2053 * If true, this is an alias CPU model. 2054 * This matters only for "-cpu help" and query-cpu-definitions 2055 */ 2056 bool is_alias; 2057 }; 2058 2059 /* Get full model name for CPU version */ 2060 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2061 X86CPUVersion version) 2062 { 2063 assert(version > 0); 2064 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2065 } 2066 2067 static const X86CPUVersionDefinition * 2068 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2069 { 2070 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2071 static const X86CPUVersionDefinition default_version_list[] = { 2072 { 1 }, 2073 { /* end of list */ } 2074 }; 2075 2076 return def->versions ?: default_version_list; 2077 } 2078 2079 static const CPUCaches epyc_cache_info = { 2080 .l1d_cache = &(CPUCacheInfo) { 2081 .type = DATA_CACHE, 2082 .level = 1, 2083 .size = 32 * KiB, 2084 .line_size = 64, 2085 .associativity = 8, 2086 .partitions = 1, 2087 .sets = 64, 2088 .lines_per_tag = 1, 2089 .self_init = 1, 2090 .no_invd_sharing = true, 2091 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2092 }, 2093 .l1i_cache = &(CPUCacheInfo) { 2094 .type = INSTRUCTION_CACHE, 2095 .level = 1, 2096 .size = 64 * KiB, 2097 .line_size = 64, 2098 .associativity = 4, 2099 .partitions = 1, 2100 .sets = 256, 2101 .lines_per_tag = 1, 2102 .self_init = 1, 2103 .no_invd_sharing = true, 2104 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2105 }, 2106 .l2_cache = &(CPUCacheInfo) { 2107 .type = UNIFIED_CACHE, 2108 .level = 2, 2109 .size = 512 * KiB, 2110 .line_size = 64, 2111 .associativity = 8, 2112 .partitions = 1, 2113 .sets = 1024, 2114 .lines_per_tag = 1, 2115 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2116 }, 2117 .l3_cache = &(CPUCacheInfo) { 2118 .type = UNIFIED_CACHE, 2119 .level = 3, 2120 .size = 8 * MiB, 2121 .line_size = 64, 2122 .associativity = 16, 2123 .partitions = 1, 2124 .sets = 8192, 2125 .lines_per_tag = 1, 2126 .self_init = true, 2127 .inclusive = true, 2128 .complex_indexing = true, 2129 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2130 }, 2131 }; 2132 2133 static CPUCaches epyc_v4_cache_info = { 2134 .l1d_cache = &(CPUCacheInfo) { 2135 .type = DATA_CACHE, 2136 .level = 1, 2137 .size = 32 * KiB, 2138 .line_size = 64, 2139 .associativity = 8, 2140 .partitions = 1, 2141 .sets = 64, 2142 .lines_per_tag = 1, 2143 .self_init = 1, 2144 .no_invd_sharing = true, 2145 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2146 }, 2147 .l1i_cache = &(CPUCacheInfo) { 2148 .type = INSTRUCTION_CACHE, 2149 .level = 1, 2150 .size = 64 * KiB, 2151 .line_size = 64, 2152 .associativity = 4, 2153 .partitions = 1, 2154 .sets = 256, 2155 .lines_per_tag = 1, 2156 .self_init = 1, 2157 .no_invd_sharing = true, 2158 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2159 }, 2160 .l2_cache = &(CPUCacheInfo) { 2161 .type = UNIFIED_CACHE, 2162 .level = 2, 2163 .size = 512 * KiB, 2164 .line_size = 64, 2165 .associativity = 8, 2166 .partitions = 1, 2167 .sets = 1024, 2168 .lines_per_tag = 1, 2169 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2170 }, 2171 .l3_cache = &(CPUCacheInfo) { 2172 .type = UNIFIED_CACHE, 2173 .level = 3, 2174 .size = 8 * MiB, 2175 .line_size = 64, 2176 .associativity = 16, 2177 .partitions = 1, 2178 .sets = 8192, 2179 .lines_per_tag = 1, 2180 .self_init = true, 2181 .inclusive = true, 2182 .complex_indexing = false, 2183 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2184 }, 2185 }; 2186 2187 static const CPUCaches epyc_rome_cache_info = { 2188 .l1d_cache = &(CPUCacheInfo) { 2189 .type = DATA_CACHE, 2190 .level = 1, 2191 .size = 32 * KiB, 2192 .line_size = 64, 2193 .associativity = 8, 2194 .partitions = 1, 2195 .sets = 64, 2196 .lines_per_tag = 1, 2197 .self_init = 1, 2198 .no_invd_sharing = true, 2199 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2200 }, 2201 .l1i_cache = &(CPUCacheInfo) { 2202 .type = INSTRUCTION_CACHE, 2203 .level = 1, 2204 .size = 32 * KiB, 2205 .line_size = 64, 2206 .associativity = 8, 2207 .partitions = 1, 2208 .sets = 64, 2209 .lines_per_tag = 1, 2210 .self_init = 1, 2211 .no_invd_sharing = true, 2212 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2213 }, 2214 .l2_cache = &(CPUCacheInfo) { 2215 .type = UNIFIED_CACHE, 2216 .level = 2, 2217 .size = 512 * KiB, 2218 .line_size = 64, 2219 .associativity = 8, 2220 .partitions = 1, 2221 .sets = 1024, 2222 .lines_per_tag = 1, 2223 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2224 }, 2225 .l3_cache = &(CPUCacheInfo) { 2226 .type = UNIFIED_CACHE, 2227 .level = 3, 2228 .size = 16 * MiB, 2229 .line_size = 64, 2230 .associativity = 16, 2231 .partitions = 1, 2232 .sets = 16384, 2233 .lines_per_tag = 1, 2234 .self_init = true, 2235 .inclusive = true, 2236 .complex_indexing = true, 2237 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2238 }, 2239 }; 2240 2241 static const CPUCaches epyc_rome_v3_cache_info = { 2242 .l1d_cache = &(CPUCacheInfo) { 2243 .type = DATA_CACHE, 2244 .level = 1, 2245 .size = 32 * KiB, 2246 .line_size = 64, 2247 .associativity = 8, 2248 .partitions = 1, 2249 .sets = 64, 2250 .lines_per_tag = 1, 2251 .self_init = 1, 2252 .no_invd_sharing = true, 2253 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2254 }, 2255 .l1i_cache = &(CPUCacheInfo) { 2256 .type = INSTRUCTION_CACHE, 2257 .level = 1, 2258 .size = 32 * KiB, 2259 .line_size = 64, 2260 .associativity = 8, 2261 .partitions = 1, 2262 .sets = 64, 2263 .lines_per_tag = 1, 2264 .self_init = 1, 2265 .no_invd_sharing = true, 2266 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2267 }, 2268 .l2_cache = &(CPUCacheInfo) { 2269 .type = UNIFIED_CACHE, 2270 .level = 2, 2271 .size = 512 * KiB, 2272 .line_size = 64, 2273 .associativity = 8, 2274 .partitions = 1, 2275 .sets = 1024, 2276 .lines_per_tag = 1, 2277 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2278 }, 2279 .l3_cache = &(CPUCacheInfo) { 2280 .type = UNIFIED_CACHE, 2281 .level = 3, 2282 .size = 16 * MiB, 2283 .line_size = 64, 2284 .associativity = 16, 2285 .partitions = 1, 2286 .sets = 16384, 2287 .lines_per_tag = 1, 2288 .self_init = true, 2289 .inclusive = true, 2290 .complex_indexing = false, 2291 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2292 }, 2293 }; 2294 2295 static const CPUCaches epyc_milan_cache_info = { 2296 .l1d_cache = &(CPUCacheInfo) { 2297 .type = DATA_CACHE, 2298 .level = 1, 2299 .size = 32 * KiB, 2300 .line_size = 64, 2301 .associativity = 8, 2302 .partitions = 1, 2303 .sets = 64, 2304 .lines_per_tag = 1, 2305 .self_init = 1, 2306 .no_invd_sharing = true, 2307 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2308 }, 2309 .l1i_cache = &(CPUCacheInfo) { 2310 .type = INSTRUCTION_CACHE, 2311 .level = 1, 2312 .size = 32 * KiB, 2313 .line_size = 64, 2314 .associativity = 8, 2315 .partitions = 1, 2316 .sets = 64, 2317 .lines_per_tag = 1, 2318 .self_init = 1, 2319 .no_invd_sharing = true, 2320 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2321 }, 2322 .l2_cache = &(CPUCacheInfo) { 2323 .type = UNIFIED_CACHE, 2324 .level = 2, 2325 .size = 512 * KiB, 2326 .line_size = 64, 2327 .associativity = 8, 2328 .partitions = 1, 2329 .sets = 1024, 2330 .lines_per_tag = 1, 2331 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2332 }, 2333 .l3_cache = &(CPUCacheInfo) { 2334 .type = UNIFIED_CACHE, 2335 .level = 3, 2336 .size = 32 * MiB, 2337 .line_size = 64, 2338 .associativity = 16, 2339 .partitions = 1, 2340 .sets = 32768, 2341 .lines_per_tag = 1, 2342 .self_init = true, 2343 .inclusive = true, 2344 .complex_indexing = true, 2345 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2346 }, 2347 }; 2348 2349 static const CPUCaches epyc_milan_v2_cache_info = { 2350 .l1d_cache = &(CPUCacheInfo) { 2351 .type = DATA_CACHE, 2352 .level = 1, 2353 .size = 32 * KiB, 2354 .line_size = 64, 2355 .associativity = 8, 2356 .partitions = 1, 2357 .sets = 64, 2358 .lines_per_tag = 1, 2359 .self_init = 1, 2360 .no_invd_sharing = true, 2361 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2362 }, 2363 .l1i_cache = &(CPUCacheInfo) { 2364 .type = INSTRUCTION_CACHE, 2365 .level = 1, 2366 .size = 32 * KiB, 2367 .line_size = 64, 2368 .associativity = 8, 2369 .partitions = 1, 2370 .sets = 64, 2371 .lines_per_tag = 1, 2372 .self_init = 1, 2373 .no_invd_sharing = true, 2374 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2375 }, 2376 .l2_cache = &(CPUCacheInfo) { 2377 .type = UNIFIED_CACHE, 2378 .level = 2, 2379 .size = 512 * KiB, 2380 .line_size = 64, 2381 .associativity = 8, 2382 .partitions = 1, 2383 .sets = 1024, 2384 .lines_per_tag = 1, 2385 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2386 }, 2387 .l3_cache = &(CPUCacheInfo) { 2388 .type = UNIFIED_CACHE, 2389 .level = 3, 2390 .size = 32 * MiB, 2391 .line_size = 64, 2392 .associativity = 16, 2393 .partitions = 1, 2394 .sets = 32768, 2395 .lines_per_tag = 1, 2396 .self_init = true, 2397 .inclusive = true, 2398 .complex_indexing = false, 2399 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2400 }, 2401 }; 2402 2403 static const CPUCaches epyc_genoa_cache_info = { 2404 .l1d_cache = &(CPUCacheInfo) { 2405 .type = DATA_CACHE, 2406 .level = 1, 2407 .size = 32 * KiB, 2408 .line_size = 64, 2409 .associativity = 8, 2410 .partitions = 1, 2411 .sets = 64, 2412 .lines_per_tag = 1, 2413 .self_init = 1, 2414 .no_invd_sharing = true, 2415 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2416 }, 2417 .l1i_cache = &(CPUCacheInfo) { 2418 .type = INSTRUCTION_CACHE, 2419 .level = 1, 2420 .size = 32 * KiB, 2421 .line_size = 64, 2422 .associativity = 8, 2423 .partitions = 1, 2424 .sets = 64, 2425 .lines_per_tag = 1, 2426 .self_init = 1, 2427 .no_invd_sharing = true, 2428 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2429 }, 2430 .l2_cache = &(CPUCacheInfo) { 2431 .type = UNIFIED_CACHE, 2432 .level = 2, 2433 .size = 1 * MiB, 2434 .line_size = 64, 2435 .associativity = 8, 2436 .partitions = 1, 2437 .sets = 2048, 2438 .lines_per_tag = 1, 2439 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2440 }, 2441 .l3_cache = &(CPUCacheInfo) { 2442 .type = UNIFIED_CACHE, 2443 .level = 3, 2444 .size = 32 * MiB, 2445 .line_size = 64, 2446 .associativity = 16, 2447 .partitions = 1, 2448 .sets = 32768, 2449 .lines_per_tag = 1, 2450 .self_init = true, 2451 .inclusive = true, 2452 .complex_indexing = false, 2453 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2454 }, 2455 }; 2456 2457 /* The following VMX features are not supported by KVM and are left out in the 2458 * CPU definitions: 2459 * 2460 * Dual-monitor support (all processors) 2461 * Entry to SMM 2462 * Deactivate dual-monitor treatment 2463 * Number of CR3-target values 2464 * Shutdown activity state 2465 * Wait-for-SIPI activity state 2466 * PAUSE-loop exiting (Westmere and newer) 2467 * EPT-violation #VE (Broadwell and newer) 2468 * Inject event with insn length=0 (Skylake and newer) 2469 * Conceal non-root operation from PT 2470 * Conceal VM exits from PT 2471 * Conceal VM entries from PT 2472 * Enable ENCLS exiting 2473 * Mode-based execute control (XS/XU) 2474 * TSC scaling (Skylake Server and newer) 2475 * GPA translation for PT (IceLake and newer) 2476 * User wait and pause 2477 * ENCLV exiting 2478 * Load IA32_RTIT_CTL 2479 * Clear IA32_RTIT_CTL 2480 * Advanced VM-exit information for EPT violations 2481 * Sub-page write permissions 2482 * PT in VMX operation 2483 */ 2484 2485 static const X86CPUDefinition builtin_x86_defs[] = { 2486 { 2487 .name = "qemu64", 2488 .level = 0xd, 2489 .vendor = CPUID_VENDOR_AMD, 2490 .family = 15, 2491 .model = 107, 2492 .stepping = 1, 2493 .features[FEAT_1_EDX] = 2494 PPRO_FEATURES | 2495 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2496 CPUID_PSE36, 2497 .features[FEAT_1_ECX] = 2498 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2499 .features[FEAT_8000_0001_EDX] = 2500 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2501 .features[FEAT_8000_0001_ECX] = 2502 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2503 .xlevel = 0x8000000A, 2504 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2505 }, 2506 { 2507 .name = "phenom", 2508 .level = 5, 2509 .vendor = CPUID_VENDOR_AMD, 2510 .family = 16, 2511 .model = 2, 2512 .stepping = 3, 2513 /* Missing: CPUID_HT */ 2514 .features[FEAT_1_EDX] = 2515 PPRO_FEATURES | 2516 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2517 CPUID_PSE36 | CPUID_VME, 2518 .features[FEAT_1_ECX] = 2519 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2520 CPUID_EXT_POPCNT, 2521 .features[FEAT_8000_0001_EDX] = 2522 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2523 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2524 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2525 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2526 CPUID_EXT3_CR8LEG, 2527 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2528 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2529 .features[FEAT_8000_0001_ECX] = 2530 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2531 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2532 /* Missing: CPUID_SVM_LBRV */ 2533 .features[FEAT_SVM] = 2534 CPUID_SVM_NPT, 2535 .xlevel = 0x8000001A, 2536 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2537 }, 2538 { 2539 .name = "core2duo", 2540 .level = 10, 2541 .vendor = CPUID_VENDOR_INTEL, 2542 .family = 6, 2543 .model = 15, 2544 .stepping = 11, 2545 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2546 .features[FEAT_1_EDX] = 2547 PPRO_FEATURES | 2548 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2549 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2550 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2551 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2552 .features[FEAT_1_ECX] = 2553 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2554 CPUID_EXT_CX16, 2555 .features[FEAT_8000_0001_EDX] = 2556 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2557 .features[FEAT_8000_0001_ECX] = 2558 CPUID_EXT3_LAHF_LM, 2559 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2560 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2561 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2562 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2563 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2564 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2565 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2566 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2567 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2568 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2569 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2570 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2571 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2572 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2573 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2574 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2575 .features[FEAT_VMX_SECONDARY_CTLS] = 2576 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2577 .xlevel = 0x80000008, 2578 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2579 }, 2580 { 2581 .name = "kvm64", 2582 .level = 0xd, 2583 .vendor = CPUID_VENDOR_INTEL, 2584 .family = 15, 2585 .model = 6, 2586 .stepping = 1, 2587 /* Missing: CPUID_HT */ 2588 .features[FEAT_1_EDX] = 2589 PPRO_FEATURES | CPUID_VME | 2590 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2591 CPUID_PSE36, 2592 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2593 .features[FEAT_1_ECX] = 2594 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2595 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2596 .features[FEAT_8000_0001_EDX] = 2597 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2598 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2599 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2600 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2601 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2602 .features[FEAT_8000_0001_ECX] = 2603 0, 2604 /* VMX features from Cedar Mill/Prescott */ 2605 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2606 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2607 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2608 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2609 VMX_PIN_BASED_NMI_EXITING, 2610 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2611 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2612 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2613 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2614 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2615 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2616 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2617 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2618 .xlevel = 0x80000008, 2619 .model_id = "Common KVM processor" 2620 }, 2621 { 2622 .name = "qemu32", 2623 .level = 4, 2624 .vendor = CPUID_VENDOR_INTEL, 2625 .family = 6, 2626 .model = 6, 2627 .stepping = 3, 2628 .features[FEAT_1_EDX] = 2629 PPRO_FEATURES, 2630 .features[FEAT_1_ECX] = 2631 CPUID_EXT_SSE3, 2632 .xlevel = 0x80000004, 2633 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2634 }, 2635 { 2636 .name = "kvm32", 2637 .level = 5, 2638 .vendor = CPUID_VENDOR_INTEL, 2639 .family = 15, 2640 .model = 6, 2641 .stepping = 1, 2642 .features[FEAT_1_EDX] = 2643 PPRO_FEATURES | CPUID_VME | 2644 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2645 .features[FEAT_1_ECX] = 2646 CPUID_EXT_SSE3, 2647 .features[FEAT_8000_0001_ECX] = 2648 0, 2649 /* VMX features from Yonah */ 2650 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2651 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2652 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2653 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2654 VMX_PIN_BASED_NMI_EXITING, 2655 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2656 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2657 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2658 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2659 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2660 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2661 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2662 .xlevel = 0x80000008, 2663 .model_id = "Common 32-bit KVM processor" 2664 }, 2665 { 2666 .name = "coreduo", 2667 .level = 10, 2668 .vendor = CPUID_VENDOR_INTEL, 2669 .family = 6, 2670 .model = 14, 2671 .stepping = 8, 2672 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2673 .features[FEAT_1_EDX] = 2674 PPRO_FEATURES | CPUID_VME | 2675 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2676 CPUID_SS, 2677 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2678 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2679 .features[FEAT_1_ECX] = 2680 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2681 .features[FEAT_8000_0001_EDX] = 2682 CPUID_EXT2_NX, 2683 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2684 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2685 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2686 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2687 VMX_PIN_BASED_NMI_EXITING, 2688 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2689 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2690 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2691 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2692 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2693 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2694 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2695 .xlevel = 0x80000008, 2696 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2697 }, 2698 { 2699 .name = "486", 2700 .level = 1, 2701 .vendor = CPUID_VENDOR_INTEL, 2702 .family = 4, 2703 .model = 8, 2704 .stepping = 0, 2705 .features[FEAT_1_EDX] = 2706 I486_FEATURES, 2707 .xlevel = 0, 2708 .model_id = "", 2709 }, 2710 { 2711 .name = "pentium", 2712 .level = 1, 2713 .vendor = CPUID_VENDOR_INTEL, 2714 .family = 5, 2715 .model = 4, 2716 .stepping = 3, 2717 .features[FEAT_1_EDX] = 2718 PENTIUM_FEATURES, 2719 .xlevel = 0, 2720 .model_id = "", 2721 }, 2722 { 2723 .name = "pentium2", 2724 .level = 2, 2725 .vendor = CPUID_VENDOR_INTEL, 2726 .family = 6, 2727 .model = 5, 2728 .stepping = 2, 2729 .features[FEAT_1_EDX] = 2730 PENTIUM2_FEATURES, 2731 .xlevel = 0, 2732 .model_id = "", 2733 }, 2734 { 2735 .name = "pentium3", 2736 .level = 3, 2737 .vendor = CPUID_VENDOR_INTEL, 2738 .family = 6, 2739 .model = 7, 2740 .stepping = 3, 2741 .features[FEAT_1_EDX] = 2742 PENTIUM3_FEATURES, 2743 .xlevel = 0, 2744 .model_id = "", 2745 }, 2746 { 2747 .name = "athlon", 2748 .level = 2, 2749 .vendor = CPUID_VENDOR_AMD, 2750 .family = 6, 2751 .model = 2, 2752 .stepping = 3, 2753 .features[FEAT_1_EDX] = 2754 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2755 CPUID_MCA, 2756 .features[FEAT_8000_0001_EDX] = 2757 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2758 .xlevel = 0x80000008, 2759 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2760 }, 2761 { 2762 .name = "n270", 2763 .level = 10, 2764 .vendor = CPUID_VENDOR_INTEL, 2765 .family = 6, 2766 .model = 28, 2767 .stepping = 2, 2768 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2769 .features[FEAT_1_EDX] = 2770 PPRO_FEATURES | 2771 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2772 CPUID_ACPI | CPUID_SS, 2773 /* Some CPUs got no CPUID_SEP */ 2774 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2775 * CPUID_EXT_XTPR */ 2776 .features[FEAT_1_ECX] = 2777 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2778 CPUID_EXT_MOVBE, 2779 .features[FEAT_8000_0001_EDX] = 2780 CPUID_EXT2_NX, 2781 .features[FEAT_8000_0001_ECX] = 2782 CPUID_EXT3_LAHF_LM, 2783 .xlevel = 0x80000008, 2784 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2785 }, 2786 { 2787 .name = "Conroe", 2788 .level = 10, 2789 .vendor = CPUID_VENDOR_INTEL, 2790 .family = 6, 2791 .model = 15, 2792 .stepping = 3, 2793 .features[FEAT_1_EDX] = 2794 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2795 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2796 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2797 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2798 CPUID_DE | CPUID_FP87, 2799 .features[FEAT_1_ECX] = 2800 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2801 .features[FEAT_8000_0001_EDX] = 2802 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2803 .features[FEAT_8000_0001_ECX] = 2804 CPUID_EXT3_LAHF_LM, 2805 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2806 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2807 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2808 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2809 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2810 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2811 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2812 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2813 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2814 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2815 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2816 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2817 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2818 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2819 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2820 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2821 .features[FEAT_VMX_SECONDARY_CTLS] = 2822 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2823 .xlevel = 0x80000008, 2824 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2825 }, 2826 { 2827 .name = "Penryn", 2828 .level = 10, 2829 .vendor = CPUID_VENDOR_INTEL, 2830 .family = 6, 2831 .model = 23, 2832 .stepping = 3, 2833 .features[FEAT_1_EDX] = 2834 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2835 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2836 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2837 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2838 CPUID_DE | CPUID_FP87, 2839 .features[FEAT_1_ECX] = 2840 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2841 CPUID_EXT_SSE3, 2842 .features[FEAT_8000_0001_EDX] = 2843 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2844 .features[FEAT_8000_0001_ECX] = 2845 CPUID_EXT3_LAHF_LM, 2846 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2847 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2848 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2849 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2850 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2851 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2852 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2853 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2854 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2855 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2856 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2857 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2858 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2859 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2860 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2861 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2862 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2863 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2864 .features[FEAT_VMX_SECONDARY_CTLS] = 2865 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2866 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2867 .xlevel = 0x80000008, 2868 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2869 }, 2870 { 2871 .name = "Nehalem", 2872 .level = 11, 2873 .vendor = CPUID_VENDOR_INTEL, 2874 .family = 6, 2875 .model = 26, 2876 .stepping = 3, 2877 .features[FEAT_1_EDX] = 2878 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2879 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2880 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2881 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2882 CPUID_DE | CPUID_FP87, 2883 .features[FEAT_1_ECX] = 2884 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2885 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2886 .features[FEAT_8000_0001_EDX] = 2887 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2888 .features[FEAT_8000_0001_ECX] = 2889 CPUID_EXT3_LAHF_LM, 2890 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2891 MSR_VMX_BASIC_TRUE_CTLS, 2892 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2893 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2894 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2895 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2896 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2897 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2898 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2899 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2900 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2901 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2902 .features[FEAT_VMX_EXIT_CTLS] = 2903 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2904 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2905 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2906 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2907 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2908 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2909 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2910 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2911 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2912 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2913 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2914 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2915 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2916 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2917 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2918 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2919 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2920 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2921 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2922 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2923 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2924 .features[FEAT_VMX_SECONDARY_CTLS] = 2925 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2926 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2927 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2928 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2929 VMX_SECONDARY_EXEC_ENABLE_VPID, 2930 .xlevel = 0x80000008, 2931 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2932 .versions = (X86CPUVersionDefinition[]) { 2933 { .version = 1 }, 2934 { 2935 .version = 2, 2936 .alias = "Nehalem-IBRS", 2937 .props = (PropValue[]) { 2938 { "spec-ctrl", "on" }, 2939 { "model-id", 2940 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2941 { /* end of list */ } 2942 } 2943 }, 2944 { /* end of list */ } 2945 } 2946 }, 2947 { 2948 .name = "Westmere", 2949 .level = 11, 2950 .vendor = CPUID_VENDOR_INTEL, 2951 .family = 6, 2952 .model = 44, 2953 .stepping = 1, 2954 .features[FEAT_1_EDX] = 2955 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2956 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2957 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2958 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2959 CPUID_DE | CPUID_FP87, 2960 .features[FEAT_1_ECX] = 2961 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2962 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2963 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2964 .features[FEAT_8000_0001_EDX] = 2965 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2966 .features[FEAT_8000_0001_ECX] = 2967 CPUID_EXT3_LAHF_LM, 2968 .features[FEAT_6_EAX] = 2969 CPUID_6_EAX_ARAT, 2970 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2971 MSR_VMX_BASIC_TRUE_CTLS, 2972 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2973 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2974 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2975 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2976 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2977 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2978 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2979 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2980 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2981 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2982 .features[FEAT_VMX_EXIT_CTLS] = 2983 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2984 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2985 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2986 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2987 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2988 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2989 MSR_VMX_MISC_STORE_LMA, 2990 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2991 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2992 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2993 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2994 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2995 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2996 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2997 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2998 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2999 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3000 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3001 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3002 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3003 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3004 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3005 .features[FEAT_VMX_SECONDARY_CTLS] = 3006 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3007 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3008 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3009 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3010 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3011 .xlevel = 0x80000008, 3012 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3013 .versions = (X86CPUVersionDefinition[]) { 3014 { .version = 1 }, 3015 { 3016 .version = 2, 3017 .alias = "Westmere-IBRS", 3018 .props = (PropValue[]) { 3019 { "spec-ctrl", "on" }, 3020 { "model-id", 3021 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3022 { /* end of list */ } 3023 } 3024 }, 3025 { /* end of list */ } 3026 } 3027 }, 3028 { 3029 .name = "SandyBridge", 3030 .level = 0xd, 3031 .vendor = CPUID_VENDOR_INTEL, 3032 .family = 6, 3033 .model = 42, 3034 .stepping = 1, 3035 .features[FEAT_1_EDX] = 3036 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3037 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3038 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3039 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3040 CPUID_DE | CPUID_FP87, 3041 .features[FEAT_1_ECX] = 3042 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3043 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3044 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3045 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3046 CPUID_EXT_SSE3, 3047 .features[FEAT_8000_0001_EDX] = 3048 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3049 CPUID_EXT2_SYSCALL, 3050 .features[FEAT_8000_0001_ECX] = 3051 CPUID_EXT3_LAHF_LM, 3052 .features[FEAT_XSAVE] = 3053 CPUID_XSAVE_XSAVEOPT, 3054 .features[FEAT_6_EAX] = 3055 CPUID_6_EAX_ARAT, 3056 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3057 MSR_VMX_BASIC_TRUE_CTLS, 3058 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3059 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3060 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3061 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3062 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3063 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3064 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3065 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3066 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3067 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3068 .features[FEAT_VMX_EXIT_CTLS] = 3069 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3070 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3071 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3072 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3073 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3074 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3075 MSR_VMX_MISC_STORE_LMA, 3076 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3077 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3078 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3079 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3080 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3081 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3082 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3083 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3084 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3085 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3086 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3087 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3088 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3089 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3090 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3091 .features[FEAT_VMX_SECONDARY_CTLS] = 3092 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3093 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3094 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3095 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3096 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3097 .xlevel = 0x80000008, 3098 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3099 .versions = (X86CPUVersionDefinition[]) { 3100 { .version = 1 }, 3101 { 3102 .version = 2, 3103 .alias = "SandyBridge-IBRS", 3104 .props = (PropValue[]) { 3105 { "spec-ctrl", "on" }, 3106 { "model-id", 3107 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3108 { /* end of list */ } 3109 } 3110 }, 3111 { /* end of list */ } 3112 } 3113 }, 3114 { 3115 .name = "IvyBridge", 3116 .level = 0xd, 3117 .vendor = CPUID_VENDOR_INTEL, 3118 .family = 6, 3119 .model = 58, 3120 .stepping = 9, 3121 .features[FEAT_1_EDX] = 3122 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3123 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3124 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3125 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3126 CPUID_DE | CPUID_FP87, 3127 .features[FEAT_1_ECX] = 3128 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3129 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3130 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3131 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3132 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3133 .features[FEAT_7_0_EBX] = 3134 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3135 CPUID_7_0_EBX_ERMS, 3136 .features[FEAT_8000_0001_EDX] = 3137 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3138 CPUID_EXT2_SYSCALL, 3139 .features[FEAT_8000_0001_ECX] = 3140 CPUID_EXT3_LAHF_LM, 3141 .features[FEAT_XSAVE] = 3142 CPUID_XSAVE_XSAVEOPT, 3143 .features[FEAT_6_EAX] = 3144 CPUID_6_EAX_ARAT, 3145 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3146 MSR_VMX_BASIC_TRUE_CTLS, 3147 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3148 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3149 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3150 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3151 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3152 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3153 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3154 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3155 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3156 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3157 .features[FEAT_VMX_EXIT_CTLS] = 3158 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3159 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3160 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3161 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3162 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3163 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3164 MSR_VMX_MISC_STORE_LMA, 3165 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3166 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3167 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3168 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3169 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3170 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3171 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3172 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3173 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3174 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3175 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3176 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3177 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3178 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3179 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3180 .features[FEAT_VMX_SECONDARY_CTLS] = 3181 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3182 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3183 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3184 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3185 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3186 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3187 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3188 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3189 .xlevel = 0x80000008, 3190 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3191 .versions = (X86CPUVersionDefinition[]) { 3192 { .version = 1 }, 3193 { 3194 .version = 2, 3195 .alias = "IvyBridge-IBRS", 3196 .props = (PropValue[]) { 3197 { "spec-ctrl", "on" }, 3198 { "model-id", 3199 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3200 { /* end of list */ } 3201 } 3202 }, 3203 { /* end of list */ } 3204 } 3205 }, 3206 { 3207 .name = "Haswell", 3208 .level = 0xd, 3209 .vendor = CPUID_VENDOR_INTEL, 3210 .family = 6, 3211 .model = 60, 3212 .stepping = 4, 3213 .features[FEAT_1_EDX] = 3214 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3215 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3216 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3217 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3218 CPUID_DE | CPUID_FP87, 3219 .features[FEAT_1_ECX] = 3220 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3221 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3222 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3223 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3224 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3225 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3226 .features[FEAT_8000_0001_EDX] = 3227 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3228 CPUID_EXT2_SYSCALL, 3229 .features[FEAT_8000_0001_ECX] = 3230 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3231 .features[FEAT_7_0_EBX] = 3232 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3233 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3234 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3235 CPUID_7_0_EBX_RTM, 3236 .features[FEAT_XSAVE] = 3237 CPUID_XSAVE_XSAVEOPT, 3238 .features[FEAT_6_EAX] = 3239 CPUID_6_EAX_ARAT, 3240 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3241 MSR_VMX_BASIC_TRUE_CTLS, 3242 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3243 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3244 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3245 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3246 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3247 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3248 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3249 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3250 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3251 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3252 .features[FEAT_VMX_EXIT_CTLS] = 3253 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3254 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3255 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3256 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3257 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3258 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3259 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3260 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3261 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3262 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3263 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3264 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3265 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3266 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3267 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3268 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3269 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3270 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3271 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3272 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3273 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3274 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3275 .features[FEAT_VMX_SECONDARY_CTLS] = 3276 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3277 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3278 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3279 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3280 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3281 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3282 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3283 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3284 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3285 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3286 .xlevel = 0x80000008, 3287 .model_id = "Intel Core Processor (Haswell)", 3288 .versions = (X86CPUVersionDefinition[]) { 3289 { .version = 1 }, 3290 { 3291 .version = 2, 3292 .alias = "Haswell-noTSX", 3293 .props = (PropValue[]) { 3294 { "hle", "off" }, 3295 { "rtm", "off" }, 3296 { "stepping", "1" }, 3297 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3298 { /* end of list */ } 3299 }, 3300 }, 3301 { 3302 .version = 3, 3303 .alias = "Haswell-IBRS", 3304 .props = (PropValue[]) { 3305 /* Restore TSX features removed by -v2 above */ 3306 { "hle", "on" }, 3307 { "rtm", "on" }, 3308 /* 3309 * Haswell and Haswell-IBRS had stepping=4 in 3310 * QEMU 4.0 and older 3311 */ 3312 { "stepping", "4" }, 3313 { "spec-ctrl", "on" }, 3314 { "model-id", 3315 "Intel Core Processor (Haswell, IBRS)" }, 3316 { /* end of list */ } 3317 } 3318 }, 3319 { 3320 .version = 4, 3321 .alias = "Haswell-noTSX-IBRS", 3322 .props = (PropValue[]) { 3323 { "hle", "off" }, 3324 { "rtm", "off" }, 3325 /* spec-ctrl was already enabled by -v3 above */ 3326 { "stepping", "1" }, 3327 { "model-id", 3328 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3329 { /* end of list */ } 3330 } 3331 }, 3332 { /* end of list */ } 3333 } 3334 }, 3335 { 3336 .name = "Broadwell", 3337 .level = 0xd, 3338 .vendor = CPUID_VENDOR_INTEL, 3339 .family = 6, 3340 .model = 61, 3341 .stepping = 2, 3342 .features[FEAT_1_EDX] = 3343 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3344 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3345 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3346 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3347 CPUID_DE | CPUID_FP87, 3348 .features[FEAT_1_ECX] = 3349 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3350 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3351 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3352 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3353 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3354 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3355 .features[FEAT_8000_0001_EDX] = 3356 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3357 CPUID_EXT2_SYSCALL, 3358 .features[FEAT_8000_0001_ECX] = 3359 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3360 .features[FEAT_7_0_EBX] = 3361 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3362 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3363 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3364 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3365 CPUID_7_0_EBX_SMAP, 3366 .features[FEAT_XSAVE] = 3367 CPUID_XSAVE_XSAVEOPT, 3368 .features[FEAT_6_EAX] = 3369 CPUID_6_EAX_ARAT, 3370 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3371 MSR_VMX_BASIC_TRUE_CTLS, 3372 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3373 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3374 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3375 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3376 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3377 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3378 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3379 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3380 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3381 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3382 .features[FEAT_VMX_EXIT_CTLS] = 3383 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3384 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3385 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3386 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3387 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3388 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3389 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3390 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3391 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3392 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3393 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3394 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3395 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3396 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3397 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3398 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3399 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3400 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3401 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3402 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3403 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3404 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3405 .features[FEAT_VMX_SECONDARY_CTLS] = 3406 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3407 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3408 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3409 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3410 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3411 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3412 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3413 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3414 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3415 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3416 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3417 .xlevel = 0x80000008, 3418 .model_id = "Intel Core Processor (Broadwell)", 3419 .versions = (X86CPUVersionDefinition[]) { 3420 { .version = 1 }, 3421 { 3422 .version = 2, 3423 .alias = "Broadwell-noTSX", 3424 .props = (PropValue[]) { 3425 { "hle", "off" }, 3426 { "rtm", "off" }, 3427 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3428 { /* end of list */ } 3429 }, 3430 }, 3431 { 3432 .version = 3, 3433 .alias = "Broadwell-IBRS", 3434 .props = (PropValue[]) { 3435 /* Restore TSX features removed by -v2 above */ 3436 { "hle", "on" }, 3437 { "rtm", "on" }, 3438 { "spec-ctrl", "on" }, 3439 { "model-id", 3440 "Intel Core Processor (Broadwell, IBRS)" }, 3441 { /* end of list */ } 3442 } 3443 }, 3444 { 3445 .version = 4, 3446 .alias = "Broadwell-noTSX-IBRS", 3447 .props = (PropValue[]) { 3448 { "hle", "off" }, 3449 { "rtm", "off" }, 3450 /* spec-ctrl was already enabled by -v3 above */ 3451 { "model-id", 3452 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3453 { /* end of list */ } 3454 } 3455 }, 3456 { /* end of list */ } 3457 } 3458 }, 3459 { 3460 .name = "Skylake-Client", 3461 .level = 0xd, 3462 .vendor = CPUID_VENDOR_INTEL, 3463 .family = 6, 3464 .model = 94, 3465 .stepping = 3, 3466 .features[FEAT_1_EDX] = 3467 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3468 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3469 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3470 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3471 CPUID_DE | CPUID_FP87, 3472 .features[FEAT_1_ECX] = 3473 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3474 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3475 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3476 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3477 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3478 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3479 .features[FEAT_8000_0001_EDX] = 3480 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3481 CPUID_EXT2_SYSCALL, 3482 .features[FEAT_8000_0001_ECX] = 3483 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3484 .features[FEAT_7_0_EBX] = 3485 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3486 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3487 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3488 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3489 CPUID_7_0_EBX_SMAP, 3490 /* XSAVES is added in version 4 */ 3491 .features[FEAT_XSAVE] = 3492 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3493 CPUID_XSAVE_XGETBV1, 3494 .features[FEAT_6_EAX] = 3495 CPUID_6_EAX_ARAT, 3496 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3497 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3498 MSR_VMX_BASIC_TRUE_CTLS, 3499 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3500 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3501 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3502 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3503 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3504 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3505 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3506 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3507 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3508 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3509 .features[FEAT_VMX_EXIT_CTLS] = 3510 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3511 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3512 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3513 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3514 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3515 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3516 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3517 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3518 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3519 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3520 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3521 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3522 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3523 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3524 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3525 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3526 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3527 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3528 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3529 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3530 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3531 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3532 .features[FEAT_VMX_SECONDARY_CTLS] = 3533 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3534 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3535 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3536 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3537 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3538 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3539 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3540 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3541 .xlevel = 0x80000008, 3542 .model_id = "Intel Core Processor (Skylake)", 3543 .versions = (X86CPUVersionDefinition[]) { 3544 { .version = 1 }, 3545 { 3546 .version = 2, 3547 .alias = "Skylake-Client-IBRS", 3548 .props = (PropValue[]) { 3549 { "spec-ctrl", "on" }, 3550 { "model-id", 3551 "Intel Core Processor (Skylake, IBRS)" }, 3552 { /* end of list */ } 3553 } 3554 }, 3555 { 3556 .version = 3, 3557 .alias = "Skylake-Client-noTSX-IBRS", 3558 .props = (PropValue[]) { 3559 { "hle", "off" }, 3560 { "rtm", "off" }, 3561 { "model-id", 3562 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3563 { /* end of list */ } 3564 } 3565 }, 3566 { 3567 .version = 4, 3568 .note = "IBRS, XSAVES, no TSX", 3569 .props = (PropValue[]) { 3570 { "xsaves", "on" }, 3571 { "vmx-xsaves", "on" }, 3572 { /* end of list */ } 3573 } 3574 }, 3575 { /* end of list */ } 3576 } 3577 }, 3578 { 3579 .name = "Skylake-Server", 3580 .level = 0xd, 3581 .vendor = CPUID_VENDOR_INTEL, 3582 .family = 6, 3583 .model = 85, 3584 .stepping = 4, 3585 .features[FEAT_1_EDX] = 3586 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3587 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3588 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3589 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3590 CPUID_DE | CPUID_FP87, 3591 .features[FEAT_1_ECX] = 3592 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3593 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3594 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3595 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3596 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3597 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3598 .features[FEAT_8000_0001_EDX] = 3599 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3600 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3601 .features[FEAT_8000_0001_ECX] = 3602 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3603 .features[FEAT_7_0_EBX] = 3604 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3605 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3606 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3607 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3608 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3609 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3610 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3611 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3612 .features[FEAT_7_0_ECX] = 3613 CPUID_7_0_ECX_PKU, 3614 /* XSAVES is added in version 5 */ 3615 .features[FEAT_XSAVE] = 3616 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3617 CPUID_XSAVE_XGETBV1, 3618 .features[FEAT_6_EAX] = 3619 CPUID_6_EAX_ARAT, 3620 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3621 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3622 MSR_VMX_BASIC_TRUE_CTLS, 3623 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3624 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3625 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3626 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3627 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3628 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3629 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3630 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3631 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3632 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3633 .features[FEAT_VMX_EXIT_CTLS] = 3634 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3635 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3636 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3637 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3638 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3639 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3640 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3641 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3642 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3643 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3644 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3645 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3646 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3647 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3648 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3649 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3650 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3651 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3652 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3653 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3654 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3655 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3656 .features[FEAT_VMX_SECONDARY_CTLS] = 3657 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3658 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3659 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3660 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3661 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3662 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3663 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3664 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3665 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3666 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3667 .xlevel = 0x80000008, 3668 .model_id = "Intel Xeon Processor (Skylake)", 3669 .versions = (X86CPUVersionDefinition[]) { 3670 { .version = 1 }, 3671 { 3672 .version = 2, 3673 .alias = "Skylake-Server-IBRS", 3674 .props = (PropValue[]) { 3675 /* clflushopt was not added to Skylake-Server-IBRS */ 3676 /* TODO: add -v3 including clflushopt */ 3677 { "clflushopt", "off" }, 3678 { "spec-ctrl", "on" }, 3679 { "model-id", 3680 "Intel Xeon Processor (Skylake, IBRS)" }, 3681 { /* end of list */ } 3682 } 3683 }, 3684 { 3685 .version = 3, 3686 .alias = "Skylake-Server-noTSX-IBRS", 3687 .props = (PropValue[]) { 3688 { "hle", "off" }, 3689 { "rtm", "off" }, 3690 { "model-id", 3691 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3692 { /* end of list */ } 3693 } 3694 }, 3695 { 3696 .version = 4, 3697 .note = "IBRS, EPT switching, no TSX", 3698 .props = (PropValue[]) { 3699 { "vmx-eptp-switching", "on" }, 3700 { /* end of list */ } 3701 } 3702 }, 3703 { 3704 .version = 5, 3705 .note = "IBRS, XSAVES, EPT switching, no TSX", 3706 .props = (PropValue[]) { 3707 { "xsaves", "on" }, 3708 { "vmx-xsaves", "on" }, 3709 { /* end of list */ } 3710 } 3711 }, 3712 { /* end of list */ } 3713 } 3714 }, 3715 { 3716 .name = "Cascadelake-Server", 3717 .level = 0xd, 3718 .vendor = CPUID_VENDOR_INTEL, 3719 .family = 6, 3720 .model = 85, 3721 .stepping = 6, 3722 .features[FEAT_1_EDX] = 3723 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3724 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3725 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3726 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3727 CPUID_DE | CPUID_FP87, 3728 .features[FEAT_1_ECX] = 3729 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3730 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3731 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3732 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3733 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3734 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3735 .features[FEAT_8000_0001_EDX] = 3736 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3737 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3738 .features[FEAT_8000_0001_ECX] = 3739 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3740 .features[FEAT_7_0_EBX] = 3741 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3742 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3743 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3744 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3745 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3746 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3747 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3748 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3749 .features[FEAT_7_0_ECX] = 3750 CPUID_7_0_ECX_PKU | 3751 CPUID_7_0_ECX_AVX512VNNI, 3752 .features[FEAT_7_0_EDX] = 3753 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3754 /* XSAVES is added in version 5 */ 3755 .features[FEAT_XSAVE] = 3756 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3757 CPUID_XSAVE_XGETBV1, 3758 .features[FEAT_6_EAX] = 3759 CPUID_6_EAX_ARAT, 3760 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3761 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3762 MSR_VMX_BASIC_TRUE_CTLS, 3763 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3764 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3765 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3766 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3767 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3768 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3769 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3770 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3771 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3772 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3773 .features[FEAT_VMX_EXIT_CTLS] = 3774 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3775 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3776 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3777 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3778 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3779 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3780 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3781 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3782 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3783 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3784 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3785 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3786 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3787 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3788 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3789 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3790 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3791 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3792 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3793 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3794 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3795 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3796 .features[FEAT_VMX_SECONDARY_CTLS] = 3797 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3798 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3799 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3800 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3801 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3802 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3803 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3804 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3805 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3806 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3807 .xlevel = 0x80000008, 3808 .model_id = "Intel Xeon Processor (Cascadelake)", 3809 .versions = (X86CPUVersionDefinition[]) { 3810 { .version = 1 }, 3811 { .version = 2, 3812 .note = "ARCH_CAPABILITIES", 3813 .props = (PropValue[]) { 3814 { "arch-capabilities", "on" }, 3815 { "rdctl-no", "on" }, 3816 { "ibrs-all", "on" }, 3817 { "skip-l1dfl-vmentry", "on" }, 3818 { "mds-no", "on" }, 3819 { /* end of list */ } 3820 }, 3821 }, 3822 { .version = 3, 3823 .alias = "Cascadelake-Server-noTSX", 3824 .note = "ARCH_CAPABILITIES, no TSX", 3825 .props = (PropValue[]) { 3826 { "hle", "off" }, 3827 { "rtm", "off" }, 3828 { /* end of list */ } 3829 }, 3830 }, 3831 { .version = 4, 3832 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 3833 .props = (PropValue[]) { 3834 { "vmx-eptp-switching", "on" }, 3835 { /* end of list */ } 3836 }, 3837 }, 3838 { .version = 5, 3839 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3840 .props = (PropValue[]) { 3841 { "xsaves", "on" }, 3842 { "vmx-xsaves", "on" }, 3843 { /* end of list */ } 3844 }, 3845 }, 3846 { /* end of list */ } 3847 } 3848 }, 3849 { 3850 .name = "Cooperlake", 3851 .level = 0xd, 3852 .vendor = CPUID_VENDOR_INTEL, 3853 .family = 6, 3854 .model = 85, 3855 .stepping = 10, 3856 .features[FEAT_1_EDX] = 3857 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3858 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3859 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3860 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3861 CPUID_DE | CPUID_FP87, 3862 .features[FEAT_1_ECX] = 3863 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3864 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3865 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3866 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3867 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3868 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3869 .features[FEAT_8000_0001_EDX] = 3870 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3871 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3872 .features[FEAT_8000_0001_ECX] = 3873 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3874 .features[FEAT_7_0_EBX] = 3875 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3876 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3877 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3878 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3879 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3880 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3881 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3882 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3883 .features[FEAT_7_0_ECX] = 3884 CPUID_7_0_ECX_PKU | 3885 CPUID_7_0_ECX_AVX512VNNI, 3886 .features[FEAT_7_0_EDX] = 3887 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3888 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3889 .features[FEAT_ARCH_CAPABILITIES] = 3890 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3891 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3892 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3893 .features[FEAT_7_1_EAX] = 3894 CPUID_7_1_EAX_AVX512_BF16, 3895 /* XSAVES is added in version 2 */ 3896 .features[FEAT_XSAVE] = 3897 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3898 CPUID_XSAVE_XGETBV1, 3899 .features[FEAT_6_EAX] = 3900 CPUID_6_EAX_ARAT, 3901 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3902 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3903 MSR_VMX_BASIC_TRUE_CTLS, 3904 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3905 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3906 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3907 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3908 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3909 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3910 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3911 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3912 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3913 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3914 .features[FEAT_VMX_EXIT_CTLS] = 3915 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3916 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3917 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3918 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3919 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3920 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3921 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3922 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3923 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3924 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3925 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3926 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3927 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3928 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3929 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3930 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3931 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3932 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3933 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3934 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3935 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3936 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3937 .features[FEAT_VMX_SECONDARY_CTLS] = 3938 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3939 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3940 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3941 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3942 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3943 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3944 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3945 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3946 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3947 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3948 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3949 .xlevel = 0x80000008, 3950 .model_id = "Intel Xeon Processor (Cooperlake)", 3951 .versions = (X86CPUVersionDefinition[]) { 3952 { .version = 1 }, 3953 { .version = 2, 3954 .note = "XSAVES", 3955 .props = (PropValue[]) { 3956 { "xsaves", "on" }, 3957 { "vmx-xsaves", "on" }, 3958 { /* end of list */ } 3959 }, 3960 }, 3961 { /* end of list */ } 3962 } 3963 }, 3964 { 3965 .name = "Icelake-Server", 3966 .level = 0xd, 3967 .vendor = CPUID_VENDOR_INTEL, 3968 .family = 6, 3969 .model = 134, 3970 .stepping = 0, 3971 .features[FEAT_1_EDX] = 3972 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3973 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3974 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3975 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3976 CPUID_DE | CPUID_FP87, 3977 .features[FEAT_1_ECX] = 3978 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3979 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3980 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3981 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3982 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3983 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3984 .features[FEAT_8000_0001_EDX] = 3985 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3986 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3987 .features[FEAT_8000_0001_ECX] = 3988 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3989 .features[FEAT_8000_0008_EBX] = 3990 CPUID_8000_0008_EBX_WBNOINVD, 3991 .features[FEAT_7_0_EBX] = 3992 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3993 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3994 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3995 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3996 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3997 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3998 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3999 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4000 .features[FEAT_7_0_ECX] = 4001 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4002 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4003 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4004 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4005 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4006 .features[FEAT_7_0_EDX] = 4007 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4008 /* XSAVES is added in version 5 */ 4009 .features[FEAT_XSAVE] = 4010 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4011 CPUID_XSAVE_XGETBV1, 4012 .features[FEAT_6_EAX] = 4013 CPUID_6_EAX_ARAT, 4014 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4015 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4016 MSR_VMX_BASIC_TRUE_CTLS, 4017 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4018 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4019 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4020 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4021 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4022 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4023 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4024 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4025 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4026 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4027 .features[FEAT_VMX_EXIT_CTLS] = 4028 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4029 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4030 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4031 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4032 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4033 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4034 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4035 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4036 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4037 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4038 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4039 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4040 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4041 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4042 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4043 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4044 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4045 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4046 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4047 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4048 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4049 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4050 .features[FEAT_VMX_SECONDARY_CTLS] = 4051 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4052 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4053 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4054 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4055 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4056 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4057 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4058 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4059 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4060 .xlevel = 0x80000008, 4061 .model_id = "Intel Xeon Processor (Icelake)", 4062 .versions = (X86CPUVersionDefinition[]) { 4063 { .version = 1 }, 4064 { 4065 .version = 2, 4066 .note = "no TSX", 4067 .alias = "Icelake-Server-noTSX", 4068 .props = (PropValue[]) { 4069 { "hle", "off" }, 4070 { "rtm", "off" }, 4071 { /* end of list */ } 4072 }, 4073 }, 4074 { 4075 .version = 3, 4076 .props = (PropValue[]) { 4077 { "arch-capabilities", "on" }, 4078 { "rdctl-no", "on" }, 4079 { "ibrs-all", "on" }, 4080 { "skip-l1dfl-vmentry", "on" }, 4081 { "mds-no", "on" }, 4082 { "pschange-mc-no", "on" }, 4083 { "taa-no", "on" }, 4084 { /* end of list */ } 4085 }, 4086 }, 4087 { 4088 .version = 4, 4089 .props = (PropValue[]) { 4090 { "sha-ni", "on" }, 4091 { "avx512ifma", "on" }, 4092 { "rdpid", "on" }, 4093 { "fsrm", "on" }, 4094 { "vmx-rdseed-exit", "on" }, 4095 { "vmx-pml", "on" }, 4096 { "vmx-eptp-switching", "on" }, 4097 { "model", "106" }, 4098 { /* end of list */ } 4099 }, 4100 }, 4101 { 4102 .version = 5, 4103 .note = "XSAVES", 4104 .props = (PropValue[]) { 4105 { "xsaves", "on" }, 4106 { "vmx-xsaves", "on" }, 4107 { /* end of list */ } 4108 }, 4109 }, 4110 { 4111 .version = 6, 4112 .note = "5-level EPT", 4113 .props = (PropValue[]) { 4114 { "vmx-page-walk-5", "on" }, 4115 { /* end of list */ } 4116 }, 4117 }, 4118 { 4119 .version = 7, 4120 .note = "TSX, taa-no", 4121 .props = (PropValue[]) { 4122 /* Restore TSX features removed by -v2 above */ 4123 { "hle", "on" }, 4124 { "rtm", "on" }, 4125 { /* end of list */ } 4126 }, 4127 }, 4128 { /* end of list */ } 4129 } 4130 }, 4131 { 4132 .name = "SapphireRapids", 4133 .level = 0x20, 4134 .vendor = CPUID_VENDOR_INTEL, 4135 .family = 6, 4136 .model = 143, 4137 .stepping = 4, 4138 /* 4139 * please keep the ascending order so that we can have a clear view of 4140 * bit position of each feature. 4141 */ 4142 .features[FEAT_1_EDX] = 4143 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4144 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4145 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4146 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4147 CPUID_SSE | CPUID_SSE2, 4148 .features[FEAT_1_ECX] = 4149 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4150 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4151 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4152 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4153 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4154 .features[FEAT_8000_0001_EDX] = 4155 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4156 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4157 .features[FEAT_8000_0001_ECX] = 4158 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4159 .features[FEAT_8000_0008_EBX] = 4160 CPUID_8000_0008_EBX_WBNOINVD, 4161 .features[FEAT_7_0_EBX] = 4162 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4163 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4164 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4165 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4166 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4167 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4168 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4169 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4170 .features[FEAT_7_0_ECX] = 4171 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4172 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4173 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4174 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4175 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4176 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4177 .features[FEAT_7_0_EDX] = 4178 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4179 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4180 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4181 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4182 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4183 .features[FEAT_ARCH_CAPABILITIES] = 4184 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4185 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4186 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4187 .features[FEAT_XSAVE] = 4188 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4189 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4190 .features[FEAT_6_EAX] = 4191 CPUID_6_EAX_ARAT, 4192 .features[FEAT_7_1_EAX] = 4193 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4194 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4195 .features[FEAT_VMX_BASIC] = 4196 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4197 .features[FEAT_VMX_ENTRY_CTLS] = 4198 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4199 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4200 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4201 .features[FEAT_VMX_EPT_VPID_CAPS] = 4202 MSR_VMX_EPT_EXECONLY | 4203 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4204 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4205 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4206 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4207 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4208 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4209 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4210 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4211 .features[FEAT_VMX_EXIT_CTLS] = 4212 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4213 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4214 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4215 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4216 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4217 .features[FEAT_VMX_MISC] = 4218 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4219 MSR_VMX_MISC_VMWRITE_VMEXIT, 4220 .features[FEAT_VMX_PINBASED_CTLS] = 4221 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4222 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4223 VMX_PIN_BASED_POSTED_INTR, 4224 .features[FEAT_VMX_PROCBASED_CTLS] = 4225 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4226 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4227 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4228 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4229 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4230 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4231 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4232 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4233 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4234 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4235 VMX_CPU_BASED_PAUSE_EXITING | 4236 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4237 .features[FEAT_VMX_SECONDARY_CTLS] = 4238 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4239 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4240 VMX_SECONDARY_EXEC_RDTSCP | 4241 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4242 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4243 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4244 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4245 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4246 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4247 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4248 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4249 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4250 VMX_SECONDARY_EXEC_XSAVES, 4251 .features[FEAT_VMX_VMFUNC] = 4252 MSR_VMX_VMFUNC_EPT_SWITCHING, 4253 .xlevel = 0x80000008, 4254 .model_id = "Intel Xeon Processor (SapphireRapids)", 4255 .versions = (X86CPUVersionDefinition[]) { 4256 { .version = 1 }, 4257 { 4258 .version = 2, 4259 .props = (PropValue[]) { 4260 { "sbdr-ssdp-no", "on" }, 4261 { "fbsdp-no", "on" }, 4262 { "psdp-no", "on" }, 4263 { /* end of list */ } 4264 } 4265 }, 4266 { 4267 .version = 3, 4268 .props = (PropValue[]) { 4269 { "ss", "on" }, 4270 { "tsc-adjust", "on" }, 4271 { "cldemote", "on" }, 4272 { "movdiri", "on" }, 4273 { "movdir64b", "on" }, 4274 { /* end of list */ } 4275 } 4276 }, 4277 { /* end of list */ } 4278 } 4279 }, 4280 { 4281 .name = "GraniteRapids", 4282 .level = 0x20, 4283 .vendor = CPUID_VENDOR_INTEL, 4284 .family = 6, 4285 .model = 173, 4286 .stepping = 0, 4287 /* 4288 * please keep the ascending order so that we can have a clear view of 4289 * bit position of each feature. 4290 */ 4291 .features[FEAT_1_EDX] = 4292 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4293 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4294 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4295 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4296 CPUID_SSE | CPUID_SSE2, 4297 .features[FEAT_1_ECX] = 4298 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4299 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4300 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4301 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4302 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4303 .features[FEAT_8000_0001_EDX] = 4304 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4305 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4306 .features[FEAT_8000_0001_ECX] = 4307 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4308 .features[FEAT_8000_0008_EBX] = 4309 CPUID_8000_0008_EBX_WBNOINVD, 4310 .features[FEAT_7_0_EBX] = 4311 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4312 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4313 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4314 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4315 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4316 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4317 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4318 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4319 .features[FEAT_7_0_ECX] = 4320 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4321 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4322 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4323 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4324 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4325 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4326 .features[FEAT_7_0_EDX] = 4327 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4328 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4329 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4330 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4331 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4332 .features[FEAT_ARCH_CAPABILITIES] = 4333 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4334 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4335 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4336 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4337 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4338 .features[FEAT_XSAVE] = 4339 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4340 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4341 .features[FEAT_6_EAX] = 4342 CPUID_6_EAX_ARAT, 4343 .features[FEAT_7_1_EAX] = 4344 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4345 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4346 CPUID_7_1_EAX_AMX_FP16, 4347 .features[FEAT_7_1_EDX] = 4348 CPUID_7_1_EDX_PREFETCHITI, 4349 .features[FEAT_7_2_EDX] = 4350 CPUID_7_2_EDX_MCDT_NO, 4351 .features[FEAT_VMX_BASIC] = 4352 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4353 .features[FEAT_VMX_ENTRY_CTLS] = 4354 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4355 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4356 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4357 .features[FEAT_VMX_EPT_VPID_CAPS] = 4358 MSR_VMX_EPT_EXECONLY | 4359 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4360 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4361 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4362 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4363 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4364 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4365 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4366 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4367 .features[FEAT_VMX_EXIT_CTLS] = 4368 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4369 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4370 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4371 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4372 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4373 .features[FEAT_VMX_MISC] = 4374 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4375 MSR_VMX_MISC_VMWRITE_VMEXIT, 4376 .features[FEAT_VMX_PINBASED_CTLS] = 4377 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4378 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4379 VMX_PIN_BASED_POSTED_INTR, 4380 .features[FEAT_VMX_PROCBASED_CTLS] = 4381 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4382 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4383 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4384 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4385 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4386 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4387 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4388 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4389 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4390 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4391 VMX_CPU_BASED_PAUSE_EXITING | 4392 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4393 .features[FEAT_VMX_SECONDARY_CTLS] = 4394 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4395 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4396 VMX_SECONDARY_EXEC_RDTSCP | 4397 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4398 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4399 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4400 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4401 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4402 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4403 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4404 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4405 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4406 VMX_SECONDARY_EXEC_XSAVES, 4407 .features[FEAT_VMX_VMFUNC] = 4408 MSR_VMX_VMFUNC_EPT_SWITCHING, 4409 .xlevel = 0x80000008, 4410 .model_id = "Intel Xeon Processor (GraniteRapids)", 4411 .versions = (X86CPUVersionDefinition[]) { 4412 { .version = 1 }, 4413 { 4414 .version = 2, 4415 .props = (PropValue[]) { 4416 { "ss", "on" }, 4417 { "tsc-adjust", "on" }, 4418 { "cldemote", "on" }, 4419 { "movdiri", "on" }, 4420 { "movdir64b", "on" }, 4421 { "avx10", "on" }, 4422 { "avx10-128", "on" }, 4423 { "avx10-256", "on" }, 4424 { "avx10-512", "on" }, 4425 { "avx10-version", "1" }, 4426 { "stepping", "1" }, 4427 { /* end of list */ } 4428 } 4429 }, 4430 { /* end of list */ }, 4431 }, 4432 }, 4433 { 4434 .name = "SierraForest", 4435 .level = 0x23, 4436 .vendor = CPUID_VENDOR_INTEL, 4437 .family = 6, 4438 .model = 175, 4439 .stepping = 0, 4440 /* 4441 * please keep the ascending order so that we can have a clear view of 4442 * bit position of each feature. 4443 */ 4444 .features[FEAT_1_EDX] = 4445 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4446 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4447 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4448 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4449 CPUID_SSE | CPUID_SSE2, 4450 .features[FEAT_1_ECX] = 4451 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4452 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4453 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4454 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4455 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4456 .features[FEAT_8000_0001_EDX] = 4457 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4458 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4459 .features[FEAT_8000_0001_ECX] = 4460 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4461 .features[FEAT_8000_0008_EBX] = 4462 CPUID_8000_0008_EBX_WBNOINVD, 4463 .features[FEAT_7_0_EBX] = 4464 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4465 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4466 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4467 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4468 CPUID_7_0_EBX_SHA_NI, 4469 .features[FEAT_7_0_ECX] = 4470 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4471 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4472 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4473 .features[FEAT_7_0_EDX] = 4474 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4475 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4476 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4477 .features[FEAT_ARCH_CAPABILITIES] = 4478 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4479 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4480 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4481 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4482 MSR_ARCH_CAP_PBRSB_NO, 4483 .features[FEAT_XSAVE] = 4484 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4485 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4486 .features[FEAT_6_EAX] = 4487 CPUID_6_EAX_ARAT, 4488 .features[FEAT_7_1_EAX] = 4489 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4490 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4491 .features[FEAT_7_1_EDX] = 4492 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4493 .features[FEAT_7_2_EDX] = 4494 CPUID_7_2_EDX_MCDT_NO, 4495 .features[FEAT_VMX_BASIC] = 4496 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4497 .features[FEAT_VMX_ENTRY_CTLS] = 4498 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4499 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4500 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4501 .features[FEAT_VMX_EPT_VPID_CAPS] = 4502 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4503 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4504 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4505 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4506 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4507 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4508 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4509 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4510 .features[FEAT_VMX_EXIT_CTLS] = 4511 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4512 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4513 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4514 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4515 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4516 .features[FEAT_VMX_MISC] = 4517 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4518 MSR_VMX_MISC_VMWRITE_VMEXIT, 4519 .features[FEAT_VMX_PINBASED_CTLS] = 4520 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4521 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4522 VMX_PIN_BASED_POSTED_INTR, 4523 .features[FEAT_VMX_PROCBASED_CTLS] = 4524 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4525 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4526 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4527 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4528 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4529 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4530 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4531 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4532 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4533 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4534 VMX_CPU_BASED_PAUSE_EXITING | 4535 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4536 .features[FEAT_VMX_SECONDARY_CTLS] = 4537 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4538 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4539 VMX_SECONDARY_EXEC_RDTSCP | 4540 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4541 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4542 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4543 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4544 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4545 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4546 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4547 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4548 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4549 VMX_SECONDARY_EXEC_XSAVES, 4550 .features[FEAT_VMX_VMFUNC] = 4551 MSR_VMX_VMFUNC_EPT_SWITCHING, 4552 .xlevel = 0x80000008, 4553 .model_id = "Intel Xeon Processor (SierraForest)", 4554 .versions = (X86CPUVersionDefinition[]) { 4555 { .version = 1 }, 4556 { 4557 .version = 2, 4558 .props = (PropValue[]) { 4559 { "ss", "on" }, 4560 { "tsc-adjust", "on" }, 4561 { "cldemote", "on" }, 4562 { "movdiri", "on" }, 4563 { "movdir64b", "on" }, 4564 { "gds-no", "on" }, 4565 { "rfds-no", "on" }, 4566 { "lam", "on" }, 4567 { "intel-psfd", "on"}, 4568 { "ipred-ctrl", "on"}, 4569 { "rrsba-ctrl", "on"}, 4570 { "bhi-ctrl", "on"}, 4571 { "stepping", "3" }, 4572 { /* end of list */ } 4573 } 4574 }, 4575 { /* end of list */ }, 4576 }, 4577 }, 4578 { 4579 .name = "ClearwaterForest", 4580 .level = 0x23, 4581 .xlevel = 0x80000008, 4582 .vendor = CPUID_VENDOR_INTEL, 4583 .family = 6, 4584 .model = 221, 4585 .stepping = 0, 4586 /* 4587 * please keep the ascending order so that we can have a clear view of 4588 * bit position of each feature. 4589 */ 4590 .features[FEAT_1_EDX] = 4591 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4592 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4593 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4594 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4595 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 4596 .features[FEAT_1_ECX] = 4597 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4598 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4599 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4600 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4601 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4602 .features[FEAT_8000_0001_EDX] = 4603 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4604 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4605 .features[FEAT_8000_0001_ECX] = 4606 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4607 .features[FEAT_8000_0008_EBX] = 4608 CPUID_8000_0008_EBX_WBNOINVD, 4609 .features[FEAT_7_0_EBX] = 4610 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 4611 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4612 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4613 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4614 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4615 CPUID_7_0_EBX_SHA_NI, 4616 .features[FEAT_7_0_ECX] = 4617 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4618 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4619 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 4620 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 4621 CPUID_7_0_ECX_MOVDIR64B, 4622 .features[FEAT_7_0_EDX] = 4623 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4624 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4625 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4626 .features[FEAT_ARCH_CAPABILITIES] = 4627 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4628 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4629 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4630 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4631 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 4632 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 4633 .features[FEAT_XSAVE] = 4634 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4635 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4636 .features[FEAT_6_EAX] = 4637 CPUID_6_EAX_ARAT, 4638 .features[FEAT_7_1_EAX] = 4639 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 4640 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4641 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 4642 CPUID_7_1_EAX_LAM, 4643 .features[FEAT_7_1_EDX] = 4644 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 4645 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 4646 .features[FEAT_7_2_EDX] = 4647 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 4648 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 4649 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 4650 .features[FEAT_VMX_BASIC] = 4651 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4652 .features[FEAT_VMX_ENTRY_CTLS] = 4653 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4654 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4655 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4656 .features[FEAT_VMX_EPT_VPID_CAPS] = 4657 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4658 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4659 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4660 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4661 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4662 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4663 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4664 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4665 .features[FEAT_VMX_EXIT_CTLS] = 4666 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4667 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4668 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4669 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4670 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4671 .features[FEAT_VMX_MISC] = 4672 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4673 MSR_VMX_MISC_VMWRITE_VMEXIT, 4674 .features[FEAT_VMX_PINBASED_CTLS] = 4675 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4676 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4677 VMX_PIN_BASED_POSTED_INTR, 4678 .features[FEAT_VMX_PROCBASED_CTLS] = 4679 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4680 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4681 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4682 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4683 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4684 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4685 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4686 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4687 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4688 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4689 VMX_CPU_BASED_PAUSE_EXITING | 4690 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4691 .features[FEAT_VMX_SECONDARY_CTLS] = 4692 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4693 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4694 VMX_SECONDARY_EXEC_RDTSCP | 4695 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4696 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4697 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4698 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4699 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4700 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4701 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4702 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4703 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4704 VMX_SECONDARY_EXEC_XSAVES, 4705 .features[FEAT_VMX_VMFUNC] = 4706 MSR_VMX_VMFUNC_EPT_SWITCHING, 4707 .model_id = "Intel Xeon Processor (ClearwaterForest)", 4708 .versions = (X86CPUVersionDefinition[]) { 4709 { .version = 1 }, 4710 { /* end of list */ }, 4711 }, 4712 }, 4713 { 4714 .name = "Denverton", 4715 .level = 21, 4716 .vendor = CPUID_VENDOR_INTEL, 4717 .family = 6, 4718 .model = 95, 4719 .stepping = 1, 4720 .features[FEAT_1_EDX] = 4721 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4722 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4723 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4724 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4725 CPUID_SSE | CPUID_SSE2, 4726 .features[FEAT_1_ECX] = 4727 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4728 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4729 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4730 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4731 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4732 .features[FEAT_8000_0001_EDX] = 4733 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4734 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4735 .features[FEAT_8000_0001_ECX] = 4736 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4737 .features[FEAT_7_0_EBX] = 4738 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4739 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4740 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4741 .features[FEAT_7_0_EDX] = 4742 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4743 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4744 /* XSAVES is added in version 3 */ 4745 .features[FEAT_XSAVE] = 4746 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4747 .features[FEAT_6_EAX] = 4748 CPUID_6_EAX_ARAT, 4749 .features[FEAT_ARCH_CAPABILITIES] = 4750 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4751 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4752 MSR_VMX_BASIC_TRUE_CTLS, 4753 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4754 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4755 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4756 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4757 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4758 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4759 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4760 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4761 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4762 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4763 .features[FEAT_VMX_EXIT_CTLS] = 4764 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4765 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4766 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4767 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4768 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4769 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4770 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4771 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4772 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4773 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4774 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4775 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4776 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4777 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4778 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4779 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4780 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4781 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4782 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4783 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4784 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4785 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4786 .features[FEAT_VMX_SECONDARY_CTLS] = 4787 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4788 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4789 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4790 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4791 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4792 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4793 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4794 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4795 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4796 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4797 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4798 .xlevel = 0x80000008, 4799 .model_id = "Intel Atom Processor (Denverton)", 4800 .versions = (X86CPUVersionDefinition[]) { 4801 { .version = 1 }, 4802 { 4803 .version = 2, 4804 .note = "no MPX, no MONITOR", 4805 .props = (PropValue[]) { 4806 { "monitor", "off" }, 4807 { "mpx", "off" }, 4808 { /* end of list */ }, 4809 }, 4810 }, 4811 { 4812 .version = 3, 4813 .note = "XSAVES, no MPX, no MONITOR", 4814 .props = (PropValue[]) { 4815 { "xsaves", "on" }, 4816 { "vmx-xsaves", "on" }, 4817 { /* end of list */ }, 4818 }, 4819 }, 4820 { /* end of list */ }, 4821 }, 4822 }, 4823 { 4824 .name = "Snowridge", 4825 .level = 27, 4826 .vendor = CPUID_VENDOR_INTEL, 4827 .family = 6, 4828 .model = 134, 4829 .stepping = 1, 4830 .features[FEAT_1_EDX] = 4831 /* missing: CPUID_PN CPUID_IA64 */ 4832 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4833 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4834 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4835 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4836 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4837 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4838 CPUID_MMX | 4839 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4840 .features[FEAT_1_ECX] = 4841 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4842 CPUID_EXT_SSSE3 | 4843 CPUID_EXT_CX16 | 4844 CPUID_EXT_SSE41 | 4845 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4846 CPUID_EXT_POPCNT | 4847 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4848 CPUID_EXT_RDRAND, 4849 .features[FEAT_8000_0001_EDX] = 4850 CPUID_EXT2_SYSCALL | 4851 CPUID_EXT2_NX | 4852 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4853 CPUID_EXT2_LM, 4854 .features[FEAT_8000_0001_ECX] = 4855 CPUID_EXT3_LAHF_LM | 4856 CPUID_EXT3_3DNOWPREFETCH, 4857 .features[FEAT_7_0_EBX] = 4858 CPUID_7_0_EBX_FSGSBASE | 4859 CPUID_7_0_EBX_SMEP | 4860 CPUID_7_0_EBX_ERMS | 4861 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4862 CPUID_7_0_EBX_RDSEED | 4863 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4864 CPUID_7_0_EBX_CLWB | 4865 CPUID_7_0_EBX_SHA_NI, 4866 .features[FEAT_7_0_ECX] = 4867 CPUID_7_0_ECX_UMIP | 4868 /* missing bit 5 */ 4869 CPUID_7_0_ECX_GFNI | 4870 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4871 CPUID_7_0_ECX_MOVDIR64B, 4872 .features[FEAT_7_0_EDX] = 4873 CPUID_7_0_EDX_SPEC_CTRL | 4874 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4875 CPUID_7_0_EDX_CORE_CAPABILITY, 4876 .features[FEAT_CORE_CAPABILITY] = 4877 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4878 /* XSAVES is added in version 3 */ 4879 .features[FEAT_XSAVE] = 4880 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4881 CPUID_XSAVE_XGETBV1, 4882 .features[FEAT_6_EAX] = 4883 CPUID_6_EAX_ARAT, 4884 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4885 MSR_VMX_BASIC_TRUE_CTLS, 4886 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4887 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4888 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4889 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4890 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4891 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4892 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4893 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4894 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4895 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4896 .features[FEAT_VMX_EXIT_CTLS] = 4897 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4898 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4899 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4900 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4901 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4902 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4903 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4904 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4905 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4906 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4907 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4908 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4909 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4910 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4911 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4912 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4913 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4914 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4915 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4916 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4917 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4918 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4919 .features[FEAT_VMX_SECONDARY_CTLS] = 4920 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4921 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4922 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4923 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4924 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4925 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4926 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4927 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4928 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4929 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4930 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4931 .xlevel = 0x80000008, 4932 .model_id = "Intel Atom Processor (SnowRidge)", 4933 .versions = (X86CPUVersionDefinition[]) { 4934 { .version = 1 }, 4935 { 4936 .version = 2, 4937 .props = (PropValue[]) { 4938 { "mpx", "off" }, 4939 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4940 { /* end of list */ }, 4941 }, 4942 }, 4943 { 4944 .version = 3, 4945 .note = "XSAVES, no MPX", 4946 .props = (PropValue[]) { 4947 { "xsaves", "on" }, 4948 { "vmx-xsaves", "on" }, 4949 { /* end of list */ }, 4950 }, 4951 }, 4952 { 4953 .version = 4, 4954 .note = "no split lock detect, no core-capability", 4955 .props = (PropValue[]) { 4956 { "split-lock-detect", "off" }, 4957 { "core-capability", "off" }, 4958 { /* end of list */ }, 4959 }, 4960 }, 4961 { /* end of list */ }, 4962 }, 4963 }, 4964 { 4965 .name = "KnightsMill", 4966 .level = 0xd, 4967 .vendor = CPUID_VENDOR_INTEL, 4968 .family = 6, 4969 .model = 133, 4970 .stepping = 0, 4971 .features[FEAT_1_EDX] = 4972 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4973 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4974 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4975 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4976 CPUID_PSE | CPUID_DE | CPUID_FP87, 4977 .features[FEAT_1_ECX] = 4978 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4979 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4980 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4981 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4982 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4983 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4984 .features[FEAT_8000_0001_EDX] = 4985 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4986 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4987 .features[FEAT_8000_0001_ECX] = 4988 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4989 .features[FEAT_7_0_EBX] = 4990 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4991 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4992 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4993 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4994 CPUID_7_0_EBX_AVX512ER, 4995 .features[FEAT_7_0_ECX] = 4996 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4997 .features[FEAT_7_0_EDX] = 4998 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4999 .features[FEAT_XSAVE] = 5000 CPUID_XSAVE_XSAVEOPT, 5001 .features[FEAT_6_EAX] = 5002 CPUID_6_EAX_ARAT, 5003 .xlevel = 0x80000008, 5004 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5005 }, 5006 { 5007 .name = "Opteron_G1", 5008 .level = 5, 5009 .vendor = CPUID_VENDOR_AMD, 5010 .family = 15, 5011 .model = 6, 5012 .stepping = 1, 5013 .features[FEAT_1_EDX] = 5014 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5015 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5016 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5017 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5018 CPUID_DE | CPUID_FP87, 5019 .features[FEAT_1_ECX] = 5020 CPUID_EXT_SSE3, 5021 .features[FEAT_8000_0001_EDX] = 5022 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5023 .xlevel = 0x80000008, 5024 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5025 }, 5026 { 5027 .name = "Opteron_G2", 5028 .level = 5, 5029 .vendor = CPUID_VENDOR_AMD, 5030 .family = 15, 5031 .model = 6, 5032 .stepping = 1, 5033 .features[FEAT_1_EDX] = 5034 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5035 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5036 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5037 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5038 CPUID_DE | CPUID_FP87, 5039 .features[FEAT_1_ECX] = 5040 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5041 .features[FEAT_8000_0001_EDX] = 5042 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5043 .features[FEAT_8000_0001_ECX] = 5044 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5045 .xlevel = 0x80000008, 5046 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5047 }, 5048 { 5049 .name = "Opteron_G3", 5050 .level = 5, 5051 .vendor = CPUID_VENDOR_AMD, 5052 .family = 16, 5053 .model = 2, 5054 .stepping = 3, 5055 .features[FEAT_1_EDX] = 5056 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5057 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5058 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5059 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5060 CPUID_DE | CPUID_FP87, 5061 .features[FEAT_1_ECX] = 5062 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5063 CPUID_EXT_SSE3, 5064 .features[FEAT_8000_0001_EDX] = 5065 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5066 CPUID_EXT2_RDTSCP, 5067 .features[FEAT_8000_0001_ECX] = 5068 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5069 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5070 .xlevel = 0x80000008, 5071 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5072 }, 5073 { 5074 .name = "Opteron_G4", 5075 .level = 0xd, 5076 .vendor = CPUID_VENDOR_AMD, 5077 .family = 21, 5078 .model = 1, 5079 .stepping = 2, 5080 .features[FEAT_1_EDX] = 5081 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5082 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5083 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5084 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5085 CPUID_DE | CPUID_FP87, 5086 .features[FEAT_1_ECX] = 5087 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5088 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5089 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5090 CPUID_EXT_SSE3, 5091 .features[FEAT_8000_0001_EDX] = 5092 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5093 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5094 .features[FEAT_8000_0001_ECX] = 5095 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5096 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5097 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5098 CPUID_EXT3_LAHF_LM, 5099 .features[FEAT_SVM] = 5100 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5101 /* no xsaveopt! */ 5102 .xlevel = 0x8000001A, 5103 .model_id = "AMD Opteron 62xx class CPU", 5104 }, 5105 { 5106 .name = "Opteron_G5", 5107 .level = 0xd, 5108 .vendor = CPUID_VENDOR_AMD, 5109 .family = 21, 5110 .model = 2, 5111 .stepping = 0, 5112 .features[FEAT_1_EDX] = 5113 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5114 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5115 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5116 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5117 CPUID_DE | CPUID_FP87, 5118 .features[FEAT_1_ECX] = 5119 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5120 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5121 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5122 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5123 .features[FEAT_8000_0001_EDX] = 5124 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5125 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5126 .features[FEAT_8000_0001_ECX] = 5127 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5128 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5129 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5130 CPUID_EXT3_LAHF_LM, 5131 .features[FEAT_SVM] = 5132 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5133 /* no xsaveopt! */ 5134 .xlevel = 0x8000001A, 5135 .model_id = "AMD Opteron 63xx class CPU", 5136 }, 5137 { 5138 .name = "EPYC", 5139 .level = 0xd, 5140 .vendor = CPUID_VENDOR_AMD, 5141 .family = 23, 5142 .model = 1, 5143 .stepping = 2, 5144 .features[FEAT_1_EDX] = 5145 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5146 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5147 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5148 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5149 CPUID_VME | CPUID_FP87, 5150 .features[FEAT_1_ECX] = 5151 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5152 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5153 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5154 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5155 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5156 .features[FEAT_8000_0001_EDX] = 5157 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5158 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5159 CPUID_EXT2_SYSCALL, 5160 .features[FEAT_8000_0001_ECX] = 5161 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5162 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5163 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5164 CPUID_EXT3_TOPOEXT, 5165 .features[FEAT_7_0_EBX] = 5166 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5167 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5168 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5169 CPUID_7_0_EBX_SHA_NI, 5170 .features[FEAT_XSAVE] = 5171 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5172 CPUID_XSAVE_XGETBV1, 5173 .features[FEAT_6_EAX] = 5174 CPUID_6_EAX_ARAT, 5175 .features[FEAT_SVM] = 5176 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5177 .xlevel = 0x8000001E, 5178 .model_id = "AMD EPYC Processor", 5179 .cache_info = &epyc_cache_info, 5180 .versions = (X86CPUVersionDefinition[]) { 5181 { .version = 1 }, 5182 { 5183 .version = 2, 5184 .alias = "EPYC-IBPB", 5185 .props = (PropValue[]) { 5186 { "ibpb", "on" }, 5187 { "model-id", 5188 "AMD EPYC Processor (with IBPB)" }, 5189 { /* end of list */ } 5190 } 5191 }, 5192 { 5193 .version = 3, 5194 .props = (PropValue[]) { 5195 { "ibpb", "on" }, 5196 { "perfctr-core", "on" }, 5197 { "clzero", "on" }, 5198 { "xsaveerptr", "on" }, 5199 { "xsaves", "on" }, 5200 { "model-id", 5201 "AMD EPYC Processor" }, 5202 { /* end of list */ } 5203 } 5204 }, 5205 { 5206 .version = 4, 5207 .props = (PropValue[]) { 5208 { "model-id", 5209 "AMD EPYC-v4 Processor" }, 5210 { /* end of list */ } 5211 }, 5212 .cache_info = &epyc_v4_cache_info 5213 }, 5214 { /* end of list */ } 5215 } 5216 }, 5217 { 5218 .name = "Dhyana", 5219 .level = 0xd, 5220 .vendor = CPUID_VENDOR_HYGON, 5221 .family = 24, 5222 .model = 0, 5223 .stepping = 1, 5224 .features[FEAT_1_EDX] = 5225 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5226 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5227 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5228 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5229 CPUID_VME | CPUID_FP87, 5230 .features[FEAT_1_ECX] = 5231 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5232 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5233 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5234 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5235 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5236 .features[FEAT_8000_0001_EDX] = 5237 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5238 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5239 CPUID_EXT2_SYSCALL, 5240 .features[FEAT_8000_0001_ECX] = 5241 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5242 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5243 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5244 CPUID_EXT3_TOPOEXT, 5245 .features[FEAT_8000_0008_EBX] = 5246 CPUID_8000_0008_EBX_IBPB, 5247 .features[FEAT_7_0_EBX] = 5248 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5249 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5250 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5251 /* XSAVES is added in version 2 */ 5252 .features[FEAT_XSAVE] = 5253 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5254 CPUID_XSAVE_XGETBV1, 5255 .features[FEAT_6_EAX] = 5256 CPUID_6_EAX_ARAT, 5257 .features[FEAT_SVM] = 5258 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5259 .xlevel = 0x8000001E, 5260 .model_id = "Hygon Dhyana Processor", 5261 .cache_info = &epyc_cache_info, 5262 .versions = (X86CPUVersionDefinition[]) { 5263 { .version = 1 }, 5264 { .version = 2, 5265 .note = "XSAVES", 5266 .props = (PropValue[]) { 5267 { "xsaves", "on" }, 5268 { /* end of list */ } 5269 }, 5270 }, 5271 { /* end of list */ } 5272 } 5273 }, 5274 { 5275 .name = "EPYC-Rome", 5276 .level = 0xd, 5277 .vendor = CPUID_VENDOR_AMD, 5278 .family = 23, 5279 .model = 49, 5280 .stepping = 0, 5281 .features[FEAT_1_EDX] = 5282 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5283 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5284 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5285 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5286 CPUID_VME | CPUID_FP87, 5287 .features[FEAT_1_ECX] = 5288 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5289 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5290 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5291 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5292 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5293 .features[FEAT_8000_0001_EDX] = 5294 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5295 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5296 CPUID_EXT2_SYSCALL, 5297 .features[FEAT_8000_0001_ECX] = 5298 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5299 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5300 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5301 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5302 .features[FEAT_8000_0008_EBX] = 5303 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5304 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5305 CPUID_8000_0008_EBX_STIBP, 5306 .features[FEAT_7_0_EBX] = 5307 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5308 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5309 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5310 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5311 .features[FEAT_7_0_ECX] = 5312 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5313 .features[FEAT_XSAVE] = 5314 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5315 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5316 .features[FEAT_6_EAX] = 5317 CPUID_6_EAX_ARAT, 5318 .features[FEAT_SVM] = 5319 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5320 .xlevel = 0x8000001E, 5321 .model_id = "AMD EPYC-Rome Processor", 5322 .cache_info = &epyc_rome_cache_info, 5323 .versions = (X86CPUVersionDefinition[]) { 5324 { .version = 1 }, 5325 { 5326 .version = 2, 5327 .props = (PropValue[]) { 5328 { "ibrs", "on" }, 5329 { "amd-ssbd", "on" }, 5330 { /* end of list */ } 5331 } 5332 }, 5333 { 5334 .version = 3, 5335 .props = (PropValue[]) { 5336 { "model-id", 5337 "AMD EPYC-Rome-v3 Processor" }, 5338 { /* end of list */ } 5339 }, 5340 .cache_info = &epyc_rome_v3_cache_info 5341 }, 5342 { 5343 .version = 4, 5344 .props = (PropValue[]) { 5345 /* Erratum 1386 */ 5346 { "model-id", 5347 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5348 { "xsaves", "off" }, 5349 { /* end of list */ } 5350 }, 5351 }, 5352 { /* end of list */ } 5353 } 5354 }, 5355 { 5356 .name = "EPYC-Milan", 5357 .level = 0xd, 5358 .vendor = CPUID_VENDOR_AMD, 5359 .family = 25, 5360 .model = 1, 5361 .stepping = 1, 5362 .features[FEAT_1_EDX] = 5363 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5364 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5365 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5366 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5367 CPUID_VME | CPUID_FP87, 5368 .features[FEAT_1_ECX] = 5369 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5370 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5371 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5372 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5373 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5374 CPUID_EXT_PCID, 5375 .features[FEAT_8000_0001_EDX] = 5376 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5377 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5378 CPUID_EXT2_SYSCALL, 5379 .features[FEAT_8000_0001_ECX] = 5380 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5381 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5382 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5383 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5384 .features[FEAT_8000_0008_EBX] = 5385 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5386 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5387 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5388 CPUID_8000_0008_EBX_AMD_SSBD, 5389 .features[FEAT_7_0_EBX] = 5390 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5391 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5392 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5393 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5394 CPUID_7_0_EBX_INVPCID, 5395 .features[FEAT_7_0_ECX] = 5396 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5397 .features[FEAT_7_0_EDX] = 5398 CPUID_7_0_EDX_FSRM, 5399 .features[FEAT_XSAVE] = 5400 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5401 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5402 .features[FEAT_6_EAX] = 5403 CPUID_6_EAX_ARAT, 5404 .features[FEAT_SVM] = 5405 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5406 .xlevel = 0x8000001E, 5407 .model_id = "AMD EPYC-Milan Processor", 5408 .cache_info = &epyc_milan_cache_info, 5409 .versions = (X86CPUVersionDefinition[]) { 5410 { .version = 1 }, 5411 { 5412 .version = 2, 5413 .props = (PropValue[]) { 5414 { "model-id", 5415 "AMD EPYC-Milan-v2 Processor" }, 5416 { "vaes", "on" }, 5417 { "vpclmulqdq", "on" }, 5418 { "stibp-always-on", "on" }, 5419 { "amd-psfd", "on" }, 5420 { "no-nested-data-bp", "on" }, 5421 { "lfence-always-serializing", "on" }, 5422 { "null-sel-clr-base", "on" }, 5423 { /* end of list */ } 5424 }, 5425 .cache_info = &epyc_milan_v2_cache_info 5426 }, 5427 { /* end of list */ } 5428 } 5429 }, 5430 { 5431 .name = "EPYC-Genoa", 5432 .level = 0xd, 5433 .vendor = CPUID_VENDOR_AMD, 5434 .family = 25, 5435 .model = 17, 5436 .stepping = 0, 5437 .features[FEAT_1_EDX] = 5438 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5439 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5440 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5441 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5442 CPUID_VME | CPUID_FP87, 5443 .features[FEAT_1_ECX] = 5444 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5445 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5446 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5447 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5448 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5449 CPUID_EXT_SSE3, 5450 .features[FEAT_8000_0001_EDX] = 5451 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5452 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5453 CPUID_EXT2_SYSCALL, 5454 .features[FEAT_8000_0001_ECX] = 5455 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5456 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5457 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5458 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5459 .features[FEAT_8000_0008_EBX] = 5460 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5461 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5462 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5463 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5464 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5465 .features[FEAT_8000_0021_EAX] = 5466 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5467 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5468 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5469 CPUID_8000_0021_EAX_AUTO_IBRS, 5470 .features[FEAT_7_0_EBX] = 5471 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5472 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5473 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5474 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5475 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5476 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5477 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5478 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5479 .features[FEAT_7_0_ECX] = 5480 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5481 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5482 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5483 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5484 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5485 CPUID_7_0_ECX_RDPID, 5486 .features[FEAT_7_0_EDX] = 5487 CPUID_7_0_EDX_FSRM, 5488 .features[FEAT_7_1_EAX] = 5489 CPUID_7_1_EAX_AVX512_BF16, 5490 .features[FEAT_XSAVE] = 5491 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5492 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5493 .features[FEAT_6_EAX] = 5494 CPUID_6_EAX_ARAT, 5495 .features[FEAT_SVM] = 5496 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5497 CPUID_SVM_SVME_ADDR_CHK, 5498 .xlevel = 0x80000022, 5499 .model_id = "AMD EPYC-Genoa Processor", 5500 .cache_info = &epyc_genoa_cache_info, 5501 }, 5502 { 5503 .name = "YongFeng", 5504 .level = 0x1F, 5505 .vendor = CPUID_VENDOR_ZHAOXIN1, 5506 .family = 7, 5507 .model = 11, 5508 .stepping = 3, 5509 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 5510 .features[FEAT_1_EDX] = 5511 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5512 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5513 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5514 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5515 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 5516 /* 5517 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 5518 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 5519 */ 5520 .features[FEAT_1_ECX] = 5521 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5522 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 5523 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 5524 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 5525 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5526 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5527 .features[FEAT_7_0_EBX] = 5528 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 5529 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 5530 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 5531 CPUID_7_0_EBX_FSGSBASE, 5532 /* missing: CPUID_7_0_ECX_OSPKE */ 5533 .features[FEAT_7_0_ECX] = 5534 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 5535 .features[FEAT_7_0_EDX] = 5536 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 5537 .features[FEAT_8000_0001_EDX] = 5538 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5539 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5540 .features[FEAT_8000_0001_ECX] = 5541 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 5542 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 5543 /* 5544 * TODO: When the Linux kernel introduces other existing definitions 5545 * for this leaf, remember to update the definitions here. 5546 */ 5547 .features[FEAT_C000_0001_EDX] = 5548 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 5549 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 5550 CPUID_C000_0001_EDX_ACE2 | 5551 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 5552 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 5553 .features[FEAT_XSAVE] = 5554 CPUID_XSAVE_XSAVEOPT, 5555 .features[FEAT_ARCH_CAPABILITIES] = 5556 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 5557 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 5558 MSR_ARCH_CAP_SSB_NO, 5559 .features[FEAT_VMX_PROCBASED_CTLS] = 5560 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 5561 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 5562 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 5563 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 5564 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 5565 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 5566 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 5567 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5568 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 5569 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5570 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5571 /* 5572 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 5573 * VMX_SECONDARY_EXEC_TSC_SCALING 5574 */ 5575 .features[FEAT_VMX_SECONDARY_CTLS] = 5576 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5577 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5578 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 5579 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5580 VMX_SECONDARY_EXEC_WBINVD_EXITING | 5581 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5582 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5583 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5584 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5585 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5586 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 5587 VMX_SECONDARY_EXEC_SHADOW_VMCS | 5588 VMX_SECONDARY_EXEC_ENABLE_PML, 5589 .features[FEAT_VMX_PINBASED_CTLS] = 5590 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5591 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5592 VMX_PIN_BASED_POSTED_INTR, 5593 .features[FEAT_VMX_EXIT_CTLS] = 5594 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 5595 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5596 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5597 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5598 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5599 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 5600 .features[FEAT_VMX_ENTRY_CTLS] = 5601 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5602 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5603 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5604 /* 5605 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 5606 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 5607 */ 5608 .features[FEAT_VMX_MISC] = 5609 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5610 MSR_VMX_MISC_VMWRITE_VMEXIT, 5611 /* missing: MSR_VMX_EPT_UC */ 5612 .features[FEAT_VMX_EPT_VPID_CAPS] = 5613 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5614 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5615 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5616 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5617 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 5618 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5619 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5620 .features[FEAT_VMX_BASIC] = 5621 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5622 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5623 .xlevel = 0x80000008, 5624 .model_id = "Zhaoxin YongFeng Processor", 5625 .versions = (X86CPUVersionDefinition[]) { 5626 { .version = 1 }, 5627 { 5628 .version = 2, 5629 .note = "with the correct model number", 5630 .props = (PropValue[]) { 5631 { "model", "0x5b" }, 5632 { /* end of list */ } 5633 } 5634 }, 5635 { /* end of list */ } 5636 } 5637 }, 5638 }; 5639 5640 /* 5641 * We resolve CPU model aliases using -v1 when using "-machine 5642 * none", but this is just for compatibility while libvirt isn't 5643 * adapted to resolve CPU model versions before creating VMs. 5644 * See "Runnability guarantee of CPU models" at 5645 * docs/about/deprecated.rst. 5646 */ 5647 X86CPUVersion default_cpu_version = 1; 5648 5649 void x86_cpu_set_default_version(X86CPUVersion version) 5650 { 5651 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5652 assert(version != CPU_VERSION_AUTO); 5653 default_cpu_version = version; 5654 } 5655 5656 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5657 { 5658 int v = 0; 5659 const X86CPUVersionDefinition *vdef = 5660 x86_cpu_def_get_versions(model->cpudef); 5661 while (vdef->version) { 5662 v = vdef->version; 5663 vdef++; 5664 } 5665 return v; 5666 } 5667 5668 /* Return the actual version being used for a specific CPU model */ 5669 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5670 { 5671 X86CPUVersion v = model->version; 5672 if (v == CPU_VERSION_AUTO) { 5673 v = default_cpu_version; 5674 } 5675 if (v == CPU_VERSION_LATEST) { 5676 return x86_cpu_model_last_version(model); 5677 } 5678 return v; 5679 } 5680 5681 static const Property max_x86_cpu_properties[] = { 5682 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5683 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5684 }; 5685 5686 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5687 { 5688 Object *obj = OBJECT(dev); 5689 5690 if (!object_property_get_int(obj, "family", &error_abort)) { 5691 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5692 object_property_set_int(obj, "family", 15, &error_abort); 5693 object_property_set_int(obj, "model", 107, &error_abort); 5694 object_property_set_int(obj, "stepping", 1, &error_abort); 5695 } else { 5696 object_property_set_int(obj, "family", 6, &error_abort); 5697 object_property_set_int(obj, "model", 6, &error_abort); 5698 object_property_set_int(obj, "stepping", 3, &error_abort); 5699 } 5700 } 5701 5702 x86_cpu_realizefn(dev, errp); 5703 } 5704 5705 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5706 { 5707 DeviceClass *dc = DEVICE_CLASS(oc); 5708 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5709 5710 xcc->ordering = 9; 5711 5712 xcc->model_description = 5713 "Enables all features supported by the accelerator in the current host"; 5714 5715 device_class_set_props(dc, max_x86_cpu_properties); 5716 dc->realize = max_x86_cpu_realize; 5717 } 5718 5719 static void max_x86_cpu_initfn(Object *obj) 5720 { 5721 X86CPU *cpu = X86_CPU(obj); 5722 5723 /* We can't fill the features array here because we don't know yet if 5724 * "migratable" is true or false. 5725 */ 5726 cpu->max_features = true; 5727 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5728 5729 /* 5730 * these defaults are used for TCG and all other accelerators 5731 * besides KVM and HVF, which overwrite these values 5732 */ 5733 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5734 &error_abort); 5735 object_property_set_str(OBJECT(cpu), "model-id", 5736 "QEMU TCG CPU version " QEMU_HW_VERSION, 5737 &error_abort); 5738 } 5739 5740 static const TypeInfo max_x86_cpu_type_info = { 5741 .name = X86_CPU_TYPE_NAME("max"), 5742 .parent = TYPE_X86_CPU, 5743 .instance_init = max_x86_cpu_initfn, 5744 .class_init = max_x86_cpu_class_init, 5745 }; 5746 5747 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5748 { 5749 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5750 5751 switch (f->type) { 5752 case CPUID_FEATURE_WORD: 5753 { 5754 const char *reg = get_register_name_32(f->cpuid.reg); 5755 assert(reg); 5756 return g_strdup_printf("CPUID.%02XH:%s", 5757 f->cpuid.eax, reg); 5758 } 5759 case MSR_FEATURE_WORD: 5760 return g_strdup_printf("MSR(%02XH)", 5761 f->msr.index); 5762 } 5763 5764 return NULL; 5765 } 5766 5767 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5768 { 5769 FeatureWord w; 5770 5771 for (w = 0; w < FEATURE_WORDS; w++) { 5772 if (cpu->filtered_features[w]) { 5773 return true; 5774 } 5775 } 5776 5777 return false; 5778 } 5779 5780 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5781 const char *verbose_prefix) 5782 { 5783 CPUX86State *env = &cpu->env; 5784 FeatureWordInfo *f = &feature_word_info[w]; 5785 int i; 5786 5787 if (!cpu->force_features) { 5788 env->features[w] &= ~mask; 5789 } 5790 cpu->filtered_features[w] |= mask; 5791 5792 if (!verbose_prefix) { 5793 return; 5794 } 5795 5796 for (i = 0; i < 64; ++i) { 5797 if ((1ULL << i) & mask) { 5798 g_autofree char *feat_word_str = feature_word_description(f, i); 5799 warn_report("%s: %s%s%s [bit %d]", 5800 verbose_prefix, 5801 feat_word_str, 5802 f->feat_names[i] ? "." : "", 5803 f->feat_names[i] ? f->feat_names[i] : "", i); 5804 } 5805 } 5806 } 5807 5808 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5809 const char *name, void *opaque, 5810 Error **errp) 5811 { 5812 X86CPU *cpu = X86_CPU(obj); 5813 CPUX86State *env = &cpu->env; 5814 uint64_t value; 5815 5816 value = (env->cpuid_version >> 8) & 0xf; 5817 if (value == 0xf) { 5818 value += (env->cpuid_version >> 20) & 0xff; 5819 } 5820 visit_type_uint64(v, name, &value, errp); 5821 } 5822 5823 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5824 const char *name, void *opaque, 5825 Error **errp) 5826 { 5827 X86CPU *cpu = X86_CPU(obj); 5828 CPUX86State *env = &cpu->env; 5829 const uint64_t max = 0xff + 0xf; 5830 uint64_t value; 5831 5832 if (!visit_type_uint64(v, name, &value, errp)) { 5833 return; 5834 } 5835 if (value > max) { 5836 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5837 name ? name : "null", max); 5838 return; 5839 } 5840 5841 env->cpuid_version &= ~0xff00f00; 5842 if (value > 0x0f) { 5843 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5844 } else { 5845 env->cpuid_version |= value << 8; 5846 } 5847 } 5848 5849 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5850 const char *name, void *opaque, 5851 Error **errp) 5852 { 5853 X86CPU *cpu = X86_CPU(obj); 5854 CPUX86State *env = &cpu->env; 5855 uint64_t value; 5856 5857 value = (env->cpuid_version >> 4) & 0xf; 5858 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5859 visit_type_uint64(v, name, &value, errp); 5860 } 5861 5862 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5863 const char *name, void *opaque, 5864 Error **errp) 5865 { 5866 X86CPU *cpu = X86_CPU(obj); 5867 CPUX86State *env = &cpu->env; 5868 const uint64_t max = 0xff; 5869 uint64_t value; 5870 5871 if (!visit_type_uint64(v, name, &value, errp)) { 5872 return; 5873 } 5874 if (value > max) { 5875 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5876 name ? name : "null", max); 5877 return; 5878 } 5879 5880 env->cpuid_version &= ~0xf00f0; 5881 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5882 } 5883 5884 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5885 const char *name, void *opaque, 5886 Error **errp) 5887 { 5888 X86CPU *cpu = X86_CPU(obj); 5889 CPUX86State *env = &cpu->env; 5890 uint64_t value; 5891 5892 value = env->cpuid_version & 0xf; 5893 visit_type_uint64(v, name, &value, errp); 5894 } 5895 5896 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5897 const char *name, void *opaque, 5898 Error **errp) 5899 { 5900 X86CPU *cpu = X86_CPU(obj); 5901 CPUX86State *env = &cpu->env; 5902 const uint64_t max = 0xf; 5903 uint64_t value; 5904 5905 if (!visit_type_uint64(v, name, &value, errp)) { 5906 return; 5907 } 5908 if (value > max) { 5909 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5910 name ? name : "null", max); 5911 return; 5912 } 5913 5914 env->cpuid_version &= ~0xf; 5915 env->cpuid_version |= value & 0xf; 5916 } 5917 5918 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5919 { 5920 X86CPU *cpu = X86_CPU(obj); 5921 CPUX86State *env = &cpu->env; 5922 char *value; 5923 5924 value = g_malloc(CPUID_VENDOR_SZ + 1); 5925 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5926 env->cpuid_vendor3); 5927 return value; 5928 } 5929 5930 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5931 Error **errp) 5932 { 5933 X86CPU *cpu = X86_CPU(obj); 5934 CPUX86State *env = &cpu->env; 5935 int i; 5936 5937 if (strlen(value) != CPUID_VENDOR_SZ) { 5938 error_setg(errp, "value of property 'vendor' must consist of" 5939 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5940 return; 5941 } 5942 5943 env->cpuid_vendor1 = 0; 5944 env->cpuid_vendor2 = 0; 5945 env->cpuid_vendor3 = 0; 5946 for (i = 0; i < 4; i++) { 5947 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5948 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5949 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5950 } 5951 } 5952 5953 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5954 { 5955 X86CPU *cpu = X86_CPU(obj); 5956 CPUX86State *env = &cpu->env; 5957 char *value; 5958 int i; 5959 5960 value = g_malloc(48 + 1); 5961 for (i = 0; i < 48; i++) { 5962 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5963 } 5964 value[48] = '\0'; 5965 return value; 5966 } 5967 5968 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5969 Error **errp) 5970 { 5971 X86CPU *cpu = X86_CPU(obj); 5972 CPUX86State *env = &cpu->env; 5973 int c, len, i; 5974 5975 if (model_id == NULL) { 5976 model_id = ""; 5977 } 5978 len = strlen(model_id); 5979 memset(env->cpuid_model, 0, 48); 5980 for (i = 0; i < 48; i++) { 5981 if (i >= len) { 5982 c = '\0'; 5983 } else { 5984 c = (uint8_t)model_id[i]; 5985 } 5986 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5987 } 5988 } 5989 5990 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5991 void *opaque, Error **errp) 5992 { 5993 X86CPU *cpu = X86_CPU(obj); 5994 int64_t value; 5995 5996 value = cpu->env.tsc_khz * 1000; 5997 visit_type_int(v, name, &value, errp); 5998 } 5999 6000 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 6001 void *opaque, Error **errp) 6002 { 6003 X86CPU *cpu = X86_CPU(obj); 6004 const int64_t max = INT64_MAX; 6005 int64_t value; 6006 6007 if (!visit_type_int(v, name, &value, errp)) { 6008 return; 6009 } 6010 if (value < 0 || value > max) { 6011 error_setg(errp, "parameter '%s' can be at most %" PRId64, 6012 name ? name : "null", max); 6013 return; 6014 } 6015 6016 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 6017 } 6018 6019 /* Generic getter for "feature-words" and "filtered-features" properties */ 6020 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 6021 const char *name, void *opaque, 6022 Error **errp) 6023 { 6024 uint64_t *array = (uint64_t *)opaque; 6025 FeatureWord w; 6026 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 6027 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 6028 X86CPUFeatureWordInfoList *list = NULL; 6029 6030 for (w = 0; w < FEATURE_WORDS; w++) { 6031 FeatureWordInfo *wi = &feature_word_info[w]; 6032 /* 6033 * We didn't have MSR features when "feature-words" was 6034 * introduced. Therefore skipped other type entries. 6035 */ 6036 if (wi->type != CPUID_FEATURE_WORD) { 6037 continue; 6038 } 6039 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 6040 qwi->cpuid_input_eax = wi->cpuid.eax; 6041 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 6042 qwi->cpuid_input_ecx = wi->cpuid.ecx; 6043 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 6044 qwi->features = array[w]; 6045 6046 /* List will be in reverse order, but order shouldn't matter */ 6047 list_entries[w].next = list; 6048 list_entries[w].value = &word_infos[w]; 6049 list = &list_entries[w]; 6050 } 6051 6052 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 6053 } 6054 6055 /* Convert all '_' in a feature string option name to '-', to make feature 6056 * name conform to QOM property naming rule, which uses '-' instead of '_'. 6057 */ 6058 static inline void feat2prop(char *s) 6059 { 6060 while ((s = strchr(s, '_'))) { 6061 *s = '-'; 6062 } 6063 } 6064 6065 /* Return the feature property name for a feature flag bit */ 6066 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 6067 { 6068 const char *name; 6069 /* XSAVE components are automatically enabled by other features, 6070 * so return the original feature name instead 6071 */ 6072 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 6073 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 6074 6075 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 6076 x86_ext_save_areas[comp].bits) { 6077 w = x86_ext_save_areas[comp].feature; 6078 bitnr = ctz32(x86_ext_save_areas[comp].bits); 6079 } 6080 } 6081 6082 assert(bitnr < 64); 6083 assert(w < FEATURE_WORDS); 6084 name = feature_word_info[w].feat_names[bitnr]; 6085 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 6086 return name; 6087 } 6088 6089 /* Compatibility hack to maintain legacy +-feat semantic, 6090 * where +-feat overwrites any feature set by 6091 * feat=on|feat even if the later is parsed after +-feat 6092 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 6093 */ 6094 static GList *plus_features, *minus_features; 6095 6096 static gint compare_string(gconstpointer a, gconstpointer b) 6097 { 6098 return g_strcmp0(a, b); 6099 } 6100 6101 /* Parse "+feature,-feature,feature=foo" CPU feature string 6102 */ 6103 static void x86_cpu_parse_featurestr(const char *typename, char *features, 6104 Error **errp) 6105 { 6106 char *featurestr; /* Single 'key=value" string being parsed */ 6107 static bool cpu_globals_initialized; 6108 bool ambiguous = false; 6109 6110 if (cpu_globals_initialized) { 6111 return; 6112 } 6113 cpu_globals_initialized = true; 6114 6115 if (!features) { 6116 return; 6117 } 6118 6119 for (featurestr = strtok(features, ","); 6120 featurestr; 6121 featurestr = strtok(NULL, ",")) { 6122 const char *name; 6123 const char *val = NULL; 6124 char *eq = NULL; 6125 char num[32]; 6126 GlobalProperty *prop; 6127 6128 /* Compatibility syntax: */ 6129 if (featurestr[0] == '+') { 6130 plus_features = g_list_append(plus_features, 6131 g_strdup(featurestr + 1)); 6132 continue; 6133 } else if (featurestr[0] == '-') { 6134 minus_features = g_list_append(minus_features, 6135 g_strdup(featurestr + 1)); 6136 continue; 6137 } 6138 6139 eq = strchr(featurestr, '='); 6140 if (eq) { 6141 *eq++ = 0; 6142 val = eq; 6143 } else { 6144 val = "on"; 6145 } 6146 6147 feat2prop(featurestr); 6148 name = featurestr; 6149 6150 if (g_list_find_custom(plus_features, name, compare_string)) { 6151 warn_report("Ambiguous CPU model string. " 6152 "Don't mix both \"+%s\" and \"%s=%s\"", 6153 name, name, val); 6154 ambiguous = true; 6155 } 6156 if (g_list_find_custom(minus_features, name, compare_string)) { 6157 warn_report("Ambiguous CPU model string. " 6158 "Don't mix both \"-%s\" and \"%s=%s\"", 6159 name, name, val); 6160 ambiguous = true; 6161 } 6162 6163 /* Special case: */ 6164 if (!strcmp(name, "tsc-freq")) { 6165 int ret; 6166 uint64_t tsc_freq; 6167 6168 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 6169 if (ret < 0 || tsc_freq > INT64_MAX) { 6170 error_setg(errp, "bad numerical value %s", val); 6171 return; 6172 } 6173 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 6174 val = num; 6175 name = "tsc-frequency"; 6176 } 6177 6178 prop = g_new0(typeof(*prop), 1); 6179 prop->driver = typename; 6180 prop->property = g_strdup(name); 6181 prop->value = g_strdup(val); 6182 qdev_prop_register_global(prop); 6183 } 6184 6185 if (ambiguous) { 6186 warn_report("Compatibility of ambiguous CPU model " 6187 "strings won't be kept on future QEMU versions"); 6188 } 6189 } 6190 6191 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 6192 6193 /* Build a list with the name of all features on a feature word array */ 6194 static void x86_cpu_list_feature_names(FeatureWordArray features, 6195 strList **list) 6196 { 6197 strList **tail = list; 6198 FeatureWord w; 6199 6200 for (w = 0; w < FEATURE_WORDS; w++) { 6201 uint64_t filtered = features[w]; 6202 int i; 6203 for (i = 0; i < 64; i++) { 6204 if (filtered & (1ULL << i)) { 6205 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 6206 } 6207 } 6208 } 6209 } 6210 6211 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 6212 const char *name, void *opaque, 6213 Error **errp) 6214 { 6215 X86CPU *xc = X86_CPU(obj); 6216 strList *result = NULL; 6217 6218 x86_cpu_list_feature_names(xc->filtered_features, &result); 6219 visit_type_strList(v, "unavailable-features", &result, errp); 6220 } 6221 6222 /* Print all cpuid feature names in featureset 6223 */ 6224 static void listflags(GList *features) 6225 { 6226 size_t len = 0; 6227 GList *tmp; 6228 6229 for (tmp = features; tmp; tmp = tmp->next) { 6230 const char *name = tmp->data; 6231 if ((len + strlen(name) + 1) >= 75) { 6232 qemu_printf("\n"); 6233 len = 0; 6234 } 6235 qemu_printf("%s%s", len == 0 ? " " : " ", name); 6236 len += strlen(name) + 1; 6237 } 6238 qemu_printf("\n"); 6239 } 6240 6241 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 6242 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 6243 { 6244 ObjectClass *class_a = (ObjectClass *)a; 6245 ObjectClass *class_b = (ObjectClass *)b; 6246 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 6247 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 6248 int ret; 6249 6250 if (cc_a->ordering != cc_b->ordering) { 6251 ret = cc_a->ordering - cc_b->ordering; 6252 } else { 6253 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 6254 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 6255 ret = strcmp(name_a, name_b); 6256 } 6257 return ret; 6258 } 6259 6260 static GSList *get_sorted_cpu_model_list(void) 6261 { 6262 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 6263 list = g_slist_sort(list, x86_cpu_list_compare); 6264 return list; 6265 } 6266 6267 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 6268 { 6269 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 6270 char *r = object_property_get_str(obj, "model-id", &error_abort); 6271 object_unref(obj); 6272 return r; 6273 } 6274 6275 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 6276 { 6277 X86CPUVersion version; 6278 6279 if (!cc->model || !cc->model->is_alias) { 6280 return NULL; 6281 } 6282 version = x86_cpu_model_resolve_version(cc->model); 6283 if (version <= 0) { 6284 return NULL; 6285 } 6286 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 6287 } 6288 6289 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 6290 { 6291 ObjectClass *oc = data; 6292 X86CPUClass *cc = X86_CPU_CLASS(oc); 6293 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6294 g_autofree char *desc = g_strdup(cc->model_description); 6295 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6296 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6297 6298 if (!desc && alias_of) { 6299 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6300 desc = g_strdup("(alias configured by machine type)"); 6301 } else { 6302 desc = g_strdup_printf("(alias of %s)", alias_of); 6303 } 6304 } 6305 if (!desc && cc->model && cc->model->note) { 6306 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6307 } 6308 if (!desc) { 6309 desc = g_strdup(model_id); 6310 } 6311 6312 if (cc->model && cc->model->cpudef->deprecation_note) { 6313 g_autofree char *olddesc = desc; 6314 desc = g_strdup_printf("%s (deprecated)", olddesc); 6315 } 6316 6317 qemu_printf(" %-20s %s\n", name, desc); 6318 } 6319 6320 /* list available CPU models and flags */ 6321 void x86_cpu_list(void) 6322 { 6323 int i, j; 6324 GSList *list; 6325 GList *names = NULL; 6326 6327 qemu_printf("Available CPUs:\n"); 6328 list = get_sorted_cpu_model_list(); 6329 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6330 g_slist_free(list); 6331 6332 names = NULL; 6333 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6334 FeatureWordInfo *fw = &feature_word_info[i]; 6335 for (j = 0; j < 64; j++) { 6336 if (fw->feat_names[j]) { 6337 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6338 } 6339 } 6340 } 6341 6342 names = g_list_sort(names, (GCompareFunc)strcmp); 6343 6344 qemu_printf("\nRecognized CPUID flags:\n"); 6345 listflags(names); 6346 qemu_printf("\n"); 6347 g_list_free(names); 6348 } 6349 6350 #ifndef CONFIG_USER_ONLY 6351 6352 /* Check for missing features that may prevent the CPU class from 6353 * running using the current machine and accelerator. 6354 */ 6355 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6356 strList **list) 6357 { 6358 strList **tail = list; 6359 X86CPU *xc; 6360 Error *err = NULL; 6361 6362 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6363 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6364 return; 6365 } 6366 6367 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6368 6369 x86_cpu_expand_features(xc, &err); 6370 if (err) { 6371 /* Errors at x86_cpu_expand_features should never happen, 6372 * but in case it does, just report the model as not 6373 * runnable at all using the "type" property. 6374 */ 6375 QAPI_LIST_APPEND(tail, g_strdup("type")); 6376 error_free(err); 6377 } 6378 6379 x86_cpu_filter_features(xc, false); 6380 6381 x86_cpu_list_feature_names(xc->filtered_features, tail); 6382 6383 object_unref(OBJECT(xc)); 6384 } 6385 6386 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6387 { 6388 ObjectClass *oc = data; 6389 X86CPUClass *cc = X86_CPU_CLASS(oc); 6390 CpuDefinitionInfoList **cpu_list = user_data; 6391 CpuDefinitionInfo *info; 6392 6393 info = g_malloc0(sizeof(*info)); 6394 info->name = x86_cpu_class_get_model_name(cc); 6395 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6396 info->has_unavailable_features = true; 6397 info->q_typename = g_strdup(object_class_get_name(oc)); 6398 info->migration_safe = cc->migration_safe; 6399 info->has_migration_safe = true; 6400 info->q_static = cc->static_model; 6401 if (cc->model && cc->model->cpudef->deprecation_note) { 6402 info->deprecated = true; 6403 } else { 6404 info->deprecated = false; 6405 } 6406 /* 6407 * Old machine types won't report aliases, so that alias translation 6408 * doesn't break compatibility with previous QEMU versions. 6409 */ 6410 if (default_cpu_version != CPU_VERSION_LEGACY) { 6411 info->alias_of = x86_cpu_class_get_alias_of(cc); 6412 } 6413 6414 QAPI_LIST_PREPEND(*cpu_list, info); 6415 } 6416 6417 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6418 { 6419 CpuDefinitionInfoList *cpu_list = NULL; 6420 GSList *list = get_sorted_cpu_model_list(); 6421 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6422 g_slist_free(list); 6423 return cpu_list; 6424 } 6425 6426 #endif /* !CONFIG_USER_ONLY */ 6427 6428 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6429 { 6430 FeatureWordInfo *wi = &feature_word_info[w]; 6431 uint64_t r = 0; 6432 uint64_t unavail = 0; 6433 6434 if (kvm_enabled()) { 6435 switch (wi->type) { 6436 case CPUID_FEATURE_WORD: 6437 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6438 wi->cpuid.ecx, 6439 wi->cpuid.reg); 6440 break; 6441 case MSR_FEATURE_WORD: 6442 r = kvm_arch_get_supported_msr_feature(kvm_state, 6443 wi->msr.index); 6444 break; 6445 } 6446 } else if (hvf_enabled()) { 6447 if (wi->type != CPUID_FEATURE_WORD) { 6448 return 0; 6449 } 6450 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6451 wi->cpuid.ecx, 6452 wi->cpuid.reg); 6453 } else if (tcg_enabled()) { 6454 r = wi->tcg_features; 6455 } else { 6456 return ~0; 6457 } 6458 6459 switch (w) { 6460 #ifndef TARGET_X86_64 6461 case FEAT_8000_0001_EDX: 6462 /* 6463 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6464 * way for userspace to get out of its 32-bit jail, we can leave 6465 * the LM bit set. 6466 */ 6467 unavail = tcg_enabled() 6468 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6469 : CPUID_EXT2_LM; 6470 break; 6471 #endif 6472 6473 case FEAT_8000_0007_EBX: 6474 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6475 /* Disable AMD machine check architecture for Intel CPU. */ 6476 unavail = ~0; 6477 } 6478 break; 6479 6480 case FEAT_7_0_EBX: 6481 #ifndef CONFIG_USER_ONLY 6482 if (!check_sgx_support()) { 6483 unavail = CPUID_7_0_EBX_SGX; 6484 } 6485 #endif 6486 break; 6487 case FEAT_7_0_ECX: 6488 #ifndef CONFIG_USER_ONLY 6489 if (!check_sgx_support()) { 6490 unavail = CPUID_7_0_ECX_SGX_LC; 6491 } 6492 #endif 6493 break; 6494 6495 default: 6496 break; 6497 } 6498 6499 r &= ~unavail; 6500 if (cpu && cpu->migratable) { 6501 r &= x86_cpu_get_migratable_flags(cpu, w); 6502 } 6503 return r; 6504 } 6505 6506 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6507 uint32_t *eax, uint32_t *ebx, 6508 uint32_t *ecx, uint32_t *edx) 6509 { 6510 if (kvm_enabled()) { 6511 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6512 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6513 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6514 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6515 } else if (hvf_enabled()) { 6516 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6517 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6518 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6519 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6520 } else { 6521 *eax = 0; 6522 *ebx = 0; 6523 *ecx = 0; 6524 *edx = 0; 6525 } 6526 } 6527 6528 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6529 uint32_t *eax, uint32_t *ebx, 6530 uint32_t *ecx, uint32_t *edx) 6531 { 6532 uint32_t level, unused; 6533 6534 /* Only return valid host leaves. */ 6535 switch (func) { 6536 case 2: 6537 case 4: 6538 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6539 break; 6540 case 0x80000005: 6541 case 0x80000006: 6542 case 0x8000001d: 6543 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6544 break; 6545 default: 6546 return; 6547 } 6548 6549 if (func > level) { 6550 *eax = 0; 6551 *ebx = 0; 6552 *ecx = 0; 6553 *edx = 0; 6554 } else { 6555 host_cpuid(func, index, eax, ebx, ecx, edx); 6556 } 6557 } 6558 6559 /* 6560 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6561 */ 6562 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6563 { 6564 PropValue *pv; 6565 for (pv = props; pv->prop; pv++) { 6566 if (!pv->value) { 6567 continue; 6568 } 6569 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6570 &error_abort); 6571 } 6572 } 6573 6574 /* 6575 * Apply properties for the CPU model version specified in model. 6576 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6577 */ 6578 6579 static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) 6580 { 6581 const X86CPUVersionDefinition *vdef; 6582 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6583 6584 if (version == CPU_VERSION_LEGACY) { 6585 return; 6586 } 6587 6588 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6589 PropValue *p; 6590 6591 for (p = vdef->props; p && p->prop; p++) { 6592 object_property_parse(OBJECT(cpu), p->prop, p->value, 6593 &error_abort); 6594 } 6595 6596 if (vdef->version == version) { 6597 break; 6598 } 6599 } 6600 6601 /* 6602 * If we reached the end of the list, version number was invalid 6603 */ 6604 assert(vdef->version == version); 6605 } 6606 6607 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6608 const X86CPUModel *model) 6609 { 6610 const X86CPUVersionDefinition *vdef; 6611 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6612 const CPUCaches *cache_info = model->cpudef->cache_info; 6613 6614 if (version == CPU_VERSION_LEGACY) { 6615 return cache_info; 6616 } 6617 6618 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6619 if (vdef->cache_info) { 6620 cache_info = vdef->cache_info; 6621 } 6622 6623 if (vdef->version == version) { 6624 break; 6625 } 6626 } 6627 6628 assert(vdef->version == version); 6629 return cache_info; 6630 } 6631 6632 /* 6633 * Load data from X86CPUDefinition into a X86CPU object. 6634 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6635 */ 6636 static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) 6637 { 6638 const X86CPUDefinition *def = model->cpudef; 6639 CPUX86State *env = &cpu->env; 6640 FeatureWord w; 6641 6642 /*NOTE: any property set by this function should be returned by 6643 * x86_cpu_static_props(), so static expansion of 6644 * query-cpu-model-expansion is always complete. 6645 */ 6646 6647 /* CPU models only set _minimum_ values for level/xlevel: */ 6648 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6649 &error_abort); 6650 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6651 &error_abort); 6652 6653 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6654 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6655 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6656 &error_abort); 6657 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6658 &error_abort); 6659 for (w = 0; w < FEATURE_WORDS; w++) { 6660 env->features[w] = def->features[w]; 6661 } 6662 6663 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6664 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6665 6666 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6667 6668 /* sysenter isn't supported in compatibility mode on AMD, 6669 * syscall isn't supported in compatibility mode on Intel. 6670 * Normally we advertise the actual CPU vendor, but you can 6671 * override this using the 'vendor' property if you want to use 6672 * KVM's sysenter/syscall emulation in compatibility mode and 6673 * when doing cross vendor migration 6674 */ 6675 6676 /* 6677 * vendor property is set here but then overloaded with the 6678 * host cpu vendor for KVM and HVF. 6679 */ 6680 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6681 6682 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 6683 &error_abort); 6684 6685 x86_cpu_apply_version_props(cpu, model); 6686 6687 /* 6688 * Properties in versioned CPU model are not user specified features. 6689 * We can simply clear env->user_features here since it will be filled later 6690 * in x86_cpu_expand_features() based on plus_features and minus_features. 6691 */ 6692 memset(&env->user_features, 0, sizeof(env->user_features)); 6693 } 6694 6695 static const gchar *x86_gdb_arch_name(CPUState *cs) 6696 { 6697 #ifdef TARGET_X86_64 6698 return "i386:x86-64"; 6699 #else 6700 return "i386"; 6701 #endif 6702 } 6703 6704 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6705 { 6706 const X86CPUModel *model = data; 6707 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6708 CPUClass *cc = CPU_CLASS(oc); 6709 6710 xcc->model = model; 6711 xcc->migration_safe = true; 6712 cc->deprecation_note = model->cpudef->deprecation_note; 6713 } 6714 6715 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6716 { 6717 g_autofree char *typename = x86_cpu_type_name(name); 6718 TypeInfo ti = { 6719 .name = typename, 6720 .parent = TYPE_X86_CPU, 6721 .class_init = x86_cpu_cpudef_class_init, 6722 .class_data = model, 6723 }; 6724 6725 type_register_static(&ti); 6726 } 6727 6728 6729 /* 6730 * register builtin_x86_defs; 6731 * "max", "base" and subclasses ("host") are not registered here. 6732 * See x86_cpu_register_types for all model registrations. 6733 */ 6734 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6735 { 6736 X86CPUModel *m; 6737 const X86CPUVersionDefinition *vdef; 6738 6739 /* AMD aliases are handled at runtime based on CPUID vendor, so 6740 * they shouldn't be set on the CPU model table. 6741 */ 6742 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6743 /* catch mistakes instead of silently truncating model_id when too long */ 6744 assert(def->model_id && strlen(def->model_id) <= 48); 6745 6746 /* Unversioned model: */ 6747 m = g_new0(X86CPUModel, 1); 6748 m->cpudef = def; 6749 m->version = CPU_VERSION_AUTO; 6750 m->is_alias = true; 6751 x86_register_cpu_model_type(def->name, m); 6752 6753 /* Versioned models: */ 6754 6755 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6756 g_autofree char *name = 6757 x86_cpu_versioned_model_name(def, vdef->version); 6758 6759 m = g_new0(X86CPUModel, 1); 6760 m->cpudef = def; 6761 m->version = vdef->version; 6762 m->note = vdef->note; 6763 x86_register_cpu_model_type(name, m); 6764 6765 if (vdef->alias) { 6766 X86CPUModel *am = g_new0(X86CPUModel, 1); 6767 am->cpudef = def; 6768 am->version = vdef->version; 6769 am->is_alias = true; 6770 x86_register_cpu_model_type(vdef->alias, am); 6771 } 6772 } 6773 6774 } 6775 6776 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6777 { 6778 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6779 return 57; /* 57 bits virtual */ 6780 } else { 6781 return 48; /* 48 bits virtual */ 6782 } 6783 } 6784 6785 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6786 uint32_t *eax, uint32_t *ebx, 6787 uint32_t *ecx, uint32_t *edx) 6788 { 6789 X86CPU *cpu = env_archcpu(env); 6790 CPUState *cs = env_cpu(env); 6791 uint32_t limit; 6792 uint32_t signature[3]; 6793 X86CPUTopoInfo *topo_info = &env->topo_info; 6794 uint32_t threads_per_pkg; 6795 6796 threads_per_pkg = x86_threads_per_pkg(topo_info); 6797 6798 /* Calculate & apply limits for different index ranges */ 6799 if (index >= 0xC0000000) { 6800 limit = env->cpuid_xlevel2; 6801 } else if (index >= 0x80000000) { 6802 limit = env->cpuid_xlevel; 6803 } else if (index >= 0x40000000) { 6804 limit = 0x40000001; 6805 } else { 6806 limit = env->cpuid_level; 6807 } 6808 6809 if (index > limit) { 6810 /* Intel documentation states that invalid EAX input will 6811 * return the same information as EAX=cpuid_level 6812 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6813 */ 6814 index = env->cpuid_level; 6815 } 6816 6817 switch(index) { 6818 case 0: 6819 *eax = env->cpuid_level; 6820 *ebx = env->cpuid_vendor1; 6821 *edx = env->cpuid_vendor2; 6822 *ecx = env->cpuid_vendor3; 6823 break; 6824 case 1: 6825 *eax = env->cpuid_version; 6826 *ebx = (cpu->apic_id << 24) | 6827 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6828 *ecx = env->features[FEAT_1_ECX]; 6829 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6830 *ecx |= CPUID_EXT_OSXSAVE; 6831 } 6832 *edx = env->features[FEAT_1_EDX]; 6833 if (threads_per_pkg > 1) { 6834 *ebx |= threads_per_pkg << 16; 6835 } 6836 if (!cpu->enable_pmu) { 6837 *ecx &= ~CPUID_EXT_PDCM; 6838 } 6839 break; 6840 case 2: 6841 /* cache info: needed for Pentium Pro compatibility */ 6842 if (cpu->cache_info_passthrough) { 6843 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6844 break; 6845 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6846 *eax = *ebx = *ecx = *edx = 0; 6847 break; 6848 } 6849 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6850 *ebx = 0; 6851 if (!cpu->enable_l3_cache) { 6852 *ecx = 0; 6853 } else { 6854 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6855 } 6856 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6857 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6858 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6859 break; 6860 case 4: 6861 /* cache info: needed for Core compatibility */ 6862 if (cpu->cache_info_passthrough) { 6863 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6864 /* 6865 * QEMU has its own number of cores/logical cpus, 6866 * set 24..14, 31..26 bit to configured values 6867 */ 6868 if (*eax & 31) { 6869 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6870 6871 *eax &= ~0xFC000000; 6872 *eax |= max_core_ids_in_package(topo_info) << 26; 6873 if (host_vcpus_per_cache > threads_per_pkg) { 6874 *eax &= ~0x3FFC000; 6875 6876 /* Share the cache at package level. */ 6877 *eax |= max_thread_ids_for_cache(topo_info, 6878 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 6879 } 6880 } 6881 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6882 *eax = *ebx = *ecx = *edx = 0; 6883 } else { 6884 *eax = 0; 6885 6886 switch (count) { 6887 case 0: /* L1 dcache info */ 6888 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6889 topo_info, 6890 eax, ebx, ecx, edx); 6891 if (!cpu->l1_cache_per_core) { 6892 *eax &= ~MAKE_64BIT_MASK(14, 12); 6893 } 6894 break; 6895 case 1: /* L1 icache info */ 6896 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6897 topo_info, 6898 eax, ebx, ecx, edx); 6899 if (!cpu->l1_cache_per_core) { 6900 *eax &= ~MAKE_64BIT_MASK(14, 12); 6901 } 6902 break; 6903 case 2: /* L2 cache info */ 6904 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6905 topo_info, 6906 eax, ebx, ecx, edx); 6907 break; 6908 case 3: /* L3 cache info */ 6909 if (cpu->enable_l3_cache) { 6910 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6911 topo_info, 6912 eax, ebx, ecx, edx); 6913 break; 6914 } 6915 /* fall through */ 6916 default: /* end of info */ 6917 *eax = *ebx = *ecx = *edx = 0; 6918 break; 6919 } 6920 } 6921 break; 6922 case 5: 6923 /* MONITOR/MWAIT Leaf */ 6924 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6925 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6926 *ecx = cpu->mwait.ecx; /* flags */ 6927 *edx = cpu->mwait.edx; /* mwait substates */ 6928 break; 6929 case 6: 6930 /* Thermal and Power Leaf */ 6931 *eax = env->features[FEAT_6_EAX]; 6932 *ebx = 0; 6933 *ecx = 0; 6934 *edx = 0; 6935 break; 6936 case 7: 6937 /* Structured Extended Feature Flags Enumeration Leaf */ 6938 if (count == 0) { 6939 /* Maximum ECX value for sub-leaves */ 6940 *eax = env->cpuid_level_func7; 6941 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6942 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6943 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6944 *ecx |= CPUID_7_0_ECX_OSPKE; 6945 } 6946 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6947 } else if (count == 1) { 6948 *eax = env->features[FEAT_7_1_EAX]; 6949 *edx = env->features[FEAT_7_1_EDX]; 6950 *ebx = 0; 6951 *ecx = 0; 6952 } else if (count == 2) { 6953 *edx = env->features[FEAT_7_2_EDX]; 6954 *eax = 0; 6955 *ebx = 0; 6956 *ecx = 0; 6957 } else { 6958 *eax = 0; 6959 *ebx = 0; 6960 *ecx = 0; 6961 *edx = 0; 6962 } 6963 break; 6964 case 9: 6965 /* Direct Cache Access Information Leaf */ 6966 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6967 *ebx = 0; 6968 *ecx = 0; 6969 *edx = 0; 6970 break; 6971 case 0xA: 6972 /* Architectural Performance Monitoring Leaf */ 6973 if (cpu->enable_pmu) { 6974 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6975 } else { 6976 *eax = 0; 6977 *ebx = 0; 6978 *ecx = 0; 6979 *edx = 0; 6980 } 6981 break; 6982 case 0xB: 6983 /* Extended Topology Enumeration Leaf */ 6984 if (!cpu->enable_cpuid_0xb) { 6985 *eax = *ebx = *ecx = *edx = 0; 6986 break; 6987 } 6988 6989 *ecx = count & 0xff; 6990 *edx = cpu->apic_id; 6991 6992 switch (count) { 6993 case 0: 6994 *eax = apicid_core_offset(topo_info); 6995 *ebx = topo_info->threads_per_core; 6996 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6997 break; 6998 case 1: 6999 *eax = apicid_pkg_offset(topo_info); 7000 *ebx = threads_per_pkg; 7001 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 7002 break; 7003 default: 7004 *eax = 0; 7005 *ebx = 0; 7006 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 7007 } 7008 7009 assert(!(*eax & ~0x1f)); 7010 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 7011 break; 7012 case 0x1C: 7013 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7014 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 7015 *edx = 0; 7016 } 7017 break; 7018 case 0x1F: 7019 /* V2 Extended Topology Enumeration Leaf */ 7020 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 7021 *eax = *ebx = *ecx = *edx = 0; 7022 break; 7023 } 7024 7025 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 7026 break; 7027 case 0xD: { 7028 /* Processor Extended State */ 7029 *eax = 0; 7030 *ebx = 0; 7031 *ecx = 0; 7032 *edx = 0; 7033 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7034 break; 7035 } 7036 7037 if (count == 0) { 7038 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 7039 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 7040 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 7041 /* 7042 * The initial value of xcr0 and ebx == 0, On host without kvm 7043 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 7044 * even through guest update xcr0, this will crash some legacy guest 7045 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 7046 */ 7047 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 7048 } else if (count == 1) { 7049 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 7050 x86_cpu_xsave_xss_components(cpu); 7051 7052 *eax = env->features[FEAT_XSAVE]; 7053 *ebx = xsave_area_size(xstate, true); 7054 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 7055 *edx = env->features[FEAT_XSAVE_XSS_HI]; 7056 if (kvm_enabled() && cpu->enable_pmu && 7057 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 7058 (*eax & CPUID_XSAVE_XSAVES)) { 7059 *ecx |= XSTATE_ARCH_LBR_MASK; 7060 } else { 7061 *ecx &= ~XSTATE_ARCH_LBR_MASK; 7062 } 7063 } else if (count == 0xf && cpu->enable_pmu 7064 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7065 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 7066 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 7067 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 7068 7069 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 7070 *eax = esa->size; 7071 *ebx = esa->offset; 7072 *ecx = esa->ecx & 7073 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 7074 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 7075 *eax = esa->size; 7076 *ebx = 0; 7077 *ecx = 1; 7078 } 7079 } 7080 break; 7081 } 7082 case 0x12: 7083 #ifndef CONFIG_USER_ONLY 7084 if (!kvm_enabled() || 7085 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 7086 *eax = *ebx = *ecx = *edx = 0; 7087 break; 7088 } 7089 7090 /* 7091 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 7092 * the EPC properties, e.g. confidentiality and integrity, from the 7093 * host's first EPC section, i.e. assume there is one EPC section or 7094 * that all EPC sections have the same security properties. 7095 */ 7096 if (count > 1) { 7097 uint64_t epc_addr, epc_size; 7098 7099 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 7100 *eax = *ebx = *ecx = *edx = 0; 7101 break; 7102 } 7103 host_cpuid(index, 2, eax, ebx, ecx, edx); 7104 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 7105 *ebx = (uint32_t)(epc_addr >> 32); 7106 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 7107 *edx = (uint32_t)(epc_size >> 32); 7108 break; 7109 } 7110 7111 /* 7112 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 7113 * and KVM, i.e. QEMU cannot emulate features to override what KVM 7114 * supports. Features can be further restricted by userspace, but not 7115 * made more permissive. 7116 */ 7117 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 7118 7119 if (count == 0) { 7120 *eax &= env->features[FEAT_SGX_12_0_EAX]; 7121 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 7122 } else { 7123 *eax &= env->features[FEAT_SGX_12_1_EAX]; 7124 *ebx &= 0; /* ebx reserve */ 7125 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 7126 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 7127 7128 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 7129 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 7130 7131 /* Access to PROVISIONKEY requires additional credentials. */ 7132 if ((*eax & (1U << 4)) && 7133 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 7134 *eax &= ~(1U << 4); 7135 } 7136 } 7137 #endif 7138 break; 7139 case 0x14: { 7140 /* Intel Processor Trace Enumeration */ 7141 *eax = 0; 7142 *ebx = 0; 7143 *ecx = 0; 7144 *edx = 0; 7145 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 7146 !kvm_enabled()) { 7147 break; 7148 } 7149 7150 /* 7151 * If these are changed, they should stay in sync with 7152 * x86_cpu_filter_features(). 7153 */ 7154 if (count == 0) { 7155 *eax = INTEL_PT_MAX_SUBLEAF; 7156 *ebx = INTEL_PT_MINIMAL_EBX; 7157 *ecx = INTEL_PT_MINIMAL_ECX; 7158 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 7159 *ecx |= CPUID_14_0_ECX_LIP; 7160 } 7161 } else if (count == 1) { 7162 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 7163 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 7164 } 7165 break; 7166 } 7167 case 0x1D: { 7168 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 7169 *eax = 0; 7170 *ebx = 0; 7171 *ecx = 0; 7172 *edx = 0; 7173 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7174 break; 7175 } 7176 7177 if (count == 0) { 7178 /* Highest numbered palette subleaf */ 7179 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 7180 } else if (count == 1) { 7181 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 7182 (INTEL_AMX_BYTES_PER_TILE << 16); 7183 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 7184 *ecx = INTEL_AMX_TILE_MAX_ROWS; 7185 } 7186 break; 7187 } 7188 case 0x1E: { 7189 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 7190 *eax = 0; 7191 *ebx = 0; 7192 *ecx = 0; 7193 *edx = 0; 7194 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7195 break; 7196 } 7197 7198 if (count == 0) { 7199 /* Highest numbered palette subleaf */ 7200 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 7201 } 7202 break; 7203 } 7204 case 0x24: { 7205 *eax = 0; 7206 *ebx = 0; 7207 *ecx = 0; 7208 *edx = 0; 7209 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 7210 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 7211 } 7212 break; 7213 } 7214 case 0x40000000: 7215 /* 7216 * CPUID code in kvm_arch_init_vcpu() ignores stuff 7217 * set here, but we restrict to TCG none the less. 7218 */ 7219 if (tcg_enabled() && cpu->expose_tcg) { 7220 memcpy(signature, "TCGTCGTCGTCG", 12); 7221 *eax = 0x40000001; 7222 *ebx = signature[0]; 7223 *ecx = signature[1]; 7224 *edx = signature[2]; 7225 } else { 7226 *eax = 0; 7227 *ebx = 0; 7228 *ecx = 0; 7229 *edx = 0; 7230 } 7231 break; 7232 case 0x40000001: 7233 *eax = 0; 7234 *ebx = 0; 7235 *ecx = 0; 7236 *edx = 0; 7237 break; 7238 case 0x80000000: 7239 *eax = env->cpuid_xlevel; 7240 *ebx = env->cpuid_vendor1; 7241 *edx = env->cpuid_vendor2; 7242 *ecx = env->cpuid_vendor3; 7243 break; 7244 case 0x80000001: 7245 *eax = env->cpuid_version; 7246 *ebx = 0; 7247 *ecx = env->features[FEAT_8000_0001_ECX]; 7248 *edx = env->features[FEAT_8000_0001_EDX]; 7249 7250 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 7251 !(env->hflags & HF_LMA_MASK)) { 7252 *edx &= ~CPUID_EXT2_SYSCALL; 7253 } 7254 break; 7255 case 0x80000002: 7256 case 0x80000003: 7257 case 0x80000004: 7258 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 7259 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 7260 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 7261 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 7262 break; 7263 case 0x80000005: 7264 /* cache info (L1 cache) */ 7265 if (cpu->cache_info_passthrough) { 7266 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7267 break; 7268 } 7269 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 7270 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 7271 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 7272 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7273 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7274 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7275 break; 7276 case 0x80000006: 7277 /* cache info (L2 cache) */ 7278 if (cpu->cache_info_passthrough) { 7279 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7280 break; 7281 } 7282 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7283 (L2_DTLB_2M_ENTRIES << 16) | 7284 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7285 (L2_ITLB_2M_ENTRIES); 7286 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7287 (L2_DTLB_4K_ENTRIES << 16) | 7288 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7289 (L2_ITLB_4K_ENTRIES); 7290 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7291 cpu->enable_l3_cache ? 7292 env->cache_info_amd.l3_cache : NULL, 7293 ecx, edx); 7294 break; 7295 case 0x80000007: 7296 *eax = 0; 7297 *ebx = env->features[FEAT_8000_0007_EBX]; 7298 *ecx = 0; 7299 *edx = env->features[FEAT_8000_0007_EDX]; 7300 break; 7301 case 0x80000008: 7302 /* virtual & phys address size in low 2 bytes. */ 7303 *eax = cpu->phys_bits; 7304 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7305 /* 64 bit processor */ 7306 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7307 *eax |= (cpu->guest_phys_bits << 16); 7308 } 7309 *ebx = env->features[FEAT_8000_0008_EBX]; 7310 if (threads_per_pkg > 1) { 7311 /* 7312 * Bits 15:12 is "The number of bits in the initial 7313 * Core::X86::Apic::ApicId[ApicId] value that indicate 7314 * thread ID within a package". 7315 * Bits 7:0 is "The number of threads in the package is NC+1" 7316 */ 7317 *ecx = (apicid_pkg_offset(topo_info) << 12) | 7318 (threads_per_pkg - 1); 7319 } else { 7320 *ecx = 0; 7321 } 7322 *edx = 0; 7323 break; 7324 case 0x8000000A: 7325 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7326 *eax = 0x00000001; /* SVM Revision */ 7327 *ebx = 0x00000010; /* nr of ASIDs */ 7328 *ecx = 0; 7329 *edx = env->features[FEAT_SVM]; /* optional features */ 7330 } else { 7331 *eax = 0; 7332 *ebx = 0; 7333 *ecx = 0; 7334 *edx = 0; 7335 } 7336 break; 7337 case 0x8000001D: 7338 *eax = 0; 7339 if (cpu->cache_info_passthrough) { 7340 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7341 break; 7342 } 7343 switch (count) { 7344 case 0: /* L1 dcache info */ 7345 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7346 topo_info, eax, ebx, ecx, edx); 7347 break; 7348 case 1: /* L1 icache info */ 7349 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7350 topo_info, eax, ebx, ecx, edx); 7351 break; 7352 case 2: /* L2 cache info */ 7353 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7354 topo_info, eax, ebx, ecx, edx); 7355 break; 7356 case 3: /* L3 cache info */ 7357 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7358 topo_info, eax, ebx, ecx, edx); 7359 break; 7360 default: /* end of info */ 7361 *eax = *ebx = *ecx = *edx = 0; 7362 break; 7363 } 7364 if (cpu->amd_topoext_features_only) { 7365 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7366 } 7367 break; 7368 case 0x8000001E: 7369 if (cpu->core_id <= 255) { 7370 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 7371 } else { 7372 *eax = 0; 7373 *ebx = 0; 7374 *ecx = 0; 7375 *edx = 0; 7376 } 7377 break; 7378 case 0x80000022: 7379 *eax = *ebx = *ecx = *edx = 0; 7380 /* AMD Extended Performance Monitoring and Debug */ 7381 if (kvm_enabled() && cpu->enable_pmu && 7382 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7383 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7384 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7385 R_EBX) & 0xf; 7386 } 7387 break; 7388 case 0xC0000000: 7389 *eax = env->cpuid_xlevel2; 7390 *ebx = 0; 7391 *ecx = 0; 7392 *edx = 0; 7393 break; 7394 case 0xC0000001: 7395 /* Support for VIA CPU's CPUID instruction */ 7396 *eax = env->cpuid_version; 7397 *ebx = 0; 7398 *ecx = 0; 7399 *edx = env->features[FEAT_C000_0001_EDX]; 7400 break; 7401 case 0xC0000002: 7402 case 0xC0000003: 7403 case 0xC0000004: 7404 /* Reserved for the future, and now filled with zero */ 7405 *eax = 0; 7406 *ebx = 0; 7407 *ecx = 0; 7408 *edx = 0; 7409 break; 7410 case 0x8000001F: 7411 *eax = *ebx = *ecx = *edx = 0; 7412 if (sev_enabled()) { 7413 *eax = 0x2; 7414 *eax |= sev_es_enabled() ? 0x8 : 0; 7415 *eax |= sev_snp_enabled() ? 0x10 : 0; 7416 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7417 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7418 } 7419 break; 7420 case 0x80000021: 7421 *eax = *ebx = *ecx = *edx = 0; 7422 *eax = env->features[FEAT_8000_0021_EAX]; 7423 *ebx = env->features[FEAT_8000_0021_EBX]; 7424 break; 7425 default: 7426 /* reserved values: zero */ 7427 *eax = 0; 7428 *ebx = 0; 7429 *ecx = 0; 7430 *edx = 0; 7431 break; 7432 } 7433 } 7434 7435 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7436 { 7437 #ifndef CONFIG_USER_ONLY 7438 /* Those default values are defined in Skylake HW */ 7439 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7440 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7441 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7442 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7443 #endif 7444 } 7445 7446 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7447 { 7448 if (!esa->size) { 7449 return false; 7450 } 7451 7452 if (env->features[esa->feature] & esa->bits) { 7453 return true; 7454 } 7455 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7456 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7457 return true; 7458 } 7459 7460 return false; 7461 } 7462 7463 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7464 { 7465 CPUState *cs = CPU(obj); 7466 X86CPU *cpu = X86_CPU(cs); 7467 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7468 CPUX86State *env = &cpu->env; 7469 target_ulong cr4; 7470 uint64_t xcr0; 7471 int i; 7472 7473 if (xcc->parent_phases.hold) { 7474 xcc->parent_phases.hold(obj, type); 7475 } 7476 7477 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7478 7479 if (tcg_enabled()) { 7480 cpu_init_fp_statuses(env); 7481 } 7482 7483 env->old_exception = -1; 7484 7485 /* init to reset state */ 7486 env->int_ctl = 0; 7487 env->hflags2 |= HF2_GIF_MASK; 7488 env->hflags2 |= HF2_VGIF_MASK; 7489 env->hflags &= ~HF_GUEST_MASK; 7490 7491 cpu_x86_update_cr0(env, 0x60000010); 7492 env->a20_mask = ~0x0; 7493 env->smbase = 0x30000; 7494 env->msr_smi_count = 0; 7495 7496 env->idt.limit = 0xffff; 7497 env->gdt.limit = 0xffff; 7498 env->ldt.limit = 0xffff; 7499 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7500 env->tr.limit = 0xffff; 7501 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7502 7503 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7504 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7505 DESC_R_MASK | DESC_A_MASK); 7506 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7507 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7508 DESC_A_MASK); 7509 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7510 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7511 DESC_A_MASK); 7512 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7513 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7514 DESC_A_MASK); 7515 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7516 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7517 DESC_A_MASK); 7518 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7519 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7520 DESC_A_MASK); 7521 7522 env->eip = 0xfff0; 7523 env->regs[R_EDX] = env->cpuid_version; 7524 7525 env->eflags = 0x2; 7526 7527 /* FPU init */ 7528 for (i = 0; i < 8; i++) { 7529 env->fptags[i] = 1; 7530 } 7531 cpu_set_fpuc(env, 0x37f); 7532 7533 env->mxcsr = 0x1f80; 7534 /* All units are in INIT state. */ 7535 env->xstate_bv = 0; 7536 7537 env->pat = 0x0007040600070406ULL; 7538 7539 if (kvm_enabled()) { 7540 /* 7541 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7542 * a new CPU, use 1 instead to force a reset. 7543 */ 7544 if (env->tsc != 0) { 7545 env->tsc = 1; 7546 } 7547 } else { 7548 env->tsc = 0; 7549 } 7550 7551 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7552 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7553 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7554 } 7555 7556 memset(env->dr, 0, sizeof(env->dr)); 7557 env->dr[6] = DR6_FIXED_1; 7558 env->dr[7] = DR7_FIXED_1; 7559 cpu_breakpoint_remove_all(cs, BP_CPU); 7560 cpu_watchpoint_remove_all(cs, BP_CPU); 7561 7562 cr4 = 0; 7563 xcr0 = XSTATE_FP_MASK; 7564 7565 #ifdef CONFIG_USER_ONLY 7566 /* Enable all the features for user-mode. */ 7567 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7568 xcr0 |= XSTATE_SSE_MASK; 7569 } 7570 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7571 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7572 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7573 continue; 7574 } 7575 if (cpuid_has_xsave_feature(env, esa)) { 7576 xcr0 |= 1ull << i; 7577 } 7578 } 7579 7580 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7581 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7582 } 7583 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7584 cr4 |= CR4_FSGSBASE_MASK; 7585 } 7586 #endif 7587 7588 env->xcr0 = xcr0; 7589 cpu_x86_update_cr4(env, cr4); 7590 7591 /* 7592 * SDM 11.11.5 requires: 7593 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7594 * - IA32_MTRR_PHYSMASKn.V = 0 7595 * All other bits are undefined. For simplification, zero it all. 7596 */ 7597 env->mtrr_deftype = 0; 7598 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7599 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7600 7601 env->interrupt_injected = -1; 7602 env->exception_nr = -1; 7603 env->exception_pending = 0; 7604 env->exception_injected = 0; 7605 env->exception_has_payload = false; 7606 env->exception_payload = 0; 7607 env->nmi_injected = false; 7608 env->triple_fault_pending = false; 7609 #if !defined(CONFIG_USER_ONLY) 7610 /* We hard-wire the BSP to the first CPU. */ 7611 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7612 7613 cs->halted = !cpu_is_bsp(cpu); 7614 7615 if (kvm_enabled()) { 7616 kvm_arch_reset_vcpu(cpu); 7617 } 7618 7619 x86_cpu_set_sgxlepubkeyhash(env); 7620 7621 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7622 7623 #endif 7624 } 7625 7626 void x86_cpu_after_reset(X86CPU *cpu) 7627 { 7628 #ifndef CONFIG_USER_ONLY 7629 if (kvm_enabled()) { 7630 kvm_arch_after_reset_vcpu(cpu); 7631 } 7632 7633 if (cpu->apic_state) { 7634 device_cold_reset(cpu->apic_state); 7635 } 7636 #endif 7637 } 7638 7639 static void mce_init(X86CPU *cpu) 7640 { 7641 CPUX86State *cenv = &cpu->env; 7642 unsigned int bank; 7643 7644 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7645 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7646 (CPUID_MCE | CPUID_MCA)) { 7647 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7648 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7649 cenv->mcg_ctl = ~(uint64_t)0; 7650 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7651 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7652 } 7653 } 7654 } 7655 7656 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7657 { 7658 if (*min < value) { 7659 *min = value; 7660 } 7661 } 7662 7663 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7664 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7665 { 7666 CPUX86State *env = &cpu->env; 7667 FeatureWordInfo *fi = &feature_word_info[w]; 7668 uint32_t eax = fi->cpuid.eax; 7669 uint32_t region = eax & 0xF0000000; 7670 7671 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7672 if (!env->features[w]) { 7673 return; 7674 } 7675 7676 switch (region) { 7677 case 0x00000000: 7678 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7679 break; 7680 case 0x80000000: 7681 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7682 break; 7683 case 0xC0000000: 7684 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7685 break; 7686 } 7687 7688 if (eax == 7) { 7689 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7690 fi->cpuid.ecx); 7691 } 7692 } 7693 7694 /* Calculate XSAVE components based on the configured CPU feature flags */ 7695 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7696 { 7697 CPUX86State *env = &cpu->env; 7698 int i; 7699 uint64_t mask; 7700 static bool request_perm; 7701 7702 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7703 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7704 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7705 env->features[FEAT_XSAVE_XSS_LO] = 0; 7706 env->features[FEAT_XSAVE_XSS_HI] = 0; 7707 return; 7708 } 7709 7710 mask = 0; 7711 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7712 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7713 if (cpuid_has_xsave_feature(env, esa)) { 7714 mask |= (1ULL << i); 7715 } 7716 } 7717 7718 /* Only request permission for first vcpu */ 7719 if (kvm_enabled() && !request_perm) { 7720 kvm_request_xsave_components(cpu, mask); 7721 request_perm = true; 7722 } 7723 7724 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7725 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7726 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7727 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7728 } 7729 7730 /***** Steps involved on loading and filtering CPUID data 7731 * 7732 * When initializing and realizing a CPU object, the steps 7733 * involved in setting up CPUID data are: 7734 * 7735 * 1) Loading CPU model definition (X86CPUDefinition). This is 7736 * implemented by x86_cpu_load_model() and should be completely 7737 * transparent, as it is done automatically by instance_init. 7738 * No code should need to look at X86CPUDefinition structs 7739 * outside instance_init. 7740 * 7741 * 2) CPU expansion. This is done by realize before CPUID 7742 * filtering, and will make sure host/accelerator data is 7743 * loaded for CPU models that depend on host capabilities 7744 * (e.g. "host"). Done by x86_cpu_expand_features(). 7745 * 7746 * 3) CPUID filtering. This initializes extra data related to 7747 * CPUID, and checks if the host supports all capabilities 7748 * required by the CPU. Runnability of a CPU model is 7749 * determined at this step. Done by x86_cpu_filter_features(). 7750 * 7751 * Some operations don't require all steps to be performed. 7752 * More precisely: 7753 * 7754 * - CPU instance creation (instance_init) will run only CPU 7755 * model loading. CPU expansion can't run at instance_init-time 7756 * because host/accelerator data may be not available yet. 7757 * - CPU realization will perform both CPU model expansion and CPUID 7758 * filtering, and return an error in case one of them fails. 7759 * - query-cpu-definitions needs to run all 3 steps. It needs 7760 * to run CPUID filtering, as the 'unavailable-features' 7761 * field is set based on the filtering results. 7762 * - The query-cpu-model-expansion QMP command only needs to run 7763 * CPU model loading and CPU expansion. It should not filter 7764 * any CPUID data based on host capabilities. 7765 */ 7766 7767 /* Expand CPU configuration data, based on configured features 7768 * and host/accelerator capabilities when appropriate. 7769 */ 7770 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7771 { 7772 CPUX86State *env = &cpu->env; 7773 FeatureWord w; 7774 int i; 7775 GList *l; 7776 7777 for (l = plus_features; l; l = l->next) { 7778 const char *prop = l->data; 7779 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7780 return; 7781 } 7782 } 7783 7784 for (l = minus_features; l; l = l->next) { 7785 const char *prop = l->data; 7786 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7787 return; 7788 } 7789 } 7790 7791 /*TODO: Now cpu->max_features doesn't overwrite features 7792 * set using QOM properties, and we can convert 7793 * plus_features & minus_features to global properties 7794 * inside x86_cpu_parse_featurestr() too. 7795 */ 7796 if (cpu->max_features) { 7797 for (w = 0; w < FEATURE_WORDS; w++) { 7798 /* Override only features that weren't set explicitly 7799 * by the user. 7800 */ 7801 env->features[w] |= 7802 x86_cpu_get_supported_feature_word(cpu, w) & 7803 ~env->user_features[w] & 7804 ~feature_word_info[w].no_autoenable_flags; 7805 } 7806 7807 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 7808 uint32_t eax, ebx, ecx, edx; 7809 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 7810 env->avx10_version = ebx & 0xff; 7811 } 7812 } 7813 7814 if (x86_threads_per_pkg(&env->topo_info) > 1) { 7815 env->features[FEAT_1_EDX] |= CPUID_HT; 7816 7817 /* 7818 * The Linux kernel checks for the CMPLegacy bit and 7819 * discards multiple thread information if it is set. 7820 * So don't set it here for Intel (and other processors 7821 * following Intel's behavior) to make Linux guests happy. 7822 */ 7823 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 7824 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 7825 } 7826 } 7827 7828 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7829 FeatureDep *d = &feature_dependencies[i]; 7830 if (!(env->features[d->from.index] & d->from.mask)) { 7831 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7832 7833 /* Not an error unless the dependent feature was added explicitly. */ 7834 mark_unavailable_features(cpu, d->to.index, 7835 unavailable_features & env->user_features[d->to.index], 7836 "This feature depends on other features that were not requested"); 7837 7838 env->features[d->to.index] &= ~unavailable_features; 7839 } 7840 } 7841 7842 if (!kvm_enabled() || !cpu->expose_kvm) { 7843 env->features[FEAT_KVM] = 0; 7844 } 7845 7846 x86_cpu_enable_xsave_components(cpu); 7847 7848 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7849 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7850 if (cpu->full_cpuid_auto_level) { 7851 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7852 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7853 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7854 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7855 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7856 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7857 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7858 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7859 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7860 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7861 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7862 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7863 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7864 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7865 7866 /* Intel Processor Trace requires CPUID[0x14] */ 7867 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7868 if (cpu->intel_pt_auto_level) { 7869 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7870 } else if (cpu->env.cpuid_min_level < 0x14) { 7871 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7872 CPUID_7_0_EBX_INTEL_PT, 7873 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7874 } 7875 } 7876 7877 /* 7878 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7879 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7880 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7881 * cpu->vendor_cpuid_only has been unset for compatibility with older 7882 * machine types. 7883 */ 7884 if (x86_has_extended_topo(env->avail_cpu_topo) && 7885 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7886 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7887 } 7888 7889 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 7890 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7891 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 7892 } 7893 7894 /* SVM requires CPUID[0x8000000A] */ 7895 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7896 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7897 } 7898 7899 /* SEV requires CPUID[0x8000001F] */ 7900 if (sev_enabled()) { 7901 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7902 } 7903 7904 if (env->features[FEAT_8000_0021_EAX]) { 7905 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7906 } 7907 7908 /* SGX requires CPUID[0x12] for EPC enumeration */ 7909 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7910 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7911 } 7912 } 7913 7914 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7915 if (env->cpuid_level_func7 == UINT32_MAX) { 7916 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7917 } 7918 if (env->cpuid_level == UINT32_MAX) { 7919 env->cpuid_level = env->cpuid_min_level; 7920 } 7921 if (env->cpuid_xlevel == UINT32_MAX) { 7922 env->cpuid_xlevel = env->cpuid_min_xlevel; 7923 } 7924 if (env->cpuid_xlevel2 == UINT32_MAX) { 7925 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7926 } 7927 7928 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7929 return; 7930 } 7931 } 7932 7933 /* 7934 * Finishes initialization of CPUID data, filters CPU feature 7935 * words based on host availability of each feature. 7936 * 7937 * Returns: true if any flag is not supported by the host, false otherwise. 7938 */ 7939 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7940 { 7941 CPUX86State *env = &cpu->env; 7942 FeatureWord w; 7943 const char *prefix = NULL; 7944 bool have_filtered_features; 7945 7946 uint32_t eax_0, ebx_0, ecx_0, edx_0; 7947 uint32_t eax_1, ebx_1, ecx_1, edx_1; 7948 7949 if (verbose) { 7950 prefix = accel_uses_host_cpuid() 7951 ? "host doesn't support requested feature" 7952 : "TCG doesn't support requested feature"; 7953 } 7954 7955 for (w = 0; w < FEATURE_WORDS; w++) { 7956 uint64_t host_feat = 7957 x86_cpu_get_supported_feature_word(NULL, w); 7958 uint64_t requested_features = env->features[w]; 7959 uint64_t unavailable_features = requested_features & ~host_feat; 7960 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7961 } 7962 7963 /* 7964 * Check that KVM actually allows the processor tracing features that 7965 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7966 */ 7967 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7968 kvm_enabled()) { 7969 x86_cpu_get_supported_cpuid(0x14, 0, 7970 &eax_0, &ebx_0, &ecx_0, &edx_0); 7971 x86_cpu_get_supported_cpuid(0x14, 1, 7972 &eax_1, &ebx_1, &ecx_1, &edx_1); 7973 7974 if (!eax_0 || 7975 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7976 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7977 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7978 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7979 INTEL_PT_ADDR_RANGES_NUM) || 7980 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7981 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7982 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7983 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7984 /* 7985 * Processor Trace capabilities aren't configurable, so if the 7986 * host can't emulate the capabilities we report on 7987 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7988 */ 7989 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7990 } 7991 } 7992 7993 have_filtered_features = x86_cpu_have_filtered_features(cpu); 7994 7995 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7996 x86_cpu_get_supported_cpuid(0x24, 0, 7997 &eax_0, &ebx_0, &ecx_0, &edx_0); 7998 uint8_t version = ebx_0 & 0xff; 7999 8000 if (version < env->avx10_version) { 8001 if (prefix) { 8002 warn_report("%s: avx10.%d. Adjust to avx10.%d", 8003 prefix, env->avx10_version, version); 8004 } 8005 env->avx10_version = version; 8006 have_filtered_features = true; 8007 } 8008 } else if (env->avx10_version) { 8009 if (prefix) { 8010 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 8011 } 8012 have_filtered_features = true; 8013 } 8014 8015 return have_filtered_features; 8016 } 8017 8018 static void x86_cpu_hyperv_realize(X86CPU *cpu) 8019 { 8020 size_t len; 8021 8022 /* Hyper-V vendor id */ 8023 if (!cpu->hyperv_vendor) { 8024 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 8025 &error_abort); 8026 } 8027 len = strlen(cpu->hyperv_vendor); 8028 if (len > 12) { 8029 warn_report("hv-vendor-id truncated to 12 characters"); 8030 len = 12; 8031 } 8032 memset(cpu->hyperv_vendor_id, 0, 12); 8033 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 8034 8035 /* 'Hv#1' interface identification*/ 8036 cpu->hyperv_interface_id[0] = 0x31237648; 8037 cpu->hyperv_interface_id[1] = 0; 8038 cpu->hyperv_interface_id[2] = 0; 8039 cpu->hyperv_interface_id[3] = 0; 8040 8041 /* Hypervisor implementation limits */ 8042 cpu->hyperv_limits[0] = 64; 8043 cpu->hyperv_limits[1] = 0; 8044 cpu->hyperv_limits[2] = 0; 8045 } 8046 8047 #ifndef CONFIG_USER_ONLY 8048 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 8049 Error **errp) 8050 { 8051 CPUX86State *env = &cpu->env; 8052 CpuTopologyLevel level; 8053 8054 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 8055 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8056 env->cache_info_cpuid4.l1d_cache->share_level = level; 8057 env->cache_info_amd.l1d_cache->share_level = level; 8058 } else { 8059 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8060 env->cache_info_cpuid4.l1d_cache->share_level); 8061 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8062 env->cache_info_amd.l1d_cache->share_level); 8063 } 8064 8065 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 8066 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8067 env->cache_info_cpuid4.l1i_cache->share_level = level; 8068 env->cache_info_amd.l1i_cache->share_level = level; 8069 } else { 8070 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8071 env->cache_info_cpuid4.l1i_cache->share_level); 8072 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8073 env->cache_info_amd.l1i_cache->share_level); 8074 } 8075 8076 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 8077 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8078 env->cache_info_cpuid4.l2_cache->share_level = level; 8079 env->cache_info_amd.l2_cache->share_level = level; 8080 } else { 8081 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8082 env->cache_info_cpuid4.l2_cache->share_level); 8083 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8084 env->cache_info_amd.l2_cache->share_level); 8085 } 8086 8087 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 8088 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8089 env->cache_info_cpuid4.l3_cache->share_level = level; 8090 env->cache_info_amd.l3_cache->share_level = level; 8091 } else { 8092 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8093 env->cache_info_cpuid4.l3_cache->share_level); 8094 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8095 env->cache_info_amd.l3_cache->share_level); 8096 } 8097 8098 if (!machine_check_smp_cache(ms, errp)) { 8099 return false; 8100 } 8101 return true; 8102 } 8103 #endif 8104 8105 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 8106 { 8107 CPUState *cs = CPU(dev); 8108 X86CPU *cpu = X86_CPU(dev); 8109 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8110 CPUX86State *env = &cpu->env; 8111 Error *local_err = NULL; 8112 unsigned requested_lbr_fmt; 8113 8114 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 8115 /* Use pc-relative instructions in system-mode */ 8116 tcg_cflags_set(cs, CF_PCREL); 8117 #endif 8118 8119 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 8120 error_setg(errp, "apic-id property was not initialized properly"); 8121 return; 8122 } 8123 8124 /* 8125 * Process Hyper-V enlightenments. 8126 * Note: this currently has to happen before the expansion of CPU features. 8127 */ 8128 x86_cpu_hyperv_realize(cpu); 8129 8130 x86_cpu_expand_features(cpu, &local_err); 8131 if (local_err) { 8132 goto out; 8133 } 8134 8135 /* 8136 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 8137 * with user-provided setting. 8138 */ 8139 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 8140 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 8141 error_setg(errp, "invalid lbr-fmt"); 8142 return; 8143 } 8144 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 8145 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 8146 } 8147 8148 /* 8149 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 8150 * 3)vPMU LBR format matches that of host setting. 8151 */ 8152 requested_lbr_fmt = 8153 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 8154 if (requested_lbr_fmt && kvm_enabled()) { 8155 uint64_t host_perf_cap = 8156 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 8157 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 8158 8159 if (!cpu->enable_pmu) { 8160 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 8161 return; 8162 } 8163 if (requested_lbr_fmt != host_lbr_fmt) { 8164 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 8165 "the host value (0x%x).", 8166 requested_lbr_fmt, host_lbr_fmt); 8167 return; 8168 } 8169 } 8170 8171 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 8172 if (cpu->enforce_cpuid) { 8173 error_setg(&local_err, 8174 accel_uses_host_cpuid() ? 8175 "Host doesn't support requested features" : 8176 "TCG doesn't support requested features"); 8177 goto out; 8178 } 8179 } 8180 8181 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 8182 * CPUID[1].EDX. 8183 */ 8184 if (IS_AMD_CPU(env)) { 8185 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 8186 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 8187 & CPUID_EXT2_AMD_ALIASES); 8188 } 8189 8190 x86_cpu_set_sgxlepubkeyhash(env); 8191 8192 /* 8193 * note: the call to the framework needs to happen after feature expansion, 8194 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 8195 * These may be set by the accel-specific code, 8196 * and the results are subsequently checked / assumed in this function. 8197 */ 8198 cpu_exec_realizefn(cs, &local_err); 8199 if (local_err != NULL) { 8200 error_propagate(errp, local_err); 8201 return; 8202 } 8203 8204 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 8205 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8206 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 8207 goto out; 8208 } 8209 8210 if (cpu->guest_phys_bits == -1) { 8211 /* 8212 * If it was not set by the user, or by the accelerator via 8213 * cpu_exec_realizefn, clear. 8214 */ 8215 cpu->guest_phys_bits = 0; 8216 } 8217 8218 if (cpu->ucode_rev == 0) { 8219 /* 8220 * The default is the same as KVM's. Note that this check 8221 * needs to happen after the evenual setting of ucode_rev in 8222 * accel-specific code in cpu_exec_realizefn. 8223 */ 8224 if (IS_AMD_CPU(env)) { 8225 cpu->ucode_rev = 0x01000065; 8226 } else { 8227 cpu->ucode_rev = 0x100000000ULL; 8228 } 8229 } 8230 8231 /* 8232 * mwait extended info: needed for Core compatibility 8233 * We always wake on interrupt even if host does not have the capability. 8234 * 8235 * requires the accel-specific code in cpu_exec_realizefn to 8236 * have already acquired the CPUID data into cpu->mwait. 8237 */ 8238 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 8239 8240 /* 8241 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 8242 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8243 * based on inputs (sockets,cores,threads), it is still better to give 8244 * users a warning. 8245 */ 8246 if (IS_AMD_CPU(env) && 8247 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8248 env->topo_info.threads_per_core > 1) { 8249 warn_report_once("This family of AMD CPU doesn't support " 8250 "hyperthreading(%d). Please configure -smp " 8251 "options properly or try enabling topoext " 8252 "feature.", env->topo_info.threads_per_core); 8253 } 8254 8255 /* For 64bit systems think about the number of physical bits to present. 8256 * ideally this should be the same as the host; anything other than matching 8257 * the host can cause incorrect guest behaviour. 8258 * QEMU used to pick the magic value of 40 bits that corresponds to 8259 * consumer AMD devices but nothing else. 8260 * 8261 * Note that this code assumes features expansion has already been done 8262 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 8263 * phys_bits adjustments to match the host have been already done in 8264 * accel-specific code in cpu_exec_realizefn. 8265 */ 8266 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8267 if (cpu->phys_bits && 8268 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 8269 cpu->phys_bits < 32)) { 8270 error_setg(errp, "phys-bits should be between 32 and %u " 8271 " (but is %u)", 8272 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 8273 return; 8274 } 8275 /* 8276 * 0 means it was not explicitly set by the user (or by machine 8277 * compat_props or by the host code in host-cpu.c). 8278 * In this case, the default is the value used by TCG (40). 8279 */ 8280 if (cpu->phys_bits == 0) { 8281 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 8282 } 8283 if (cpu->guest_phys_bits && 8284 (cpu->guest_phys_bits > cpu->phys_bits || 8285 cpu->guest_phys_bits < 32)) { 8286 error_setg(errp, "guest-phys-bits should be between 32 and %u " 8287 " (but is %u)", 8288 cpu->phys_bits, cpu->guest_phys_bits); 8289 return; 8290 } 8291 } else { 8292 /* For 32 bit systems don't use the user set value, but keep 8293 * phys_bits consistent with what we tell the guest. 8294 */ 8295 if (cpu->phys_bits != 0) { 8296 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 8297 return; 8298 } 8299 if (cpu->guest_phys_bits != 0) { 8300 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 8301 return; 8302 } 8303 8304 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 8305 cpu->phys_bits = 36; 8306 } else { 8307 cpu->phys_bits = 32; 8308 } 8309 } 8310 8311 /* Cache information initialization */ 8312 if (!cpu->legacy_cache) { 8313 const CPUCaches *cache_info = 8314 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 8315 8316 if (!xcc->model || !cache_info) { 8317 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8318 error_setg(errp, 8319 "CPU model '%s' doesn't support legacy-cache=off", name); 8320 return; 8321 } 8322 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 8323 *cache_info; 8324 } else { 8325 /* Build legacy cache information */ 8326 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 8327 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 8328 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 8329 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 8330 8331 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 8332 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 8333 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 8334 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 8335 8336 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 8337 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 8338 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 8339 env->cache_info_amd.l3_cache = &legacy_l3_cache; 8340 } 8341 8342 #ifndef CONFIG_USER_ONLY 8343 MachineState *ms = MACHINE(qdev_get_machine()); 8344 MachineClass *mc = MACHINE_GET_CLASS(ms); 8345 8346 if (mc->smp_props.has_caches) { 8347 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 8348 return; 8349 } 8350 } 8351 8352 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 8353 8354 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 8355 x86_cpu_apic_create(cpu, &local_err); 8356 if (local_err != NULL) { 8357 goto out; 8358 } 8359 } 8360 #endif 8361 8362 mce_init(cpu); 8363 8364 x86_cpu_gdb_init(cs); 8365 qemu_init_vcpu(cs); 8366 8367 #ifndef CONFIG_USER_ONLY 8368 x86_cpu_apic_realize(cpu, &local_err); 8369 if (local_err != NULL) { 8370 goto out; 8371 } 8372 #endif /* !CONFIG_USER_ONLY */ 8373 cpu_reset(cs); 8374 8375 xcc->parent_realize(dev, &local_err); 8376 8377 out: 8378 if (local_err != NULL) { 8379 error_propagate(errp, local_err); 8380 return; 8381 } 8382 } 8383 8384 static void x86_cpu_unrealizefn(DeviceState *dev) 8385 { 8386 X86CPU *cpu = X86_CPU(dev); 8387 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8388 8389 #ifndef CONFIG_USER_ONLY 8390 cpu_remove_sync(CPU(dev)); 8391 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8392 #endif 8393 8394 if (cpu->apic_state) { 8395 object_unparent(OBJECT(cpu->apic_state)); 8396 cpu->apic_state = NULL; 8397 } 8398 8399 xcc->parent_unrealize(dev); 8400 } 8401 8402 typedef struct BitProperty { 8403 FeatureWord w; 8404 uint64_t mask; 8405 } BitProperty; 8406 8407 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8408 void *opaque, Error **errp) 8409 { 8410 X86CPU *cpu = X86_CPU(obj); 8411 BitProperty *fp = opaque; 8412 uint64_t f = cpu->env.features[fp->w]; 8413 bool value = (f & fp->mask) == fp->mask; 8414 visit_type_bool(v, name, &value, errp); 8415 } 8416 8417 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8418 void *opaque, Error **errp) 8419 { 8420 DeviceState *dev = DEVICE(obj); 8421 X86CPU *cpu = X86_CPU(obj); 8422 BitProperty *fp = opaque; 8423 bool value; 8424 8425 if (dev->realized) { 8426 qdev_prop_set_after_realize(dev, name, errp); 8427 return; 8428 } 8429 8430 if (!visit_type_bool(v, name, &value, errp)) { 8431 return; 8432 } 8433 8434 if (value) { 8435 cpu->env.features[fp->w] |= fp->mask; 8436 } else { 8437 cpu->env.features[fp->w] &= ~fp->mask; 8438 } 8439 cpu->env.user_features[fp->w] |= fp->mask; 8440 } 8441 8442 /* Register a boolean property to get/set a single bit in a uint32_t field. 8443 * 8444 * The same property name can be registered multiple times to make it affect 8445 * multiple bits in the same FeatureWord. In that case, the getter will return 8446 * true only if all bits are set. 8447 */ 8448 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8449 const char *prop_name, 8450 FeatureWord w, 8451 int bitnr) 8452 { 8453 ObjectClass *oc = OBJECT_CLASS(xcc); 8454 BitProperty *fp; 8455 ObjectProperty *op; 8456 uint64_t mask = (1ULL << bitnr); 8457 8458 op = object_class_property_find(oc, prop_name); 8459 if (op) { 8460 fp = op->opaque; 8461 assert(fp->w == w); 8462 fp->mask |= mask; 8463 } else { 8464 fp = g_new0(BitProperty, 1); 8465 fp->w = w; 8466 fp->mask = mask; 8467 object_class_property_add(oc, prop_name, "bool", 8468 x86_cpu_get_bit_prop, 8469 x86_cpu_set_bit_prop, 8470 NULL, fp); 8471 } 8472 } 8473 8474 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8475 FeatureWord w, 8476 int bitnr) 8477 { 8478 FeatureWordInfo *fi = &feature_word_info[w]; 8479 const char *name = fi->feat_names[bitnr]; 8480 8481 if (!name) { 8482 return; 8483 } 8484 8485 /* Property names should use "-" instead of "_". 8486 * Old names containing underscores are registered as aliases 8487 * using object_property_add_alias() 8488 */ 8489 assert(!strchr(name, '_')); 8490 /* aliases don't use "|" delimiters anymore, they are registered 8491 * manually using object_property_add_alias() */ 8492 assert(!strchr(name, '|')); 8493 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8494 } 8495 8496 static void x86_cpu_post_initfn(Object *obj) 8497 { 8498 static bool first = true; 8499 uint64_t supported_xcr0; 8500 int i; 8501 8502 if (first) { 8503 first = false; 8504 8505 supported_xcr0 = 8506 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 8507 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 8508 8509 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 8510 ExtSaveArea *esa = &x86_ext_save_areas[i]; 8511 8512 if (!(supported_xcr0 & (1 << i))) { 8513 esa->size = 0; 8514 } 8515 } 8516 } 8517 8518 accel_cpu_instance_init(CPU(obj)); 8519 } 8520 8521 static void x86_cpu_init_default_topo(X86CPU *cpu) 8522 { 8523 CPUX86State *env = &cpu->env; 8524 8525 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 8526 8527 /* thread, core and socket levels are set by default. */ 8528 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 8529 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 8530 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 8531 } 8532 8533 static void x86_cpu_initfn(Object *obj) 8534 { 8535 X86CPU *cpu = X86_CPU(obj); 8536 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8537 CPUX86State *env = &cpu->env; 8538 8539 x86_cpu_init_default_topo(cpu); 8540 8541 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8542 x86_cpu_get_feature_words, 8543 NULL, NULL, (void *)env->features); 8544 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8545 x86_cpu_get_feature_words, 8546 NULL, NULL, (void *)cpu->filtered_features); 8547 8548 object_property_add_alias(obj, "sse3", obj, "pni"); 8549 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8550 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8551 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8552 object_property_add_alias(obj, "xd", obj, "nx"); 8553 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8554 object_property_add_alias(obj, "i64", obj, "lm"); 8555 8556 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8557 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8558 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8559 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8560 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8561 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8562 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8563 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8564 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8565 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8566 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8567 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8568 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8569 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8570 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8571 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8572 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8573 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8574 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8575 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8576 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8577 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8578 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8579 8580 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8581 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8582 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8583 8584 if (xcc->model) { 8585 x86_cpu_load_model(cpu, xcc->model); 8586 } 8587 } 8588 8589 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8590 { 8591 X86CPU *cpu = X86_CPU(cs); 8592 8593 return cpu->apic_id; 8594 } 8595 8596 #if !defined(CONFIG_USER_ONLY) 8597 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8598 { 8599 X86CPU *cpu = X86_CPU(cs); 8600 8601 return cpu->env.cr[0] & CR0_PG_MASK; 8602 } 8603 #endif /* !CONFIG_USER_ONLY */ 8604 8605 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8606 { 8607 X86CPU *cpu = X86_CPU(cs); 8608 8609 cpu->env.eip = value; 8610 } 8611 8612 static vaddr x86_cpu_get_pc(CPUState *cs) 8613 { 8614 X86CPU *cpu = X86_CPU(cs); 8615 8616 /* Match cpu_get_tb_cpu_state. */ 8617 return cpu->env.eip + cpu->env.segs[R_CS].base; 8618 } 8619 8620 #if !defined(CONFIG_USER_ONLY) 8621 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8622 { 8623 X86CPU *cpu = X86_CPU(cs); 8624 CPUX86State *env = &cpu->env; 8625 8626 if (interrupt_request & CPU_INTERRUPT_POLL) { 8627 return CPU_INTERRUPT_POLL; 8628 } 8629 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8630 return CPU_INTERRUPT_SIPI; 8631 } 8632 8633 if (env->hflags2 & HF2_GIF_MASK) { 8634 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8635 !(env->hflags & HF_SMM_MASK)) { 8636 return CPU_INTERRUPT_SMI; 8637 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8638 !(env->hflags2 & HF2_NMI_MASK)) { 8639 return CPU_INTERRUPT_NMI; 8640 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8641 return CPU_INTERRUPT_MCE; 8642 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8643 (((env->hflags2 & HF2_VINTR_MASK) && 8644 (env->hflags2 & HF2_HIF_MASK)) || 8645 (!(env->hflags2 & HF2_VINTR_MASK) && 8646 (env->eflags & IF_MASK && 8647 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8648 return CPU_INTERRUPT_HARD; 8649 } else if (env->hflags2 & HF2_VGIF_MASK) { 8650 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8651 (env->eflags & IF_MASK) && 8652 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8653 return CPU_INTERRUPT_VIRQ; 8654 } 8655 } 8656 } 8657 8658 return 0; 8659 } 8660 8661 static bool x86_cpu_has_work(CPUState *cs) 8662 { 8663 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8664 } 8665 #endif /* !CONFIG_USER_ONLY */ 8666 8667 int x86_mmu_index_pl(CPUX86State *env, unsigned pl) 8668 { 8669 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8670 int mmu_index_base = 8671 pl == 3 ? MMU_USER64_IDX : 8672 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8673 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8674 8675 return mmu_index_base + mmu_index_32; 8676 } 8677 8678 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8679 { 8680 CPUX86State *env = cpu_env(cs); 8681 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); 8682 } 8683 8684 static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) 8685 { 8686 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; 8687 int mmu_index_base = 8688 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8689 (pl < 3 && (env->eflags & AC_MASK) 8690 ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); 8691 8692 return mmu_index_base + mmu_index_32; 8693 } 8694 8695 int cpu_mmu_index_kernel(CPUX86State *env) 8696 { 8697 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); 8698 } 8699 8700 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8701 { 8702 X86CPU *cpu = X86_CPU(cs); 8703 CPUX86State *env = &cpu->env; 8704 8705 info->endian = BFD_ENDIAN_LITTLE; 8706 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8707 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8708 : bfd_mach_i386_i8086); 8709 8710 info->cap_arch = CS_ARCH_X86; 8711 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8712 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8713 : CS_MODE_16); 8714 info->cap_insn_unit = 1; 8715 info->cap_insn_split = 8; 8716 } 8717 8718 void x86_update_hflags(CPUX86State *env) 8719 { 8720 uint32_t hflags; 8721 #define HFLAG_COPY_MASK \ 8722 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8723 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8724 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8725 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8726 8727 hflags = env->hflags & HFLAG_COPY_MASK; 8728 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8729 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8730 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8731 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8732 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8733 8734 if (env->cr[4] & CR4_OSFXSR_MASK) { 8735 hflags |= HF_OSFXSR_MASK; 8736 } 8737 8738 if (env->efer & MSR_EFER_LMA) { 8739 hflags |= HF_LMA_MASK; 8740 } 8741 8742 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8743 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8744 } else { 8745 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8746 (DESC_B_SHIFT - HF_CS32_SHIFT); 8747 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8748 (DESC_B_SHIFT - HF_SS32_SHIFT); 8749 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8750 !(hflags & HF_CS32_MASK)) { 8751 hflags |= HF_ADDSEG_MASK; 8752 } else { 8753 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8754 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8755 } 8756 } 8757 env->hflags = hflags; 8758 } 8759 8760 static const Property x86_cpu_properties[] = { 8761 #ifdef CONFIG_USER_ONLY 8762 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8763 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8764 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8765 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8766 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8767 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8768 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8769 #else 8770 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8771 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8772 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8773 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8774 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8775 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8776 #endif 8777 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8778 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8779 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8780 8781 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8782 HYPERV_SPINLOCK_NEVER_NOTIFY), 8783 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8784 HYPERV_FEAT_RELAXED, 0), 8785 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8786 HYPERV_FEAT_VAPIC, 0), 8787 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8788 HYPERV_FEAT_TIME, 0), 8789 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8790 HYPERV_FEAT_CRASH, 0), 8791 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8792 HYPERV_FEAT_RESET, 0), 8793 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8794 HYPERV_FEAT_VPINDEX, 0), 8795 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8796 HYPERV_FEAT_RUNTIME, 0), 8797 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8798 HYPERV_FEAT_SYNIC, 0), 8799 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8800 HYPERV_FEAT_STIMER, 0), 8801 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8802 HYPERV_FEAT_FREQUENCIES, 0), 8803 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8804 HYPERV_FEAT_REENLIGHTENMENT, 0), 8805 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8806 HYPERV_FEAT_TLBFLUSH, 0), 8807 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8808 HYPERV_FEAT_EVMCS, 0), 8809 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8810 HYPERV_FEAT_IPI, 0), 8811 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8812 HYPERV_FEAT_STIMER_DIRECT, 0), 8813 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8814 HYPERV_FEAT_AVIC, 0), 8815 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8816 HYPERV_FEAT_MSR_BITMAP, 0), 8817 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8818 HYPERV_FEAT_XMM_INPUT, 0), 8819 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8820 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8821 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8822 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8823 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8824 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8825 #ifdef CONFIG_SYNDBG 8826 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8827 HYPERV_FEAT_SYNDBG, 0), 8828 #endif 8829 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8830 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8831 8832 /* WS2008R2 identify by default */ 8833 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8834 0x3839), 8835 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8836 0x000A), 8837 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8838 0x0000), 8839 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8840 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8841 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8842 8843 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8844 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8845 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8846 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8847 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8848 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8849 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8850 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8851 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8852 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8853 UINT32_MAX), 8854 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8855 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8856 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8857 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8858 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8859 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8860 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 8861 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8862 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8863 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8864 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8865 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8866 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8867 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8868 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8869 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8870 false), 8871 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8872 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8873 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8874 true), 8875 /* 8876 * lecacy_cache defaults to true unless the CPU model provides its 8877 * own cache information (see x86_cpu_load_def()). 8878 */ 8879 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8880 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8881 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8882 8883 /* 8884 * From "Requirements for Implementing the Microsoft 8885 * Hypervisor Interface": 8886 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8887 * 8888 * "Starting with Windows Server 2012 and Windows 8, if 8889 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8890 * the hypervisor imposes no specific limit to the number of VPs. 8891 * In this case, Windows Server 2012 guest VMs may use more than 8892 * 64 VPs, up to the maximum supported number of processors applicable 8893 * to the specific Windows version being used." 8894 */ 8895 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8896 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8897 false), 8898 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8899 true), 8900 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8901 }; 8902 8903 #ifndef CONFIG_USER_ONLY 8904 #include "hw/core/sysemu-cpu-ops.h" 8905 8906 static const struct SysemuCPUOps i386_sysemu_ops = { 8907 .has_work = x86_cpu_has_work, 8908 .get_memory_mapping = x86_cpu_get_memory_mapping, 8909 .get_paging_enabled = x86_cpu_get_paging_enabled, 8910 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8911 .asidx_from_attrs = x86_asidx_from_attrs, 8912 .get_crash_info = x86_cpu_get_crash_info, 8913 .write_elf32_note = x86_cpu_write_elf32_note, 8914 .write_elf64_note = x86_cpu_write_elf64_note, 8915 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8916 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8917 .legacy_vmsd = &vmstate_x86_cpu, 8918 }; 8919 #endif 8920 8921 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8922 { 8923 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8924 CPUClass *cc = CPU_CLASS(oc); 8925 DeviceClass *dc = DEVICE_CLASS(oc); 8926 ResettableClass *rc = RESETTABLE_CLASS(oc); 8927 FeatureWord w; 8928 8929 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8930 &xcc->parent_realize); 8931 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8932 &xcc->parent_unrealize); 8933 device_class_set_props(dc, x86_cpu_properties); 8934 8935 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8936 &xcc->parent_phases); 8937 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8938 8939 cc->class_by_name = x86_cpu_class_by_name; 8940 cc->parse_features = x86_cpu_parse_featurestr; 8941 cc->mmu_index = x86_cpu_mmu_index; 8942 cc->dump_state = x86_cpu_dump_state; 8943 cc->set_pc = x86_cpu_set_pc; 8944 cc->get_pc = x86_cpu_get_pc; 8945 cc->gdb_read_register = x86_cpu_gdb_read_register; 8946 cc->gdb_write_register = x86_cpu_gdb_write_register; 8947 cc->get_arch_id = x86_cpu_get_arch_id; 8948 8949 #ifndef CONFIG_USER_ONLY 8950 cc->sysemu_ops = &i386_sysemu_ops; 8951 #endif /* !CONFIG_USER_ONLY */ 8952 8953 cc->gdb_arch_name = x86_gdb_arch_name; 8954 #ifdef TARGET_X86_64 8955 cc->gdb_core_xml_file = "i386-64bit.xml"; 8956 #else 8957 cc->gdb_core_xml_file = "i386-32bit.xml"; 8958 #endif 8959 cc->disas_set_info = x86_disas_set_info; 8960 8961 dc->user_creatable = true; 8962 8963 object_class_property_add(oc, "family", "int", 8964 x86_cpuid_version_get_family, 8965 x86_cpuid_version_set_family, NULL, NULL); 8966 object_class_property_add(oc, "model", "int", 8967 x86_cpuid_version_get_model, 8968 x86_cpuid_version_set_model, NULL, NULL); 8969 object_class_property_add(oc, "stepping", "int", 8970 x86_cpuid_version_get_stepping, 8971 x86_cpuid_version_set_stepping, NULL, NULL); 8972 object_class_property_add_str(oc, "vendor", 8973 x86_cpuid_get_vendor, 8974 x86_cpuid_set_vendor); 8975 object_class_property_add_str(oc, "model-id", 8976 x86_cpuid_get_model_id, 8977 x86_cpuid_set_model_id); 8978 object_class_property_add(oc, "tsc-frequency", "int", 8979 x86_cpuid_get_tsc_freq, 8980 x86_cpuid_set_tsc_freq, NULL, NULL); 8981 /* 8982 * The "unavailable-features" property has the same semantics as 8983 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8984 * QMP command: they list the features that would have prevented the 8985 * CPU from running if the "enforce" flag was set. 8986 */ 8987 object_class_property_add(oc, "unavailable-features", "strList", 8988 x86_cpu_get_unavailable_features, 8989 NULL, NULL, NULL); 8990 8991 #if !defined(CONFIG_USER_ONLY) 8992 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8993 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8994 #endif 8995 8996 for (w = 0; w < FEATURE_WORDS; w++) { 8997 int bitnr; 8998 for (bitnr = 0; bitnr < 64; bitnr++) { 8999 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 9000 } 9001 } 9002 } 9003 9004 static const TypeInfo x86_cpu_type_info = { 9005 .name = TYPE_X86_CPU, 9006 .parent = TYPE_CPU, 9007 .instance_size = sizeof(X86CPU), 9008 .instance_align = __alignof(X86CPU), 9009 .instance_init = x86_cpu_initfn, 9010 .instance_post_init = x86_cpu_post_initfn, 9011 9012 .abstract = true, 9013 .class_size = sizeof(X86CPUClass), 9014 .class_init = x86_cpu_common_class_init, 9015 }; 9016 9017 /* "base" CPU model, used by query-cpu-model-expansion */ 9018 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 9019 { 9020 X86CPUClass *xcc = X86_CPU_CLASS(oc); 9021 9022 xcc->static_model = true; 9023 xcc->migration_safe = true; 9024 xcc->model_description = "base CPU model type with no features enabled"; 9025 xcc->ordering = 8; 9026 } 9027 9028 static const TypeInfo x86_base_cpu_type_info = { 9029 .name = X86_CPU_TYPE_NAME("base"), 9030 .parent = TYPE_X86_CPU, 9031 .class_init = x86_cpu_base_class_init, 9032 }; 9033 9034 static void x86_cpu_register_types(void) 9035 { 9036 int i; 9037 9038 type_register_static(&x86_cpu_type_info); 9039 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 9040 x86_register_cpudef_types(&builtin_x86_defs[i]); 9041 } 9042 type_register_static(&max_x86_cpu_type_info); 9043 type_register_static(&x86_base_cpu_type_info); 9044 } 9045 9046 type_init(x86_cpu_register_types) 9047