1 /* 2 * i386 CPUID helper functions 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/bitops.h" 24 #include "qemu/qemu-print.h" 25 26 #include "cpu.h" 27 #include "exec/exec-all.h" 28 #include "sysemu/kvm.h" 29 #include "sysemu/reset.h" 30 #include "sysemu/hvf.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/xen.h" 33 #include "kvm_i386.h" 34 #include "sev_i386.h" 35 36 #include "qemu/error-report.h" 37 #include "qemu/module.h" 38 #include "qemu/option.h" 39 #include "qemu/config-file.h" 40 #include "qapi/error.h" 41 #include "qapi/qapi-visit-machine.h" 42 #include "qapi/qapi-visit-run-state.h" 43 #include "qapi/qmp/qdict.h" 44 #include "qapi/qmp/qerror.h" 45 #include "qapi/visitor.h" 46 #include "qom/qom-qobject.h" 47 #include "sysemu/arch_init.h" 48 #include "qapi/qapi-commands-machine-target.h" 49 50 #include "standard-headers/asm-x86/kvm_para.h" 51 52 #include "sysemu/sysemu.h" 53 #include "sysemu/tcg.h" 54 #include "hw/qdev-properties.h" 55 #include "hw/i386/topology.h" 56 #ifndef CONFIG_USER_ONLY 57 #include "exec/address-spaces.h" 58 #include "hw/i386/apic_internal.h" 59 #include "hw/boards.h" 60 #endif 61 62 #include "disas/capstone.h" 63 64 /* Helpers for building CPUID[2] descriptors: */ 65 66 struct CPUID2CacheDescriptorInfo { 67 enum CacheType type; 68 int level; 69 int size; 70 int line_size; 71 int associativity; 72 }; 73 74 /* 75 * Known CPUID 2 cache descriptors. 76 * From Intel SDM Volume 2A, CPUID instruction 77 */ 78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 80 .associativity = 4, .line_size = 32, }, 81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 82 .associativity = 4, .line_size = 32, }, 83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 84 .associativity = 4, .line_size = 64, }, 85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 86 .associativity = 2, .line_size = 32, }, 87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 88 .associativity = 4, .line_size = 32, }, 89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 90 .associativity = 4, .line_size = 64, }, 91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 92 .associativity = 6, .line_size = 64, }, 93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 94 .associativity = 2, .line_size = 64, }, 95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 96 .associativity = 8, .line_size = 64, }, 97 /* lines per sector is not supported cpuid2_cache_descriptor(), 98 * so descriptors 0x22, 0x23 are not included 99 */ 100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 101 .associativity = 16, .line_size = 64, }, 102 /* lines per sector is not supported cpuid2_cache_descriptor(), 103 * so descriptors 0x25, 0x20 are not included 104 */ 105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 106 .associativity = 8, .line_size = 64, }, 107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 108 .associativity = 8, .line_size = 64, }, 109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 110 .associativity = 4, .line_size = 32, }, 111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 112 .associativity = 4, .line_size = 32, }, 113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 114 .associativity = 4, .line_size = 32, }, 115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 116 .associativity = 4, .line_size = 32, }, 117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 118 .associativity = 4, .line_size = 32, }, 119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 120 .associativity = 4, .line_size = 64, }, 121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 122 .associativity = 8, .line_size = 64, }, 123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 124 .associativity = 12, .line_size = 64, }, 125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 127 .associativity = 12, .line_size = 64, }, 128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 129 .associativity = 16, .line_size = 64, }, 130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 131 .associativity = 12, .line_size = 64, }, 132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 133 .associativity = 16, .line_size = 64, }, 134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 135 .associativity = 24, .line_size = 64, }, 136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 139 .associativity = 4, .line_size = 64, }, 140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 141 .associativity = 4, .line_size = 64, }, 142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 143 .associativity = 4, .line_size = 64, }, 144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 145 .associativity = 4, .line_size = 64, }, 146 /* lines per sector is not supported cpuid2_cache_descriptor(), 147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 148 */ 149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 150 .associativity = 8, .line_size = 64, }, 151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 152 .associativity = 2, .line_size = 64, }, 153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 8, .line_size = 64, }, 155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 156 .associativity = 8, .line_size = 32, }, 157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 158 .associativity = 8, .line_size = 32, }, 159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 8, .line_size = 32, }, 161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 8, .line_size = 32, }, 163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 164 .associativity = 4, .line_size = 64, }, 165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 166 .associativity = 8, .line_size = 64, }, 167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 168 .associativity = 4, .line_size = 64, }, 169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 170 .associativity = 4, .line_size = 64, }, 171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 172 .associativity = 4, .line_size = 64, }, 173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 174 .associativity = 8, .line_size = 64, }, 175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 176 .associativity = 8, .line_size = 64, }, 177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 178 .associativity = 8, .line_size = 64, }, 179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 180 .associativity = 12, .line_size = 64, }, 181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 182 .associativity = 12, .line_size = 64, }, 183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 184 .associativity = 12, .line_size = 64, }, 185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 186 .associativity = 16, .line_size = 64, }, 187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 188 .associativity = 16, .line_size = 64, }, 189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 190 .associativity = 16, .line_size = 64, }, 191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 192 .associativity = 24, .line_size = 64, }, 193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 194 .associativity = 24, .line_size = 64, }, 195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 196 .associativity = 24, .line_size = 64, }, 197 }; 198 199 /* 200 * "CPUID leaf 2 does not report cache descriptor information, 201 * use CPUID leaf 4 to query cache parameters" 202 */ 203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 204 205 /* 206 * Return a CPUID 2 cache descriptor for a given cache. 207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 208 */ 209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 210 { 211 int i; 212 213 assert(cache->size > 0); 214 assert(cache->level > 0); 215 assert(cache->line_size > 0); 216 assert(cache->associativity > 0); 217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 219 if (d->level == cache->level && d->type == cache->type && 220 d->size == cache->size && d->line_size == cache->line_size && 221 d->associativity == cache->associativity) { 222 return i; 223 } 224 } 225 226 return CACHE_DESCRIPTOR_UNAVAILABLE; 227 } 228 229 /* CPUID Leaf 4 constants: */ 230 231 /* EAX: */ 232 #define CACHE_TYPE_D 1 233 #define CACHE_TYPE_I 2 234 #define CACHE_TYPE_UNIFIED 3 235 236 #define CACHE_LEVEL(l) (l << 5) 237 238 #define CACHE_SELF_INIT_LEVEL (1 << 8) 239 240 /* EDX: */ 241 #define CACHE_NO_INVD_SHARING (1 << 0) 242 #define CACHE_INCLUSIVE (1 << 1) 243 #define CACHE_COMPLEX_IDX (1 << 2) 244 245 /* Encode CacheType for CPUID[4].EAX */ 246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 249 0 /* Invalid value */) 250 251 252 /* Encode cache info for CPUID[4] */ 253 static void encode_cache_cpuid4(CPUCacheInfo *cache, 254 int num_apic_ids, int num_cores, 255 uint32_t *eax, uint32_t *ebx, 256 uint32_t *ecx, uint32_t *edx) 257 { 258 assert(cache->size == cache->line_size * cache->associativity * 259 cache->partitions * cache->sets); 260 261 assert(num_apic_ids > 0); 262 *eax = CACHE_TYPE(cache->type) | 263 CACHE_LEVEL(cache->level) | 264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 265 ((num_cores - 1) << 26) | 266 ((num_apic_ids - 1) << 14); 267 268 assert(cache->line_size > 0); 269 assert(cache->partitions > 0); 270 assert(cache->associativity > 0); 271 /* We don't implement fully-associative caches */ 272 assert(cache->associativity < cache->sets); 273 *ebx = (cache->line_size - 1) | 274 ((cache->partitions - 1) << 12) | 275 ((cache->associativity - 1) << 22); 276 277 assert(cache->sets > 0); 278 *ecx = cache->sets - 1; 279 280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 281 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 283 } 284 285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 287 { 288 assert(cache->size % 1024 == 0); 289 assert(cache->lines_per_tag > 0); 290 assert(cache->associativity > 0); 291 assert(cache->line_size > 0); 292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 293 (cache->lines_per_tag << 8) | (cache->line_size); 294 } 295 296 #define ASSOC_FULL 0xFF 297 298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 300 a == 2 ? 0x2 : \ 301 a == 4 ? 0x4 : \ 302 a == 8 ? 0x6 : \ 303 a == 16 ? 0x8 : \ 304 a == 32 ? 0xA : \ 305 a == 48 ? 0xB : \ 306 a == 64 ? 0xC : \ 307 a == 96 ? 0xD : \ 308 a == 128 ? 0xE : \ 309 a == ASSOC_FULL ? 0xF : \ 310 0 /* invalid value */) 311 312 /* 313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 314 * @l3 can be NULL. 315 */ 316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 317 CPUCacheInfo *l3, 318 uint32_t *ecx, uint32_t *edx) 319 { 320 assert(l2->size % 1024 == 0); 321 assert(l2->associativity > 0); 322 assert(l2->lines_per_tag > 0); 323 assert(l2->line_size > 0); 324 *ecx = ((l2->size / 1024) << 16) | 325 (AMD_ENC_ASSOC(l2->associativity) << 12) | 326 (l2->lines_per_tag << 8) | (l2->line_size); 327 328 if (l3) { 329 assert(l3->size % (512 * 1024) == 0); 330 assert(l3->associativity > 0); 331 assert(l3->lines_per_tag > 0); 332 assert(l3->line_size > 0); 333 *edx = ((l3->size / (512 * 1024)) << 18) | 334 (AMD_ENC_ASSOC(l3->associativity) << 12) | 335 (l3->lines_per_tag << 8) | (l3->line_size); 336 } else { 337 *edx = 0; 338 } 339 } 340 341 /* Encode cache info for CPUID[8000001D] */ 342 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 343 X86CPUTopoInfo *topo_info, 344 uint32_t *eax, uint32_t *ebx, 345 uint32_t *ecx, uint32_t *edx) 346 { 347 uint32_t l3_cores; 348 unsigned nodes = MAX(topo_info->nodes_per_pkg, 1); 349 350 assert(cache->size == cache->line_size * cache->associativity * 351 cache->partitions * cache->sets); 352 353 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 354 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 355 356 /* L3 is shared among multiple cores */ 357 if (cache->level == 3) { 358 l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg * 359 topo_info->cores_per_die * 360 topo_info->threads_per_core), 361 nodes); 362 *eax |= (l3_cores - 1) << 14; 363 } else { 364 *eax |= ((topo_info->threads_per_core - 1) << 14); 365 } 366 367 assert(cache->line_size > 0); 368 assert(cache->partitions > 0); 369 assert(cache->associativity > 0); 370 /* We don't implement fully-associative caches */ 371 assert(cache->associativity < cache->sets); 372 *ebx = (cache->line_size - 1) | 373 ((cache->partitions - 1) << 12) | 374 ((cache->associativity - 1) << 22); 375 376 assert(cache->sets > 0); 377 *ecx = cache->sets - 1; 378 379 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 380 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 381 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 382 } 383 384 /* Encode cache info for CPUID[8000001E] */ 385 static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu, 386 uint32_t *eax, uint32_t *ebx, 387 uint32_t *ecx, uint32_t *edx) 388 { 389 X86CPUTopoIDs topo_ids = {0}; 390 unsigned long nodes = MAX(topo_info->nodes_per_pkg, 1); 391 int shift; 392 393 x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids); 394 395 *eax = cpu->apic_id; 396 /* 397 * CPUID_Fn8000001E_EBX 398 * 31:16 Reserved 399 * 15:8 Threads per core (The number of threads per core is 400 * Threads per core + 1) 401 * 7:0 Core id (see bit decoding below) 402 * SMT: 403 * 4:3 node id 404 * 2 Core complex id 405 * 1:0 Core id 406 * Non SMT: 407 * 5:4 node id 408 * 3 Core complex id 409 * 1:0 Core id 410 */ 411 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.node_id << 3) | 412 (topo_ids.core_id); 413 /* 414 * CPUID_Fn8000001E_ECX 415 * 31:11 Reserved 416 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1) 417 * 7:0 Node id (see bit decoding below) 418 * 2 Socket id 419 * 1:0 Node id 420 */ 421 if (nodes <= 4) { 422 *ecx = ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.node_id; 423 } else { 424 /* 425 * Node id fix up. Actual hardware supports up to 4 nodes. But with 426 * more than 32 cores, we may end up with more than 4 nodes. 427 * Node id is a combination of socket id and node id. Only requirement 428 * here is that this number should be unique accross the system. 429 * Shift the socket id to accommodate more nodes. We dont expect both 430 * socket id and node id to be big number at the same time. This is not 431 * an ideal config but we need to to support it. Max nodes we can have 432 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need 433 * 5 bits for nodes. Find the left most set bit to represent the total 434 * number of nodes. find_last_bit returns last set bit(0 based). Left 435 * shift(+1) the socket id to represent all the nodes. 436 */ 437 nodes -= 1; 438 shift = find_last_bit(&nodes, 8); 439 *ecx = (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) | 440 topo_ids.node_id; 441 } 442 *edx = 0; 443 } 444 445 /* 446 * Definitions of the hardcoded cache entries we expose: 447 * These are legacy cache values. If there is a need to change any 448 * of these values please use builtin_x86_defs 449 */ 450 451 /* L1 data cache: */ 452 static CPUCacheInfo legacy_l1d_cache = { 453 .type = DATA_CACHE, 454 .level = 1, 455 .size = 32 * KiB, 456 .self_init = 1, 457 .line_size = 64, 458 .associativity = 8, 459 .sets = 64, 460 .partitions = 1, 461 .no_invd_sharing = true, 462 }; 463 464 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 465 static CPUCacheInfo legacy_l1d_cache_amd = { 466 .type = DATA_CACHE, 467 .level = 1, 468 .size = 64 * KiB, 469 .self_init = 1, 470 .line_size = 64, 471 .associativity = 2, 472 .sets = 512, 473 .partitions = 1, 474 .lines_per_tag = 1, 475 .no_invd_sharing = true, 476 }; 477 478 /* L1 instruction cache: */ 479 static CPUCacheInfo legacy_l1i_cache = { 480 .type = INSTRUCTION_CACHE, 481 .level = 1, 482 .size = 32 * KiB, 483 .self_init = 1, 484 .line_size = 64, 485 .associativity = 8, 486 .sets = 64, 487 .partitions = 1, 488 .no_invd_sharing = true, 489 }; 490 491 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 492 static CPUCacheInfo legacy_l1i_cache_amd = { 493 .type = INSTRUCTION_CACHE, 494 .level = 1, 495 .size = 64 * KiB, 496 .self_init = 1, 497 .line_size = 64, 498 .associativity = 2, 499 .sets = 512, 500 .partitions = 1, 501 .lines_per_tag = 1, 502 .no_invd_sharing = true, 503 }; 504 505 /* Level 2 unified cache: */ 506 static CPUCacheInfo legacy_l2_cache = { 507 .type = UNIFIED_CACHE, 508 .level = 2, 509 .size = 4 * MiB, 510 .self_init = 1, 511 .line_size = 64, 512 .associativity = 16, 513 .sets = 4096, 514 .partitions = 1, 515 .no_invd_sharing = true, 516 }; 517 518 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 519 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 520 .type = UNIFIED_CACHE, 521 .level = 2, 522 .size = 2 * MiB, 523 .line_size = 64, 524 .associativity = 8, 525 }; 526 527 528 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 529 static CPUCacheInfo legacy_l2_cache_amd = { 530 .type = UNIFIED_CACHE, 531 .level = 2, 532 .size = 512 * KiB, 533 .line_size = 64, 534 .lines_per_tag = 1, 535 .associativity = 16, 536 .sets = 512, 537 .partitions = 1, 538 }; 539 540 /* Level 3 unified cache: */ 541 static CPUCacheInfo legacy_l3_cache = { 542 .type = UNIFIED_CACHE, 543 .level = 3, 544 .size = 16 * MiB, 545 .line_size = 64, 546 .associativity = 16, 547 .sets = 16384, 548 .partitions = 1, 549 .lines_per_tag = 1, 550 .self_init = true, 551 .inclusive = true, 552 .complex_indexing = true, 553 }; 554 555 /* TLB definitions: */ 556 557 #define L1_DTLB_2M_ASSOC 1 558 #define L1_DTLB_2M_ENTRIES 255 559 #define L1_DTLB_4K_ASSOC 1 560 #define L1_DTLB_4K_ENTRIES 255 561 562 #define L1_ITLB_2M_ASSOC 1 563 #define L1_ITLB_2M_ENTRIES 255 564 #define L1_ITLB_4K_ASSOC 1 565 #define L1_ITLB_4K_ENTRIES 255 566 567 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 568 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 569 #define L2_DTLB_4K_ASSOC 4 570 #define L2_DTLB_4K_ENTRIES 512 571 572 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 573 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 574 #define L2_ITLB_4K_ASSOC 4 575 #define L2_ITLB_4K_ENTRIES 512 576 577 /* CPUID Leaf 0x14 constants: */ 578 #define INTEL_PT_MAX_SUBLEAF 0x1 579 /* 580 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 581 * MSR can be accessed; 582 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 583 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 584 * of Intel PT MSRs across warm reset; 585 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 586 */ 587 #define INTEL_PT_MINIMAL_EBX 0xf 588 /* 589 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 590 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 591 * accessed; 592 * bit[01]: ToPA tables can hold any number of output entries, up to the 593 * maximum allowed by the MaskOrTableOffset field of 594 * IA32_RTIT_OUTPUT_MASK_PTRS; 595 * bit[02]: Support Single-Range Output scheme; 596 */ 597 #define INTEL_PT_MINIMAL_ECX 0x7 598 /* generated packets which contain IP payloads have LIP values */ 599 #define INTEL_PT_IP_LIP (1 << 31) 600 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 601 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 602 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 603 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 604 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 605 606 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 607 uint32_t vendor2, uint32_t vendor3) 608 { 609 int i; 610 for (i = 0; i < 4; i++) { 611 dst[i] = vendor1 >> (8 * i); 612 dst[i + 4] = vendor2 >> (8 * i); 613 dst[i + 8] = vendor3 >> (8 * i); 614 } 615 dst[CPUID_VENDOR_SZ] = '\0'; 616 } 617 618 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 619 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 620 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 621 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 622 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 623 CPUID_PSE36 | CPUID_FXSR) 624 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 625 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 626 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 627 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 628 CPUID_PAE | CPUID_SEP | CPUID_APIC) 629 630 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 631 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 632 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 633 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 634 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 635 /* partly implemented: 636 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 637 /* missing: 638 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 639 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 640 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 641 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 642 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 643 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 644 CPUID_EXT_RDRAND) 645 /* missing: 646 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 647 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, 648 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 649 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX, 650 CPUID_EXT_F16C */ 651 652 #ifdef TARGET_X86_64 653 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 654 #else 655 #define TCG_EXT2_X86_64_FEATURES 0 656 #endif 657 658 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 659 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 660 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 661 TCG_EXT2_X86_64_FEATURES) 662 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 663 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 664 #define TCG_EXT4_FEATURES 0 665 #define TCG_SVM_FEATURES CPUID_SVM_NPT 666 #define TCG_KVM_FEATURES 0 667 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 668 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 669 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 670 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 671 CPUID_7_0_EBX_ERMS) 672 /* missing: 673 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, 674 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 675 CPUID_7_0_EBX_RDSEED */ 676 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \ 677 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 678 CPUID_7_0_ECX_LA57) 679 #define TCG_7_0_EDX_FEATURES 0 680 #define TCG_7_1_EAX_FEATURES 0 681 #define TCG_APM_FEATURES 0 682 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 683 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 684 /* missing: 685 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 686 687 typedef enum FeatureWordType { 688 CPUID_FEATURE_WORD, 689 MSR_FEATURE_WORD, 690 } FeatureWordType; 691 692 typedef struct FeatureWordInfo { 693 FeatureWordType type; 694 /* feature flags names are taken from "Intel Processor Identification and 695 * the CPUID Instruction" and AMD's "CPUID Specification". 696 * In cases of disagreement between feature naming conventions, 697 * aliases may be added. 698 */ 699 const char *feat_names[64]; 700 union { 701 /* If type==CPUID_FEATURE_WORD */ 702 struct { 703 uint32_t eax; /* Input EAX for CPUID */ 704 bool needs_ecx; /* CPUID instruction uses ECX as input */ 705 uint32_t ecx; /* Input ECX value for CPUID */ 706 int reg; /* output register (R_* constant) */ 707 } cpuid; 708 /* If type==MSR_FEATURE_WORD */ 709 struct { 710 uint32_t index; 711 } msr; 712 }; 713 uint64_t tcg_features; /* Feature flags supported by TCG */ 714 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */ 715 uint64_t migratable_flags; /* Feature flags known to be migratable */ 716 /* Features that shouldn't be auto-enabled by "-cpu host" */ 717 uint64_t no_autoenable_flags; 718 } FeatureWordInfo; 719 720 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 721 [FEAT_1_EDX] = { 722 .type = CPUID_FEATURE_WORD, 723 .feat_names = { 724 "fpu", "vme", "de", "pse", 725 "tsc", "msr", "pae", "mce", 726 "cx8", "apic", NULL, "sep", 727 "mtrr", "pge", "mca", "cmov", 728 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 729 NULL, "ds" /* Intel dts */, "acpi", "mmx", 730 "fxsr", "sse", "sse2", "ss", 731 "ht" /* Intel htt */, "tm", "ia64", "pbe", 732 }, 733 .cpuid = {.eax = 1, .reg = R_EDX, }, 734 .tcg_features = TCG_FEATURES, 735 }, 736 [FEAT_1_ECX] = { 737 .type = CPUID_FEATURE_WORD, 738 .feat_names = { 739 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 740 "ds-cpl", "vmx", "smx", "est", 741 "tm2", "ssse3", "cid", NULL, 742 "fma", "cx16", "xtpr", "pdcm", 743 NULL, "pcid", "dca", "sse4.1", 744 "sse4.2", "x2apic", "movbe", "popcnt", 745 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 746 "avx", "f16c", "rdrand", "hypervisor", 747 }, 748 .cpuid = { .eax = 1, .reg = R_ECX, }, 749 .tcg_features = TCG_EXT_FEATURES, 750 }, 751 /* Feature names that are already defined on feature_name[] but 752 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 753 * names on feat_names below. They are copied automatically 754 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 755 */ 756 [FEAT_8000_0001_EDX] = { 757 .type = CPUID_FEATURE_WORD, 758 .feat_names = { 759 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 760 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 761 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 762 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 763 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 764 "nx", NULL, "mmxext", NULL /* mmx */, 765 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 766 NULL, "lm", "3dnowext", "3dnow", 767 }, 768 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 769 .tcg_features = TCG_EXT2_FEATURES, 770 }, 771 [FEAT_8000_0001_ECX] = { 772 .type = CPUID_FEATURE_WORD, 773 .feat_names = { 774 "lahf-lm", "cmp-legacy", "svm", "extapic", 775 "cr8legacy", "abm", "sse4a", "misalignsse", 776 "3dnowprefetch", "osvw", "ibs", "xop", 777 "skinit", "wdt", NULL, "lwp", 778 "fma4", "tce", NULL, "nodeid-msr", 779 NULL, "tbm", "topoext", "perfctr-core", 780 "perfctr-nb", NULL, NULL, NULL, 781 NULL, NULL, NULL, NULL, 782 }, 783 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 784 .tcg_features = TCG_EXT3_FEATURES, 785 /* 786 * TOPOEXT is always allowed but can't be enabled blindly by 787 * "-cpu host", as it requires consistent cache topology info 788 * to be provided so it doesn't confuse guests. 789 */ 790 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 791 }, 792 [FEAT_C000_0001_EDX] = { 793 .type = CPUID_FEATURE_WORD, 794 .feat_names = { 795 NULL, NULL, "xstore", "xstore-en", 796 NULL, NULL, "xcrypt", "xcrypt-en", 797 "ace2", "ace2-en", "phe", "phe-en", 798 "pmm", "pmm-en", NULL, NULL, 799 NULL, NULL, NULL, NULL, 800 NULL, NULL, NULL, NULL, 801 NULL, NULL, NULL, NULL, 802 NULL, NULL, NULL, NULL, 803 }, 804 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 805 .tcg_features = TCG_EXT4_FEATURES, 806 }, 807 [FEAT_KVM] = { 808 .type = CPUID_FEATURE_WORD, 809 .feat_names = { 810 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 811 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 812 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 813 "kvm-poll-control", "kvm-pv-sched-yield", NULL, NULL, 814 NULL, NULL, NULL, NULL, 815 NULL, NULL, NULL, NULL, 816 "kvmclock-stable-bit", NULL, NULL, NULL, 817 NULL, NULL, NULL, NULL, 818 }, 819 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 820 .tcg_features = TCG_KVM_FEATURES, 821 }, 822 [FEAT_KVM_HINTS] = { 823 .type = CPUID_FEATURE_WORD, 824 .feat_names = { 825 "kvm-hint-dedicated", NULL, NULL, NULL, 826 NULL, NULL, NULL, NULL, 827 NULL, NULL, NULL, NULL, 828 NULL, NULL, NULL, NULL, 829 NULL, NULL, NULL, NULL, 830 NULL, NULL, NULL, NULL, 831 NULL, NULL, NULL, NULL, 832 NULL, NULL, NULL, NULL, 833 }, 834 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 835 .tcg_features = TCG_KVM_FEATURES, 836 /* 837 * KVM hints aren't auto-enabled by -cpu host, they need to be 838 * explicitly enabled in the command-line. 839 */ 840 .no_autoenable_flags = ~0U, 841 }, 842 /* 843 * .feat_names are commented out for Hyper-V enlightenments because we 844 * don't want to have two different ways for enabling them on QEMU command 845 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require 846 * enabling several feature bits simultaneously, exposing these bits 847 * individually may just confuse guests. 848 */ 849 [FEAT_HYPERV_EAX] = { 850 .type = CPUID_FEATURE_WORD, 851 .feat_names = { 852 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */, 853 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */, 854 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */, 855 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */, 856 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */, 857 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */, 858 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */, 859 NULL, NULL, 860 NULL, NULL, NULL, NULL, 861 NULL, NULL, NULL, NULL, 862 NULL, NULL, NULL, NULL, 863 NULL, NULL, NULL, NULL, 864 }, 865 .cpuid = { .eax = 0x40000003, .reg = R_EAX, }, 866 }, 867 [FEAT_HYPERV_EBX] = { 868 .type = CPUID_FEATURE_WORD, 869 .feat_names = { 870 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */, 871 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */, 872 NULL /* hv_post_messages */, NULL /* hv_signal_events */, 873 NULL /* hv_create_port */, NULL /* hv_connect_port */, 874 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */, 875 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */, 876 NULL, NULL, 877 NULL, NULL, NULL, NULL, 878 NULL, NULL, NULL, NULL, 879 NULL, NULL, NULL, NULL, 880 NULL, NULL, NULL, NULL, 881 }, 882 .cpuid = { .eax = 0x40000003, .reg = R_EBX, }, 883 }, 884 [FEAT_HYPERV_EDX] = { 885 .type = CPUID_FEATURE_WORD, 886 .feat_names = { 887 NULL /* hv_mwait */, NULL /* hv_guest_debugging */, 888 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */, 889 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */, 890 NULL, NULL, 891 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL, 892 NULL, NULL, NULL, NULL, 893 NULL, NULL, NULL, NULL, 894 NULL, NULL, NULL, NULL, 895 NULL, NULL, NULL, NULL, 896 NULL, NULL, NULL, NULL, 897 }, 898 .cpuid = { .eax = 0x40000003, .reg = R_EDX, }, 899 }, 900 [FEAT_HV_RECOMM_EAX] = { 901 .type = CPUID_FEATURE_WORD, 902 .feat_names = { 903 NULL /* hv_recommend_pv_as_switch */, 904 NULL /* hv_recommend_pv_tlbflush_local */, 905 NULL /* hv_recommend_pv_tlbflush_remote */, 906 NULL /* hv_recommend_msr_apic_access */, 907 NULL /* hv_recommend_msr_reset */, 908 NULL /* hv_recommend_relaxed_timing */, 909 NULL /* hv_recommend_dma_remapping */, 910 NULL /* hv_recommend_int_remapping */, 911 NULL /* hv_recommend_x2apic_msrs */, 912 NULL /* hv_recommend_autoeoi_deprecation */, 913 NULL /* hv_recommend_pv_ipi */, 914 NULL /* hv_recommend_ex_hypercalls */, 915 NULL /* hv_hypervisor_is_nested */, 916 NULL /* hv_recommend_int_mbec */, 917 NULL /* hv_recommend_evmcs */, 918 NULL, 919 NULL, NULL, NULL, NULL, 920 NULL, NULL, NULL, NULL, 921 NULL, NULL, NULL, NULL, 922 NULL, NULL, NULL, NULL, 923 }, 924 .cpuid = { .eax = 0x40000004, .reg = R_EAX, }, 925 }, 926 [FEAT_HV_NESTED_EAX] = { 927 .type = CPUID_FEATURE_WORD, 928 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, }, 929 }, 930 [FEAT_SVM] = { 931 .type = CPUID_FEATURE_WORD, 932 .feat_names = { 933 "npt", "lbrv", "svm-lock", "nrip-save", 934 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 935 NULL, NULL, "pause-filter", NULL, 936 "pfthreshold", NULL, NULL, NULL, 937 NULL, NULL, NULL, NULL, 938 NULL, NULL, NULL, NULL, 939 NULL, NULL, NULL, NULL, 940 NULL, NULL, NULL, NULL, 941 }, 942 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 943 .tcg_features = TCG_SVM_FEATURES, 944 }, 945 [FEAT_7_0_EBX] = { 946 .type = CPUID_FEATURE_WORD, 947 .feat_names = { 948 "fsgsbase", "tsc-adjust", NULL, "bmi1", 949 "hle", "avx2", NULL, "smep", 950 "bmi2", "erms", "invpcid", "rtm", 951 NULL, NULL, "mpx", NULL, 952 "avx512f", "avx512dq", "rdseed", "adx", 953 "smap", "avx512ifma", "pcommit", "clflushopt", 954 "clwb", "intel-pt", "avx512pf", "avx512er", 955 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 956 }, 957 .cpuid = { 958 .eax = 7, 959 .needs_ecx = true, .ecx = 0, 960 .reg = R_EBX, 961 }, 962 .tcg_features = TCG_7_0_EBX_FEATURES, 963 }, 964 [FEAT_7_0_ECX] = { 965 .type = CPUID_FEATURE_WORD, 966 .feat_names = { 967 NULL, "avx512vbmi", "umip", "pku", 968 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 969 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 970 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 971 "la57", NULL, NULL, NULL, 972 NULL, NULL, "rdpid", NULL, 973 NULL, "cldemote", NULL, "movdiri", 974 "movdir64b", NULL, NULL, NULL, 975 }, 976 .cpuid = { 977 .eax = 7, 978 .needs_ecx = true, .ecx = 0, 979 .reg = R_ECX, 980 }, 981 .tcg_features = TCG_7_0_ECX_FEATURES, 982 }, 983 [FEAT_7_0_EDX] = { 984 .type = CPUID_FEATURE_WORD, 985 .feat_names = { 986 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 987 NULL, NULL, NULL, NULL, 988 "avx512-vp2intersect", NULL, "md-clear", NULL, 989 NULL, NULL, NULL, NULL, 990 NULL, NULL, NULL /* pconfig */, NULL, 991 NULL, NULL, NULL, NULL, 992 NULL, NULL, "spec-ctrl", "stibp", 993 NULL, "arch-capabilities", "core-capability", "ssbd", 994 }, 995 .cpuid = { 996 .eax = 7, 997 .needs_ecx = true, .ecx = 0, 998 .reg = R_EDX, 999 }, 1000 .tcg_features = TCG_7_0_EDX_FEATURES, 1001 }, 1002 [FEAT_7_1_EAX] = { 1003 .type = CPUID_FEATURE_WORD, 1004 .feat_names = { 1005 NULL, NULL, NULL, NULL, 1006 NULL, "avx512-bf16", NULL, NULL, 1007 NULL, NULL, NULL, NULL, 1008 NULL, NULL, NULL, NULL, 1009 NULL, NULL, NULL, NULL, 1010 NULL, NULL, NULL, NULL, 1011 NULL, NULL, NULL, NULL, 1012 NULL, NULL, NULL, NULL, 1013 }, 1014 .cpuid = { 1015 .eax = 7, 1016 .needs_ecx = true, .ecx = 1, 1017 .reg = R_EAX, 1018 }, 1019 .tcg_features = TCG_7_1_EAX_FEATURES, 1020 }, 1021 [FEAT_8000_0007_EDX] = { 1022 .type = CPUID_FEATURE_WORD, 1023 .feat_names = { 1024 NULL, NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 "invtsc", NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 NULL, NULL, NULL, NULL, 1030 NULL, NULL, NULL, NULL, 1031 NULL, NULL, NULL, NULL, 1032 }, 1033 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1034 .tcg_features = TCG_APM_FEATURES, 1035 .unmigratable_flags = CPUID_APM_INVTSC, 1036 }, 1037 [FEAT_8000_0008_EBX] = { 1038 .type = CPUID_FEATURE_WORD, 1039 .feat_names = { 1040 "clzero", NULL, "xsaveerptr", NULL, 1041 NULL, NULL, NULL, NULL, 1042 NULL, "wbnoinvd", NULL, NULL, 1043 "ibpb", NULL, NULL, "amd-stibp", 1044 NULL, NULL, NULL, NULL, 1045 NULL, NULL, NULL, NULL, 1046 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1047 NULL, NULL, NULL, NULL, 1048 }, 1049 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1050 .tcg_features = 0, 1051 .unmigratable_flags = 0, 1052 }, 1053 [FEAT_XSAVE] = { 1054 .type = CPUID_FEATURE_WORD, 1055 .feat_names = { 1056 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1057 NULL, NULL, NULL, NULL, 1058 NULL, NULL, NULL, NULL, 1059 NULL, NULL, NULL, NULL, 1060 NULL, NULL, NULL, NULL, 1061 NULL, NULL, NULL, NULL, 1062 NULL, NULL, NULL, NULL, 1063 NULL, NULL, NULL, NULL, 1064 }, 1065 .cpuid = { 1066 .eax = 0xd, 1067 .needs_ecx = true, .ecx = 1, 1068 .reg = R_EAX, 1069 }, 1070 .tcg_features = TCG_XSAVE_FEATURES, 1071 }, 1072 [FEAT_6_EAX] = { 1073 .type = CPUID_FEATURE_WORD, 1074 .feat_names = { 1075 NULL, NULL, "arat", NULL, 1076 NULL, NULL, NULL, NULL, 1077 NULL, NULL, NULL, NULL, 1078 NULL, NULL, NULL, NULL, 1079 NULL, NULL, NULL, NULL, 1080 NULL, NULL, NULL, NULL, 1081 NULL, NULL, NULL, NULL, 1082 NULL, NULL, NULL, NULL, 1083 }, 1084 .cpuid = { .eax = 6, .reg = R_EAX, }, 1085 .tcg_features = TCG_6_EAX_FEATURES, 1086 }, 1087 [FEAT_XSAVE_COMP_LO] = { 1088 .type = CPUID_FEATURE_WORD, 1089 .cpuid = { 1090 .eax = 0xD, 1091 .needs_ecx = true, .ecx = 0, 1092 .reg = R_EAX, 1093 }, 1094 .tcg_features = ~0U, 1095 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1096 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1097 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1098 XSTATE_PKRU_MASK, 1099 }, 1100 [FEAT_XSAVE_COMP_HI] = { 1101 .type = CPUID_FEATURE_WORD, 1102 .cpuid = { 1103 .eax = 0xD, 1104 .needs_ecx = true, .ecx = 0, 1105 .reg = R_EDX, 1106 }, 1107 .tcg_features = ~0U, 1108 }, 1109 /*Below are MSR exposed features*/ 1110 [FEAT_ARCH_CAPABILITIES] = { 1111 .type = MSR_FEATURE_WORD, 1112 .feat_names = { 1113 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1114 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1115 "taa-no", NULL, NULL, NULL, 1116 NULL, NULL, NULL, NULL, 1117 NULL, NULL, NULL, NULL, 1118 NULL, NULL, NULL, NULL, 1119 NULL, NULL, NULL, NULL, 1120 NULL, NULL, NULL, NULL, 1121 }, 1122 .msr = { 1123 .index = MSR_IA32_ARCH_CAPABILITIES, 1124 }, 1125 }, 1126 [FEAT_CORE_CAPABILITY] = { 1127 .type = MSR_FEATURE_WORD, 1128 .feat_names = { 1129 NULL, NULL, NULL, NULL, 1130 NULL, "split-lock-detect", NULL, NULL, 1131 NULL, NULL, NULL, NULL, 1132 NULL, NULL, NULL, NULL, 1133 NULL, NULL, NULL, NULL, 1134 NULL, NULL, NULL, NULL, 1135 NULL, NULL, NULL, NULL, 1136 NULL, NULL, NULL, NULL, 1137 }, 1138 .msr = { 1139 .index = MSR_IA32_CORE_CAPABILITY, 1140 }, 1141 }, 1142 [FEAT_PERF_CAPABILITIES] = { 1143 .type = MSR_FEATURE_WORD, 1144 .feat_names = { 1145 NULL, NULL, NULL, NULL, 1146 NULL, NULL, NULL, NULL, 1147 NULL, NULL, NULL, NULL, 1148 NULL, "full-width-write", NULL, NULL, 1149 NULL, NULL, NULL, NULL, 1150 NULL, NULL, NULL, NULL, 1151 NULL, NULL, NULL, NULL, 1152 NULL, NULL, NULL, NULL, 1153 }, 1154 .msr = { 1155 .index = MSR_IA32_PERF_CAPABILITIES, 1156 }, 1157 }, 1158 1159 [FEAT_VMX_PROCBASED_CTLS] = { 1160 .type = MSR_FEATURE_WORD, 1161 .feat_names = { 1162 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1163 NULL, NULL, NULL, "vmx-hlt-exit", 1164 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1165 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1166 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1167 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1168 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1169 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1170 }, 1171 .msr = { 1172 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1173 } 1174 }, 1175 1176 [FEAT_VMX_SECONDARY_CTLS] = { 1177 .type = MSR_FEATURE_WORD, 1178 .feat_names = { 1179 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1180 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1181 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1182 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1183 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1184 "vmx-xsaves", NULL, NULL, NULL, 1185 NULL, NULL, NULL, NULL, 1186 NULL, NULL, NULL, NULL, 1187 }, 1188 .msr = { 1189 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1190 } 1191 }, 1192 1193 [FEAT_VMX_PINBASED_CTLS] = { 1194 .type = MSR_FEATURE_WORD, 1195 .feat_names = { 1196 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1197 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1198 NULL, NULL, NULL, NULL, 1199 NULL, NULL, NULL, NULL, 1200 NULL, NULL, NULL, NULL, 1201 NULL, NULL, NULL, NULL, 1202 NULL, NULL, NULL, NULL, 1203 NULL, NULL, NULL, NULL, 1204 }, 1205 .msr = { 1206 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1207 } 1208 }, 1209 1210 [FEAT_VMX_EXIT_CTLS] = { 1211 .type = MSR_FEATURE_WORD, 1212 /* 1213 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1214 * the LM CPUID bit. 1215 */ 1216 .feat_names = { 1217 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1218 NULL, NULL, NULL, NULL, 1219 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1220 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1221 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1222 "vmx-exit-save-efer", "vmx-exit-load-efer", 1223 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1224 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 }, 1227 .msr = { 1228 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1229 } 1230 }, 1231 1232 [FEAT_VMX_ENTRY_CTLS] = { 1233 .type = MSR_FEATURE_WORD, 1234 .feat_names = { 1235 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1236 NULL, NULL, NULL, NULL, 1237 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1238 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1239 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 }, 1244 .msr = { 1245 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1246 } 1247 }, 1248 1249 [FEAT_VMX_MISC] = { 1250 .type = MSR_FEATURE_WORD, 1251 .feat_names = { 1252 NULL, NULL, NULL, NULL, 1253 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1254 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1255 NULL, NULL, NULL, NULL, 1256 NULL, NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1260 }, 1261 .msr = { 1262 .index = MSR_IA32_VMX_MISC, 1263 } 1264 }, 1265 1266 [FEAT_VMX_EPT_VPID_CAPS] = { 1267 .type = MSR_FEATURE_WORD, 1268 .feat_names = { 1269 "vmx-ept-execonly", NULL, NULL, NULL, 1270 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1271 NULL, NULL, NULL, NULL, 1272 NULL, NULL, NULL, NULL, 1273 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1274 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1275 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1276 NULL, NULL, NULL, NULL, 1277 "vmx-invvpid", NULL, NULL, NULL, 1278 NULL, NULL, NULL, NULL, 1279 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1280 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 }, 1287 .msr = { 1288 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1289 } 1290 }, 1291 1292 [FEAT_VMX_BASIC] = { 1293 .type = MSR_FEATURE_WORD, 1294 .feat_names = { 1295 [54] = "vmx-ins-outs", 1296 [55] = "vmx-true-ctls", 1297 }, 1298 .msr = { 1299 .index = MSR_IA32_VMX_BASIC, 1300 }, 1301 /* Just to be safe - we don't support setting the MSEG version field. */ 1302 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1303 }, 1304 1305 [FEAT_VMX_VMFUNC] = { 1306 .type = MSR_FEATURE_WORD, 1307 .feat_names = { 1308 [0] = "vmx-eptp-switching", 1309 }, 1310 .msr = { 1311 .index = MSR_IA32_VMX_VMFUNC, 1312 } 1313 }, 1314 1315 }; 1316 1317 typedef struct FeatureMask { 1318 FeatureWord index; 1319 uint64_t mask; 1320 } FeatureMask; 1321 1322 typedef struct FeatureDep { 1323 FeatureMask from, to; 1324 } FeatureDep; 1325 1326 static FeatureDep feature_dependencies[] = { 1327 { 1328 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1329 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1330 }, 1331 { 1332 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1333 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1334 }, 1335 { 1336 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1337 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1338 }, 1339 { 1340 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1341 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1342 }, 1343 { 1344 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1345 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1346 }, 1347 { 1348 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1349 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1350 }, 1351 { 1352 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1353 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1354 }, 1355 { 1356 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1357 .to = { FEAT_VMX_MISC, ~0ull }, 1358 }, 1359 { 1360 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1361 .to = { FEAT_VMX_BASIC, ~0ull }, 1362 }, 1363 { 1364 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1365 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1366 }, 1367 { 1368 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1369 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1370 }, 1371 { 1372 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1373 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1374 }, 1375 { 1376 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1377 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1378 }, 1379 { 1380 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1381 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1382 }, 1383 { 1384 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1385 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1386 }, 1387 { 1388 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1389 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1390 }, 1391 { 1392 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1393 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1394 }, 1395 { 1396 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1397 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1398 }, 1399 { 1400 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1401 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1402 }, 1403 { 1404 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1405 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1406 }, 1407 }; 1408 1409 typedef struct X86RegisterInfo32 { 1410 /* Name of register */ 1411 const char *name; 1412 /* QAPI enum value register */ 1413 X86CPURegister32 qapi_enum; 1414 } X86RegisterInfo32; 1415 1416 #define REGISTER(reg) \ 1417 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1418 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1419 REGISTER(EAX), 1420 REGISTER(ECX), 1421 REGISTER(EDX), 1422 REGISTER(EBX), 1423 REGISTER(ESP), 1424 REGISTER(EBP), 1425 REGISTER(ESI), 1426 REGISTER(EDI), 1427 }; 1428 #undef REGISTER 1429 1430 typedef struct ExtSaveArea { 1431 uint32_t feature, bits; 1432 uint32_t offset, size; 1433 } ExtSaveArea; 1434 1435 static const ExtSaveArea x86_ext_save_areas[] = { 1436 [XSTATE_FP_BIT] = { 1437 /* x87 FP state component is always enabled if XSAVE is supported */ 1438 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1439 /* x87 state is in the legacy region of the XSAVE area */ 1440 .offset = 0, 1441 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1442 }, 1443 [XSTATE_SSE_BIT] = { 1444 /* SSE state component is always enabled if XSAVE is supported */ 1445 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1446 /* SSE state is in the legacy region of the XSAVE area */ 1447 .offset = 0, 1448 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1449 }, 1450 [XSTATE_YMM_BIT] = 1451 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1452 .offset = offsetof(X86XSaveArea, avx_state), 1453 .size = sizeof(XSaveAVX) }, 1454 [XSTATE_BNDREGS_BIT] = 1455 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1456 .offset = offsetof(X86XSaveArea, bndreg_state), 1457 .size = sizeof(XSaveBNDREG) }, 1458 [XSTATE_BNDCSR_BIT] = 1459 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1460 .offset = offsetof(X86XSaveArea, bndcsr_state), 1461 .size = sizeof(XSaveBNDCSR) }, 1462 [XSTATE_OPMASK_BIT] = 1463 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1464 .offset = offsetof(X86XSaveArea, opmask_state), 1465 .size = sizeof(XSaveOpmask) }, 1466 [XSTATE_ZMM_Hi256_BIT] = 1467 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1468 .offset = offsetof(X86XSaveArea, zmm_hi256_state), 1469 .size = sizeof(XSaveZMM_Hi256) }, 1470 [XSTATE_Hi16_ZMM_BIT] = 1471 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1472 .offset = offsetof(X86XSaveArea, hi16_zmm_state), 1473 .size = sizeof(XSaveHi16_ZMM) }, 1474 [XSTATE_PKRU_BIT] = 1475 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1476 .offset = offsetof(X86XSaveArea, pkru_state), 1477 .size = sizeof(XSavePKRU) }, 1478 }; 1479 1480 static uint32_t xsave_area_size(uint64_t mask) 1481 { 1482 int i; 1483 uint64_t ret = 0; 1484 1485 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1486 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 1487 if ((mask >> i) & 1) { 1488 ret = MAX(ret, esa->offset + esa->size); 1489 } 1490 } 1491 return ret; 1492 } 1493 1494 static inline bool accel_uses_host_cpuid(void) 1495 { 1496 return kvm_enabled() || hvf_enabled(); 1497 } 1498 1499 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) 1500 { 1501 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 | 1502 cpu->env.features[FEAT_XSAVE_COMP_LO]; 1503 } 1504 1505 const char *get_register_name_32(unsigned int reg) 1506 { 1507 if (reg >= CPU_NB_REGS32) { 1508 return NULL; 1509 } 1510 return x86_reg_info_32[reg].name; 1511 } 1512 1513 /* 1514 * Returns the set of feature flags that are supported and migratable by 1515 * QEMU, for a given FeatureWord. 1516 */ 1517 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1518 { 1519 FeatureWordInfo *wi = &feature_word_info[w]; 1520 uint64_t r = 0; 1521 int i; 1522 1523 for (i = 0; i < 64; i++) { 1524 uint64_t f = 1ULL << i; 1525 1526 /* If the feature name is known, it is implicitly considered migratable, 1527 * unless it is explicitly set in unmigratable_flags */ 1528 if ((wi->migratable_flags & f) || 1529 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1530 r |= f; 1531 } 1532 } 1533 return r; 1534 } 1535 1536 void host_cpuid(uint32_t function, uint32_t count, 1537 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1538 { 1539 uint32_t vec[4]; 1540 1541 #ifdef __x86_64__ 1542 asm volatile("cpuid" 1543 : "=a"(vec[0]), "=b"(vec[1]), 1544 "=c"(vec[2]), "=d"(vec[3]) 1545 : "0"(function), "c"(count) : "cc"); 1546 #elif defined(__i386__) 1547 asm volatile("pusha \n\t" 1548 "cpuid \n\t" 1549 "mov %%eax, 0(%2) \n\t" 1550 "mov %%ebx, 4(%2) \n\t" 1551 "mov %%ecx, 8(%2) \n\t" 1552 "mov %%edx, 12(%2) \n\t" 1553 "popa" 1554 : : "a"(function), "c"(count), "S"(vec) 1555 : "memory", "cc"); 1556 #else 1557 abort(); 1558 #endif 1559 1560 if (eax) 1561 *eax = vec[0]; 1562 if (ebx) 1563 *ebx = vec[1]; 1564 if (ecx) 1565 *ecx = vec[2]; 1566 if (edx) 1567 *edx = vec[3]; 1568 } 1569 1570 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping) 1571 { 1572 uint32_t eax, ebx, ecx, edx; 1573 1574 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); 1575 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); 1576 1577 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); 1578 if (family) { 1579 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); 1580 } 1581 if (model) { 1582 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); 1583 } 1584 if (stepping) { 1585 *stepping = eax & 0x0F; 1586 } 1587 } 1588 1589 /* CPU class name definitions: */ 1590 1591 /* Return type name for a given CPU model name 1592 * Caller is responsible for freeing the returned string. 1593 */ 1594 static char *x86_cpu_type_name(const char *model_name) 1595 { 1596 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1597 } 1598 1599 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1600 { 1601 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1602 return object_class_by_name(typename); 1603 } 1604 1605 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1606 { 1607 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1608 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1609 return g_strndup(class_name, 1610 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1611 } 1612 1613 typedef struct PropValue { 1614 const char *prop, *value; 1615 } PropValue; 1616 1617 typedef struct X86CPUVersionDefinition { 1618 X86CPUVersion version; 1619 const char *alias; 1620 const char *note; 1621 PropValue *props; 1622 } X86CPUVersionDefinition; 1623 1624 /* Base definition for a CPU model */ 1625 typedef struct X86CPUDefinition { 1626 const char *name; 1627 uint32_t level; 1628 uint32_t xlevel; 1629 /* vendor is zero-terminated, 12 character ASCII string */ 1630 char vendor[CPUID_VENDOR_SZ + 1]; 1631 int family; 1632 int model; 1633 int stepping; 1634 FeatureWordArray features; 1635 const char *model_id; 1636 CPUCaches *cache_info; 1637 1638 /* Use AMD EPYC encoding for apic id */ 1639 bool use_epyc_apic_id_encoding; 1640 1641 /* 1642 * Definitions for alternative versions of CPU model. 1643 * List is terminated by item with version == 0. 1644 * If NULL, version 1 will be registered automatically. 1645 */ 1646 const X86CPUVersionDefinition *versions; 1647 } X86CPUDefinition; 1648 1649 /* Reference to a specific CPU model version */ 1650 struct X86CPUModel { 1651 /* Base CPU definition */ 1652 X86CPUDefinition *cpudef; 1653 /* CPU model version */ 1654 X86CPUVersion version; 1655 const char *note; 1656 /* 1657 * If true, this is an alias CPU model. 1658 * This matters only for "-cpu help" and query-cpu-definitions 1659 */ 1660 bool is_alias; 1661 }; 1662 1663 /* Get full model name for CPU version */ 1664 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef, 1665 X86CPUVersion version) 1666 { 1667 assert(version > 0); 1668 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1669 } 1670 1671 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def) 1672 { 1673 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1674 static const X86CPUVersionDefinition default_version_list[] = { 1675 { 1 }, 1676 { /* end of list */ } 1677 }; 1678 1679 return def->versions ?: default_version_list; 1680 } 1681 1682 bool cpu_x86_use_epyc_apic_id_encoding(const char *cpu_type) 1683 { 1684 X86CPUClass *xcc = X86_CPU_CLASS(object_class_by_name(cpu_type)); 1685 1686 assert(xcc); 1687 if (xcc->model && xcc->model->cpudef) { 1688 return xcc->model->cpudef->use_epyc_apic_id_encoding; 1689 } else { 1690 return false; 1691 } 1692 } 1693 1694 static CPUCaches epyc_cache_info = { 1695 .l1d_cache = &(CPUCacheInfo) { 1696 .type = DATA_CACHE, 1697 .level = 1, 1698 .size = 32 * KiB, 1699 .line_size = 64, 1700 .associativity = 8, 1701 .partitions = 1, 1702 .sets = 64, 1703 .lines_per_tag = 1, 1704 .self_init = 1, 1705 .no_invd_sharing = true, 1706 }, 1707 .l1i_cache = &(CPUCacheInfo) { 1708 .type = INSTRUCTION_CACHE, 1709 .level = 1, 1710 .size = 64 * KiB, 1711 .line_size = 64, 1712 .associativity = 4, 1713 .partitions = 1, 1714 .sets = 256, 1715 .lines_per_tag = 1, 1716 .self_init = 1, 1717 .no_invd_sharing = true, 1718 }, 1719 .l2_cache = &(CPUCacheInfo) { 1720 .type = UNIFIED_CACHE, 1721 .level = 2, 1722 .size = 512 * KiB, 1723 .line_size = 64, 1724 .associativity = 8, 1725 .partitions = 1, 1726 .sets = 1024, 1727 .lines_per_tag = 1, 1728 }, 1729 .l3_cache = &(CPUCacheInfo) { 1730 .type = UNIFIED_CACHE, 1731 .level = 3, 1732 .size = 8 * MiB, 1733 .line_size = 64, 1734 .associativity = 16, 1735 .partitions = 1, 1736 .sets = 8192, 1737 .lines_per_tag = 1, 1738 .self_init = true, 1739 .inclusive = true, 1740 .complex_indexing = true, 1741 }, 1742 }; 1743 1744 static CPUCaches epyc_rome_cache_info = { 1745 .l1d_cache = &(CPUCacheInfo) { 1746 .type = DATA_CACHE, 1747 .level = 1, 1748 .size = 32 * KiB, 1749 .line_size = 64, 1750 .associativity = 8, 1751 .partitions = 1, 1752 .sets = 64, 1753 .lines_per_tag = 1, 1754 .self_init = 1, 1755 .no_invd_sharing = true, 1756 }, 1757 .l1i_cache = &(CPUCacheInfo) { 1758 .type = INSTRUCTION_CACHE, 1759 .level = 1, 1760 .size = 32 * KiB, 1761 .line_size = 64, 1762 .associativity = 8, 1763 .partitions = 1, 1764 .sets = 64, 1765 .lines_per_tag = 1, 1766 .self_init = 1, 1767 .no_invd_sharing = true, 1768 }, 1769 .l2_cache = &(CPUCacheInfo) { 1770 .type = UNIFIED_CACHE, 1771 .level = 2, 1772 .size = 512 * KiB, 1773 .line_size = 64, 1774 .associativity = 8, 1775 .partitions = 1, 1776 .sets = 1024, 1777 .lines_per_tag = 1, 1778 }, 1779 .l3_cache = &(CPUCacheInfo) { 1780 .type = UNIFIED_CACHE, 1781 .level = 3, 1782 .size = 16 * MiB, 1783 .line_size = 64, 1784 .associativity = 16, 1785 .partitions = 1, 1786 .sets = 16384, 1787 .lines_per_tag = 1, 1788 .self_init = true, 1789 .inclusive = true, 1790 .complex_indexing = true, 1791 }, 1792 }; 1793 1794 /* The following VMX features are not supported by KVM and are left out in the 1795 * CPU definitions: 1796 * 1797 * Dual-monitor support (all processors) 1798 * Entry to SMM 1799 * Deactivate dual-monitor treatment 1800 * Number of CR3-target values 1801 * Shutdown activity state 1802 * Wait-for-SIPI activity state 1803 * PAUSE-loop exiting (Westmere and newer) 1804 * EPT-violation #VE (Broadwell and newer) 1805 * Inject event with insn length=0 (Skylake and newer) 1806 * Conceal non-root operation from PT 1807 * Conceal VM exits from PT 1808 * Conceal VM entries from PT 1809 * Enable ENCLS exiting 1810 * Mode-based execute control (XS/XU) 1811 s TSC scaling (Skylake Server and newer) 1812 * GPA translation for PT (IceLake and newer) 1813 * User wait and pause 1814 * ENCLV exiting 1815 * Load IA32_RTIT_CTL 1816 * Clear IA32_RTIT_CTL 1817 * Advanced VM-exit information for EPT violations 1818 * Sub-page write permissions 1819 * PT in VMX operation 1820 */ 1821 1822 static X86CPUDefinition builtin_x86_defs[] = { 1823 { 1824 .name = "qemu64", 1825 .level = 0xd, 1826 .vendor = CPUID_VENDOR_AMD, 1827 .family = 6, 1828 .model = 6, 1829 .stepping = 3, 1830 .features[FEAT_1_EDX] = 1831 PPRO_FEATURES | 1832 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1833 CPUID_PSE36, 1834 .features[FEAT_1_ECX] = 1835 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1836 .features[FEAT_8000_0001_EDX] = 1837 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1838 .features[FEAT_8000_0001_ECX] = 1839 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 1840 .xlevel = 0x8000000A, 1841 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1842 }, 1843 { 1844 .name = "phenom", 1845 .level = 5, 1846 .vendor = CPUID_VENDOR_AMD, 1847 .family = 16, 1848 .model = 2, 1849 .stepping = 3, 1850 /* Missing: CPUID_HT */ 1851 .features[FEAT_1_EDX] = 1852 PPRO_FEATURES | 1853 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1854 CPUID_PSE36 | CPUID_VME, 1855 .features[FEAT_1_ECX] = 1856 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 1857 CPUID_EXT_POPCNT, 1858 .features[FEAT_8000_0001_EDX] = 1859 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 1860 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 1861 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 1862 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1863 CPUID_EXT3_CR8LEG, 1864 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1865 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 1866 .features[FEAT_8000_0001_ECX] = 1867 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 1868 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 1869 /* Missing: CPUID_SVM_LBRV */ 1870 .features[FEAT_SVM] = 1871 CPUID_SVM_NPT, 1872 .xlevel = 0x8000001A, 1873 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 1874 }, 1875 { 1876 .name = "core2duo", 1877 .level = 10, 1878 .vendor = CPUID_VENDOR_INTEL, 1879 .family = 6, 1880 .model = 15, 1881 .stepping = 11, 1882 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1883 .features[FEAT_1_EDX] = 1884 PPRO_FEATURES | 1885 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1886 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 1887 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 1888 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1889 .features[FEAT_1_ECX] = 1890 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1891 CPUID_EXT_CX16, 1892 .features[FEAT_8000_0001_EDX] = 1893 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1894 .features[FEAT_8000_0001_ECX] = 1895 CPUID_EXT3_LAHF_LM, 1896 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 1897 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1898 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1899 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1900 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1901 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 1902 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1903 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1904 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1905 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1906 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1907 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1908 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1909 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 1910 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 1911 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 1912 .features[FEAT_VMX_SECONDARY_CTLS] = 1913 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 1914 .xlevel = 0x80000008, 1915 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 1916 }, 1917 { 1918 .name = "kvm64", 1919 .level = 0xd, 1920 .vendor = CPUID_VENDOR_INTEL, 1921 .family = 15, 1922 .model = 6, 1923 .stepping = 1, 1924 /* Missing: CPUID_HT */ 1925 .features[FEAT_1_EDX] = 1926 PPRO_FEATURES | CPUID_VME | 1927 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1928 CPUID_PSE36, 1929 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 1930 .features[FEAT_1_ECX] = 1931 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1932 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 1933 .features[FEAT_8000_0001_EDX] = 1934 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1935 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1936 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 1937 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1938 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 1939 .features[FEAT_8000_0001_ECX] = 1940 0, 1941 /* VMX features from Cedar Mill/Prescott */ 1942 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1943 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1944 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1945 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1946 VMX_PIN_BASED_NMI_EXITING, 1947 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1948 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1949 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1950 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1951 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1952 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1953 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1954 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 1955 .xlevel = 0x80000008, 1956 .model_id = "Common KVM processor" 1957 }, 1958 { 1959 .name = "qemu32", 1960 .level = 4, 1961 .vendor = CPUID_VENDOR_INTEL, 1962 .family = 6, 1963 .model = 6, 1964 .stepping = 3, 1965 .features[FEAT_1_EDX] = 1966 PPRO_FEATURES, 1967 .features[FEAT_1_ECX] = 1968 CPUID_EXT_SSE3, 1969 .xlevel = 0x80000004, 1970 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1971 }, 1972 { 1973 .name = "kvm32", 1974 .level = 5, 1975 .vendor = CPUID_VENDOR_INTEL, 1976 .family = 15, 1977 .model = 6, 1978 .stepping = 1, 1979 .features[FEAT_1_EDX] = 1980 PPRO_FEATURES | CPUID_VME | 1981 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 1982 .features[FEAT_1_ECX] = 1983 CPUID_EXT_SSE3, 1984 .features[FEAT_8000_0001_ECX] = 1985 0, 1986 /* VMX features from Yonah */ 1987 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1988 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1989 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1990 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1991 VMX_PIN_BASED_NMI_EXITING, 1992 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1993 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1994 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1995 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1996 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 1997 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 1998 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 1999 .xlevel = 0x80000008, 2000 .model_id = "Common 32-bit KVM processor" 2001 }, 2002 { 2003 .name = "coreduo", 2004 .level = 10, 2005 .vendor = CPUID_VENDOR_INTEL, 2006 .family = 6, 2007 .model = 14, 2008 .stepping = 8, 2009 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2010 .features[FEAT_1_EDX] = 2011 PPRO_FEATURES | CPUID_VME | 2012 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2013 CPUID_SS, 2014 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2015 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2016 .features[FEAT_1_ECX] = 2017 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2018 .features[FEAT_8000_0001_EDX] = 2019 CPUID_EXT2_NX, 2020 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2021 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2022 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2023 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2024 VMX_PIN_BASED_NMI_EXITING, 2025 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2026 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2027 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2028 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2029 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2030 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2031 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2032 .xlevel = 0x80000008, 2033 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2034 }, 2035 { 2036 .name = "486", 2037 .level = 1, 2038 .vendor = CPUID_VENDOR_INTEL, 2039 .family = 4, 2040 .model = 8, 2041 .stepping = 0, 2042 .features[FEAT_1_EDX] = 2043 I486_FEATURES, 2044 .xlevel = 0, 2045 .model_id = "", 2046 }, 2047 { 2048 .name = "pentium", 2049 .level = 1, 2050 .vendor = CPUID_VENDOR_INTEL, 2051 .family = 5, 2052 .model = 4, 2053 .stepping = 3, 2054 .features[FEAT_1_EDX] = 2055 PENTIUM_FEATURES, 2056 .xlevel = 0, 2057 .model_id = "", 2058 }, 2059 { 2060 .name = "pentium2", 2061 .level = 2, 2062 .vendor = CPUID_VENDOR_INTEL, 2063 .family = 6, 2064 .model = 5, 2065 .stepping = 2, 2066 .features[FEAT_1_EDX] = 2067 PENTIUM2_FEATURES, 2068 .xlevel = 0, 2069 .model_id = "", 2070 }, 2071 { 2072 .name = "pentium3", 2073 .level = 3, 2074 .vendor = CPUID_VENDOR_INTEL, 2075 .family = 6, 2076 .model = 7, 2077 .stepping = 3, 2078 .features[FEAT_1_EDX] = 2079 PENTIUM3_FEATURES, 2080 .xlevel = 0, 2081 .model_id = "", 2082 }, 2083 { 2084 .name = "athlon", 2085 .level = 2, 2086 .vendor = CPUID_VENDOR_AMD, 2087 .family = 6, 2088 .model = 2, 2089 .stepping = 3, 2090 .features[FEAT_1_EDX] = 2091 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2092 CPUID_MCA, 2093 .features[FEAT_8000_0001_EDX] = 2094 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2095 .xlevel = 0x80000008, 2096 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2097 }, 2098 { 2099 .name = "n270", 2100 .level = 10, 2101 .vendor = CPUID_VENDOR_INTEL, 2102 .family = 6, 2103 .model = 28, 2104 .stepping = 2, 2105 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2106 .features[FEAT_1_EDX] = 2107 PPRO_FEATURES | 2108 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2109 CPUID_ACPI | CPUID_SS, 2110 /* Some CPUs got no CPUID_SEP */ 2111 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2112 * CPUID_EXT_XTPR */ 2113 .features[FEAT_1_ECX] = 2114 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2115 CPUID_EXT_MOVBE, 2116 .features[FEAT_8000_0001_EDX] = 2117 CPUID_EXT2_NX, 2118 .features[FEAT_8000_0001_ECX] = 2119 CPUID_EXT3_LAHF_LM, 2120 .xlevel = 0x80000008, 2121 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2122 }, 2123 { 2124 .name = "Conroe", 2125 .level = 10, 2126 .vendor = CPUID_VENDOR_INTEL, 2127 .family = 6, 2128 .model = 15, 2129 .stepping = 3, 2130 .features[FEAT_1_EDX] = 2131 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2132 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2133 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2134 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2135 CPUID_DE | CPUID_FP87, 2136 .features[FEAT_1_ECX] = 2137 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2138 .features[FEAT_8000_0001_EDX] = 2139 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2140 .features[FEAT_8000_0001_ECX] = 2141 CPUID_EXT3_LAHF_LM, 2142 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2143 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2144 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2145 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2146 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2147 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2148 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2149 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2150 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2151 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2152 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2153 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2154 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2155 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2156 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2157 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2158 .features[FEAT_VMX_SECONDARY_CTLS] = 2159 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2160 .xlevel = 0x80000008, 2161 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2162 }, 2163 { 2164 .name = "Penryn", 2165 .level = 10, 2166 .vendor = CPUID_VENDOR_INTEL, 2167 .family = 6, 2168 .model = 23, 2169 .stepping = 3, 2170 .features[FEAT_1_EDX] = 2171 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2172 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2173 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2174 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2175 CPUID_DE | CPUID_FP87, 2176 .features[FEAT_1_ECX] = 2177 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2178 CPUID_EXT_SSE3, 2179 .features[FEAT_8000_0001_EDX] = 2180 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2181 .features[FEAT_8000_0001_ECX] = 2182 CPUID_EXT3_LAHF_LM, 2183 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2184 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2185 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2186 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2187 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2188 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2189 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2190 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2191 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2192 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2193 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2194 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2195 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2196 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2197 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2198 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2199 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2200 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2201 .features[FEAT_VMX_SECONDARY_CTLS] = 2202 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2203 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2204 .xlevel = 0x80000008, 2205 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2206 }, 2207 { 2208 .name = "Nehalem", 2209 .level = 11, 2210 .vendor = CPUID_VENDOR_INTEL, 2211 .family = 6, 2212 .model = 26, 2213 .stepping = 3, 2214 .features[FEAT_1_EDX] = 2215 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2216 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2217 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2218 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2219 CPUID_DE | CPUID_FP87, 2220 .features[FEAT_1_ECX] = 2221 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2222 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2223 .features[FEAT_8000_0001_EDX] = 2224 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2225 .features[FEAT_8000_0001_ECX] = 2226 CPUID_EXT3_LAHF_LM, 2227 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2228 MSR_VMX_BASIC_TRUE_CTLS, 2229 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2230 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2231 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2232 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2233 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2234 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2235 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2236 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2237 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2238 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2239 .features[FEAT_VMX_EXIT_CTLS] = 2240 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2241 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2242 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2243 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2244 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2245 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2246 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2247 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2248 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2249 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2250 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2251 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2252 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2253 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2254 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2255 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2256 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2257 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2258 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2259 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2260 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2261 .features[FEAT_VMX_SECONDARY_CTLS] = 2262 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2263 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2264 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2265 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2266 VMX_SECONDARY_EXEC_ENABLE_VPID, 2267 .xlevel = 0x80000008, 2268 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2269 .versions = (X86CPUVersionDefinition[]) { 2270 { .version = 1 }, 2271 { 2272 .version = 2, 2273 .alias = "Nehalem-IBRS", 2274 .props = (PropValue[]) { 2275 { "spec-ctrl", "on" }, 2276 { "model-id", 2277 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2278 { /* end of list */ } 2279 } 2280 }, 2281 { /* end of list */ } 2282 } 2283 }, 2284 { 2285 .name = "Westmere", 2286 .level = 11, 2287 .vendor = CPUID_VENDOR_INTEL, 2288 .family = 6, 2289 .model = 44, 2290 .stepping = 1, 2291 .features[FEAT_1_EDX] = 2292 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2293 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2294 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2295 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2296 CPUID_DE | CPUID_FP87, 2297 .features[FEAT_1_ECX] = 2298 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2299 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2300 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2301 .features[FEAT_8000_0001_EDX] = 2302 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2303 .features[FEAT_8000_0001_ECX] = 2304 CPUID_EXT3_LAHF_LM, 2305 .features[FEAT_6_EAX] = 2306 CPUID_6_EAX_ARAT, 2307 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2308 MSR_VMX_BASIC_TRUE_CTLS, 2309 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2310 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2311 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2312 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2313 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2314 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2315 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2316 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2317 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2318 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2319 .features[FEAT_VMX_EXIT_CTLS] = 2320 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2321 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2322 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2323 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2324 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2325 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2326 MSR_VMX_MISC_STORE_LMA, 2327 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2328 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2329 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2330 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2331 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2332 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2333 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2334 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2335 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2336 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2337 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2338 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2339 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2340 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2341 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2342 .features[FEAT_VMX_SECONDARY_CTLS] = 2343 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2344 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2345 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2346 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2347 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2348 .xlevel = 0x80000008, 2349 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2350 .versions = (X86CPUVersionDefinition[]) { 2351 { .version = 1 }, 2352 { 2353 .version = 2, 2354 .alias = "Westmere-IBRS", 2355 .props = (PropValue[]) { 2356 { "spec-ctrl", "on" }, 2357 { "model-id", 2358 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2359 { /* end of list */ } 2360 } 2361 }, 2362 { /* end of list */ } 2363 } 2364 }, 2365 { 2366 .name = "SandyBridge", 2367 .level = 0xd, 2368 .vendor = CPUID_VENDOR_INTEL, 2369 .family = 6, 2370 .model = 42, 2371 .stepping = 1, 2372 .features[FEAT_1_EDX] = 2373 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2374 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2375 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2376 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2377 CPUID_DE | CPUID_FP87, 2378 .features[FEAT_1_ECX] = 2379 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2380 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2381 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2382 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2383 CPUID_EXT_SSE3, 2384 .features[FEAT_8000_0001_EDX] = 2385 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2386 CPUID_EXT2_SYSCALL, 2387 .features[FEAT_8000_0001_ECX] = 2388 CPUID_EXT3_LAHF_LM, 2389 .features[FEAT_XSAVE] = 2390 CPUID_XSAVE_XSAVEOPT, 2391 .features[FEAT_6_EAX] = 2392 CPUID_6_EAX_ARAT, 2393 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2394 MSR_VMX_BASIC_TRUE_CTLS, 2395 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2396 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2397 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2398 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2399 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2400 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2401 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2402 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2403 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2404 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2405 .features[FEAT_VMX_EXIT_CTLS] = 2406 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2407 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2408 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2409 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2410 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2411 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2412 MSR_VMX_MISC_STORE_LMA, 2413 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2414 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2415 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2416 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2417 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2418 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2419 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2420 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2421 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2422 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2423 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2424 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2425 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2426 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2427 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2428 .features[FEAT_VMX_SECONDARY_CTLS] = 2429 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2430 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2431 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2432 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2433 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2434 .xlevel = 0x80000008, 2435 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2436 .versions = (X86CPUVersionDefinition[]) { 2437 { .version = 1 }, 2438 { 2439 .version = 2, 2440 .alias = "SandyBridge-IBRS", 2441 .props = (PropValue[]) { 2442 { "spec-ctrl", "on" }, 2443 { "model-id", 2444 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2445 { /* end of list */ } 2446 } 2447 }, 2448 { /* end of list */ } 2449 } 2450 }, 2451 { 2452 .name = "IvyBridge", 2453 .level = 0xd, 2454 .vendor = CPUID_VENDOR_INTEL, 2455 .family = 6, 2456 .model = 58, 2457 .stepping = 9, 2458 .features[FEAT_1_EDX] = 2459 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2460 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2461 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2462 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2463 CPUID_DE | CPUID_FP87, 2464 .features[FEAT_1_ECX] = 2465 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2466 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2467 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2468 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2469 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2470 .features[FEAT_7_0_EBX] = 2471 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2472 CPUID_7_0_EBX_ERMS, 2473 .features[FEAT_8000_0001_EDX] = 2474 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2475 CPUID_EXT2_SYSCALL, 2476 .features[FEAT_8000_0001_ECX] = 2477 CPUID_EXT3_LAHF_LM, 2478 .features[FEAT_XSAVE] = 2479 CPUID_XSAVE_XSAVEOPT, 2480 .features[FEAT_6_EAX] = 2481 CPUID_6_EAX_ARAT, 2482 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2483 MSR_VMX_BASIC_TRUE_CTLS, 2484 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2485 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2486 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2487 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2488 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2489 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2490 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2491 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2492 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2493 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2494 .features[FEAT_VMX_EXIT_CTLS] = 2495 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2496 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2497 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2498 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2499 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2500 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2501 MSR_VMX_MISC_STORE_LMA, 2502 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2503 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2504 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2505 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2506 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2507 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2508 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2509 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2510 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2511 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2512 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2513 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2514 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2515 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2516 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2517 .features[FEAT_VMX_SECONDARY_CTLS] = 2518 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2519 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2520 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2521 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2522 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2523 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2524 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2525 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2526 .xlevel = 0x80000008, 2527 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2528 .versions = (X86CPUVersionDefinition[]) { 2529 { .version = 1 }, 2530 { 2531 .version = 2, 2532 .alias = "IvyBridge-IBRS", 2533 .props = (PropValue[]) { 2534 { "spec-ctrl", "on" }, 2535 { "model-id", 2536 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2537 { /* end of list */ } 2538 } 2539 }, 2540 { /* end of list */ } 2541 } 2542 }, 2543 { 2544 .name = "Haswell", 2545 .level = 0xd, 2546 .vendor = CPUID_VENDOR_INTEL, 2547 .family = 6, 2548 .model = 60, 2549 .stepping = 4, 2550 .features[FEAT_1_EDX] = 2551 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2552 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2553 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2554 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2555 CPUID_DE | CPUID_FP87, 2556 .features[FEAT_1_ECX] = 2557 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2558 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2559 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2560 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2561 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2562 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2563 .features[FEAT_8000_0001_EDX] = 2564 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2565 CPUID_EXT2_SYSCALL, 2566 .features[FEAT_8000_0001_ECX] = 2567 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2568 .features[FEAT_7_0_EBX] = 2569 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2570 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2571 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2572 CPUID_7_0_EBX_RTM, 2573 .features[FEAT_XSAVE] = 2574 CPUID_XSAVE_XSAVEOPT, 2575 .features[FEAT_6_EAX] = 2576 CPUID_6_EAX_ARAT, 2577 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2578 MSR_VMX_BASIC_TRUE_CTLS, 2579 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2580 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2581 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2582 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2583 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2584 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2585 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2586 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2587 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2588 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2589 .features[FEAT_VMX_EXIT_CTLS] = 2590 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2591 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2592 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2593 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2594 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2595 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2596 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2597 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2598 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2599 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2600 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2601 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2602 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2603 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2604 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2605 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2606 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2607 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2608 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2609 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2610 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2611 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2612 .features[FEAT_VMX_SECONDARY_CTLS] = 2613 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2614 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2615 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2616 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2617 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2618 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2619 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2620 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2621 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2622 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2623 .xlevel = 0x80000008, 2624 .model_id = "Intel Core Processor (Haswell)", 2625 .versions = (X86CPUVersionDefinition[]) { 2626 { .version = 1 }, 2627 { 2628 .version = 2, 2629 .alias = "Haswell-noTSX", 2630 .props = (PropValue[]) { 2631 { "hle", "off" }, 2632 { "rtm", "off" }, 2633 { "stepping", "1" }, 2634 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2635 { /* end of list */ } 2636 }, 2637 }, 2638 { 2639 .version = 3, 2640 .alias = "Haswell-IBRS", 2641 .props = (PropValue[]) { 2642 /* Restore TSX features removed by -v2 above */ 2643 { "hle", "on" }, 2644 { "rtm", "on" }, 2645 /* 2646 * Haswell and Haswell-IBRS had stepping=4 in 2647 * QEMU 4.0 and older 2648 */ 2649 { "stepping", "4" }, 2650 { "spec-ctrl", "on" }, 2651 { "model-id", 2652 "Intel Core Processor (Haswell, IBRS)" }, 2653 { /* end of list */ } 2654 } 2655 }, 2656 { 2657 .version = 4, 2658 .alias = "Haswell-noTSX-IBRS", 2659 .props = (PropValue[]) { 2660 { "hle", "off" }, 2661 { "rtm", "off" }, 2662 /* spec-ctrl was already enabled by -v3 above */ 2663 { "stepping", "1" }, 2664 { "model-id", 2665 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2666 { /* end of list */ } 2667 } 2668 }, 2669 { /* end of list */ } 2670 } 2671 }, 2672 { 2673 .name = "Broadwell", 2674 .level = 0xd, 2675 .vendor = CPUID_VENDOR_INTEL, 2676 .family = 6, 2677 .model = 61, 2678 .stepping = 2, 2679 .features[FEAT_1_EDX] = 2680 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2681 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2682 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2683 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2684 CPUID_DE | CPUID_FP87, 2685 .features[FEAT_1_ECX] = 2686 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2687 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2688 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2689 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2690 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2691 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2692 .features[FEAT_8000_0001_EDX] = 2693 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2694 CPUID_EXT2_SYSCALL, 2695 .features[FEAT_8000_0001_ECX] = 2696 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2697 .features[FEAT_7_0_EBX] = 2698 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2699 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2700 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2701 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2702 CPUID_7_0_EBX_SMAP, 2703 .features[FEAT_XSAVE] = 2704 CPUID_XSAVE_XSAVEOPT, 2705 .features[FEAT_6_EAX] = 2706 CPUID_6_EAX_ARAT, 2707 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2708 MSR_VMX_BASIC_TRUE_CTLS, 2709 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2710 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2711 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2712 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2713 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2714 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2715 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2716 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2717 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2718 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2719 .features[FEAT_VMX_EXIT_CTLS] = 2720 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2721 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2722 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2723 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2724 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2725 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2726 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2727 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2728 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2729 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2730 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2731 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2732 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2733 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2734 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2735 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2736 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2737 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2738 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2739 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2740 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2741 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2742 .features[FEAT_VMX_SECONDARY_CTLS] = 2743 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2744 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2745 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2746 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2747 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2748 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2749 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2750 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2751 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2752 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2753 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2754 .xlevel = 0x80000008, 2755 .model_id = "Intel Core Processor (Broadwell)", 2756 .versions = (X86CPUVersionDefinition[]) { 2757 { .version = 1 }, 2758 { 2759 .version = 2, 2760 .alias = "Broadwell-noTSX", 2761 .props = (PropValue[]) { 2762 { "hle", "off" }, 2763 { "rtm", "off" }, 2764 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 2765 { /* end of list */ } 2766 }, 2767 }, 2768 { 2769 .version = 3, 2770 .alias = "Broadwell-IBRS", 2771 .props = (PropValue[]) { 2772 /* Restore TSX features removed by -v2 above */ 2773 { "hle", "on" }, 2774 { "rtm", "on" }, 2775 { "spec-ctrl", "on" }, 2776 { "model-id", 2777 "Intel Core Processor (Broadwell, IBRS)" }, 2778 { /* end of list */ } 2779 } 2780 }, 2781 { 2782 .version = 4, 2783 .alias = "Broadwell-noTSX-IBRS", 2784 .props = (PropValue[]) { 2785 { "hle", "off" }, 2786 { "rtm", "off" }, 2787 /* spec-ctrl was already enabled by -v3 above */ 2788 { "model-id", 2789 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 2790 { /* end of list */ } 2791 } 2792 }, 2793 { /* end of list */ } 2794 } 2795 }, 2796 { 2797 .name = "Skylake-Client", 2798 .level = 0xd, 2799 .vendor = CPUID_VENDOR_INTEL, 2800 .family = 6, 2801 .model = 94, 2802 .stepping = 3, 2803 .features[FEAT_1_EDX] = 2804 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2805 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2806 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2807 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2808 CPUID_DE | CPUID_FP87, 2809 .features[FEAT_1_ECX] = 2810 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2811 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2812 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2813 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2814 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2815 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2816 .features[FEAT_8000_0001_EDX] = 2817 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2818 CPUID_EXT2_SYSCALL, 2819 .features[FEAT_8000_0001_ECX] = 2820 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2821 .features[FEAT_7_0_EBX] = 2822 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2823 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2824 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2825 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2826 CPUID_7_0_EBX_SMAP, 2827 /* Missing: XSAVES (not supported by some Linux versions, 2828 * including v4.1 to v4.12). 2829 * KVM doesn't yet expose any XSAVES state save component, 2830 * and the only one defined in Skylake (processor tracing) 2831 * probably will block migration anyway. 2832 */ 2833 .features[FEAT_XSAVE] = 2834 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2835 CPUID_XSAVE_XGETBV1, 2836 .features[FEAT_6_EAX] = 2837 CPUID_6_EAX_ARAT, 2838 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2839 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2840 MSR_VMX_BASIC_TRUE_CTLS, 2841 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2842 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2843 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2844 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2845 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2846 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2847 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2848 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2849 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2850 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2851 .features[FEAT_VMX_EXIT_CTLS] = 2852 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2853 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2854 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2855 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2856 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2857 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2858 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2859 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2860 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2861 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2862 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2863 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2864 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2865 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2866 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2867 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2868 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2869 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2870 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2871 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2872 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2873 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2874 .features[FEAT_VMX_SECONDARY_CTLS] = 2875 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2876 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2877 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2878 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2879 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2880 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2881 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2882 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2883 .xlevel = 0x80000008, 2884 .model_id = "Intel Core Processor (Skylake)", 2885 .versions = (X86CPUVersionDefinition[]) { 2886 { .version = 1 }, 2887 { 2888 .version = 2, 2889 .alias = "Skylake-Client-IBRS", 2890 .props = (PropValue[]) { 2891 { "spec-ctrl", "on" }, 2892 { "model-id", 2893 "Intel Core Processor (Skylake, IBRS)" }, 2894 { /* end of list */ } 2895 } 2896 }, 2897 { 2898 .version = 3, 2899 .alias = "Skylake-Client-noTSX-IBRS", 2900 .props = (PropValue[]) { 2901 { "hle", "off" }, 2902 { "rtm", "off" }, 2903 { "model-id", 2904 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 2905 { /* end of list */ } 2906 } 2907 }, 2908 { /* end of list */ } 2909 } 2910 }, 2911 { 2912 .name = "Skylake-Server", 2913 .level = 0xd, 2914 .vendor = CPUID_VENDOR_INTEL, 2915 .family = 6, 2916 .model = 85, 2917 .stepping = 4, 2918 .features[FEAT_1_EDX] = 2919 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2920 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2921 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2922 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2923 CPUID_DE | CPUID_FP87, 2924 .features[FEAT_1_ECX] = 2925 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2926 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2927 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2928 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2929 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2930 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2931 .features[FEAT_8000_0001_EDX] = 2932 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2933 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2934 .features[FEAT_8000_0001_ECX] = 2935 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2936 .features[FEAT_7_0_EBX] = 2937 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2938 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2939 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2940 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2941 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2942 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2943 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2944 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2945 .features[FEAT_7_0_ECX] = 2946 CPUID_7_0_ECX_PKU, 2947 /* Missing: XSAVES (not supported by some Linux versions, 2948 * including v4.1 to v4.12). 2949 * KVM doesn't yet expose any XSAVES state save component, 2950 * and the only one defined in Skylake (processor tracing) 2951 * probably will block migration anyway. 2952 */ 2953 .features[FEAT_XSAVE] = 2954 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2955 CPUID_XSAVE_XGETBV1, 2956 .features[FEAT_6_EAX] = 2957 CPUID_6_EAX_ARAT, 2958 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2959 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2960 MSR_VMX_BASIC_TRUE_CTLS, 2961 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2962 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2963 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2964 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2965 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2966 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2967 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2968 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2969 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2970 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2971 .features[FEAT_VMX_EXIT_CTLS] = 2972 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2973 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2974 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2975 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2976 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2977 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2978 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2979 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2980 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2981 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2982 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2983 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2984 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2985 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2986 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2987 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2988 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2989 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2990 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2991 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2992 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2993 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2994 .features[FEAT_VMX_SECONDARY_CTLS] = 2995 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2996 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2997 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2998 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2999 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3000 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3001 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3002 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3003 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3004 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3005 .xlevel = 0x80000008, 3006 .model_id = "Intel Xeon Processor (Skylake)", 3007 .versions = (X86CPUVersionDefinition[]) { 3008 { .version = 1 }, 3009 { 3010 .version = 2, 3011 .alias = "Skylake-Server-IBRS", 3012 .props = (PropValue[]) { 3013 /* clflushopt was not added to Skylake-Server-IBRS */ 3014 /* TODO: add -v3 including clflushopt */ 3015 { "clflushopt", "off" }, 3016 { "spec-ctrl", "on" }, 3017 { "model-id", 3018 "Intel Xeon Processor (Skylake, IBRS)" }, 3019 { /* end of list */ } 3020 } 3021 }, 3022 { 3023 .version = 3, 3024 .alias = "Skylake-Server-noTSX-IBRS", 3025 .props = (PropValue[]) { 3026 { "hle", "off" }, 3027 { "rtm", "off" }, 3028 { "model-id", 3029 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3030 { /* end of list */ } 3031 } 3032 }, 3033 { /* end of list */ } 3034 } 3035 }, 3036 { 3037 .name = "Cascadelake-Server", 3038 .level = 0xd, 3039 .vendor = CPUID_VENDOR_INTEL, 3040 .family = 6, 3041 .model = 85, 3042 .stepping = 6, 3043 .features[FEAT_1_EDX] = 3044 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3045 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3046 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3047 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3048 CPUID_DE | CPUID_FP87, 3049 .features[FEAT_1_ECX] = 3050 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3051 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3052 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3053 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3054 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3055 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3056 .features[FEAT_8000_0001_EDX] = 3057 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3058 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3059 .features[FEAT_8000_0001_ECX] = 3060 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3061 .features[FEAT_7_0_EBX] = 3062 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3063 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3064 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3065 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3066 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3067 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3068 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3069 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3070 .features[FEAT_7_0_ECX] = 3071 CPUID_7_0_ECX_PKU | 3072 CPUID_7_0_ECX_AVX512VNNI, 3073 .features[FEAT_7_0_EDX] = 3074 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3075 /* Missing: XSAVES (not supported by some Linux versions, 3076 * including v4.1 to v4.12). 3077 * KVM doesn't yet expose any XSAVES state save component, 3078 * and the only one defined in Skylake (processor tracing) 3079 * probably will block migration anyway. 3080 */ 3081 .features[FEAT_XSAVE] = 3082 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3083 CPUID_XSAVE_XGETBV1, 3084 .features[FEAT_6_EAX] = 3085 CPUID_6_EAX_ARAT, 3086 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3087 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3088 MSR_VMX_BASIC_TRUE_CTLS, 3089 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3090 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3091 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3092 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3093 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3094 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3095 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3096 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3097 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3098 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3099 .features[FEAT_VMX_EXIT_CTLS] = 3100 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3101 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3102 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3103 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3104 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3105 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3106 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3107 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3108 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3109 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3110 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3111 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3112 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3113 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3114 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3115 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3116 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3117 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3118 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3119 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3120 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3121 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3122 .features[FEAT_VMX_SECONDARY_CTLS] = 3123 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3124 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3125 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3126 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3127 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3128 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3129 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3130 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3131 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3132 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3133 .xlevel = 0x80000008, 3134 .model_id = "Intel Xeon Processor (Cascadelake)", 3135 .versions = (X86CPUVersionDefinition[]) { 3136 { .version = 1 }, 3137 { .version = 2, 3138 .note = "ARCH_CAPABILITIES", 3139 .props = (PropValue[]) { 3140 { "arch-capabilities", "on" }, 3141 { "rdctl-no", "on" }, 3142 { "ibrs-all", "on" }, 3143 { "skip-l1dfl-vmentry", "on" }, 3144 { "mds-no", "on" }, 3145 { /* end of list */ } 3146 }, 3147 }, 3148 { .version = 3, 3149 .alias = "Cascadelake-Server-noTSX", 3150 .note = "ARCH_CAPABILITIES, no TSX", 3151 .props = (PropValue[]) { 3152 { "hle", "off" }, 3153 { "rtm", "off" }, 3154 { /* end of list */ } 3155 }, 3156 }, 3157 { /* end of list */ } 3158 } 3159 }, 3160 { 3161 .name = "Cooperlake", 3162 .level = 0xd, 3163 .vendor = CPUID_VENDOR_INTEL, 3164 .family = 6, 3165 .model = 85, 3166 .stepping = 10, 3167 .features[FEAT_1_EDX] = 3168 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3169 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3170 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3171 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3172 CPUID_DE | CPUID_FP87, 3173 .features[FEAT_1_ECX] = 3174 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3175 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3176 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3177 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3178 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3179 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3180 .features[FEAT_8000_0001_EDX] = 3181 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3182 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3183 .features[FEAT_8000_0001_ECX] = 3184 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3185 .features[FEAT_7_0_EBX] = 3186 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3187 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3188 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3189 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3190 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3191 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3192 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3193 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3194 .features[FEAT_7_0_ECX] = 3195 CPUID_7_0_ECX_PKU | 3196 CPUID_7_0_ECX_AVX512VNNI, 3197 .features[FEAT_7_0_EDX] = 3198 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3199 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3200 .features[FEAT_ARCH_CAPABILITIES] = 3201 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3202 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3203 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3204 .features[FEAT_7_1_EAX] = 3205 CPUID_7_1_EAX_AVX512_BF16, 3206 /* 3207 * Missing: XSAVES (not supported by some Linux versions, 3208 * including v4.1 to v4.12). 3209 * KVM doesn't yet expose any XSAVES state save component, 3210 * and the only one defined in Skylake (processor tracing) 3211 * probably will block migration anyway. 3212 */ 3213 .features[FEAT_XSAVE] = 3214 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3215 CPUID_XSAVE_XGETBV1, 3216 .features[FEAT_6_EAX] = 3217 CPUID_6_EAX_ARAT, 3218 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3219 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3220 MSR_VMX_BASIC_TRUE_CTLS, 3221 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3222 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3223 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3224 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3225 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3226 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3227 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3228 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3229 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3230 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3231 .features[FEAT_VMX_EXIT_CTLS] = 3232 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3233 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3234 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3235 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3236 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3237 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3238 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3239 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3240 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3241 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3242 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3243 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3244 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3245 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3246 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3247 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3248 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3249 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3250 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3251 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3252 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3253 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3254 .features[FEAT_VMX_SECONDARY_CTLS] = 3255 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3256 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3257 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3258 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3259 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3260 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3261 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3262 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3263 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3264 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3265 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3266 .xlevel = 0x80000008, 3267 .model_id = "Intel Xeon Processor (Cooperlake)", 3268 }, 3269 { 3270 .name = "Icelake-Client", 3271 .level = 0xd, 3272 .vendor = CPUID_VENDOR_INTEL, 3273 .family = 6, 3274 .model = 126, 3275 .stepping = 0, 3276 .features[FEAT_1_EDX] = 3277 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3278 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3279 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3280 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3281 CPUID_DE | CPUID_FP87, 3282 .features[FEAT_1_ECX] = 3283 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3284 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3285 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3286 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3287 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3288 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3289 .features[FEAT_8000_0001_EDX] = 3290 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3291 CPUID_EXT2_SYSCALL, 3292 .features[FEAT_8000_0001_ECX] = 3293 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3294 .features[FEAT_8000_0008_EBX] = 3295 CPUID_8000_0008_EBX_WBNOINVD, 3296 .features[FEAT_7_0_EBX] = 3297 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3298 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3299 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3300 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3301 CPUID_7_0_EBX_SMAP, 3302 .features[FEAT_7_0_ECX] = 3303 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3304 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3305 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3306 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3307 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3308 .features[FEAT_7_0_EDX] = 3309 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3310 /* Missing: XSAVES (not supported by some Linux versions, 3311 * including v4.1 to v4.12). 3312 * KVM doesn't yet expose any XSAVES state save component, 3313 * and the only one defined in Skylake (processor tracing) 3314 * probably will block migration anyway. 3315 */ 3316 .features[FEAT_XSAVE] = 3317 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3318 CPUID_XSAVE_XGETBV1, 3319 .features[FEAT_6_EAX] = 3320 CPUID_6_EAX_ARAT, 3321 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3322 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3323 MSR_VMX_BASIC_TRUE_CTLS, 3324 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3325 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3326 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3327 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3328 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3329 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3330 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3331 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3332 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3333 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3334 .features[FEAT_VMX_EXIT_CTLS] = 3335 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3336 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3337 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3338 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3339 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3340 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3341 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3342 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3343 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3344 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3345 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3346 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3347 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3348 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3349 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3350 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3351 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3352 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3353 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3354 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3355 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3356 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3357 .features[FEAT_VMX_SECONDARY_CTLS] = 3358 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3359 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3360 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3361 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3362 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3363 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3364 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3365 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3366 .xlevel = 0x80000008, 3367 .model_id = "Intel Core Processor (Icelake)", 3368 .versions = (X86CPUVersionDefinition[]) { 3369 { .version = 1 }, 3370 { 3371 .version = 2, 3372 .note = "no TSX", 3373 .alias = "Icelake-Client-noTSX", 3374 .props = (PropValue[]) { 3375 { "hle", "off" }, 3376 { "rtm", "off" }, 3377 { /* end of list */ } 3378 }, 3379 }, 3380 { /* end of list */ } 3381 } 3382 }, 3383 { 3384 .name = "Icelake-Server", 3385 .level = 0xd, 3386 .vendor = CPUID_VENDOR_INTEL, 3387 .family = 6, 3388 .model = 134, 3389 .stepping = 0, 3390 .features[FEAT_1_EDX] = 3391 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3392 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3393 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3394 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3395 CPUID_DE | CPUID_FP87, 3396 .features[FEAT_1_ECX] = 3397 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3398 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3399 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3400 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3401 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3402 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3403 .features[FEAT_8000_0001_EDX] = 3404 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3405 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3406 .features[FEAT_8000_0001_ECX] = 3407 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3408 .features[FEAT_8000_0008_EBX] = 3409 CPUID_8000_0008_EBX_WBNOINVD, 3410 .features[FEAT_7_0_EBX] = 3411 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3412 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3413 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3414 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3415 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3416 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3417 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3418 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3419 .features[FEAT_7_0_ECX] = 3420 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3421 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3422 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3423 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3424 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3425 .features[FEAT_7_0_EDX] = 3426 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3427 /* Missing: XSAVES (not supported by some Linux versions, 3428 * including v4.1 to v4.12). 3429 * KVM doesn't yet expose any XSAVES state save component, 3430 * and the only one defined in Skylake (processor tracing) 3431 * probably will block migration anyway. 3432 */ 3433 .features[FEAT_XSAVE] = 3434 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3435 CPUID_XSAVE_XGETBV1, 3436 .features[FEAT_6_EAX] = 3437 CPUID_6_EAX_ARAT, 3438 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3439 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3440 MSR_VMX_BASIC_TRUE_CTLS, 3441 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3442 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3443 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3444 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3445 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3446 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3447 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3448 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3449 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3450 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3451 .features[FEAT_VMX_EXIT_CTLS] = 3452 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3453 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3454 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3455 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3456 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3457 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3458 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3459 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3460 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3461 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3462 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3463 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3464 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3465 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3466 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3467 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3468 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3469 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3470 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3471 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3472 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3473 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3474 .features[FEAT_VMX_SECONDARY_CTLS] = 3475 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3476 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3477 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3478 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3479 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3480 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3481 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3482 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3483 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3484 .xlevel = 0x80000008, 3485 .model_id = "Intel Xeon Processor (Icelake)", 3486 .versions = (X86CPUVersionDefinition[]) { 3487 { .version = 1 }, 3488 { 3489 .version = 2, 3490 .note = "no TSX", 3491 .alias = "Icelake-Server-noTSX", 3492 .props = (PropValue[]) { 3493 { "hle", "off" }, 3494 { "rtm", "off" }, 3495 { /* end of list */ } 3496 }, 3497 }, 3498 { 3499 .version = 3, 3500 .props = (PropValue[]) { 3501 { "arch-capabilities", "on" }, 3502 { "rdctl-no", "on" }, 3503 { "ibrs-all", "on" }, 3504 { "skip-l1dfl-vmentry", "on" }, 3505 { "mds-no", "on" }, 3506 { "pschange-mc-no", "on" }, 3507 { "taa-no", "on" }, 3508 { /* end of list */ } 3509 }, 3510 }, 3511 { /* end of list */ } 3512 } 3513 }, 3514 { 3515 .name = "Denverton", 3516 .level = 21, 3517 .vendor = CPUID_VENDOR_INTEL, 3518 .family = 6, 3519 .model = 95, 3520 .stepping = 1, 3521 .features[FEAT_1_EDX] = 3522 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3523 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3524 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3525 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3526 CPUID_SSE | CPUID_SSE2, 3527 .features[FEAT_1_ECX] = 3528 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3529 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3530 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3531 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3532 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3533 .features[FEAT_8000_0001_EDX] = 3534 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3535 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3536 .features[FEAT_8000_0001_ECX] = 3537 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3538 .features[FEAT_7_0_EBX] = 3539 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3540 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3541 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3542 .features[FEAT_7_0_EDX] = 3543 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3544 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3545 /* 3546 * Missing: XSAVES (not supported by some Linux versions, 3547 * including v4.1 to v4.12). 3548 * KVM doesn't yet expose any XSAVES state save component, 3549 * and the only one defined in Skylake (processor tracing) 3550 * probably will block migration anyway. 3551 */ 3552 .features[FEAT_XSAVE] = 3553 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3554 .features[FEAT_6_EAX] = 3555 CPUID_6_EAX_ARAT, 3556 .features[FEAT_ARCH_CAPABILITIES] = 3557 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3558 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3559 MSR_VMX_BASIC_TRUE_CTLS, 3560 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3561 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3562 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3563 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3564 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3565 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3566 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3567 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3568 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3569 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3570 .features[FEAT_VMX_EXIT_CTLS] = 3571 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3572 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3573 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3574 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3575 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3576 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3577 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3578 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3579 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3580 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3581 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3582 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3583 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3584 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3585 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3586 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3587 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3588 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3589 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3590 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3591 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3592 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3593 .features[FEAT_VMX_SECONDARY_CTLS] = 3594 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3595 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3596 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3597 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3598 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3599 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3600 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3601 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3602 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3603 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3604 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3605 .xlevel = 0x80000008, 3606 .model_id = "Intel Atom Processor (Denverton)", 3607 .versions = (X86CPUVersionDefinition[]) { 3608 { .version = 1 }, 3609 { 3610 .version = 2, 3611 .note = "no MPX, no MONITOR", 3612 .props = (PropValue[]) { 3613 { "monitor", "off" }, 3614 { "mpx", "off" }, 3615 { /* end of list */ }, 3616 }, 3617 }, 3618 { /* end of list */ }, 3619 }, 3620 }, 3621 { 3622 .name = "Snowridge", 3623 .level = 27, 3624 .vendor = CPUID_VENDOR_INTEL, 3625 .family = 6, 3626 .model = 134, 3627 .stepping = 1, 3628 .features[FEAT_1_EDX] = 3629 /* missing: CPUID_PN CPUID_IA64 */ 3630 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3631 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 3632 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 3633 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 3634 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3635 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 3636 CPUID_MMX | 3637 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 3638 .features[FEAT_1_ECX] = 3639 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3640 CPUID_EXT_SSSE3 | 3641 CPUID_EXT_CX16 | 3642 CPUID_EXT_SSE41 | 3643 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3644 CPUID_EXT_POPCNT | 3645 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 3646 CPUID_EXT_RDRAND, 3647 .features[FEAT_8000_0001_EDX] = 3648 CPUID_EXT2_SYSCALL | 3649 CPUID_EXT2_NX | 3650 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3651 CPUID_EXT2_LM, 3652 .features[FEAT_8000_0001_ECX] = 3653 CPUID_EXT3_LAHF_LM | 3654 CPUID_EXT3_3DNOWPREFETCH, 3655 .features[FEAT_7_0_EBX] = 3656 CPUID_7_0_EBX_FSGSBASE | 3657 CPUID_7_0_EBX_SMEP | 3658 CPUID_7_0_EBX_ERMS | 3659 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 3660 CPUID_7_0_EBX_RDSEED | 3661 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3662 CPUID_7_0_EBX_CLWB | 3663 CPUID_7_0_EBX_SHA_NI, 3664 .features[FEAT_7_0_ECX] = 3665 CPUID_7_0_ECX_UMIP | 3666 /* missing bit 5 */ 3667 CPUID_7_0_ECX_GFNI | 3668 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 3669 CPUID_7_0_ECX_MOVDIR64B, 3670 .features[FEAT_7_0_EDX] = 3671 CPUID_7_0_EDX_SPEC_CTRL | 3672 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 3673 CPUID_7_0_EDX_CORE_CAPABILITY, 3674 .features[FEAT_CORE_CAPABILITY] = 3675 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 3676 /* 3677 * Missing: XSAVES (not supported by some Linux versions, 3678 * including v4.1 to v4.12). 3679 * KVM doesn't yet expose any XSAVES state save component, 3680 * and the only one defined in Skylake (processor tracing) 3681 * probably will block migration anyway. 3682 */ 3683 .features[FEAT_XSAVE] = 3684 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3685 CPUID_XSAVE_XGETBV1, 3686 .features[FEAT_6_EAX] = 3687 CPUID_6_EAX_ARAT, 3688 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3689 MSR_VMX_BASIC_TRUE_CTLS, 3690 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3691 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3692 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3693 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3694 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3695 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3696 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3697 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3698 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3699 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3700 .features[FEAT_VMX_EXIT_CTLS] = 3701 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3702 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3703 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3704 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3705 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3706 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3707 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3708 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3709 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3710 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3711 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3712 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3713 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3714 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3715 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3716 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3717 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3718 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3719 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3720 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3721 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3722 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3723 .features[FEAT_VMX_SECONDARY_CTLS] = 3724 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3725 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3726 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3727 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3728 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3729 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3730 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3731 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3732 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3733 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3734 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3735 .xlevel = 0x80000008, 3736 .model_id = "Intel Atom Processor (SnowRidge)", 3737 .versions = (X86CPUVersionDefinition[]) { 3738 { .version = 1 }, 3739 { 3740 .version = 2, 3741 .props = (PropValue[]) { 3742 { "mpx", "off" }, 3743 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 3744 { /* end of list */ }, 3745 }, 3746 }, 3747 { /* end of list */ }, 3748 }, 3749 }, 3750 { 3751 .name = "KnightsMill", 3752 .level = 0xd, 3753 .vendor = CPUID_VENDOR_INTEL, 3754 .family = 6, 3755 .model = 133, 3756 .stepping = 0, 3757 .features[FEAT_1_EDX] = 3758 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 3759 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 3760 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 3761 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 3762 CPUID_PSE | CPUID_DE | CPUID_FP87, 3763 .features[FEAT_1_ECX] = 3764 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3765 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3766 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3767 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3768 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3769 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3770 .features[FEAT_8000_0001_EDX] = 3771 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3772 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3773 .features[FEAT_8000_0001_ECX] = 3774 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3775 .features[FEAT_7_0_EBX] = 3776 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3777 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 3778 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 3779 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 3780 CPUID_7_0_EBX_AVX512ER, 3781 .features[FEAT_7_0_ECX] = 3782 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3783 .features[FEAT_7_0_EDX] = 3784 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 3785 .features[FEAT_XSAVE] = 3786 CPUID_XSAVE_XSAVEOPT, 3787 .features[FEAT_6_EAX] = 3788 CPUID_6_EAX_ARAT, 3789 .xlevel = 0x80000008, 3790 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 3791 }, 3792 { 3793 .name = "Opteron_G1", 3794 .level = 5, 3795 .vendor = CPUID_VENDOR_AMD, 3796 .family = 15, 3797 .model = 6, 3798 .stepping = 1, 3799 .features[FEAT_1_EDX] = 3800 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3801 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3802 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3803 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3804 CPUID_DE | CPUID_FP87, 3805 .features[FEAT_1_ECX] = 3806 CPUID_EXT_SSE3, 3807 .features[FEAT_8000_0001_EDX] = 3808 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3809 .xlevel = 0x80000008, 3810 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 3811 }, 3812 { 3813 .name = "Opteron_G2", 3814 .level = 5, 3815 .vendor = CPUID_VENDOR_AMD, 3816 .family = 15, 3817 .model = 6, 3818 .stepping = 1, 3819 .features[FEAT_1_EDX] = 3820 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3821 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3822 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3823 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3824 CPUID_DE | CPUID_FP87, 3825 .features[FEAT_1_ECX] = 3826 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 3827 .features[FEAT_8000_0001_EDX] = 3828 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3829 .features[FEAT_8000_0001_ECX] = 3830 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3831 .xlevel = 0x80000008, 3832 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 3833 }, 3834 { 3835 .name = "Opteron_G3", 3836 .level = 5, 3837 .vendor = CPUID_VENDOR_AMD, 3838 .family = 16, 3839 .model = 2, 3840 .stepping = 3, 3841 .features[FEAT_1_EDX] = 3842 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3843 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3844 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3845 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3846 CPUID_DE | CPUID_FP87, 3847 .features[FEAT_1_ECX] = 3848 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 3849 CPUID_EXT_SSE3, 3850 .features[FEAT_8000_0001_EDX] = 3851 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 3852 CPUID_EXT2_RDTSCP, 3853 .features[FEAT_8000_0001_ECX] = 3854 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 3855 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3856 .xlevel = 0x80000008, 3857 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 3858 }, 3859 { 3860 .name = "Opteron_G4", 3861 .level = 0xd, 3862 .vendor = CPUID_VENDOR_AMD, 3863 .family = 21, 3864 .model = 1, 3865 .stepping = 2, 3866 .features[FEAT_1_EDX] = 3867 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3868 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3869 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3870 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3871 CPUID_DE | CPUID_FP87, 3872 .features[FEAT_1_ECX] = 3873 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3874 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3875 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3876 CPUID_EXT_SSE3, 3877 .features[FEAT_8000_0001_EDX] = 3878 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3879 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3880 .features[FEAT_8000_0001_ECX] = 3881 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3882 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3883 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3884 CPUID_EXT3_LAHF_LM, 3885 .features[FEAT_SVM] = 3886 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3887 /* no xsaveopt! */ 3888 .xlevel = 0x8000001A, 3889 .model_id = "AMD Opteron 62xx class CPU", 3890 }, 3891 { 3892 .name = "Opteron_G5", 3893 .level = 0xd, 3894 .vendor = CPUID_VENDOR_AMD, 3895 .family = 21, 3896 .model = 2, 3897 .stepping = 0, 3898 .features[FEAT_1_EDX] = 3899 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3900 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3901 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3902 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3903 CPUID_DE | CPUID_FP87, 3904 .features[FEAT_1_ECX] = 3905 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 3906 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 3907 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 3908 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3909 .features[FEAT_8000_0001_EDX] = 3910 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3911 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3912 .features[FEAT_8000_0001_ECX] = 3913 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3914 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3915 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3916 CPUID_EXT3_LAHF_LM, 3917 .features[FEAT_SVM] = 3918 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3919 /* no xsaveopt! */ 3920 .xlevel = 0x8000001A, 3921 .model_id = "AMD Opteron 63xx class CPU", 3922 }, 3923 { 3924 .name = "EPYC", 3925 .level = 0xd, 3926 .vendor = CPUID_VENDOR_AMD, 3927 .family = 23, 3928 .model = 1, 3929 .stepping = 2, 3930 .features[FEAT_1_EDX] = 3931 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 3932 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 3933 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 3934 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 3935 CPUID_VME | CPUID_FP87, 3936 .features[FEAT_1_ECX] = 3937 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 3938 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 3939 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3940 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 3941 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3942 .features[FEAT_8000_0001_EDX] = 3943 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 3944 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 3945 CPUID_EXT2_SYSCALL, 3946 .features[FEAT_8000_0001_ECX] = 3947 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 3948 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 3949 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 3950 CPUID_EXT3_TOPOEXT, 3951 .features[FEAT_7_0_EBX] = 3952 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3953 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 3954 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3955 CPUID_7_0_EBX_SHA_NI, 3956 .features[FEAT_XSAVE] = 3957 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3958 CPUID_XSAVE_XGETBV1, 3959 .features[FEAT_6_EAX] = 3960 CPUID_6_EAX_ARAT, 3961 .features[FEAT_SVM] = 3962 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3963 .xlevel = 0x8000001E, 3964 .model_id = "AMD EPYC Processor", 3965 .cache_info = &epyc_cache_info, 3966 .use_epyc_apic_id_encoding = 1, 3967 .versions = (X86CPUVersionDefinition[]) { 3968 { .version = 1 }, 3969 { 3970 .version = 2, 3971 .alias = "EPYC-IBPB", 3972 .props = (PropValue[]) { 3973 { "ibpb", "on" }, 3974 { "model-id", 3975 "AMD EPYC Processor (with IBPB)" }, 3976 { /* end of list */ } 3977 } 3978 }, 3979 { 3980 .version = 3, 3981 .props = (PropValue[]) { 3982 { "ibpb", "on" }, 3983 { "perfctr-core", "on" }, 3984 { "clzero", "on" }, 3985 { "xsaveerptr", "on" }, 3986 { "xsaves", "on" }, 3987 { "model-id", 3988 "AMD EPYC Processor" }, 3989 { /* end of list */ } 3990 } 3991 }, 3992 { /* end of list */ } 3993 } 3994 }, 3995 { 3996 .name = "Dhyana", 3997 .level = 0xd, 3998 .vendor = CPUID_VENDOR_HYGON, 3999 .family = 24, 4000 .model = 0, 4001 .stepping = 1, 4002 .features[FEAT_1_EDX] = 4003 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4004 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4005 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4006 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4007 CPUID_VME | CPUID_FP87, 4008 .features[FEAT_1_ECX] = 4009 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4010 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4011 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4012 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4013 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4014 .features[FEAT_8000_0001_EDX] = 4015 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4016 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4017 CPUID_EXT2_SYSCALL, 4018 .features[FEAT_8000_0001_ECX] = 4019 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4020 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4021 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4022 CPUID_EXT3_TOPOEXT, 4023 .features[FEAT_8000_0008_EBX] = 4024 CPUID_8000_0008_EBX_IBPB, 4025 .features[FEAT_7_0_EBX] = 4026 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4027 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4028 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4029 /* 4030 * Missing: XSAVES (not supported by some Linux versions, 4031 * including v4.1 to v4.12). 4032 * KVM doesn't yet expose any XSAVES state save component. 4033 */ 4034 .features[FEAT_XSAVE] = 4035 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4036 CPUID_XSAVE_XGETBV1, 4037 .features[FEAT_6_EAX] = 4038 CPUID_6_EAX_ARAT, 4039 .features[FEAT_SVM] = 4040 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4041 .xlevel = 0x8000001E, 4042 .model_id = "Hygon Dhyana Processor", 4043 .cache_info = &epyc_cache_info, 4044 }, 4045 { 4046 .name = "EPYC-Rome", 4047 .level = 0xd, 4048 .vendor = CPUID_VENDOR_AMD, 4049 .family = 23, 4050 .model = 49, 4051 .stepping = 0, 4052 .features[FEAT_1_EDX] = 4053 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4054 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4055 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4056 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4057 CPUID_VME | CPUID_FP87, 4058 .features[FEAT_1_ECX] = 4059 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4060 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4061 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4062 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4063 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4064 .features[FEAT_8000_0001_EDX] = 4065 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4066 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4067 CPUID_EXT2_SYSCALL, 4068 .features[FEAT_8000_0001_ECX] = 4069 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4070 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4071 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4072 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4073 .features[FEAT_8000_0008_EBX] = 4074 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4075 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4076 CPUID_8000_0008_EBX_STIBP, 4077 .features[FEAT_7_0_EBX] = 4078 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4079 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4080 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4081 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4082 .features[FEAT_7_0_ECX] = 4083 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4084 .features[FEAT_XSAVE] = 4085 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4086 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4087 .features[FEAT_6_EAX] = 4088 CPUID_6_EAX_ARAT, 4089 .features[FEAT_SVM] = 4090 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4091 .xlevel = 0x8000001E, 4092 .model_id = "AMD EPYC-Rome Processor", 4093 .cache_info = &epyc_rome_cache_info, 4094 .use_epyc_apic_id_encoding = 1, 4095 }, 4096 }; 4097 4098 /* KVM-specific features that are automatically added/removed 4099 * from all CPU models when KVM is enabled. 4100 */ 4101 static PropValue kvm_default_props[] = { 4102 { "kvmclock", "on" }, 4103 { "kvm-nopiodelay", "on" }, 4104 { "kvm-asyncpf", "on" }, 4105 { "kvm-steal-time", "on" }, 4106 { "kvm-pv-eoi", "on" }, 4107 { "kvmclock-stable-bit", "on" }, 4108 { "x2apic", "on" }, 4109 { "acpi", "off" }, 4110 { "monitor", "off" }, 4111 { "svm", "off" }, 4112 { NULL, NULL }, 4113 }; 4114 4115 /* TCG-specific defaults that override all CPU models when using TCG 4116 */ 4117 static PropValue tcg_default_props[] = { 4118 { "vme", "off" }, 4119 { NULL, NULL }, 4120 }; 4121 4122 4123 /* 4124 * We resolve CPU model aliases using -v1 when using "-machine 4125 * none", but this is just for compatibility while libvirt isn't 4126 * adapted to resolve CPU model versions before creating VMs. 4127 * See "Runnability guarantee of CPU models" at * qemu-deprecated.texi. 4128 */ 4129 X86CPUVersion default_cpu_version = 1; 4130 4131 void x86_cpu_set_default_version(X86CPUVersion version) 4132 { 4133 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4134 assert(version != CPU_VERSION_AUTO); 4135 default_cpu_version = version; 4136 } 4137 4138 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4139 { 4140 int v = 0; 4141 const X86CPUVersionDefinition *vdef = 4142 x86_cpu_def_get_versions(model->cpudef); 4143 while (vdef->version) { 4144 v = vdef->version; 4145 vdef++; 4146 } 4147 return v; 4148 } 4149 4150 /* Return the actual version being used for a specific CPU model */ 4151 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4152 { 4153 X86CPUVersion v = model->version; 4154 if (v == CPU_VERSION_AUTO) { 4155 v = default_cpu_version; 4156 } 4157 if (v == CPU_VERSION_LATEST) { 4158 return x86_cpu_model_last_version(model); 4159 } 4160 return v; 4161 } 4162 4163 void x86_cpu_change_kvm_default(const char *prop, const char *value) 4164 { 4165 PropValue *pv; 4166 for (pv = kvm_default_props; pv->prop; pv++) { 4167 if (!strcmp(pv->prop, prop)) { 4168 pv->value = value; 4169 break; 4170 } 4171 } 4172 4173 /* It is valid to call this function only for properties that 4174 * are already present in the kvm_default_props table. 4175 */ 4176 assert(pv->prop); 4177 } 4178 4179 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 4180 bool migratable_only); 4181 4182 static bool lmce_supported(void) 4183 { 4184 uint64_t mce_cap = 0; 4185 4186 #ifdef CONFIG_KVM 4187 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) { 4188 return false; 4189 } 4190 #endif 4191 4192 return !!(mce_cap & MCG_LMCE_P); 4193 } 4194 4195 #define CPUID_MODEL_ID_SZ 48 4196 4197 /** 4198 * cpu_x86_fill_model_id: 4199 * Get CPUID model ID string from host CPU. 4200 * 4201 * @str should have at least CPUID_MODEL_ID_SZ bytes 4202 * 4203 * The function does NOT add a null terminator to the string 4204 * automatically. 4205 */ 4206 static int cpu_x86_fill_model_id(char *str) 4207 { 4208 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; 4209 int i; 4210 4211 for (i = 0; i < 3; i++) { 4212 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); 4213 memcpy(str + i * 16 + 0, &eax, 4); 4214 memcpy(str + i * 16 + 4, &ebx, 4); 4215 memcpy(str + i * 16 + 8, &ecx, 4); 4216 memcpy(str + i * 16 + 12, &edx, 4); 4217 } 4218 return 0; 4219 } 4220 4221 static Property max_x86_cpu_properties[] = { 4222 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4223 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4224 DEFINE_PROP_END_OF_LIST() 4225 }; 4226 4227 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4228 { 4229 DeviceClass *dc = DEVICE_CLASS(oc); 4230 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4231 4232 xcc->ordering = 9; 4233 4234 xcc->model_description = 4235 "Enables all features supported by the accelerator in the current host"; 4236 4237 device_class_set_props(dc, max_x86_cpu_properties); 4238 } 4239 4240 static void max_x86_cpu_initfn(Object *obj) 4241 { 4242 X86CPU *cpu = X86_CPU(obj); 4243 CPUX86State *env = &cpu->env; 4244 KVMState *s = kvm_state; 4245 4246 /* We can't fill the features array here because we don't know yet if 4247 * "migratable" is true or false. 4248 */ 4249 cpu->max_features = true; 4250 4251 if (accel_uses_host_cpuid()) { 4252 char vendor[CPUID_VENDOR_SZ + 1] = { 0 }; 4253 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 }; 4254 int family, model, stepping; 4255 4256 host_vendor_fms(vendor, &family, &model, &stepping); 4257 cpu_x86_fill_model_id(model_id); 4258 4259 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort); 4260 object_property_set_int(OBJECT(cpu), family, "family", &error_abort); 4261 object_property_set_int(OBJECT(cpu), model, "model", &error_abort); 4262 object_property_set_int(OBJECT(cpu), stepping, "stepping", 4263 &error_abort); 4264 object_property_set_str(OBJECT(cpu), model_id, "model-id", 4265 &error_abort); 4266 4267 if (kvm_enabled()) { 4268 env->cpuid_min_level = 4269 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); 4270 env->cpuid_min_xlevel = 4271 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); 4272 env->cpuid_min_xlevel2 = 4273 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); 4274 } else { 4275 env->cpuid_min_level = 4276 hvf_get_supported_cpuid(0x0, 0, R_EAX); 4277 env->cpuid_min_xlevel = 4278 hvf_get_supported_cpuid(0x80000000, 0, R_EAX); 4279 env->cpuid_min_xlevel2 = 4280 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); 4281 } 4282 4283 if (lmce_supported()) { 4284 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort); 4285 } 4286 } else { 4287 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD, 4288 "vendor", &error_abort); 4289 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort); 4290 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort); 4291 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort); 4292 object_property_set_str(OBJECT(cpu), 4293 "QEMU TCG CPU version " QEMU_HW_VERSION, 4294 "model-id", &error_abort); 4295 } 4296 4297 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort); 4298 } 4299 4300 static const TypeInfo max_x86_cpu_type_info = { 4301 .name = X86_CPU_TYPE_NAME("max"), 4302 .parent = TYPE_X86_CPU, 4303 .instance_init = max_x86_cpu_initfn, 4304 .class_init = max_x86_cpu_class_init, 4305 }; 4306 4307 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 4308 static void host_x86_cpu_class_init(ObjectClass *oc, void *data) 4309 { 4310 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4311 4312 xcc->host_cpuid_required = true; 4313 xcc->ordering = 8; 4314 4315 #if defined(CONFIG_KVM) 4316 xcc->model_description = 4317 "KVM processor with all supported host features "; 4318 #elif defined(CONFIG_HVF) 4319 xcc->model_description = 4320 "HVF processor with all supported host features "; 4321 #endif 4322 } 4323 4324 static const TypeInfo host_x86_cpu_type_info = { 4325 .name = X86_CPU_TYPE_NAME("host"), 4326 .parent = X86_CPU_TYPE_NAME("max"), 4327 .class_init = host_x86_cpu_class_init, 4328 }; 4329 4330 #endif 4331 4332 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4333 { 4334 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4335 4336 switch (f->type) { 4337 case CPUID_FEATURE_WORD: 4338 { 4339 const char *reg = get_register_name_32(f->cpuid.reg); 4340 assert(reg); 4341 return g_strdup_printf("CPUID.%02XH:%s", 4342 f->cpuid.eax, reg); 4343 } 4344 case MSR_FEATURE_WORD: 4345 return g_strdup_printf("MSR(%02XH)", 4346 f->msr.index); 4347 } 4348 4349 return NULL; 4350 } 4351 4352 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4353 { 4354 FeatureWord w; 4355 4356 for (w = 0; w < FEATURE_WORDS; w++) { 4357 if (cpu->filtered_features[w]) { 4358 return true; 4359 } 4360 } 4361 4362 return false; 4363 } 4364 4365 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4366 const char *verbose_prefix) 4367 { 4368 CPUX86State *env = &cpu->env; 4369 FeatureWordInfo *f = &feature_word_info[w]; 4370 int i; 4371 4372 if (!cpu->force_features) { 4373 env->features[w] &= ~mask; 4374 } 4375 cpu->filtered_features[w] |= mask; 4376 4377 if (!verbose_prefix) { 4378 return; 4379 } 4380 4381 for (i = 0; i < 64; ++i) { 4382 if ((1ULL << i) & mask) { 4383 g_autofree char *feat_word_str = feature_word_description(f, i); 4384 warn_report("%s: %s%s%s [bit %d]", 4385 verbose_prefix, 4386 feat_word_str, 4387 f->feat_names[i] ? "." : "", 4388 f->feat_names[i] ? f->feat_names[i] : "", i); 4389 } 4390 } 4391 } 4392 4393 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4394 const char *name, void *opaque, 4395 Error **errp) 4396 { 4397 X86CPU *cpu = X86_CPU(obj); 4398 CPUX86State *env = &cpu->env; 4399 int64_t value; 4400 4401 value = (env->cpuid_version >> 8) & 0xf; 4402 if (value == 0xf) { 4403 value += (env->cpuid_version >> 20) & 0xff; 4404 } 4405 visit_type_int(v, name, &value, errp); 4406 } 4407 4408 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4409 const char *name, void *opaque, 4410 Error **errp) 4411 { 4412 X86CPU *cpu = X86_CPU(obj); 4413 CPUX86State *env = &cpu->env; 4414 const int64_t min = 0; 4415 const int64_t max = 0xff + 0xf; 4416 Error *local_err = NULL; 4417 int64_t value; 4418 4419 visit_type_int(v, name, &value, &local_err); 4420 if (local_err) { 4421 error_propagate(errp, local_err); 4422 return; 4423 } 4424 if (value < min || value > max) { 4425 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4426 name ? name : "null", value, min, max); 4427 return; 4428 } 4429 4430 env->cpuid_version &= ~0xff00f00; 4431 if (value > 0x0f) { 4432 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4433 } else { 4434 env->cpuid_version |= value << 8; 4435 } 4436 } 4437 4438 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4439 const char *name, void *opaque, 4440 Error **errp) 4441 { 4442 X86CPU *cpu = X86_CPU(obj); 4443 CPUX86State *env = &cpu->env; 4444 int64_t value; 4445 4446 value = (env->cpuid_version >> 4) & 0xf; 4447 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4448 visit_type_int(v, name, &value, errp); 4449 } 4450 4451 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4452 const char *name, void *opaque, 4453 Error **errp) 4454 { 4455 X86CPU *cpu = X86_CPU(obj); 4456 CPUX86State *env = &cpu->env; 4457 const int64_t min = 0; 4458 const int64_t max = 0xff; 4459 Error *local_err = NULL; 4460 int64_t value; 4461 4462 visit_type_int(v, name, &value, &local_err); 4463 if (local_err) { 4464 error_propagate(errp, local_err); 4465 return; 4466 } 4467 if (value < min || value > max) { 4468 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4469 name ? name : "null", value, min, max); 4470 return; 4471 } 4472 4473 env->cpuid_version &= ~0xf00f0; 4474 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4475 } 4476 4477 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4478 const char *name, void *opaque, 4479 Error **errp) 4480 { 4481 X86CPU *cpu = X86_CPU(obj); 4482 CPUX86State *env = &cpu->env; 4483 int64_t value; 4484 4485 value = env->cpuid_version & 0xf; 4486 visit_type_int(v, name, &value, errp); 4487 } 4488 4489 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4490 const char *name, void *opaque, 4491 Error **errp) 4492 { 4493 X86CPU *cpu = X86_CPU(obj); 4494 CPUX86State *env = &cpu->env; 4495 const int64_t min = 0; 4496 const int64_t max = 0xf; 4497 Error *local_err = NULL; 4498 int64_t value; 4499 4500 visit_type_int(v, name, &value, &local_err); 4501 if (local_err) { 4502 error_propagate(errp, local_err); 4503 return; 4504 } 4505 if (value < min || value > max) { 4506 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4507 name ? name : "null", value, min, max); 4508 return; 4509 } 4510 4511 env->cpuid_version &= ~0xf; 4512 env->cpuid_version |= value & 0xf; 4513 } 4514 4515 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 4516 { 4517 X86CPU *cpu = X86_CPU(obj); 4518 CPUX86State *env = &cpu->env; 4519 char *value; 4520 4521 value = g_malloc(CPUID_VENDOR_SZ + 1); 4522 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 4523 env->cpuid_vendor3); 4524 return value; 4525 } 4526 4527 static void x86_cpuid_set_vendor(Object *obj, const char *value, 4528 Error **errp) 4529 { 4530 X86CPU *cpu = X86_CPU(obj); 4531 CPUX86State *env = &cpu->env; 4532 int i; 4533 4534 if (strlen(value) != CPUID_VENDOR_SZ) { 4535 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 4536 return; 4537 } 4538 4539 env->cpuid_vendor1 = 0; 4540 env->cpuid_vendor2 = 0; 4541 env->cpuid_vendor3 = 0; 4542 for (i = 0; i < 4; i++) { 4543 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 4544 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 4545 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 4546 } 4547 } 4548 4549 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 4550 { 4551 X86CPU *cpu = X86_CPU(obj); 4552 CPUX86State *env = &cpu->env; 4553 char *value; 4554 int i; 4555 4556 value = g_malloc(48 + 1); 4557 for (i = 0; i < 48; i++) { 4558 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 4559 } 4560 value[48] = '\0'; 4561 return value; 4562 } 4563 4564 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 4565 Error **errp) 4566 { 4567 X86CPU *cpu = X86_CPU(obj); 4568 CPUX86State *env = &cpu->env; 4569 int c, len, i; 4570 4571 if (model_id == NULL) { 4572 model_id = ""; 4573 } 4574 len = strlen(model_id); 4575 memset(env->cpuid_model, 0, 48); 4576 for (i = 0; i < 48; i++) { 4577 if (i >= len) { 4578 c = '\0'; 4579 } else { 4580 c = (uint8_t)model_id[i]; 4581 } 4582 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 4583 } 4584 } 4585 4586 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 4587 void *opaque, Error **errp) 4588 { 4589 X86CPU *cpu = X86_CPU(obj); 4590 int64_t value; 4591 4592 value = cpu->env.tsc_khz * 1000; 4593 visit_type_int(v, name, &value, errp); 4594 } 4595 4596 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 4597 void *opaque, Error **errp) 4598 { 4599 X86CPU *cpu = X86_CPU(obj); 4600 const int64_t min = 0; 4601 const int64_t max = INT64_MAX; 4602 Error *local_err = NULL; 4603 int64_t value; 4604 4605 visit_type_int(v, name, &value, &local_err); 4606 if (local_err) { 4607 error_propagate(errp, local_err); 4608 return; 4609 } 4610 if (value < min || value > max) { 4611 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4612 name ? name : "null", value, min, max); 4613 return; 4614 } 4615 4616 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 4617 } 4618 4619 /* Generic getter for "feature-words" and "filtered-features" properties */ 4620 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 4621 const char *name, void *opaque, 4622 Error **errp) 4623 { 4624 uint64_t *array = (uint64_t *)opaque; 4625 FeatureWord w; 4626 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 4627 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 4628 X86CPUFeatureWordInfoList *list = NULL; 4629 4630 for (w = 0; w < FEATURE_WORDS; w++) { 4631 FeatureWordInfo *wi = &feature_word_info[w]; 4632 /* 4633 * We didn't have MSR features when "feature-words" was 4634 * introduced. Therefore skipped other type entries. 4635 */ 4636 if (wi->type != CPUID_FEATURE_WORD) { 4637 continue; 4638 } 4639 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 4640 qwi->cpuid_input_eax = wi->cpuid.eax; 4641 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 4642 qwi->cpuid_input_ecx = wi->cpuid.ecx; 4643 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 4644 qwi->features = array[w]; 4645 4646 /* List will be in reverse order, but order shouldn't matter */ 4647 list_entries[w].next = list; 4648 list_entries[w].value = &word_infos[w]; 4649 list = &list_entries[w]; 4650 } 4651 4652 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 4653 } 4654 4655 /* Convert all '_' in a feature string option name to '-', to make feature 4656 * name conform to QOM property naming rule, which uses '-' instead of '_'. 4657 */ 4658 static inline void feat2prop(char *s) 4659 { 4660 while ((s = strchr(s, '_'))) { 4661 *s = '-'; 4662 } 4663 } 4664 4665 /* Return the feature property name for a feature flag bit */ 4666 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 4667 { 4668 const char *name; 4669 /* XSAVE components are automatically enabled by other features, 4670 * so return the original feature name instead 4671 */ 4672 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) { 4673 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr; 4674 4675 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 4676 x86_ext_save_areas[comp].bits) { 4677 w = x86_ext_save_areas[comp].feature; 4678 bitnr = ctz32(x86_ext_save_areas[comp].bits); 4679 } 4680 } 4681 4682 assert(bitnr < 64); 4683 assert(w < FEATURE_WORDS); 4684 name = feature_word_info[w].feat_names[bitnr]; 4685 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 4686 return name; 4687 } 4688 4689 /* Compatibily hack to maintain legacy +-feat semantic, 4690 * where +-feat overwrites any feature set by 4691 * feat=on|feat even if the later is parsed after +-feat 4692 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 4693 */ 4694 static GList *plus_features, *minus_features; 4695 4696 static gint compare_string(gconstpointer a, gconstpointer b) 4697 { 4698 return g_strcmp0(a, b); 4699 } 4700 4701 /* Parse "+feature,-feature,feature=foo" CPU feature string 4702 */ 4703 static void x86_cpu_parse_featurestr(const char *typename, char *features, 4704 Error **errp) 4705 { 4706 char *featurestr; /* Single 'key=value" string being parsed */ 4707 static bool cpu_globals_initialized; 4708 bool ambiguous = false; 4709 4710 if (cpu_globals_initialized) { 4711 return; 4712 } 4713 cpu_globals_initialized = true; 4714 4715 if (!features) { 4716 return; 4717 } 4718 4719 for (featurestr = strtok(features, ","); 4720 featurestr; 4721 featurestr = strtok(NULL, ",")) { 4722 const char *name; 4723 const char *val = NULL; 4724 char *eq = NULL; 4725 char num[32]; 4726 GlobalProperty *prop; 4727 4728 /* Compatibility syntax: */ 4729 if (featurestr[0] == '+') { 4730 plus_features = g_list_append(plus_features, 4731 g_strdup(featurestr + 1)); 4732 continue; 4733 } else if (featurestr[0] == '-') { 4734 minus_features = g_list_append(minus_features, 4735 g_strdup(featurestr + 1)); 4736 continue; 4737 } 4738 4739 eq = strchr(featurestr, '='); 4740 if (eq) { 4741 *eq++ = 0; 4742 val = eq; 4743 } else { 4744 val = "on"; 4745 } 4746 4747 feat2prop(featurestr); 4748 name = featurestr; 4749 4750 if (g_list_find_custom(plus_features, name, compare_string)) { 4751 warn_report("Ambiguous CPU model string. " 4752 "Don't mix both \"+%s\" and \"%s=%s\"", 4753 name, name, val); 4754 ambiguous = true; 4755 } 4756 if (g_list_find_custom(minus_features, name, compare_string)) { 4757 warn_report("Ambiguous CPU model string. " 4758 "Don't mix both \"-%s\" and \"%s=%s\"", 4759 name, name, val); 4760 ambiguous = true; 4761 } 4762 4763 /* Special case: */ 4764 if (!strcmp(name, "tsc-freq")) { 4765 int ret; 4766 uint64_t tsc_freq; 4767 4768 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 4769 if (ret < 0 || tsc_freq > INT64_MAX) { 4770 error_setg(errp, "bad numerical value %s", val); 4771 return; 4772 } 4773 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 4774 val = num; 4775 name = "tsc-frequency"; 4776 } 4777 4778 prop = g_new0(typeof(*prop), 1); 4779 prop->driver = typename; 4780 prop->property = g_strdup(name); 4781 prop->value = g_strdup(val); 4782 qdev_prop_register_global(prop); 4783 } 4784 4785 if (ambiguous) { 4786 warn_report("Compatibility of ambiguous CPU model " 4787 "strings won't be kept on future QEMU versions"); 4788 } 4789 } 4790 4791 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp); 4792 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 4793 4794 /* Build a list with the name of all features on a feature word array */ 4795 static void x86_cpu_list_feature_names(FeatureWordArray features, 4796 strList **feat_names) 4797 { 4798 FeatureWord w; 4799 strList **next = feat_names; 4800 4801 for (w = 0; w < FEATURE_WORDS; w++) { 4802 uint64_t filtered = features[w]; 4803 int i; 4804 for (i = 0; i < 64; i++) { 4805 if (filtered & (1ULL << i)) { 4806 strList *new = g_new0(strList, 1); 4807 new->value = g_strdup(x86_cpu_feature_name(w, i)); 4808 *next = new; 4809 next = &new->next; 4810 } 4811 } 4812 } 4813 } 4814 4815 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 4816 const char *name, void *opaque, 4817 Error **errp) 4818 { 4819 X86CPU *xc = X86_CPU(obj); 4820 strList *result = NULL; 4821 4822 x86_cpu_list_feature_names(xc->filtered_features, &result); 4823 visit_type_strList(v, "unavailable-features", &result, errp); 4824 } 4825 4826 /* Check for missing features that may prevent the CPU class from 4827 * running using the current machine and accelerator. 4828 */ 4829 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 4830 strList **missing_feats) 4831 { 4832 X86CPU *xc; 4833 Error *err = NULL; 4834 strList **next = missing_feats; 4835 4836 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 4837 strList *new = g_new0(strList, 1); 4838 new->value = g_strdup("kvm"); 4839 *missing_feats = new; 4840 return; 4841 } 4842 4843 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 4844 4845 x86_cpu_expand_features(xc, &err); 4846 if (err) { 4847 /* Errors at x86_cpu_expand_features should never happen, 4848 * but in case it does, just report the model as not 4849 * runnable at all using the "type" property. 4850 */ 4851 strList *new = g_new0(strList, 1); 4852 new->value = g_strdup("type"); 4853 *next = new; 4854 next = &new->next; 4855 } 4856 4857 x86_cpu_filter_features(xc, false); 4858 4859 x86_cpu_list_feature_names(xc->filtered_features, next); 4860 4861 object_unref(OBJECT(xc)); 4862 } 4863 4864 /* Print all cpuid feature names in featureset 4865 */ 4866 static void listflags(GList *features) 4867 { 4868 size_t len = 0; 4869 GList *tmp; 4870 4871 for (tmp = features; tmp; tmp = tmp->next) { 4872 const char *name = tmp->data; 4873 if ((len + strlen(name) + 1) >= 75) { 4874 qemu_printf("\n"); 4875 len = 0; 4876 } 4877 qemu_printf("%s%s", len == 0 ? " " : " ", name); 4878 len += strlen(name) + 1; 4879 } 4880 qemu_printf("\n"); 4881 } 4882 4883 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 4884 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 4885 { 4886 ObjectClass *class_a = (ObjectClass *)a; 4887 ObjectClass *class_b = (ObjectClass *)b; 4888 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 4889 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 4890 int ret; 4891 4892 if (cc_a->ordering != cc_b->ordering) { 4893 ret = cc_a->ordering - cc_b->ordering; 4894 } else { 4895 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 4896 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 4897 ret = strcmp(name_a, name_b); 4898 } 4899 return ret; 4900 } 4901 4902 static GSList *get_sorted_cpu_model_list(void) 4903 { 4904 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 4905 list = g_slist_sort(list, x86_cpu_list_compare); 4906 return list; 4907 } 4908 4909 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 4910 { 4911 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 4912 char *r = object_property_get_str(obj, "model-id", &error_abort); 4913 object_unref(obj); 4914 return r; 4915 } 4916 4917 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 4918 { 4919 X86CPUVersion version; 4920 4921 if (!cc->model || !cc->model->is_alias) { 4922 return NULL; 4923 } 4924 version = x86_cpu_model_resolve_version(cc->model); 4925 if (version <= 0) { 4926 return NULL; 4927 } 4928 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 4929 } 4930 4931 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 4932 { 4933 ObjectClass *oc = data; 4934 X86CPUClass *cc = X86_CPU_CLASS(oc); 4935 g_autofree char *name = x86_cpu_class_get_model_name(cc); 4936 g_autofree char *desc = g_strdup(cc->model_description); 4937 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 4938 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 4939 4940 if (!desc && alias_of) { 4941 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 4942 desc = g_strdup("(alias configured by machine type)"); 4943 } else { 4944 desc = g_strdup_printf("(alias of %s)", alias_of); 4945 } 4946 } 4947 if (!desc && cc->model && cc->model->note) { 4948 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 4949 } 4950 if (!desc) { 4951 desc = g_strdup_printf("%s", model_id); 4952 } 4953 4954 qemu_printf("x86 %-20s %-58s\n", name, desc); 4955 } 4956 4957 /* list available CPU models and flags */ 4958 void x86_cpu_list(void) 4959 { 4960 int i, j; 4961 GSList *list; 4962 GList *names = NULL; 4963 4964 qemu_printf("Available CPUs:\n"); 4965 list = get_sorted_cpu_model_list(); 4966 g_slist_foreach(list, x86_cpu_list_entry, NULL); 4967 g_slist_free(list); 4968 4969 names = NULL; 4970 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 4971 FeatureWordInfo *fw = &feature_word_info[i]; 4972 for (j = 0; j < 64; j++) { 4973 if (fw->feat_names[j]) { 4974 names = g_list_append(names, (gpointer)fw->feat_names[j]); 4975 } 4976 } 4977 } 4978 4979 names = g_list_sort(names, (GCompareFunc)strcmp); 4980 4981 qemu_printf("\nRecognized CPUID flags:\n"); 4982 listflags(names); 4983 qemu_printf("\n"); 4984 g_list_free(names); 4985 } 4986 4987 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 4988 { 4989 ObjectClass *oc = data; 4990 X86CPUClass *cc = X86_CPU_CLASS(oc); 4991 CpuDefinitionInfoList **cpu_list = user_data; 4992 CpuDefinitionInfoList *entry; 4993 CpuDefinitionInfo *info; 4994 4995 info = g_malloc0(sizeof(*info)); 4996 info->name = x86_cpu_class_get_model_name(cc); 4997 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 4998 info->has_unavailable_features = true; 4999 info->q_typename = g_strdup(object_class_get_name(oc)); 5000 info->migration_safe = cc->migration_safe; 5001 info->has_migration_safe = true; 5002 info->q_static = cc->static_model; 5003 /* 5004 * Old machine types won't report aliases, so that alias translation 5005 * doesn't break compatibility with previous QEMU versions. 5006 */ 5007 if (default_cpu_version != CPU_VERSION_LEGACY) { 5008 info->alias_of = x86_cpu_class_get_alias_of(cc); 5009 info->has_alias_of = !!info->alias_of; 5010 } 5011 5012 entry = g_malloc0(sizeof(*entry)); 5013 entry->value = info; 5014 entry->next = *cpu_list; 5015 *cpu_list = entry; 5016 } 5017 5018 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5019 { 5020 CpuDefinitionInfoList *cpu_list = NULL; 5021 GSList *list = get_sorted_cpu_model_list(); 5022 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5023 g_slist_free(list); 5024 return cpu_list; 5025 } 5026 5027 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5028 bool migratable_only) 5029 { 5030 FeatureWordInfo *wi = &feature_word_info[w]; 5031 uint64_t r = 0; 5032 5033 if (kvm_enabled()) { 5034 switch (wi->type) { 5035 case CPUID_FEATURE_WORD: 5036 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5037 wi->cpuid.ecx, 5038 wi->cpuid.reg); 5039 break; 5040 case MSR_FEATURE_WORD: 5041 r = kvm_arch_get_supported_msr_feature(kvm_state, 5042 wi->msr.index); 5043 break; 5044 } 5045 } else if (hvf_enabled()) { 5046 if (wi->type != CPUID_FEATURE_WORD) { 5047 return 0; 5048 } 5049 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5050 wi->cpuid.ecx, 5051 wi->cpuid.reg); 5052 } else if (tcg_enabled()) { 5053 r = wi->tcg_features; 5054 } else { 5055 return ~0; 5056 } 5057 if (migratable_only) { 5058 r &= x86_cpu_get_migratable_flags(w); 5059 } 5060 return r; 5061 } 5062 5063 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5064 { 5065 PropValue *pv; 5066 for (pv = props; pv->prop; pv++) { 5067 if (!pv->value) { 5068 continue; 5069 } 5070 object_property_parse(OBJECT(cpu), pv->value, pv->prop, 5071 &error_abort); 5072 } 5073 } 5074 5075 /* Apply properties for the CPU model version specified in model */ 5076 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5077 { 5078 const X86CPUVersionDefinition *vdef; 5079 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5080 5081 if (version == CPU_VERSION_LEGACY) { 5082 return; 5083 } 5084 5085 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5086 PropValue *p; 5087 5088 for (p = vdef->props; p && p->prop; p++) { 5089 object_property_parse(OBJECT(cpu), p->value, p->prop, 5090 &error_abort); 5091 } 5092 5093 if (vdef->version == version) { 5094 break; 5095 } 5096 } 5097 5098 /* 5099 * If we reached the end of the list, version number was invalid 5100 */ 5101 assert(vdef->version == version); 5102 } 5103 5104 /* Load data from X86CPUDefinition into a X86CPU object 5105 */ 5106 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5107 { 5108 X86CPUDefinition *def = model->cpudef; 5109 CPUX86State *env = &cpu->env; 5110 const char *vendor; 5111 char host_vendor[CPUID_VENDOR_SZ + 1]; 5112 FeatureWord w; 5113 5114 /*NOTE: any property set by this function should be returned by 5115 * x86_cpu_static_props(), so static expansion of 5116 * query-cpu-model-expansion is always complete. 5117 */ 5118 5119 /* CPU models only set _minimum_ values for level/xlevel: */ 5120 object_property_set_uint(OBJECT(cpu), def->level, "min-level", 5121 &error_abort); 5122 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", 5123 &error_abort); 5124 5125 object_property_set_int(OBJECT(cpu), def->family, "family", 5126 &error_abort); 5127 object_property_set_int(OBJECT(cpu), def->model, "model", 5128 &error_abort); 5129 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", 5130 &error_abort); 5131 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", 5132 &error_abort); 5133 for (w = 0; w < FEATURE_WORDS; w++) { 5134 env->features[w] = def->features[w]; 5135 } 5136 5137 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5138 cpu->legacy_cache = !def->cache_info; 5139 5140 /* Special cases not set in the X86CPUDefinition structs: */ 5141 /* TODO: in-kernel irqchip for hvf */ 5142 if (kvm_enabled()) { 5143 if (!kvm_irqchip_in_kernel()) { 5144 x86_cpu_change_kvm_default("x2apic", "off"); 5145 } 5146 5147 x86_cpu_apply_props(cpu, kvm_default_props); 5148 } else if (tcg_enabled()) { 5149 x86_cpu_apply_props(cpu, tcg_default_props); 5150 } 5151 5152 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5153 5154 /* sysenter isn't supported in compatibility mode on AMD, 5155 * syscall isn't supported in compatibility mode on Intel. 5156 * Normally we advertise the actual CPU vendor, but you can 5157 * override this using the 'vendor' property if you want to use 5158 * KVM's sysenter/syscall emulation in compatibility mode and 5159 * when doing cross vendor migration 5160 */ 5161 vendor = def->vendor; 5162 if (accel_uses_host_cpuid()) { 5163 uint32_t ebx = 0, ecx = 0, edx = 0; 5164 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); 5165 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx); 5166 vendor = host_vendor; 5167 } 5168 5169 object_property_set_str(OBJECT(cpu), vendor, "vendor", 5170 &error_abort); 5171 5172 x86_cpu_apply_version_props(cpu, model); 5173 } 5174 5175 #ifndef CONFIG_USER_ONLY 5176 /* Return a QDict containing keys for all properties that can be included 5177 * in static expansion of CPU models. All properties set by x86_cpu_load_model() 5178 * must be included in the dictionary. 5179 */ 5180 static QDict *x86_cpu_static_props(void) 5181 { 5182 FeatureWord w; 5183 int i; 5184 static const char *props[] = { 5185 "min-level", 5186 "min-xlevel", 5187 "family", 5188 "model", 5189 "stepping", 5190 "model-id", 5191 "vendor", 5192 "lmce", 5193 NULL, 5194 }; 5195 static QDict *d; 5196 5197 if (d) { 5198 return d; 5199 } 5200 5201 d = qdict_new(); 5202 for (i = 0; props[i]; i++) { 5203 qdict_put_null(d, props[i]); 5204 } 5205 5206 for (w = 0; w < FEATURE_WORDS; w++) { 5207 FeatureWordInfo *fi = &feature_word_info[w]; 5208 int bit; 5209 for (bit = 0; bit < 64; bit++) { 5210 if (!fi->feat_names[bit]) { 5211 continue; 5212 } 5213 qdict_put_null(d, fi->feat_names[bit]); 5214 } 5215 } 5216 5217 return d; 5218 } 5219 5220 /* Add an entry to @props dict, with the value for property. */ 5221 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop) 5222 { 5223 QObject *value = object_property_get_qobject(OBJECT(cpu), prop, 5224 &error_abort); 5225 5226 qdict_put_obj(props, prop, value); 5227 } 5228 5229 /* Convert CPU model data from X86CPU object to a property dictionary 5230 * that can recreate exactly the same CPU model. 5231 */ 5232 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props) 5233 { 5234 QDict *sprops = x86_cpu_static_props(); 5235 const QDictEntry *e; 5236 5237 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) { 5238 const char *prop = qdict_entry_key(e); 5239 x86_cpu_expand_prop(cpu, props, prop); 5240 } 5241 } 5242 5243 /* Convert CPU model data from X86CPU object to a property dictionary 5244 * that can recreate exactly the same CPU model, including every 5245 * writeable QOM property. 5246 */ 5247 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props) 5248 { 5249 ObjectPropertyIterator iter; 5250 ObjectProperty *prop; 5251 5252 object_property_iter_init(&iter, OBJECT(cpu)); 5253 while ((prop = object_property_iter_next(&iter))) { 5254 /* skip read-only or write-only properties */ 5255 if (!prop->get || !prop->set) { 5256 continue; 5257 } 5258 5259 /* "hotplugged" is the only property that is configurable 5260 * on the command-line but will be set differently on CPUs 5261 * created using "-cpu ... -smp ..." and by CPUs created 5262 * on the fly by x86_cpu_from_model() for querying. Skip it. 5263 */ 5264 if (!strcmp(prop->name, "hotplugged")) { 5265 continue; 5266 } 5267 x86_cpu_expand_prop(cpu, props, prop->name); 5268 } 5269 } 5270 5271 static void object_apply_props(Object *obj, QDict *props, Error **errp) 5272 { 5273 const QDictEntry *prop; 5274 Error *err = NULL; 5275 5276 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) { 5277 object_property_set_qobject(obj, qdict_entry_value(prop), 5278 qdict_entry_key(prop), &err); 5279 if (err) { 5280 break; 5281 } 5282 } 5283 5284 error_propagate(errp, err); 5285 } 5286 5287 /* Create X86CPU object according to model+props specification */ 5288 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp) 5289 { 5290 X86CPU *xc = NULL; 5291 X86CPUClass *xcc; 5292 Error *err = NULL; 5293 5294 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model)); 5295 if (xcc == NULL) { 5296 error_setg(&err, "CPU model '%s' not found", model); 5297 goto out; 5298 } 5299 5300 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5301 if (props) { 5302 object_apply_props(OBJECT(xc), props, &err); 5303 if (err) { 5304 goto out; 5305 } 5306 } 5307 5308 x86_cpu_expand_features(xc, &err); 5309 if (err) { 5310 goto out; 5311 } 5312 5313 out: 5314 if (err) { 5315 error_propagate(errp, err); 5316 object_unref(OBJECT(xc)); 5317 xc = NULL; 5318 } 5319 return xc; 5320 } 5321 5322 CpuModelExpansionInfo * 5323 qmp_query_cpu_model_expansion(CpuModelExpansionType type, 5324 CpuModelInfo *model, 5325 Error **errp) 5326 { 5327 X86CPU *xc = NULL; 5328 Error *err = NULL; 5329 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1); 5330 QDict *props = NULL; 5331 const char *base_name; 5332 5333 xc = x86_cpu_from_model(model->name, 5334 model->has_props ? 5335 qobject_to(QDict, model->props) : 5336 NULL, &err); 5337 if (err) { 5338 goto out; 5339 } 5340 5341 props = qdict_new(); 5342 ret->model = g_new0(CpuModelInfo, 1); 5343 ret->model->props = QOBJECT(props); 5344 ret->model->has_props = true; 5345 5346 switch (type) { 5347 case CPU_MODEL_EXPANSION_TYPE_STATIC: 5348 /* Static expansion will be based on "base" only */ 5349 base_name = "base"; 5350 x86_cpu_to_dict(xc, props); 5351 break; 5352 case CPU_MODEL_EXPANSION_TYPE_FULL: 5353 /* As we don't return every single property, full expansion needs 5354 * to keep the original model name+props, and add extra 5355 * properties on top of that. 5356 */ 5357 base_name = model->name; 5358 x86_cpu_to_dict_full(xc, props); 5359 break; 5360 default: 5361 error_setg(&err, "Unsupported expansion type"); 5362 goto out; 5363 } 5364 5365 x86_cpu_to_dict(xc, props); 5366 5367 ret->model->name = g_strdup(base_name); 5368 5369 out: 5370 object_unref(OBJECT(xc)); 5371 if (err) { 5372 error_propagate(errp, err); 5373 qapi_free_CpuModelExpansionInfo(ret); 5374 ret = NULL; 5375 } 5376 return ret; 5377 } 5378 #endif /* !CONFIG_USER_ONLY */ 5379 5380 static gchar *x86_gdb_arch_name(CPUState *cs) 5381 { 5382 #ifdef TARGET_X86_64 5383 return g_strdup("i386:x86-64"); 5384 #else 5385 return g_strdup("i386"); 5386 #endif 5387 } 5388 5389 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5390 { 5391 X86CPUModel *model = data; 5392 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5393 5394 xcc->model = model; 5395 xcc->migration_safe = true; 5396 } 5397 5398 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5399 { 5400 g_autofree char *typename = x86_cpu_type_name(name); 5401 TypeInfo ti = { 5402 .name = typename, 5403 .parent = TYPE_X86_CPU, 5404 .class_init = x86_cpu_cpudef_class_init, 5405 .class_data = model, 5406 }; 5407 5408 type_register(&ti); 5409 } 5410 5411 static void x86_register_cpudef_types(X86CPUDefinition *def) 5412 { 5413 X86CPUModel *m; 5414 const X86CPUVersionDefinition *vdef; 5415 5416 /* AMD aliases are handled at runtime based on CPUID vendor, so 5417 * they shouldn't be set on the CPU model table. 5418 */ 5419 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5420 /* catch mistakes instead of silently truncating model_id when too long */ 5421 assert(def->model_id && strlen(def->model_id) <= 48); 5422 5423 /* Unversioned model: */ 5424 m = g_new0(X86CPUModel, 1); 5425 m->cpudef = def; 5426 m->version = CPU_VERSION_AUTO; 5427 m->is_alias = true; 5428 x86_register_cpu_model_type(def->name, m); 5429 5430 /* Versioned models: */ 5431 5432 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5433 X86CPUModel *m = g_new0(X86CPUModel, 1); 5434 g_autofree char *name = 5435 x86_cpu_versioned_model_name(def, vdef->version); 5436 m->cpudef = def; 5437 m->version = vdef->version; 5438 m->note = vdef->note; 5439 x86_register_cpu_model_type(name, m); 5440 5441 if (vdef->alias) { 5442 X86CPUModel *am = g_new0(X86CPUModel, 1); 5443 am->cpudef = def; 5444 am->version = vdef->version; 5445 am->is_alias = true; 5446 x86_register_cpu_model_type(vdef->alias, am); 5447 } 5448 } 5449 5450 } 5451 5452 #if !defined(CONFIG_USER_ONLY) 5453 5454 void cpu_clear_apic_feature(CPUX86State *env) 5455 { 5456 env->features[FEAT_1_EDX] &= ~CPUID_APIC; 5457 } 5458 5459 #endif /* !CONFIG_USER_ONLY */ 5460 5461 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5462 uint32_t *eax, uint32_t *ebx, 5463 uint32_t *ecx, uint32_t *edx) 5464 { 5465 X86CPU *cpu = env_archcpu(env); 5466 CPUState *cs = env_cpu(env); 5467 uint32_t die_offset; 5468 uint32_t limit; 5469 uint32_t signature[3]; 5470 X86CPUTopoInfo topo_info; 5471 5472 topo_info.nodes_per_pkg = env->nr_nodes; 5473 topo_info.dies_per_pkg = env->nr_dies; 5474 topo_info.cores_per_die = cs->nr_cores; 5475 topo_info.threads_per_core = cs->nr_threads; 5476 5477 /* Calculate & apply limits for different index ranges */ 5478 if (index >= 0xC0000000) { 5479 limit = env->cpuid_xlevel2; 5480 } else if (index >= 0x80000000) { 5481 limit = env->cpuid_xlevel; 5482 } else if (index >= 0x40000000) { 5483 limit = 0x40000001; 5484 } else { 5485 limit = env->cpuid_level; 5486 } 5487 5488 if (index > limit) { 5489 /* Intel documentation states that invalid EAX input will 5490 * return the same information as EAX=cpuid_level 5491 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5492 */ 5493 index = env->cpuid_level; 5494 } 5495 5496 switch(index) { 5497 case 0: 5498 *eax = env->cpuid_level; 5499 *ebx = env->cpuid_vendor1; 5500 *edx = env->cpuid_vendor2; 5501 *ecx = env->cpuid_vendor3; 5502 break; 5503 case 1: 5504 *eax = env->cpuid_version; 5505 *ebx = (cpu->apic_id << 24) | 5506 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5507 *ecx = env->features[FEAT_1_ECX]; 5508 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5509 *ecx |= CPUID_EXT_OSXSAVE; 5510 } 5511 *edx = env->features[FEAT_1_EDX]; 5512 if (cs->nr_cores * cs->nr_threads > 1) { 5513 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5514 *edx |= CPUID_HT; 5515 } 5516 if (!cpu->enable_pmu) { 5517 *ecx &= ~CPUID_EXT_PDCM; 5518 } 5519 break; 5520 case 2: 5521 /* cache info: needed for Pentium Pro compatibility */ 5522 if (cpu->cache_info_passthrough) { 5523 host_cpuid(index, 0, eax, ebx, ecx, edx); 5524 break; 5525 } 5526 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5527 *ebx = 0; 5528 if (!cpu->enable_l3_cache) { 5529 *ecx = 0; 5530 } else { 5531 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5532 } 5533 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5534 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5535 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5536 break; 5537 case 4: 5538 /* cache info: needed for Core compatibility */ 5539 if (cpu->cache_info_passthrough) { 5540 host_cpuid(index, count, eax, ebx, ecx, edx); 5541 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ 5542 *eax &= ~0xFC000000; 5543 if ((*eax & 31) && cs->nr_cores > 1) { 5544 *eax |= (cs->nr_cores - 1) << 26; 5545 } 5546 } else { 5547 *eax = 0; 5548 switch (count) { 5549 case 0: /* L1 dcache info */ 5550 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5551 1, cs->nr_cores, 5552 eax, ebx, ecx, edx); 5553 break; 5554 case 1: /* L1 icache info */ 5555 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5556 1, cs->nr_cores, 5557 eax, ebx, ecx, edx); 5558 break; 5559 case 2: /* L2 cache info */ 5560 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5561 cs->nr_threads, cs->nr_cores, 5562 eax, ebx, ecx, edx); 5563 break; 5564 case 3: /* L3 cache info */ 5565 die_offset = apicid_die_offset(&topo_info); 5566 if (cpu->enable_l3_cache) { 5567 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5568 (1 << die_offset), cs->nr_cores, 5569 eax, ebx, ecx, edx); 5570 break; 5571 } 5572 /* fall through */ 5573 default: /* end of info */ 5574 *eax = *ebx = *ecx = *edx = 0; 5575 break; 5576 } 5577 } 5578 break; 5579 case 5: 5580 /* MONITOR/MWAIT Leaf */ 5581 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5582 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5583 *ecx = cpu->mwait.ecx; /* flags */ 5584 *edx = cpu->mwait.edx; /* mwait substates */ 5585 break; 5586 case 6: 5587 /* Thermal and Power Leaf */ 5588 *eax = env->features[FEAT_6_EAX]; 5589 *ebx = 0; 5590 *ecx = 0; 5591 *edx = 0; 5592 break; 5593 case 7: 5594 /* Structured Extended Feature Flags Enumeration Leaf */ 5595 if (count == 0) { 5596 /* Maximum ECX value for sub-leaves */ 5597 *eax = env->cpuid_level_func7; 5598 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5599 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5600 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5601 *ecx |= CPUID_7_0_ECX_OSPKE; 5602 } 5603 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5604 } else if (count == 1) { 5605 *eax = env->features[FEAT_7_1_EAX]; 5606 *ebx = 0; 5607 *ecx = 0; 5608 *edx = 0; 5609 } else { 5610 *eax = 0; 5611 *ebx = 0; 5612 *ecx = 0; 5613 *edx = 0; 5614 } 5615 break; 5616 case 9: 5617 /* Direct Cache Access Information Leaf */ 5618 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 5619 *ebx = 0; 5620 *ecx = 0; 5621 *edx = 0; 5622 break; 5623 case 0xA: 5624 /* Architectural Performance Monitoring Leaf */ 5625 if (kvm_enabled() && cpu->enable_pmu) { 5626 KVMState *s = cs->kvm_state; 5627 5628 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); 5629 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); 5630 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); 5631 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); 5632 } else if (hvf_enabled() && cpu->enable_pmu) { 5633 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX); 5634 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX); 5635 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX); 5636 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX); 5637 } else { 5638 *eax = 0; 5639 *ebx = 0; 5640 *ecx = 0; 5641 *edx = 0; 5642 } 5643 break; 5644 case 0xB: 5645 /* Extended Topology Enumeration Leaf */ 5646 if (!cpu->enable_cpuid_0xb) { 5647 *eax = *ebx = *ecx = *edx = 0; 5648 break; 5649 } 5650 5651 *ecx = count & 0xff; 5652 *edx = cpu->apic_id; 5653 5654 switch (count) { 5655 case 0: 5656 *eax = apicid_core_offset(&topo_info); 5657 *ebx = cs->nr_threads; 5658 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5659 break; 5660 case 1: 5661 *eax = env->pkg_offset; 5662 *ebx = cs->nr_cores * cs->nr_threads; 5663 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5664 break; 5665 default: 5666 *eax = 0; 5667 *ebx = 0; 5668 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5669 } 5670 5671 assert(!(*eax & ~0x1f)); 5672 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5673 break; 5674 case 0x1F: 5675 /* V2 Extended Topology Enumeration Leaf */ 5676 if (env->nr_dies < 2) { 5677 *eax = *ebx = *ecx = *edx = 0; 5678 break; 5679 } 5680 5681 *ecx = count & 0xff; 5682 *edx = cpu->apic_id; 5683 switch (count) { 5684 case 0: 5685 *eax = apicid_core_offset(&topo_info); 5686 *ebx = cs->nr_threads; 5687 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5688 break; 5689 case 1: 5690 *eax = apicid_die_offset(&topo_info); 5691 *ebx = cs->nr_cores * cs->nr_threads; 5692 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5693 break; 5694 case 2: 5695 *eax = env->pkg_offset; 5696 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 5697 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 5698 break; 5699 default: 5700 *eax = 0; 5701 *ebx = 0; 5702 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5703 } 5704 assert(!(*eax & ~0x1f)); 5705 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5706 break; 5707 case 0xD: { 5708 /* Processor Extended State */ 5709 *eax = 0; 5710 *ebx = 0; 5711 *ecx = 0; 5712 *edx = 0; 5713 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5714 break; 5715 } 5716 5717 if (count == 0) { 5718 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu)); 5719 *eax = env->features[FEAT_XSAVE_COMP_LO]; 5720 *edx = env->features[FEAT_XSAVE_COMP_HI]; 5721 /* 5722 * The initial value of xcr0 and ebx == 0, On host without kvm 5723 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 5724 * even through guest update xcr0, this will crash some legacy guest 5725 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 5726 */ 5727 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0); 5728 } else if (count == 1) { 5729 *eax = env->features[FEAT_XSAVE]; 5730 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 5731 if ((x86_cpu_xsave_components(cpu) >> count) & 1) { 5732 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 5733 *eax = esa->size; 5734 *ebx = esa->offset; 5735 } 5736 } 5737 break; 5738 } 5739 case 0x14: { 5740 /* Intel Processor Trace Enumeration */ 5741 *eax = 0; 5742 *ebx = 0; 5743 *ecx = 0; 5744 *edx = 0; 5745 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 5746 !kvm_enabled()) { 5747 break; 5748 } 5749 5750 if (count == 0) { 5751 *eax = INTEL_PT_MAX_SUBLEAF; 5752 *ebx = INTEL_PT_MINIMAL_EBX; 5753 *ecx = INTEL_PT_MINIMAL_ECX; 5754 } else if (count == 1) { 5755 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 5756 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 5757 } 5758 break; 5759 } 5760 case 0x40000000: 5761 /* 5762 * CPUID code in kvm_arch_init_vcpu() ignores stuff 5763 * set here, but we restrict to TCG none the less. 5764 */ 5765 if (tcg_enabled() && cpu->expose_tcg) { 5766 memcpy(signature, "TCGTCGTCGTCG", 12); 5767 *eax = 0x40000001; 5768 *ebx = signature[0]; 5769 *ecx = signature[1]; 5770 *edx = signature[2]; 5771 } else { 5772 *eax = 0; 5773 *ebx = 0; 5774 *ecx = 0; 5775 *edx = 0; 5776 } 5777 break; 5778 case 0x40000001: 5779 *eax = 0; 5780 *ebx = 0; 5781 *ecx = 0; 5782 *edx = 0; 5783 break; 5784 case 0x80000000: 5785 *eax = env->cpuid_xlevel; 5786 *ebx = env->cpuid_vendor1; 5787 *edx = env->cpuid_vendor2; 5788 *ecx = env->cpuid_vendor3; 5789 break; 5790 case 0x80000001: 5791 *eax = env->cpuid_version; 5792 *ebx = 0; 5793 *ecx = env->features[FEAT_8000_0001_ECX]; 5794 *edx = env->features[FEAT_8000_0001_EDX]; 5795 5796 /* The Linux kernel checks for the CMPLegacy bit and 5797 * discards multiple thread information if it is set. 5798 * So don't set it here for Intel to make Linux guests happy. 5799 */ 5800 if (cs->nr_cores * cs->nr_threads > 1) { 5801 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 5802 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 5803 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 5804 *ecx |= 1 << 1; /* CmpLegacy bit */ 5805 } 5806 } 5807 break; 5808 case 0x80000002: 5809 case 0x80000003: 5810 case 0x80000004: 5811 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 5812 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 5813 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 5814 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 5815 break; 5816 case 0x80000005: 5817 /* cache info (L1 cache) */ 5818 if (cpu->cache_info_passthrough) { 5819 host_cpuid(index, 0, eax, ebx, ecx, edx); 5820 break; 5821 } 5822 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 5823 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 5824 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 5825 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 5826 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 5827 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 5828 break; 5829 case 0x80000006: 5830 /* cache info (L2 cache) */ 5831 if (cpu->cache_info_passthrough) { 5832 host_cpuid(index, 0, eax, ebx, ecx, edx); 5833 break; 5834 } 5835 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 5836 (L2_DTLB_2M_ENTRIES << 16) | 5837 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 5838 (L2_ITLB_2M_ENTRIES); 5839 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 5840 (L2_DTLB_4K_ENTRIES << 16) | 5841 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 5842 (L2_ITLB_4K_ENTRIES); 5843 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 5844 cpu->enable_l3_cache ? 5845 env->cache_info_amd.l3_cache : NULL, 5846 ecx, edx); 5847 break; 5848 case 0x80000007: 5849 *eax = 0; 5850 *ebx = 0; 5851 *ecx = 0; 5852 *edx = env->features[FEAT_8000_0007_EDX]; 5853 break; 5854 case 0x80000008: 5855 /* virtual & phys address size in low 2 bytes. */ 5856 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5857 /* 64 bit processor */ 5858 *eax = cpu->phys_bits; /* configurable physical bits */ 5859 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5860 *eax |= 0x00003900; /* 57 bits virtual */ 5861 } else { 5862 *eax |= 0x00003000; /* 48 bits virtual */ 5863 } 5864 } else { 5865 *eax = cpu->phys_bits; 5866 } 5867 *ebx = env->features[FEAT_8000_0008_EBX]; 5868 if (cs->nr_cores * cs->nr_threads > 1) { 5869 /* 5870 * Bits 15:12 is "The number of bits in the initial 5871 * Core::X86::Apic::ApicId[ApicId] value that indicate 5872 * thread ID within a package". This is already stored at 5873 * CPUX86State::pkg_offset. 5874 * Bits 7:0 is "The number of threads in the package is NC+1" 5875 */ 5876 *ecx = (env->pkg_offset << 12) | 5877 ((cs->nr_cores * cs->nr_threads) - 1); 5878 } else { 5879 *ecx = 0; 5880 } 5881 *edx = 0; 5882 break; 5883 case 0x8000000A: 5884 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5885 *eax = 0x00000001; /* SVM Revision */ 5886 *ebx = 0x00000010; /* nr of ASIDs */ 5887 *ecx = 0; 5888 *edx = env->features[FEAT_SVM]; /* optional features */ 5889 } else { 5890 *eax = 0; 5891 *ebx = 0; 5892 *ecx = 0; 5893 *edx = 0; 5894 } 5895 break; 5896 case 0x8000001D: 5897 *eax = 0; 5898 if (cpu->cache_info_passthrough) { 5899 host_cpuid(index, count, eax, ebx, ecx, edx); 5900 break; 5901 } 5902 switch (count) { 5903 case 0: /* L1 dcache info */ 5904 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 5905 &topo_info, eax, ebx, ecx, edx); 5906 break; 5907 case 1: /* L1 icache info */ 5908 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 5909 &topo_info, eax, ebx, ecx, edx); 5910 break; 5911 case 2: /* L2 cache info */ 5912 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 5913 &topo_info, eax, ebx, ecx, edx); 5914 break; 5915 case 3: /* L3 cache info */ 5916 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 5917 &topo_info, eax, ebx, ecx, edx); 5918 break; 5919 default: /* end of info */ 5920 *eax = *ebx = *ecx = *edx = 0; 5921 break; 5922 } 5923 break; 5924 case 0x8000001E: 5925 assert(cpu->core_id <= 255); 5926 encode_topo_cpuid8000001e(&topo_info, cpu, eax, ebx, ecx, edx); 5927 break; 5928 case 0xC0000000: 5929 *eax = env->cpuid_xlevel2; 5930 *ebx = 0; 5931 *ecx = 0; 5932 *edx = 0; 5933 break; 5934 case 0xC0000001: 5935 /* Support for VIA CPU's CPUID instruction */ 5936 *eax = env->cpuid_version; 5937 *ebx = 0; 5938 *ecx = 0; 5939 *edx = env->features[FEAT_C000_0001_EDX]; 5940 break; 5941 case 0xC0000002: 5942 case 0xC0000003: 5943 case 0xC0000004: 5944 /* Reserved for the future, and now filled with zero */ 5945 *eax = 0; 5946 *ebx = 0; 5947 *ecx = 0; 5948 *edx = 0; 5949 break; 5950 case 0x8000001F: 5951 *eax = sev_enabled() ? 0x2 : 0; 5952 *ebx = sev_get_cbit_position(); 5953 *ebx |= sev_get_reduced_phys_bits() << 6; 5954 *ecx = 0; 5955 *edx = 0; 5956 break; 5957 default: 5958 /* reserved values: zero */ 5959 *eax = 0; 5960 *ebx = 0; 5961 *ecx = 0; 5962 *edx = 0; 5963 break; 5964 } 5965 } 5966 5967 static void x86_cpu_reset(DeviceState *dev) 5968 { 5969 CPUState *s = CPU(dev); 5970 X86CPU *cpu = X86_CPU(s); 5971 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 5972 CPUX86State *env = &cpu->env; 5973 target_ulong cr4; 5974 uint64_t xcr0; 5975 int i; 5976 5977 xcc->parent_reset(dev); 5978 5979 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 5980 5981 env->old_exception = -1; 5982 5983 /* init to reset state */ 5984 5985 env->hflags2 |= HF2_GIF_MASK; 5986 5987 cpu_x86_update_cr0(env, 0x60000010); 5988 env->a20_mask = ~0x0; 5989 env->smbase = 0x30000; 5990 env->msr_smi_count = 0; 5991 5992 env->idt.limit = 0xffff; 5993 env->gdt.limit = 0xffff; 5994 env->ldt.limit = 0xffff; 5995 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 5996 env->tr.limit = 0xffff; 5997 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 5998 5999 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6000 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6001 DESC_R_MASK | DESC_A_MASK); 6002 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6003 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6004 DESC_A_MASK); 6005 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6006 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6007 DESC_A_MASK); 6008 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6009 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6010 DESC_A_MASK); 6011 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6012 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6013 DESC_A_MASK); 6014 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6015 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6016 DESC_A_MASK); 6017 6018 env->eip = 0xfff0; 6019 env->regs[R_EDX] = env->cpuid_version; 6020 6021 env->eflags = 0x2; 6022 6023 /* FPU init */ 6024 for (i = 0; i < 8; i++) { 6025 env->fptags[i] = 1; 6026 } 6027 cpu_set_fpuc(env, 0x37f); 6028 6029 env->mxcsr = 0x1f80; 6030 /* All units are in INIT state. */ 6031 env->xstate_bv = 0; 6032 6033 env->pat = 0x0007040600070406ULL; 6034 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6035 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6036 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6037 } 6038 6039 memset(env->dr, 0, sizeof(env->dr)); 6040 env->dr[6] = DR6_FIXED_1; 6041 env->dr[7] = DR7_FIXED_1; 6042 cpu_breakpoint_remove_all(s, BP_CPU); 6043 cpu_watchpoint_remove_all(s, BP_CPU); 6044 6045 cr4 = 0; 6046 xcr0 = XSTATE_FP_MASK; 6047 6048 #ifdef CONFIG_USER_ONLY 6049 /* Enable all the features for user-mode. */ 6050 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6051 xcr0 |= XSTATE_SSE_MASK; 6052 } 6053 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6054 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6055 if (env->features[esa->feature] & esa->bits) { 6056 xcr0 |= 1ull << i; 6057 } 6058 } 6059 6060 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6061 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6062 } 6063 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6064 cr4 |= CR4_FSGSBASE_MASK; 6065 } 6066 #endif 6067 6068 env->xcr0 = xcr0; 6069 cpu_x86_update_cr4(env, cr4); 6070 6071 /* 6072 * SDM 11.11.5 requires: 6073 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6074 * - IA32_MTRR_PHYSMASKn.V = 0 6075 * All other bits are undefined. For simplification, zero it all. 6076 */ 6077 env->mtrr_deftype = 0; 6078 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6079 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6080 6081 env->interrupt_injected = -1; 6082 env->exception_nr = -1; 6083 env->exception_pending = 0; 6084 env->exception_injected = 0; 6085 env->exception_has_payload = false; 6086 env->exception_payload = 0; 6087 env->nmi_injected = false; 6088 #if !defined(CONFIG_USER_ONLY) 6089 /* We hard-wire the BSP to the first CPU. */ 6090 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 6091 6092 s->halted = !cpu_is_bsp(cpu); 6093 6094 if (kvm_enabled()) { 6095 kvm_arch_reset_vcpu(cpu); 6096 } 6097 else if (hvf_enabled()) { 6098 hvf_reset_vcpu(s); 6099 } 6100 #endif 6101 } 6102 6103 #ifndef CONFIG_USER_ONLY 6104 bool cpu_is_bsp(X86CPU *cpu) 6105 { 6106 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP; 6107 } 6108 6109 /* TODO: remove me, when reset over QOM tree is implemented */ 6110 static void x86_cpu_machine_reset_cb(void *opaque) 6111 { 6112 X86CPU *cpu = opaque; 6113 cpu_reset(CPU(cpu)); 6114 } 6115 #endif 6116 6117 static void mce_init(X86CPU *cpu) 6118 { 6119 CPUX86State *cenv = &cpu->env; 6120 unsigned int bank; 6121 6122 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 6123 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 6124 (CPUID_MCE | CPUID_MCA)) { 6125 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 6126 (cpu->enable_lmce ? MCG_LMCE_P : 0); 6127 cenv->mcg_ctl = ~(uint64_t)0; 6128 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 6129 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 6130 } 6131 } 6132 } 6133 6134 #ifndef CONFIG_USER_ONLY 6135 APICCommonClass *apic_get_class(void) 6136 { 6137 const char *apic_type = "apic"; 6138 6139 /* TODO: in-kernel irqchip for hvf */ 6140 if (kvm_apic_in_kernel()) { 6141 apic_type = "kvm-apic"; 6142 } else if (xen_enabled()) { 6143 apic_type = "xen-apic"; 6144 } 6145 6146 return APIC_COMMON_CLASS(object_class_by_name(apic_type)); 6147 } 6148 6149 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) 6150 { 6151 APICCommonState *apic; 6152 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class()); 6153 6154 cpu->apic_state = DEVICE(object_new_with_class(apic_class)); 6155 6156 object_property_add_child(OBJECT(cpu), "lapic", 6157 OBJECT(cpu->apic_state)); 6158 object_unref(OBJECT(cpu->apic_state)); 6159 6160 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id); 6161 /* TODO: convert to link<> */ 6162 apic = APIC_COMMON(cpu->apic_state); 6163 apic->cpu = cpu; 6164 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; 6165 } 6166 6167 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) 6168 { 6169 APICCommonState *apic; 6170 static bool apic_mmio_map_once; 6171 6172 if (cpu->apic_state == NULL) { 6173 return; 6174 } 6175 qdev_realize(DEVICE(cpu->apic_state), NULL, errp); 6176 6177 /* Map APIC MMIO area */ 6178 apic = APIC_COMMON(cpu->apic_state); 6179 if (!apic_mmio_map_once) { 6180 memory_region_add_subregion_overlap(get_system_memory(), 6181 apic->apicbase & 6182 MSR_IA32_APICBASE_BASE, 6183 &apic->io_memory, 6184 0x1000); 6185 apic_mmio_map_once = true; 6186 } 6187 } 6188 6189 static void x86_cpu_machine_done(Notifier *n, void *unused) 6190 { 6191 X86CPU *cpu = container_of(n, X86CPU, machine_done); 6192 MemoryRegion *smram = 6193 (MemoryRegion *) object_resolve_path("/machine/smram", NULL); 6194 6195 if (smram) { 6196 cpu->smram = g_new(MemoryRegion, 1); 6197 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", 6198 smram, 0, 4 * GiB); 6199 memory_region_set_enabled(cpu->smram, true); 6200 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1); 6201 } 6202 } 6203 #else 6204 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) 6205 { 6206 } 6207 #endif 6208 6209 /* Note: Only safe for use on x86(-64) hosts */ 6210 static uint32_t x86_host_phys_bits(void) 6211 { 6212 uint32_t eax; 6213 uint32_t host_phys_bits; 6214 6215 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); 6216 if (eax >= 0x80000008) { 6217 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); 6218 /* Note: According to AMD doc 25481 rev 2.34 they have a field 6219 * at 23:16 that can specify a maximum physical address bits for 6220 * the guest that can override this value; but I've not seen 6221 * anything with that set. 6222 */ 6223 host_phys_bits = eax & 0xff; 6224 } else { 6225 /* It's an odd 64 bit machine that doesn't have the leaf for 6226 * physical address bits; fall back to 36 that's most older 6227 * Intel. 6228 */ 6229 host_phys_bits = 36; 6230 } 6231 6232 return host_phys_bits; 6233 } 6234 6235 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 6236 { 6237 if (*min < value) { 6238 *min = value; 6239 } 6240 } 6241 6242 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 6243 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 6244 { 6245 CPUX86State *env = &cpu->env; 6246 FeatureWordInfo *fi = &feature_word_info[w]; 6247 uint32_t eax = fi->cpuid.eax; 6248 uint32_t region = eax & 0xF0000000; 6249 6250 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 6251 if (!env->features[w]) { 6252 return; 6253 } 6254 6255 switch (region) { 6256 case 0x00000000: 6257 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 6258 break; 6259 case 0x80000000: 6260 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 6261 break; 6262 case 0xC0000000: 6263 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 6264 break; 6265 } 6266 6267 if (eax == 7) { 6268 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 6269 fi->cpuid.ecx); 6270 } 6271 } 6272 6273 /* Calculate XSAVE components based on the configured CPU feature flags */ 6274 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 6275 { 6276 CPUX86State *env = &cpu->env; 6277 int i; 6278 uint64_t mask; 6279 6280 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6281 return; 6282 } 6283 6284 mask = 0; 6285 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6286 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6287 if (env->features[esa->feature] & esa->bits) { 6288 mask |= (1ULL << i); 6289 } 6290 } 6291 6292 env->features[FEAT_XSAVE_COMP_LO] = mask; 6293 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32; 6294 } 6295 6296 /***** Steps involved on loading and filtering CPUID data 6297 * 6298 * When initializing and realizing a CPU object, the steps 6299 * involved in setting up CPUID data are: 6300 * 6301 * 1) Loading CPU model definition (X86CPUDefinition). This is 6302 * implemented by x86_cpu_load_model() and should be completely 6303 * transparent, as it is done automatically by instance_init. 6304 * No code should need to look at X86CPUDefinition structs 6305 * outside instance_init. 6306 * 6307 * 2) CPU expansion. This is done by realize before CPUID 6308 * filtering, and will make sure host/accelerator data is 6309 * loaded for CPU models that depend on host capabilities 6310 * (e.g. "host"). Done by x86_cpu_expand_features(). 6311 * 6312 * 3) CPUID filtering. This initializes extra data related to 6313 * CPUID, and checks if the host supports all capabilities 6314 * required by the CPU. Runnability of a CPU model is 6315 * determined at this step. Done by x86_cpu_filter_features(). 6316 * 6317 * Some operations don't require all steps to be performed. 6318 * More precisely: 6319 * 6320 * - CPU instance creation (instance_init) will run only CPU 6321 * model loading. CPU expansion can't run at instance_init-time 6322 * because host/accelerator data may be not available yet. 6323 * - CPU realization will perform both CPU model expansion and CPUID 6324 * filtering, and return an error in case one of them fails. 6325 * - query-cpu-definitions needs to run all 3 steps. It needs 6326 * to run CPUID filtering, as the 'unavailable-features' 6327 * field is set based on the filtering results. 6328 * - The query-cpu-model-expansion QMP command only needs to run 6329 * CPU model loading and CPU expansion. It should not filter 6330 * any CPUID data based on host capabilities. 6331 */ 6332 6333 /* Expand CPU configuration data, based on configured features 6334 * and host/accelerator capabilities when appropriate. 6335 */ 6336 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6337 { 6338 CPUX86State *env = &cpu->env; 6339 FeatureWord w; 6340 int i; 6341 GList *l; 6342 Error *local_err = NULL; 6343 6344 for (l = plus_features; l; l = l->next) { 6345 const char *prop = l->data; 6346 object_property_set_bool(OBJECT(cpu), true, prop, &local_err); 6347 if (local_err) { 6348 goto out; 6349 } 6350 } 6351 6352 for (l = minus_features; l; l = l->next) { 6353 const char *prop = l->data; 6354 object_property_set_bool(OBJECT(cpu), false, prop, &local_err); 6355 if (local_err) { 6356 goto out; 6357 } 6358 } 6359 6360 /*TODO: Now cpu->max_features doesn't overwrite features 6361 * set using QOM properties, and we can convert 6362 * plus_features & minus_features to global properties 6363 * inside x86_cpu_parse_featurestr() too. 6364 */ 6365 if (cpu->max_features) { 6366 for (w = 0; w < FEATURE_WORDS; w++) { 6367 /* Override only features that weren't set explicitly 6368 * by the user. 6369 */ 6370 env->features[w] |= 6371 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 6372 ~env->user_features[w] & 6373 ~feature_word_info[w].no_autoenable_flags; 6374 } 6375 } 6376 6377 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 6378 FeatureDep *d = &feature_dependencies[i]; 6379 if (!(env->features[d->from.index] & d->from.mask)) { 6380 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 6381 6382 /* Not an error unless the dependent feature was added explicitly. */ 6383 mark_unavailable_features(cpu, d->to.index, 6384 unavailable_features & env->user_features[d->to.index], 6385 "This feature depends on other features that were not requested"); 6386 6387 env->user_features[d->to.index] |= unavailable_features; 6388 env->features[d->to.index] &= ~unavailable_features; 6389 } 6390 } 6391 6392 if (!kvm_enabled() || !cpu->expose_kvm) { 6393 env->features[FEAT_KVM] = 0; 6394 } 6395 6396 x86_cpu_enable_xsave_components(cpu); 6397 6398 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 6399 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 6400 if (cpu->full_cpuid_auto_level) { 6401 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 6402 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 6403 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 6404 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 6405 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 6406 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 6407 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 6408 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 6409 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 6410 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 6411 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 6412 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 6413 6414 /* Intel Processor Trace requires CPUID[0x14] */ 6415 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 6416 if (cpu->intel_pt_auto_level) { 6417 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 6418 } else if (cpu->env.cpuid_min_level < 0x14) { 6419 mark_unavailable_features(cpu, FEAT_7_0_EBX, 6420 CPUID_7_0_EBX_INTEL_PT, 6421 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,+intel-pt,level=0x14\""); 6422 } 6423 } 6424 6425 /* CPU topology with multi-dies support requires CPUID[0x1F] */ 6426 if (env->nr_dies > 1) { 6427 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 6428 } 6429 6430 /* SVM requires CPUID[0x8000000A] */ 6431 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6432 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 6433 } 6434 6435 /* SEV requires CPUID[0x8000001F] */ 6436 if (sev_enabled()) { 6437 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 6438 } 6439 } 6440 6441 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6442 if (env->cpuid_level_func7 == UINT32_MAX) { 6443 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6444 } 6445 if (env->cpuid_level == UINT32_MAX) { 6446 env->cpuid_level = env->cpuid_min_level; 6447 } 6448 if (env->cpuid_xlevel == UINT32_MAX) { 6449 env->cpuid_xlevel = env->cpuid_min_xlevel; 6450 } 6451 if (env->cpuid_xlevel2 == UINT32_MAX) { 6452 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6453 } 6454 6455 out: 6456 if (local_err != NULL) { 6457 error_propagate(errp, local_err); 6458 } 6459 } 6460 6461 /* 6462 * Finishes initialization of CPUID data, filters CPU feature 6463 * words based on host availability of each feature. 6464 * 6465 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6466 */ 6467 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6468 { 6469 CPUX86State *env = &cpu->env; 6470 FeatureWord w; 6471 const char *prefix = NULL; 6472 6473 if (verbose) { 6474 prefix = accel_uses_host_cpuid() 6475 ? "host doesn't support requested feature" 6476 : "TCG doesn't support requested feature"; 6477 } 6478 6479 for (w = 0; w < FEATURE_WORDS; w++) { 6480 uint64_t host_feat = 6481 x86_cpu_get_supported_feature_word(w, false); 6482 uint64_t requested_features = env->features[w]; 6483 uint64_t unavailable_features = requested_features & ~host_feat; 6484 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6485 } 6486 6487 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6488 kvm_enabled()) { 6489 KVMState *s = CPU(cpu)->kvm_state; 6490 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6491 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6492 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6493 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6494 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6495 6496 if (!eax_0 || 6497 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6498 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6499 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6500 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6501 INTEL_PT_ADDR_RANGES_NUM) || 6502 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6503 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6504 (ecx_0 & INTEL_PT_IP_LIP)) { 6505 /* 6506 * Processor Trace capabilities aren't configurable, so if the 6507 * host can't emulate the capabilities we report on 6508 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 6509 */ 6510 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 6511 } 6512 } 6513 } 6514 6515 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 6516 { 6517 CPUState *cs = CPU(dev); 6518 X86CPU *cpu = X86_CPU(dev); 6519 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6520 CPUX86State *env = &cpu->env; 6521 Error *local_err = NULL; 6522 static bool ht_warned; 6523 6524 if (xcc->host_cpuid_required) { 6525 if (!accel_uses_host_cpuid()) { 6526 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6527 error_setg(&local_err, "CPU model '%s' requires KVM", name); 6528 goto out; 6529 } 6530 } 6531 6532 if (cpu->max_features && accel_uses_host_cpuid()) { 6533 if (enable_cpu_pm) { 6534 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, 6535 &cpu->mwait.ecx, &cpu->mwait.edx); 6536 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR; 6537 } 6538 if (kvm_enabled() && cpu->ucode_rev == 0) { 6539 cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state, 6540 MSR_IA32_UCODE_REV); 6541 } 6542 } 6543 6544 if (cpu->ucode_rev == 0) { 6545 /* The default is the same as KVM's. */ 6546 if (IS_AMD_CPU(env)) { 6547 cpu->ucode_rev = 0x01000065; 6548 } else { 6549 cpu->ucode_rev = 0x100000000ULL; 6550 } 6551 } 6552 6553 /* mwait extended info: needed for Core compatibility */ 6554 /* We always wake on interrupt even if host does not have the capability */ 6555 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 6556 6557 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 6558 error_setg(errp, "apic-id property was not initialized properly"); 6559 return; 6560 } 6561 6562 x86_cpu_expand_features(cpu, &local_err); 6563 if (local_err) { 6564 goto out; 6565 } 6566 6567 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 6568 6569 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 6570 error_setg(&local_err, 6571 accel_uses_host_cpuid() ? 6572 "Host doesn't support requested features" : 6573 "TCG doesn't support requested features"); 6574 goto out; 6575 } 6576 6577 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 6578 * CPUID[1].EDX. 6579 */ 6580 if (IS_AMD_CPU(env)) { 6581 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 6582 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 6583 & CPUID_EXT2_AMD_ALIASES); 6584 } 6585 6586 /* For 64bit systems think about the number of physical bits to present. 6587 * ideally this should be the same as the host; anything other than matching 6588 * the host can cause incorrect guest behaviour. 6589 * QEMU used to pick the magic value of 40 bits that corresponds to 6590 * consumer AMD devices but nothing else. 6591 */ 6592 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6593 if (accel_uses_host_cpuid()) { 6594 uint32_t host_phys_bits = x86_host_phys_bits(); 6595 static bool warned; 6596 6597 /* Print a warning if the user set it to a value that's not the 6598 * host value. 6599 */ 6600 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 && 6601 !warned) { 6602 warn_report("Host physical bits (%u)" 6603 " does not match phys-bits property (%u)", 6604 host_phys_bits, cpu->phys_bits); 6605 warned = true; 6606 } 6607 6608 if (cpu->host_phys_bits) { 6609 /* The user asked for us to use the host physical bits */ 6610 cpu->phys_bits = host_phys_bits; 6611 if (cpu->host_phys_bits_limit && 6612 cpu->phys_bits > cpu->host_phys_bits_limit) { 6613 cpu->phys_bits = cpu->host_phys_bits_limit; 6614 } 6615 } 6616 6617 if (cpu->phys_bits && 6618 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 6619 cpu->phys_bits < 32)) { 6620 error_setg(errp, "phys-bits should be between 32 and %u " 6621 " (but is %u)", 6622 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 6623 return; 6624 } 6625 } else { 6626 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { 6627 error_setg(errp, "TCG only supports phys-bits=%u", 6628 TCG_PHYS_ADDR_BITS); 6629 return; 6630 } 6631 } 6632 /* 0 means it was not explicitly set by the user (or by machine 6633 * compat_props or by the host code above). In this case, the default 6634 * is the value used by TCG (40). 6635 */ 6636 if (cpu->phys_bits == 0) { 6637 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 6638 } 6639 } else { 6640 /* For 32 bit systems don't use the user set value, but keep 6641 * phys_bits consistent with what we tell the guest. 6642 */ 6643 if (cpu->phys_bits != 0) { 6644 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 6645 return; 6646 } 6647 6648 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 6649 cpu->phys_bits = 36; 6650 } else { 6651 cpu->phys_bits = 32; 6652 } 6653 } 6654 6655 /* Cache information initialization */ 6656 if (!cpu->legacy_cache) { 6657 if (!xcc->model || !xcc->model->cpudef->cache_info) { 6658 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6659 error_setg(errp, 6660 "CPU model '%s' doesn't support legacy-cache=off", name); 6661 return; 6662 } 6663 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 6664 *xcc->model->cpudef->cache_info; 6665 } else { 6666 /* Build legacy cache information */ 6667 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 6668 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 6669 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 6670 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 6671 6672 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 6673 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 6674 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 6675 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 6676 6677 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 6678 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 6679 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 6680 env->cache_info_amd.l3_cache = &legacy_l3_cache; 6681 } 6682 6683 6684 cpu_exec_realizefn(cs, &local_err); 6685 if (local_err != NULL) { 6686 error_propagate(errp, local_err); 6687 return; 6688 } 6689 6690 #ifndef CONFIG_USER_ONLY 6691 MachineState *ms = MACHINE(qdev_get_machine()); 6692 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 6693 6694 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 6695 x86_cpu_apic_create(cpu, &local_err); 6696 if (local_err != NULL) { 6697 goto out; 6698 } 6699 } 6700 #endif 6701 6702 mce_init(cpu); 6703 6704 #ifndef CONFIG_USER_ONLY 6705 if (tcg_enabled()) { 6706 cpu->cpu_as_mem = g_new(MemoryRegion, 1); 6707 cpu->cpu_as_root = g_new(MemoryRegion, 1); 6708 6709 /* Outer container... */ 6710 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); 6711 memory_region_set_enabled(cpu->cpu_as_root, true); 6712 6713 /* ... with two regions inside: normal system memory with low 6714 * priority, and... 6715 */ 6716 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", 6717 get_system_memory(), 0, ~0ull); 6718 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0); 6719 memory_region_set_enabled(cpu->cpu_as_mem, true); 6720 6721 cs->num_ases = 2; 6722 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); 6723 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); 6724 6725 /* ... SMRAM with higher priority, linked from /machine/smram. */ 6726 cpu->machine_done.notify = x86_cpu_machine_done; 6727 qemu_add_machine_init_done_notifier(&cpu->machine_done); 6728 } 6729 #endif 6730 6731 qemu_init_vcpu(cs); 6732 6733 /* 6734 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 6735 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 6736 * based on inputs (sockets,cores,threads), it is still better to give 6737 * users a warning. 6738 * 6739 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 6740 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 6741 */ 6742 if (IS_AMD_CPU(env) && 6743 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 6744 cs->nr_threads > 1 && !ht_warned) { 6745 warn_report("This family of AMD CPU doesn't support " 6746 "hyperthreading(%d)", 6747 cs->nr_threads); 6748 error_printf("Please configure -smp options properly" 6749 " or try enabling topoext feature.\n"); 6750 ht_warned = true; 6751 } 6752 6753 x86_cpu_apic_realize(cpu, &local_err); 6754 if (local_err != NULL) { 6755 goto out; 6756 } 6757 cpu_reset(cs); 6758 6759 xcc->parent_realize(dev, &local_err); 6760 6761 out: 6762 if (local_err != NULL) { 6763 error_propagate(errp, local_err); 6764 return; 6765 } 6766 } 6767 6768 static void x86_cpu_unrealizefn(DeviceState *dev) 6769 { 6770 X86CPU *cpu = X86_CPU(dev); 6771 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6772 6773 #ifndef CONFIG_USER_ONLY 6774 cpu_remove_sync(CPU(dev)); 6775 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 6776 #endif 6777 6778 if (cpu->apic_state) { 6779 object_unparent(OBJECT(cpu->apic_state)); 6780 cpu->apic_state = NULL; 6781 } 6782 6783 xcc->parent_unrealize(dev); 6784 } 6785 6786 typedef struct BitProperty { 6787 FeatureWord w; 6788 uint64_t mask; 6789 } BitProperty; 6790 6791 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 6792 void *opaque, Error **errp) 6793 { 6794 X86CPU *cpu = X86_CPU(obj); 6795 BitProperty *fp = opaque; 6796 uint64_t f = cpu->env.features[fp->w]; 6797 bool value = (f & fp->mask) == fp->mask; 6798 visit_type_bool(v, name, &value, errp); 6799 } 6800 6801 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 6802 void *opaque, Error **errp) 6803 { 6804 DeviceState *dev = DEVICE(obj); 6805 X86CPU *cpu = X86_CPU(obj); 6806 BitProperty *fp = opaque; 6807 Error *local_err = NULL; 6808 bool value; 6809 6810 if (dev->realized) { 6811 qdev_prop_set_after_realize(dev, name, errp); 6812 return; 6813 } 6814 6815 visit_type_bool(v, name, &value, &local_err); 6816 if (local_err) { 6817 error_propagate(errp, local_err); 6818 return; 6819 } 6820 6821 if (value) { 6822 cpu->env.features[fp->w] |= fp->mask; 6823 } else { 6824 cpu->env.features[fp->w] &= ~fp->mask; 6825 } 6826 cpu->env.user_features[fp->w] |= fp->mask; 6827 } 6828 6829 static void x86_cpu_release_bit_prop(Object *obj, const char *name, 6830 void *opaque) 6831 { 6832 BitProperty *prop = opaque; 6833 g_free(prop); 6834 } 6835 6836 /* Register a boolean property to get/set a single bit in a uint32_t field. 6837 * 6838 * The same property name can be registered multiple times to make it affect 6839 * multiple bits in the same FeatureWord. In that case, the getter will return 6840 * true only if all bits are set. 6841 */ 6842 static void x86_cpu_register_bit_prop(X86CPU *cpu, 6843 const char *prop_name, 6844 FeatureWord w, 6845 int bitnr) 6846 { 6847 BitProperty *fp; 6848 ObjectProperty *op; 6849 uint64_t mask = (1ULL << bitnr); 6850 6851 op = object_property_find(OBJECT(cpu), prop_name, NULL); 6852 if (op) { 6853 fp = op->opaque; 6854 assert(fp->w == w); 6855 fp->mask |= mask; 6856 } else { 6857 fp = g_new0(BitProperty, 1); 6858 fp->w = w; 6859 fp->mask = mask; 6860 object_property_add(OBJECT(cpu), prop_name, "bool", 6861 x86_cpu_get_bit_prop, 6862 x86_cpu_set_bit_prop, 6863 x86_cpu_release_bit_prop, fp); 6864 } 6865 } 6866 6867 static void x86_cpu_register_feature_bit_props(X86CPU *cpu, 6868 FeatureWord w, 6869 int bitnr) 6870 { 6871 FeatureWordInfo *fi = &feature_word_info[w]; 6872 const char *name = fi->feat_names[bitnr]; 6873 6874 if (!name) { 6875 return; 6876 } 6877 6878 /* Property names should use "-" instead of "_". 6879 * Old names containing underscores are registered as aliases 6880 * using object_property_add_alias() 6881 */ 6882 assert(!strchr(name, '_')); 6883 /* aliases don't use "|" delimiters anymore, they are registered 6884 * manually using object_property_add_alias() */ 6885 assert(!strchr(name, '|')); 6886 x86_cpu_register_bit_prop(cpu, name, w, bitnr); 6887 } 6888 6889 #if !defined(CONFIG_USER_ONLY) 6890 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs) 6891 { 6892 X86CPU *cpu = X86_CPU(cs); 6893 CPUX86State *env = &cpu->env; 6894 GuestPanicInformation *panic_info = NULL; 6895 6896 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) { 6897 panic_info = g_malloc0(sizeof(GuestPanicInformation)); 6898 6899 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V; 6900 6901 assert(HV_CRASH_PARAMS >= 5); 6902 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0]; 6903 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1]; 6904 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2]; 6905 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3]; 6906 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4]; 6907 } 6908 6909 return panic_info; 6910 } 6911 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, 6912 const char *name, void *opaque, 6913 Error **errp) 6914 { 6915 CPUState *cs = CPU(obj); 6916 GuestPanicInformation *panic_info; 6917 6918 if (!cs->crash_occurred) { 6919 error_setg(errp, "No crash occured"); 6920 return; 6921 } 6922 6923 panic_info = x86_cpu_get_crash_info(cs); 6924 if (panic_info == NULL) { 6925 error_setg(errp, "No crash information"); 6926 return; 6927 } 6928 6929 visit_type_GuestPanicInformation(v, "crash-information", &panic_info, 6930 errp); 6931 qapi_free_GuestPanicInformation(panic_info); 6932 } 6933 #endif /* !CONFIG_USER_ONLY */ 6934 6935 static void x86_cpu_initfn(Object *obj) 6936 { 6937 X86CPU *cpu = X86_CPU(obj); 6938 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6939 CPUX86State *env = &cpu->env; 6940 FeatureWord w; 6941 6942 env->nr_dies = 1; 6943 env->nr_nodes = 1; 6944 cpu_set_cpustate_pointers(cpu); 6945 6946 object_property_add(obj, "family", "int", 6947 x86_cpuid_version_get_family, 6948 x86_cpuid_version_set_family, NULL, NULL); 6949 object_property_add(obj, "model", "int", 6950 x86_cpuid_version_get_model, 6951 x86_cpuid_version_set_model, NULL, NULL); 6952 object_property_add(obj, "stepping", "int", 6953 x86_cpuid_version_get_stepping, 6954 x86_cpuid_version_set_stepping, NULL, NULL); 6955 object_property_add_str(obj, "vendor", 6956 x86_cpuid_get_vendor, 6957 x86_cpuid_set_vendor); 6958 object_property_add_str(obj, "model-id", 6959 x86_cpuid_get_model_id, 6960 x86_cpuid_set_model_id); 6961 object_property_add(obj, "tsc-frequency", "int", 6962 x86_cpuid_get_tsc_freq, 6963 x86_cpuid_set_tsc_freq, NULL, NULL); 6964 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 6965 x86_cpu_get_feature_words, 6966 NULL, NULL, (void *)env->features); 6967 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 6968 x86_cpu_get_feature_words, 6969 NULL, NULL, (void *)cpu->filtered_features); 6970 /* 6971 * The "unavailable-features" property has the same semantics as 6972 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 6973 * QMP command: they list the features that would have prevented the 6974 * CPU from running if the "enforce" flag was set. 6975 */ 6976 object_property_add(obj, "unavailable-features", "strList", 6977 x86_cpu_get_unavailable_features, 6978 NULL, NULL, NULL); 6979 6980 #if !defined(CONFIG_USER_ONLY) 6981 object_property_add(obj, "crash-information", "GuestPanicInformation", 6982 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 6983 #endif 6984 6985 for (w = 0; w < FEATURE_WORDS; w++) { 6986 int bitnr; 6987 6988 for (bitnr = 0; bitnr < 64; bitnr++) { 6989 x86_cpu_register_feature_bit_props(cpu, w, bitnr); 6990 } 6991 } 6992 6993 object_property_add_alias(obj, "sse3", obj, "pni"); 6994 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 6995 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 6996 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 6997 object_property_add_alias(obj, "xd", obj, "nx"); 6998 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 6999 object_property_add_alias(obj, "i64", obj, "lm"); 7000 7001 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 7002 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 7003 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 7004 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 7005 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 7006 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 7007 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 7008 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 7009 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 7010 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 7011 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 7012 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 7013 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 7014 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 7015 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 7016 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 7017 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 7018 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 7019 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 7020 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 7021 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 7022 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 7023 7024 if (xcc->model) { 7025 x86_cpu_load_model(cpu, xcc->model); 7026 } 7027 } 7028 7029 static int64_t x86_cpu_get_arch_id(CPUState *cs) 7030 { 7031 X86CPU *cpu = X86_CPU(cs); 7032 7033 return cpu->apic_id; 7034 } 7035 7036 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 7037 { 7038 X86CPU *cpu = X86_CPU(cs); 7039 7040 return cpu->env.cr[0] & CR0_PG_MASK; 7041 } 7042 7043 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 7044 { 7045 X86CPU *cpu = X86_CPU(cs); 7046 7047 cpu->env.eip = value; 7048 } 7049 7050 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 7051 { 7052 X86CPU *cpu = X86_CPU(cs); 7053 7054 cpu->env.eip = tb->pc - tb->cs_base; 7055 } 7056 7057 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 7058 { 7059 X86CPU *cpu = X86_CPU(cs); 7060 CPUX86State *env = &cpu->env; 7061 7062 #if !defined(CONFIG_USER_ONLY) 7063 if (interrupt_request & CPU_INTERRUPT_POLL) { 7064 return CPU_INTERRUPT_POLL; 7065 } 7066 #endif 7067 if (interrupt_request & CPU_INTERRUPT_SIPI) { 7068 return CPU_INTERRUPT_SIPI; 7069 } 7070 7071 if (env->hflags2 & HF2_GIF_MASK) { 7072 if ((interrupt_request & CPU_INTERRUPT_SMI) && 7073 !(env->hflags & HF_SMM_MASK)) { 7074 return CPU_INTERRUPT_SMI; 7075 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 7076 !(env->hflags2 & HF2_NMI_MASK)) { 7077 return CPU_INTERRUPT_NMI; 7078 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 7079 return CPU_INTERRUPT_MCE; 7080 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 7081 (((env->hflags2 & HF2_VINTR_MASK) && 7082 (env->hflags2 & HF2_HIF_MASK)) || 7083 (!(env->hflags2 & HF2_VINTR_MASK) && 7084 (env->eflags & IF_MASK && 7085 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 7086 return CPU_INTERRUPT_HARD; 7087 #if !defined(CONFIG_USER_ONLY) 7088 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && 7089 (env->eflags & IF_MASK) && 7090 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 7091 return CPU_INTERRUPT_VIRQ; 7092 #endif 7093 } 7094 } 7095 7096 return 0; 7097 } 7098 7099 static bool x86_cpu_has_work(CPUState *cs) 7100 { 7101 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 7102 } 7103 7104 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 7105 { 7106 X86CPU *cpu = X86_CPU(cs); 7107 CPUX86State *env = &cpu->env; 7108 7109 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 7110 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 7111 : bfd_mach_i386_i8086); 7112 info->print_insn = print_insn_i386; 7113 7114 info->cap_arch = CS_ARCH_X86; 7115 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 7116 : env->hflags & HF_CS32_MASK ? CS_MODE_32 7117 : CS_MODE_16); 7118 info->cap_insn_unit = 1; 7119 info->cap_insn_split = 8; 7120 } 7121 7122 void x86_update_hflags(CPUX86State *env) 7123 { 7124 uint32_t hflags; 7125 #define HFLAG_COPY_MASK \ 7126 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7127 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7128 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7129 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7130 7131 hflags = env->hflags & HFLAG_COPY_MASK; 7132 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7133 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7134 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7135 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7136 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7137 7138 if (env->cr[4] & CR4_OSFXSR_MASK) { 7139 hflags |= HF_OSFXSR_MASK; 7140 } 7141 7142 if (env->efer & MSR_EFER_LMA) { 7143 hflags |= HF_LMA_MASK; 7144 } 7145 7146 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7147 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7148 } else { 7149 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7150 (DESC_B_SHIFT - HF_CS32_SHIFT); 7151 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7152 (DESC_B_SHIFT - HF_SS32_SHIFT); 7153 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7154 !(hflags & HF_CS32_MASK)) { 7155 hflags |= HF_ADDSEG_MASK; 7156 } else { 7157 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7158 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7159 } 7160 } 7161 env->hflags = hflags; 7162 } 7163 7164 static Property x86_cpu_properties[] = { 7165 #ifdef CONFIG_USER_ONLY 7166 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7167 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7168 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7169 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7170 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7171 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7172 #else 7173 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7174 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7175 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7176 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7177 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7178 #endif 7179 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7180 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7181 7182 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7183 HYPERV_SPINLOCK_NEVER_RETRY), 7184 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7185 HYPERV_FEAT_RELAXED, 0), 7186 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7187 HYPERV_FEAT_VAPIC, 0), 7188 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7189 HYPERV_FEAT_TIME, 0), 7190 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7191 HYPERV_FEAT_CRASH, 0), 7192 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7193 HYPERV_FEAT_RESET, 0), 7194 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7195 HYPERV_FEAT_VPINDEX, 0), 7196 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7197 HYPERV_FEAT_RUNTIME, 0), 7198 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7199 HYPERV_FEAT_SYNIC, 0), 7200 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7201 HYPERV_FEAT_STIMER, 0), 7202 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 7203 HYPERV_FEAT_FREQUENCIES, 0), 7204 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 7205 HYPERV_FEAT_REENLIGHTENMENT, 0), 7206 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 7207 HYPERV_FEAT_TLBFLUSH, 0), 7208 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 7209 HYPERV_FEAT_EVMCS, 0), 7210 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 7211 HYPERV_FEAT_IPI, 0), 7212 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 7213 HYPERV_FEAT_STIMER_DIRECT, 0), 7214 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 7215 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 7216 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 7217 7218 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 7219 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 7220 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 7221 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 7222 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 7223 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 7224 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 7225 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 7226 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 7227 UINT32_MAX), 7228 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 7229 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 7230 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 7231 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7232 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7233 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7234 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7235 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7236 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), 7237 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 7238 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 7239 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 7240 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 7241 false), 7242 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 7243 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 7244 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 7245 true), 7246 /* 7247 * lecacy_cache defaults to true unless the CPU model provides its 7248 * own cache information (see x86_cpu_load_def()). 7249 */ 7250 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 7251 7252 /* 7253 * From "Requirements for Implementing the Microsoft 7254 * Hypervisor Interface": 7255 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7256 * 7257 * "Starting with Windows Server 2012 and Windows 8, if 7258 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 7259 * the hypervisor imposes no specific limit to the number of VPs. 7260 * In this case, Windows Server 2012 guest VMs may use more than 7261 * 64 VPs, up to the maximum supported number of processors applicable 7262 * to the specific Windows version being used." 7263 */ 7264 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 7265 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 7266 false), 7267 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 7268 true), 7269 DEFINE_PROP_END_OF_LIST() 7270 }; 7271 7272 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 7273 { 7274 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7275 CPUClass *cc = CPU_CLASS(oc); 7276 DeviceClass *dc = DEVICE_CLASS(oc); 7277 7278 device_class_set_parent_realize(dc, x86_cpu_realizefn, 7279 &xcc->parent_realize); 7280 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7281 &xcc->parent_unrealize); 7282 device_class_set_props(dc, x86_cpu_properties); 7283 7284 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset); 7285 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7286 7287 cc->class_by_name = x86_cpu_class_by_name; 7288 cc->parse_features = x86_cpu_parse_featurestr; 7289 cc->has_work = x86_cpu_has_work; 7290 #ifdef CONFIG_TCG 7291 cc->do_interrupt = x86_cpu_do_interrupt; 7292 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt; 7293 #endif 7294 cc->dump_state = x86_cpu_dump_state; 7295 cc->set_pc = x86_cpu_set_pc; 7296 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; 7297 cc->gdb_read_register = x86_cpu_gdb_read_register; 7298 cc->gdb_write_register = x86_cpu_gdb_write_register; 7299 cc->get_arch_id = x86_cpu_get_arch_id; 7300 cc->get_paging_enabled = x86_cpu_get_paging_enabled; 7301 #ifndef CONFIG_USER_ONLY 7302 cc->asidx_from_attrs = x86_asidx_from_attrs; 7303 cc->get_memory_mapping = x86_cpu_get_memory_mapping; 7304 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug; 7305 cc->get_crash_info = x86_cpu_get_crash_info; 7306 cc->write_elf64_note = x86_cpu_write_elf64_note; 7307 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote; 7308 cc->write_elf32_note = x86_cpu_write_elf32_note; 7309 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote; 7310 cc->vmsd = &vmstate_x86_cpu; 7311 #endif 7312 cc->gdb_arch_name = x86_gdb_arch_name; 7313 #ifdef TARGET_X86_64 7314 cc->gdb_core_xml_file = "i386-64bit.xml"; 7315 cc->gdb_num_core_regs = 66; 7316 #else 7317 cc->gdb_core_xml_file = "i386-32bit.xml"; 7318 cc->gdb_num_core_regs = 50; 7319 #endif 7320 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7321 cc->debug_excp_handler = breakpoint_handler; 7322 #endif 7323 cc->cpu_exec_enter = x86_cpu_exec_enter; 7324 cc->cpu_exec_exit = x86_cpu_exec_exit; 7325 #ifdef CONFIG_TCG 7326 cc->tcg_initialize = tcg_x86_init; 7327 cc->tlb_fill = x86_cpu_tlb_fill; 7328 #endif 7329 cc->disas_set_info = x86_disas_set_info; 7330 7331 dc->user_creatable = true; 7332 } 7333 7334 static const TypeInfo x86_cpu_type_info = { 7335 .name = TYPE_X86_CPU, 7336 .parent = TYPE_CPU, 7337 .instance_size = sizeof(X86CPU), 7338 .instance_init = x86_cpu_initfn, 7339 .abstract = true, 7340 .class_size = sizeof(X86CPUClass), 7341 .class_init = x86_cpu_common_class_init, 7342 }; 7343 7344 7345 /* "base" CPU model, used by query-cpu-model-expansion */ 7346 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 7347 { 7348 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7349 7350 xcc->static_model = true; 7351 xcc->migration_safe = true; 7352 xcc->model_description = "base CPU model type with no features enabled"; 7353 xcc->ordering = 8; 7354 } 7355 7356 static const TypeInfo x86_base_cpu_type_info = { 7357 .name = X86_CPU_TYPE_NAME("base"), 7358 .parent = TYPE_X86_CPU, 7359 .class_init = x86_cpu_base_class_init, 7360 }; 7361 7362 static void x86_cpu_register_types(void) 7363 { 7364 int i; 7365 7366 type_register_static(&x86_cpu_type_info); 7367 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 7368 x86_register_cpudef_types(&builtin_x86_defs[i]); 7369 } 7370 type_register_static(&max_x86_cpu_type_info); 7371 type_register_static(&x86_base_cpu_type_info); 7372 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 7373 type_register_static(&host_x86_cpu_type_info); 7374 #endif 7375 } 7376 7377 type_init(x86_cpu_register_types) 7378