1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "system/reset.h" 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 51 uint32_t *eax, uint32_t *ebx, 52 uint32_t *ecx, uint32_t *edx); 53 54 /* Helpers for building CPUID[2] descriptors: */ 55 56 struct CPUID2CacheDescriptorInfo { 57 enum CacheType type; 58 int level; 59 int size; 60 int line_size; 61 int associativity; 62 }; 63 64 /* 65 * Known CPUID 2 cache descriptors. 66 * From Intel SDM Volume 2A, CPUID instruction 67 */ 68 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 69 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 70 .associativity = 4, .line_size = 32, }, 71 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 72 .associativity = 4, .line_size = 32, }, 73 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 74 .associativity = 4, .line_size = 64, }, 75 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 76 .associativity = 2, .line_size = 32, }, 77 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 78 .associativity = 4, .line_size = 32, }, 79 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 80 .associativity = 4, .line_size = 64, }, 81 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 82 .associativity = 6, .line_size = 64, }, 83 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 84 .associativity = 2, .line_size = 64, }, 85 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 86 .associativity = 8, .line_size = 64, }, 87 /* lines per sector is not supported cpuid2_cache_descriptor(), 88 * so descriptors 0x22, 0x23 are not included 89 */ 90 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 91 .associativity = 16, .line_size = 64, }, 92 /* lines per sector is not supported cpuid2_cache_descriptor(), 93 * so descriptors 0x25, 0x20 are not included 94 */ 95 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 96 .associativity = 8, .line_size = 64, }, 97 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 98 .associativity = 8, .line_size = 64, }, 99 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 100 .associativity = 4, .line_size = 32, }, 101 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 106 .associativity = 4, .line_size = 32, }, 107 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 108 .associativity = 4, .line_size = 32, }, 109 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 110 .associativity = 4, .line_size = 64, }, 111 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 112 .associativity = 8, .line_size = 64, }, 113 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 116 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 119 .associativity = 16, .line_size = 64, }, 120 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 121 .associativity = 12, .line_size = 64, }, 122 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 123 .associativity = 16, .line_size = 64, }, 124 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 125 .associativity = 24, .line_size = 64, }, 126 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 127 .associativity = 8, .line_size = 64, }, 128 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 129 .associativity = 4, .line_size = 64, }, 130 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 131 .associativity = 4, .line_size = 64, }, 132 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 133 .associativity = 4, .line_size = 64, }, 134 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 135 .associativity = 4, .line_size = 64, }, 136 /* lines per sector is not supported cpuid2_cache_descriptor(), 137 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 138 */ 139 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 140 .associativity = 8, .line_size = 64, }, 141 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 142 .associativity = 2, .line_size = 64, }, 143 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 8, .line_size = 64, }, 145 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 146 .associativity = 8, .line_size = 32, }, 147 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 150 .associativity = 8, .line_size = 32, }, 151 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 152 .associativity = 8, .line_size = 32, }, 153 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 4, .line_size = 64, }, 155 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 156 .associativity = 8, .line_size = 64, }, 157 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 158 .associativity = 4, .line_size = 64, }, 159 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 4, .line_size = 64, }, 161 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 4, .line_size = 64, }, 163 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 164 .associativity = 8, .line_size = 64, }, 165 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 166 .associativity = 8, .line_size = 64, }, 167 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 168 .associativity = 8, .line_size = 64, }, 169 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 170 .associativity = 12, .line_size = 64, }, 171 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 172 .associativity = 12, .line_size = 64, }, 173 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 174 .associativity = 12, .line_size = 64, }, 175 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 176 .associativity = 16, .line_size = 64, }, 177 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 178 .associativity = 16, .line_size = 64, }, 179 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 180 .associativity = 16, .line_size = 64, }, 181 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 182 .associativity = 24, .line_size = 64, }, 183 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 184 .associativity = 24, .line_size = 64, }, 185 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 186 .associativity = 24, .line_size = 64, }, 187 }; 188 189 /* 190 * "CPUID leaf 2 does not report cache descriptor information, 191 * use CPUID leaf 4 to query cache parameters" 192 */ 193 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 194 195 /* 196 * Return a CPUID 2 cache descriptor for a given cache. 197 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 198 */ 199 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 200 { 201 int i; 202 203 assert(cache->size > 0); 204 assert(cache->level > 0); 205 assert(cache->line_size > 0); 206 assert(cache->associativity > 0); 207 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 208 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 209 if (d->level == cache->level && d->type == cache->type && 210 d->size == cache->size && d->line_size == cache->line_size && 211 d->associativity == cache->associativity) { 212 return i; 213 } 214 } 215 216 return CACHE_DESCRIPTOR_UNAVAILABLE; 217 } 218 219 /* CPUID Leaf 4 constants: */ 220 221 /* EAX: */ 222 #define CACHE_TYPE_D 1 223 #define CACHE_TYPE_I 2 224 #define CACHE_TYPE_UNIFIED 3 225 226 #define CACHE_LEVEL(l) (l << 5) 227 228 #define CACHE_SELF_INIT_LEVEL (1 << 8) 229 230 /* EDX: */ 231 #define CACHE_NO_INVD_SHARING (1 << 0) 232 #define CACHE_INCLUSIVE (1 << 1) 233 #define CACHE_COMPLEX_IDX (1 << 2) 234 235 /* Encode CacheType for CPUID[4].EAX */ 236 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 237 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 238 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 239 0 /* Invalid value */) 240 241 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 242 enum CpuTopologyLevel share_level) 243 { 244 uint32_t num_ids = 0; 245 246 switch (share_level) { 247 case CPU_TOPOLOGY_LEVEL_CORE: 248 num_ids = 1 << apicid_core_offset(topo_info); 249 break; 250 case CPU_TOPOLOGY_LEVEL_DIE: 251 num_ids = 1 << apicid_die_offset(topo_info); 252 break; 253 case CPU_TOPOLOGY_LEVEL_SOCKET: 254 num_ids = 1 << apicid_pkg_offset(topo_info); 255 break; 256 default: 257 /* 258 * Currently there is no use case for THREAD and MODULE, so use 259 * assert directly to facilitate debugging. 260 */ 261 g_assert_not_reached(); 262 } 263 264 return num_ids - 1; 265 } 266 267 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 268 { 269 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 270 apicid_core_offset(topo_info)); 271 return num_cores - 1; 272 } 273 274 /* Encode cache info for CPUID[4] */ 275 static void encode_cache_cpuid4(CPUCacheInfo *cache, 276 X86CPUTopoInfo *topo_info, 277 uint32_t *eax, uint32_t *ebx, 278 uint32_t *ecx, uint32_t *edx) 279 { 280 assert(cache->size == cache->line_size * cache->associativity * 281 cache->partitions * cache->sets); 282 283 *eax = CACHE_TYPE(cache->type) | 284 CACHE_LEVEL(cache->level) | 285 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 286 (max_core_ids_in_package(topo_info) << 26) | 287 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 288 289 assert(cache->line_size > 0); 290 assert(cache->partitions > 0); 291 assert(cache->associativity > 0); 292 /* We don't implement fully-associative caches */ 293 assert(cache->associativity < cache->sets); 294 *ebx = (cache->line_size - 1) | 295 ((cache->partitions - 1) << 12) | 296 ((cache->associativity - 1) << 22); 297 298 assert(cache->sets > 0); 299 *ecx = cache->sets - 1; 300 301 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 302 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 303 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 304 } 305 306 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 307 enum CpuTopologyLevel topo_level) 308 { 309 switch (topo_level) { 310 case CPU_TOPOLOGY_LEVEL_THREAD: 311 return 1; 312 case CPU_TOPOLOGY_LEVEL_CORE: 313 return topo_info->threads_per_core; 314 case CPU_TOPOLOGY_LEVEL_MODULE: 315 return topo_info->threads_per_core * topo_info->cores_per_module; 316 case CPU_TOPOLOGY_LEVEL_DIE: 317 return topo_info->threads_per_core * topo_info->cores_per_module * 318 topo_info->modules_per_die; 319 case CPU_TOPOLOGY_LEVEL_SOCKET: 320 return topo_info->threads_per_core * topo_info->cores_per_module * 321 topo_info->modules_per_die * topo_info->dies_per_pkg; 322 default: 323 g_assert_not_reached(); 324 } 325 return 0; 326 } 327 328 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 329 enum CpuTopologyLevel topo_level) 330 { 331 switch (topo_level) { 332 case CPU_TOPOLOGY_LEVEL_THREAD: 333 return 0; 334 case CPU_TOPOLOGY_LEVEL_CORE: 335 return apicid_core_offset(topo_info); 336 case CPU_TOPOLOGY_LEVEL_MODULE: 337 return apicid_module_offset(topo_info); 338 case CPU_TOPOLOGY_LEVEL_DIE: 339 return apicid_die_offset(topo_info); 340 case CPU_TOPOLOGY_LEVEL_SOCKET: 341 return apicid_pkg_offset(topo_info); 342 default: 343 g_assert_not_reached(); 344 } 345 return 0; 346 } 347 348 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 349 { 350 switch (topo_level) { 351 case CPU_TOPOLOGY_LEVEL_INVALID: 352 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 353 case CPU_TOPOLOGY_LEVEL_THREAD: 354 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 355 case CPU_TOPOLOGY_LEVEL_CORE: 356 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 357 case CPU_TOPOLOGY_LEVEL_MODULE: 358 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 359 case CPU_TOPOLOGY_LEVEL_DIE: 360 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 361 default: 362 /* Other types are not supported in QEMU. */ 363 g_assert_not_reached(); 364 } 365 return 0; 366 } 367 368 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 369 X86CPUTopoInfo *topo_info, 370 uint32_t *eax, uint32_t *ebx, 371 uint32_t *ecx, uint32_t *edx) 372 { 373 X86CPU *cpu = env_archcpu(env); 374 unsigned long level, base_level, next_level; 375 uint32_t num_threads_next_level, offset_next_level; 376 377 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 378 379 /* 380 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 381 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 382 */ 383 level = CPU_TOPOLOGY_LEVEL_THREAD; 384 base_level = level; 385 for (int i = 0; i <= count; i++) { 386 level = find_next_bit(env->avail_cpu_topo, 387 CPU_TOPOLOGY_LEVEL_SOCKET, 388 base_level); 389 390 /* 391 * CPUID[0x1f] doesn't explicitly encode the package level, 392 * and it just encodes the invalid level (all fields are 0) 393 * into the last subleaf of 0x1f. 394 */ 395 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 396 level = CPU_TOPOLOGY_LEVEL_INVALID; 397 break; 398 } 399 /* Search the next level. */ 400 base_level = level + 1; 401 } 402 403 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 404 num_threads_next_level = 0; 405 offset_next_level = 0; 406 } else { 407 next_level = find_next_bit(env->avail_cpu_topo, 408 CPU_TOPOLOGY_LEVEL_SOCKET, 409 level + 1); 410 num_threads_next_level = num_threads_by_topo_level(topo_info, 411 next_level); 412 offset_next_level = apicid_offset_by_topo_level(topo_info, 413 next_level); 414 } 415 416 *eax = offset_next_level; 417 /* The count (bits 15-00) doesn't need to be reliable. */ 418 *ebx = num_threads_next_level & 0xffff; 419 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 420 *edx = cpu->apic_id; 421 422 assert(!(*eax & ~0x1f)); 423 } 424 425 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 426 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 427 { 428 assert(cache->size % 1024 == 0); 429 assert(cache->lines_per_tag > 0); 430 assert(cache->associativity > 0); 431 assert(cache->line_size > 0); 432 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 433 (cache->lines_per_tag << 8) | (cache->line_size); 434 } 435 436 #define ASSOC_FULL 0xFF 437 438 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 439 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 440 a == 2 ? 0x2 : \ 441 a == 4 ? 0x4 : \ 442 a == 8 ? 0x6 : \ 443 a == 16 ? 0x8 : \ 444 a == 32 ? 0xA : \ 445 a == 48 ? 0xB : \ 446 a == 64 ? 0xC : \ 447 a == 96 ? 0xD : \ 448 a == 128 ? 0xE : \ 449 a == ASSOC_FULL ? 0xF : \ 450 0 /* invalid value */) 451 452 /* 453 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 454 * @l3 can be NULL. 455 */ 456 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 457 CPUCacheInfo *l3, 458 uint32_t *ecx, uint32_t *edx) 459 { 460 assert(l2->size % 1024 == 0); 461 assert(l2->associativity > 0); 462 assert(l2->lines_per_tag > 0); 463 assert(l2->line_size > 0); 464 *ecx = ((l2->size / 1024) << 16) | 465 (AMD_ENC_ASSOC(l2->associativity) << 12) | 466 (l2->lines_per_tag << 8) | (l2->line_size); 467 468 if (l3) { 469 assert(l3->size % (512 * 1024) == 0); 470 assert(l3->associativity > 0); 471 assert(l3->lines_per_tag > 0); 472 assert(l3->line_size > 0); 473 *edx = ((l3->size / (512 * 1024)) << 18) | 474 (AMD_ENC_ASSOC(l3->associativity) << 12) | 475 (l3->lines_per_tag << 8) | (l3->line_size); 476 } else { 477 *edx = 0; 478 } 479 } 480 481 /* Encode cache info for CPUID[8000001D] */ 482 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 483 X86CPUTopoInfo *topo_info, 484 uint32_t *eax, uint32_t *ebx, 485 uint32_t *ecx, uint32_t *edx) 486 { 487 assert(cache->size == cache->line_size * cache->associativity * 488 cache->partitions * cache->sets); 489 490 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 491 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 492 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 493 494 assert(cache->line_size > 0); 495 assert(cache->partitions > 0); 496 assert(cache->associativity > 0); 497 /* We don't implement fully-associative caches */ 498 assert(cache->associativity < cache->sets); 499 *ebx = (cache->line_size - 1) | 500 ((cache->partitions - 1) << 12) | 501 ((cache->associativity - 1) << 22); 502 503 assert(cache->sets > 0); 504 *ecx = cache->sets - 1; 505 506 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 507 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 508 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 509 } 510 511 /* Encode cache info for CPUID[8000001E] */ 512 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 513 uint32_t *eax, uint32_t *ebx, 514 uint32_t *ecx, uint32_t *edx) 515 { 516 X86CPUTopoIDs topo_ids; 517 518 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 519 520 *eax = cpu->apic_id; 521 522 /* 523 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 524 * Read-only. Reset: 0000_XXXXh. 525 * See Core::X86::Cpuid::ExtApicId. 526 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 527 * Bits Description 528 * 31:16 Reserved. 529 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 530 * The number of threads per core is ThreadsPerCore+1. 531 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 532 * 533 * NOTE: CoreId is already part of apic_id. Just use it. We can 534 * use all the 8 bits to represent the core_id here. 535 */ 536 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 537 538 /* 539 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 540 * Read-only. Reset: 0000_0XXXh. 541 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 542 * Bits Description 543 * 31:11 Reserved. 544 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 545 * ValidValues: 546 * Value Description 547 * 0h 1 node per processor. 548 * 7h-1h Reserved. 549 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 550 * 551 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 552 * But users can create more nodes than the actual hardware can 553 * support. To genaralize we can use all the upper 8 bits for nodes. 554 * NodeId is combination of node and socket_id which is already decoded 555 * in apic_id. Just use it by shifting. 556 */ 557 if (cpu->legacy_multi_node) { 558 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 559 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 560 } else { 561 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 562 } 563 564 *edx = 0; 565 } 566 567 /* 568 * Definitions of the hardcoded cache entries we expose: 569 * These are legacy cache values. If there is a need to change any 570 * of these values please use builtin_x86_defs 571 */ 572 573 /* L1 data cache: */ 574 static CPUCacheInfo legacy_l1d_cache = { 575 .type = DATA_CACHE, 576 .level = 1, 577 .size = 32 * KiB, 578 .self_init = 1, 579 .line_size = 64, 580 .associativity = 8, 581 .sets = 64, 582 .partitions = 1, 583 .no_invd_sharing = true, 584 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 585 }; 586 587 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 588 static CPUCacheInfo legacy_l1d_cache_amd = { 589 .type = DATA_CACHE, 590 .level = 1, 591 .size = 64 * KiB, 592 .self_init = 1, 593 .line_size = 64, 594 .associativity = 2, 595 .sets = 512, 596 .partitions = 1, 597 .lines_per_tag = 1, 598 .no_invd_sharing = true, 599 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 600 }; 601 602 /* L1 instruction cache: */ 603 static CPUCacheInfo legacy_l1i_cache = { 604 .type = INSTRUCTION_CACHE, 605 .level = 1, 606 .size = 32 * KiB, 607 .self_init = 1, 608 .line_size = 64, 609 .associativity = 8, 610 .sets = 64, 611 .partitions = 1, 612 .no_invd_sharing = true, 613 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 614 }; 615 616 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 617 static CPUCacheInfo legacy_l1i_cache_amd = { 618 .type = INSTRUCTION_CACHE, 619 .level = 1, 620 .size = 64 * KiB, 621 .self_init = 1, 622 .line_size = 64, 623 .associativity = 2, 624 .sets = 512, 625 .partitions = 1, 626 .lines_per_tag = 1, 627 .no_invd_sharing = true, 628 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 629 }; 630 631 /* Level 2 unified cache: */ 632 static CPUCacheInfo legacy_l2_cache = { 633 .type = UNIFIED_CACHE, 634 .level = 2, 635 .size = 4 * MiB, 636 .self_init = 1, 637 .line_size = 64, 638 .associativity = 16, 639 .sets = 4096, 640 .partitions = 1, 641 .no_invd_sharing = true, 642 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 643 }; 644 645 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 646 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 647 .type = UNIFIED_CACHE, 648 .level = 2, 649 .size = 2 * MiB, 650 .line_size = 64, 651 .associativity = 8, 652 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 653 }; 654 655 656 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 657 static CPUCacheInfo legacy_l2_cache_amd = { 658 .type = UNIFIED_CACHE, 659 .level = 2, 660 .size = 512 * KiB, 661 .line_size = 64, 662 .lines_per_tag = 1, 663 .associativity = 16, 664 .sets = 512, 665 .partitions = 1, 666 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 667 }; 668 669 /* Level 3 unified cache: */ 670 static CPUCacheInfo legacy_l3_cache = { 671 .type = UNIFIED_CACHE, 672 .level = 3, 673 .size = 16 * MiB, 674 .line_size = 64, 675 .associativity = 16, 676 .sets = 16384, 677 .partitions = 1, 678 .lines_per_tag = 1, 679 .self_init = true, 680 .inclusive = true, 681 .complex_indexing = true, 682 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 683 }; 684 685 /* TLB definitions: */ 686 687 #define L1_DTLB_2M_ASSOC 1 688 #define L1_DTLB_2M_ENTRIES 255 689 #define L1_DTLB_4K_ASSOC 1 690 #define L1_DTLB_4K_ENTRIES 255 691 692 #define L1_ITLB_2M_ASSOC 1 693 #define L1_ITLB_2M_ENTRIES 255 694 #define L1_ITLB_4K_ASSOC 1 695 #define L1_ITLB_4K_ENTRIES 255 696 697 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 698 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 699 #define L2_DTLB_4K_ASSOC 4 700 #define L2_DTLB_4K_ENTRIES 512 701 702 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 703 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 704 #define L2_ITLB_4K_ASSOC 4 705 #define L2_ITLB_4K_ENTRIES 512 706 707 /* CPUID Leaf 0x14 constants: */ 708 #define INTEL_PT_MAX_SUBLEAF 0x1 709 /* 710 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 711 * MSR can be accessed; 712 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 713 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 714 * of Intel PT MSRs across warm reset; 715 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 716 */ 717 #define INTEL_PT_MINIMAL_EBX 0xf 718 /* 719 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 720 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 721 * accessed; 722 * bit[01]: ToPA tables can hold any number of output entries, up to the 723 * maximum allowed by the MaskOrTableOffset field of 724 * IA32_RTIT_OUTPUT_MASK_PTRS; 725 * bit[02]: Support Single-Range Output scheme; 726 */ 727 #define INTEL_PT_MINIMAL_ECX 0x7 728 /* generated packets which contain IP payloads have LIP values */ 729 #define INTEL_PT_IP_LIP (1 << 31) 730 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 731 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 732 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 733 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 734 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 735 736 /* CPUID Leaf 0x1D constants: */ 737 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 738 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 739 #define INTEL_AMX_BYTES_PER_TILE 0x400 740 #define INTEL_AMX_BYTES_PER_ROW 0x40 741 #define INTEL_AMX_TILE_MAX_NAMES 0x8 742 #define INTEL_AMX_TILE_MAX_ROWS 0x10 743 744 /* CPUID Leaf 0x1E constants: */ 745 #define INTEL_AMX_TMUL_MAX_K 0x10 746 #define INTEL_AMX_TMUL_MAX_N 0x40 747 748 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 749 uint32_t vendor2, uint32_t vendor3) 750 { 751 int i; 752 for (i = 0; i < 4; i++) { 753 dst[i] = vendor1 >> (8 * i); 754 dst[i + 4] = vendor2 >> (8 * i); 755 dst[i + 8] = vendor3 >> (8 * i); 756 } 757 dst[CPUID_VENDOR_SZ] = '\0'; 758 } 759 760 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 761 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 762 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 763 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 764 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 765 CPUID_PSE36 | CPUID_FXSR) 766 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 767 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 768 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 769 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 770 CPUID_PAE | CPUID_SEP | CPUID_APIC) 771 772 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 773 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 774 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 775 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 776 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 777 /* partly implemented: 778 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 779 /* missing: 780 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 781 782 /* 783 * Kernel-only features that can be shown to usermode programs even if 784 * they aren't actually supported by TCG, because qemu-user only runs 785 * in CPL=3; remove them if they are ever implemented for system emulation. 786 */ 787 #if defined CONFIG_USER_ONLY 788 #define CPUID_EXT_KERNEL_FEATURES \ 789 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 790 #else 791 #define CPUID_EXT_KERNEL_FEATURES 0 792 #endif 793 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 794 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 795 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 796 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 797 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 798 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 799 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 800 /* missing: 801 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 802 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 803 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 804 CPUID_EXT_TSC_DEADLINE_TIMER 805 */ 806 807 #ifdef TARGET_X86_64 808 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 809 #else 810 #define TCG_EXT2_X86_64_FEATURES 0 811 #endif 812 813 /* 814 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 815 * in usermode or by 32-bit programs. Those are added to supported 816 * TCG features unconditionally in user-mode emulation mode. This may 817 * indeed seem strange or incorrect, but it works because code running 818 * under usermode emulation cannot access them. 819 * 820 * Even for long mode, qemu-i386 is not running "a userspace program on a 821 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 822 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 823 * but again the difference is only visible in kernel mode. 824 */ 825 #if defined CONFIG_LINUX_USER 826 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 827 #elif defined CONFIG_USER_ONLY 828 /* FIXME: Long mode not yet supported for i386 bsd-user */ 829 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 830 #else 831 #define CPUID_EXT2_KERNEL_FEATURES 0 832 #endif 833 834 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 835 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 836 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 837 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 838 CPUID_EXT2_KERNEL_FEATURES) 839 840 #if defined CONFIG_USER_ONLY 841 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 842 #else 843 #define CPUID_EXT3_KERNEL_FEATURES 0 844 #endif 845 846 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 847 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 848 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 849 850 #define TCG_EXT4_FEATURES 0 851 852 #if defined CONFIG_USER_ONLY 853 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 854 #else 855 #define CPUID_SVM_KERNEL_FEATURES 0 856 #endif 857 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 858 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 859 860 #define TCG_KVM_FEATURES 0 861 862 #if defined CONFIG_USER_ONLY 863 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 864 #else 865 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 866 #endif 867 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 868 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 869 CPUID_7_0_EBX_CLFLUSHOPT | \ 870 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 871 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 872 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 873 /* missing: 874 CPUID_7_0_EBX_HLE 875 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 876 877 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 878 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 879 #else 880 #define TCG_7_0_ECX_RDPID 0 881 #endif 882 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 883 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 884 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 885 TCG_7_0_ECX_RDPID) 886 887 #if defined CONFIG_USER_ONLY 888 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 889 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 890 #else 891 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 892 #endif 893 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 894 895 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 896 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 897 #define TCG_7_1_EDX_FEATURES 0 898 #define TCG_7_2_EDX_FEATURES 0 899 #define TCG_APM_FEATURES 0 900 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 901 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 902 /* missing: 903 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 904 #define TCG_14_0_ECX_FEATURES 0 905 #define TCG_SGX_12_0_EAX_FEATURES 0 906 #define TCG_SGX_12_0_EBX_FEATURES 0 907 #define TCG_SGX_12_1_EAX_FEATURES 0 908 #define TCG_24_0_EBX_FEATURES 0 909 910 #if defined CONFIG_USER_ONLY 911 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 912 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 913 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 914 CPUID_8000_0008_EBX_AMD_PSFD) 915 #else 916 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 917 #endif 918 919 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 920 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 921 922 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 923 [FEAT_1_EDX] = { 924 .type = CPUID_FEATURE_WORD, 925 .feat_names = { 926 "fpu", "vme", "de", "pse", 927 "tsc", "msr", "pae", "mce", 928 "cx8", "apic", NULL, "sep", 929 "mtrr", "pge", "mca", "cmov", 930 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 931 NULL, "ds" /* Intel dts */, "acpi", "mmx", 932 "fxsr", "sse", "sse2", "ss", 933 "ht" /* Intel htt */, "tm", "ia64", "pbe", 934 }, 935 .cpuid = {.eax = 1, .reg = R_EDX, }, 936 .tcg_features = TCG_FEATURES, 937 .no_autoenable_flags = CPUID_HT, 938 }, 939 [FEAT_1_ECX] = { 940 .type = CPUID_FEATURE_WORD, 941 .feat_names = { 942 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 943 "ds-cpl", "vmx", "smx", "est", 944 "tm2", "ssse3", "cid", NULL, 945 "fma", "cx16", "xtpr", "pdcm", 946 NULL, "pcid", "dca", "sse4.1", 947 "sse4.2", "x2apic", "movbe", "popcnt", 948 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 949 "avx", "f16c", "rdrand", "hypervisor", 950 }, 951 .cpuid = { .eax = 1, .reg = R_ECX, }, 952 .tcg_features = TCG_EXT_FEATURES, 953 }, 954 /* Feature names that are already defined on feature_name[] but 955 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 956 * names on feat_names below. They are copied automatically 957 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 958 */ 959 [FEAT_8000_0001_EDX] = { 960 .type = CPUID_FEATURE_WORD, 961 .feat_names = { 962 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 963 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 964 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 965 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 966 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 967 "nx", NULL, "mmxext", NULL /* mmx */, 968 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 969 NULL, "lm", "3dnowext", "3dnow", 970 }, 971 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 972 .tcg_features = TCG_EXT2_FEATURES, 973 }, 974 [FEAT_8000_0001_ECX] = { 975 .type = CPUID_FEATURE_WORD, 976 .feat_names = { 977 "lahf-lm", "cmp-legacy", "svm", "extapic", 978 "cr8legacy", "abm", "sse4a", "misalignsse", 979 "3dnowprefetch", "osvw", "ibs", "xop", 980 "skinit", "wdt", NULL, "lwp", 981 "fma4", "tce", NULL, "nodeid-msr", 982 NULL, "tbm", "topoext", "perfctr-core", 983 "perfctr-nb", NULL, NULL, NULL, 984 NULL, NULL, NULL, NULL, 985 }, 986 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 987 .tcg_features = TCG_EXT3_FEATURES, 988 /* 989 * TOPOEXT is always allowed but can't be enabled blindly by 990 * "-cpu host", as it requires consistent cache topology info 991 * to be provided so it doesn't confuse guests. 992 */ 993 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 994 }, 995 [FEAT_C000_0001_EDX] = { 996 .type = CPUID_FEATURE_WORD, 997 .feat_names = { 998 NULL, NULL, "xstore", "xstore-en", 999 NULL, NULL, "xcrypt", "xcrypt-en", 1000 "ace2", "ace2-en", "phe", "phe-en", 1001 "pmm", "pmm-en", NULL, NULL, 1002 NULL, NULL, NULL, NULL, 1003 NULL, NULL, NULL, NULL, 1004 NULL, NULL, NULL, NULL, 1005 NULL, NULL, NULL, NULL, 1006 }, 1007 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1008 .tcg_features = TCG_EXT4_FEATURES, 1009 }, 1010 [FEAT_KVM] = { 1011 .type = CPUID_FEATURE_WORD, 1012 .feat_names = { 1013 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1014 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1015 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1016 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1017 NULL, NULL, NULL, NULL, 1018 NULL, NULL, NULL, NULL, 1019 "kvmclock-stable-bit", NULL, NULL, NULL, 1020 NULL, NULL, NULL, NULL, 1021 }, 1022 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1023 .tcg_features = TCG_KVM_FEATURES, 1024 }, 1025 [FEAT_KVM_HINTS] = { 1026 .type = CPUID_FEATURE_WORD, 1027 .feat_names = { 1028 "kvm-hint-dedicated", NULL, NULL, NULL, 1029 NULL, NULL, NULL, NULL, 1030 NULL, NULL, NULL, NULL, 1031 NULL, NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 NULL, NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 NULL, NULL, NULL, NULL, 1036 }, 1037 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1038 .tcg_features = TCG_KVM_FEATURES, 1039 /* 1040 * KVM hints aren't auto-enabled by -cpu host, they need to be 1041 * explicitly enabled in the command-line. 1042 */ 1043 .no_autoenable_flags = ~0U, 1044 }, 1045 [FEAT_SVM] = { 1046 .type = CPUID_FEATURE_WORD, 1047 .feat_names = { 1048 "npt", "lbrv", "svm-lock", "nrip-save", 1049 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1050 NULL, NULL, "pause-filter", NULL, 1051 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1052 "vgif", NULL, NULL, NULL, 1053 NULL, NULL, NULL, NULL, 1054 NULL, "vnmi", NULL, NULL, 1055 "svme-addr-chk", NULL, NULL, NULL, 1056 }, 1057 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1058 .tcg_features = TCG_SVM_FEATURES, 1059 }, 1060 [FEAT_7_0_EBX] = { 1061 .type = CPUID_FEATURE_WORD, 1062 .feat_names = { 1063 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1064 "hle", "avx2", "fdp-excptn-only", "smep", 1065 "bmi2", "erms", "invpcid", "rtm", 1066 NULL, "zero-fcs-fds", "mpx", NULL, 1067 "avx512f", "avx512dq", "rdseed", "adx", 1068 "smap", "avx512ifma", "pcommit", "clflushopt", 1069 "clwb", "intel-pt", "avx512pf", "avx512er", 1070 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1071 }, 1072 .cpuid = { 1073 .eax = 7, 1074 .needs_ecx = true, .ecx = 0, 1075 .reg = R_EBX, 1076 }, 1077 .tcg_features = TCG_7_0_EBX_FEATURES, 1078 }, 1079 [FEAT_7_0_ECX] = { 1080 .type = CPUID_FEATURE_WORD, 1081 .feat_names = { 1082 NULL, "avx512vbmi", "umip", "pku", 1083 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1084 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1085 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1086 "la57", NULL, NULL, NULL, 1087 NULL, NULL, "rdpid", NULL, 1088 "bus-lock-detect", "cldemote", NULL, "movdiri", 1089 "movdir64b", NULL, "sgxlc", "pks", 1090 }, 1091 .cpuid = { 1092 .eax = 7, 1093 .needs_ecx = true, .ecx = 0, 1094 .reg = R_ECX, 1095 }, 1096 .tcg_features = TCG_7_0_ECX_FEATURES, 1097 }, 1098 [FEAT_7_0_EDX] = { 1099 .type = CPUID_FEATURE_WORD, 1100 .feat_names = { 1101 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1102 "fsrm", NULL, NULL, NULL, 1103 "avx512-vp2intersect", NULL, "md-clear", NULL, 1104 NULL, NULL, "serialize", NULL, 1105 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1106 NULL, NULL, "amx-bf16", "avx512-fp16", 1107 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1108 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1109 }, 1110 .cpuid = { 1111 .eax = 7, 1112 .needs_ecx = true, .ecx = 0, 1113 .reg = R_EDX, 1114 }, 1115 .tcg_features = TCG_7_0_EDX_FEATURES, 1116 }, 1117 [FEAT_7_1_EAX] = { 1118 .type = CPUID_FEATURE_WORD, 1119 .feat_names = { 1120 "sha512", "sm3", "sm4", NULL, 1121 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1122 NULL, NULL, "fzrm", "fsrs", 1123 "fsrc", NULL, NULL, NULL, 1124 NULL, "fred", "lkgs", "wrmsrns", 1125 NULL, "amx-fp16", NULL, "avx-ifma", 1126 NULL, NULL, "lam", NULL, 1127 NULL, NULL, NULL, NULL, 1128 }, 1129 .cpuid = { 1130 .eax = 7, 1131 .needs_ecx = true, .ecx = 1, 1132 .reg = R_EAX, 1133 }, 1134 .tcg_features = TCG_7_1_EAX_FEATURES, 1135 }, 1136 [FEAT_7_1_EDX] = { 1137 .type = CPUID_FEATURE_WORD, 1138 .feat_names = { 1139 NULL, NULL, NULL, NULL, 1140 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1141 "amx-complex", NULL, "avx-vnni-int16", NULL, 1142 NULL, NULL, "prefetchiti", NULL, 1143 NULL, NULL, NULL, "avx10", 1144 NULL, NULL, NULL, NULL, 1145 NULL, NULL, NULL, NULL, 1146 NULL, NULL, NULL, NULL, 1147 }, 1148 .cpuid = { 1149 .eax = 7, 1150 .needs_ecx = true, .ecx = 1, 1151 .reg = R_EDX, 1152 }, 1153 .tcg_features = TCG_7_1_EDX_FEATURES, 1154 }, 1155 [FEAT_7_2_EDX] = { 1156 .type = CPUID_FEATURE_WORD, 1157 .feat_names = { 1158 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1159 "bhi-ctrl", "mcdt-no", NULL, NULL, 1160 NULL, NULL, NULL, NULL, 1161 NULL, NULL, NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 NULL, NULL, NULL, NULL, 1164 NULL, NULL, NULL, NULL, 1165 NULL, NULL, NULL, NULL, 1166 }, 1167 .cpuid = { 1168 .eax = 7, 1169 .needs_ecx = true, .ecx = 2, 1170 .reg = R_EDX, 1171 }, 1172 .tcg_features = TCG_7_2_EDX_FEATURES, 1173 }, 1174 [FEAT_24_0_EBX] = { 1175 .type = CPUID_FEATURE_WORD, 1176 .feat_names = { 1177 [16] = "avx10-128", 1178 [17] = "avx10-256", 1179 [18] = "avx10-512", 1180 }, 1181 .cpuid = { 1182 .eax = 0x24, 1183 .needs_ecx = true, .ecx = 0, 1184 .reg = R_EBX, 1185 }, 1186 .tcg_features = TCG_24_0_EBX_FEATURES, 1187 }, 1188 [FEAT_8000_0007_EDX] = { 1189 .type = CPUID_FEATURE_WORD, 1190 .feat_names = { 1191 NULL, NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 "invtsc", NULL, NULL, NULL, 1194 NULL, NULL, NULL, NULL, 1195 NULL, NULL, NULL, NULL, 1196 NULL, NULL, NULL, NULL, 1197 NULL, NULL, NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 }, 1200 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1201 .tcg_features = TCG_APM_FEATURES, 1202 .unmigratable_flags = CPUID_APM_INVTSC, 1203 }, 1204 [FEAT_8000_0007_EBX] = { 1205 .type = CPUID_FEATURE_WORD, 1206 .feat_names = { 1207 "overflow-recov", "succor", NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 NULL, NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 }, 1216 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1217 .tcg_features = 0, 1218 .unmigratable_flags = 0, 1219 }, 1220 [FEAT_8000_0008_EBX] = { 1221 .type = CPUID_FEATURE_WORD, 1222 .feat_names = { 1223 "clzero", NULL, "xsaveerptr", NULL, 1224 NULL, NULL, NULL, NULL, 1225 NULL, "wbnoinvd", NULL, NULL, 1226 "ibpb", NULL, "ibrs", "amd-stibp", 1227 NULL, "stibp-always-on", NULL, NULL, 1228 NULL, NULL, NULL, NULL, 1229 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1230 "amd-psfd", NULL, NULL, NULL, 1231 }, 1232 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1233 .tcg_features = TCG_8000_0008_EBX, 1234 .unmigratable_flags = 0, 1235 }, 1236 [FEAT_8000_0021_EAX] = { 1237 .type = CPUID_FEATURE_WORD, 1238 .feat_names = { 1239 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1240 NULL, NULL, "null-sel-clr-base", NULL, 1241 "auto-ibrs", NULL, NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 NULL, NULL, NULL, NULL, 1244 NULL, NULL, NULL, NULL, 1245 "eraps", NULL, NULL, "sbpb", 1246 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1247 }, 1248 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1249 .tcg_features = 0, 1250 .unmigratable_flags = 0, 1251 }, 1252 [FEAT_8000_0021_EBX] = { 1253 .type = CPUID_FEATURE_WORD, 1254 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1255 .tcg_features = 0, 1256 .unmigratable_flags = 0, 1257 }, 1258 [FEAT_8000_0022_EAX] = { 1259 .type = CPUID_FEATURE_WORD, 1260 .feat_names = { 1261 "perfmon-v2", NULL, NULL, NULL, 1262 NULL, NULL, NULL, NULL, 1263 NULL, NULL, NULL, NULL, 1264 NULL, NULL, NULL, NULL, 1265 NULL, NULL, NULL, NULL, 1266 NULL, NULL, NULL, NULL, 1267 NULL, NULL, NULL, NULL, 1268 NULL, NULL, NULL, NULL, 1269 }, 1270 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1271 .tcg_features = 0, 1272 .unmigratable_flags = 0, 1273 }, 1274 [FEAT_XSAVE] = { 1275 .type = CPUID_FEATURE_WORD, 1276 .feat_names = { 1277 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1278 "xfd", NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 }, 1286 .cpuid = { 1287 .eax = 0xd, 1288 .needs_ecx = true, .ecx = 1, 1289 .reg = R_EAX, 1290 }, 1291 .tcg_features = TCG_XSAVE_FEATURES, 1292 }, 1293 [FEAT_XSAVE_XSS_LO] = { 1294 .type = CPUID_FEATURE_WORD, 1295 .feat_names = { 1296 NULL, NULL, NULL, NULL, 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 NULL, NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 NULL, NULL, NULL, NULL, 1302 NULL, NULL, NULL, NULL, 1303 NULL, NULL, NULL, NULL, 1304 }, 1305 .cpuid = { 1306 .eax = 0xD, 1307 .needs_ecx = true, 1308 .ecx = 1, 1309 .reg = R_ECX, 1310 }, 1311 }, 1312 [FEAT_XSAVE_XSS_HI] = { 1313 .type = CPUID_FEATURE_WORD, 1314 .cpuid = { 1315 .eax = 0xD, 1316 .needs_ecx = true, 1317 .ecx = 1, 1318 .reg = R_EDX 1319 }, 1320 }, 1321 [FEAT_6_EAX] = { 1322 .type = CPUID_FEATURE_WORD, 1323 .feat_names = { 1324 NULL, NULL, "arat", NULL, 1325 NULL, NULL, NULL, NULL, 1326 NULL, NULL, NULL, NULL, 1327 NULL, NULL, NULL, NULL, 1328 NULL, NULL, NULL, NULL, 1329 NULL, NULL, NULL, NULL, 1330 NULL, NULL, NULL, NULL, 1331 NULL, NULL, NULL, NULL, 1332 }, 1333 .cpuid = { .eax = 6, .reg = R_EAX, }, 1334 .tcg_features = TCG_6_EAX_FEATURES, 1335 }, 1336 [FEAT_XSAVE_XCR0_LO] = { 1337 .type = CPUID_FEATURE_WORD, 1338 .cpuid = { 1339 .eax = 0xD, 1340 .needs_ecx = true, .ecx = 0, 1341 .reg = R_EAX, 1342 }, 1343 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1344 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1345 XSTATE_PKRU_MASK, 1346 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1347 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1348 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1349 XSTATE_PKRU_MASK, 1350 }, 1351 [FEAT_XSAVE_XCR0_HI] = { 1352 .type = CPUID_FEATURE_WORD, 1353 .cpuid = { 1354 .eax = 0xD, 1355 .needs_ecx = true, .ecx = 0, 1356 .reg = R_EDX, 1357 }, 1358 .tcg_features = 0U, 1359 }, 1360 /*Below are MSR exposed features*/ 1361 [FEAT_ARCH_CAPABILITIES] = { 1362 .type = MSR_FEATURE_WORD, 1363 .feat_names = { 1364 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1365 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1366 "taa-no", NULL, NULL, NULL, 1367 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1368 NULL, "fb-clear", NULL, NULL, 1369 NULL, NULL, NULL, NULL, 1370 "pbrsb-no", NULL, "gds-no", "rfds-no", 1371 "rfds-clear", NULL, NULL, NULL, 1372 }, 1373 .msr = { 1374 .index = MSR_IA32_ARCH_CAPABILITIES, 1375 }, 1376 /* 1377 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1378 * cannot be read from user mode. Therefore, it has no impact 1379 > on any user-mode operation, and warnings about unsupported 1380 * features do not matter. 1381 */ 1382 .tcg_features = ~0U, 1383 }, 1384 [FEAT_CORE_CAPABILITY] = { 1385 .type = MSR_FEATURE_WORD, 1386 .feat_names = { 1387 NULL, NULL, NULL, NULL, 1388 NULL, "split-lock-detect", NULL, NULL, 1389 NULL, NULL, NULL, NULL, 1390 NULL, NULL, NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 NULL, NULL, NULL, NULL, 1395 }, 1396 .msr = { 1397 .index = MSR_IA32_CORE_CAPABILITY, 1398 }, 1399 }, 1400 [FEAT_PERF_CAPABILITIES] = { 1401 .type = MSR_FEATURE_WORD, 1402 .feat_names = { 1403 NULL, NULL, NULL, NULL, 1404 NULL, NULL, NULL, NULL, 1405 NULL, NULL, NULL, NULL, 1406 NULL, "full-width-write", NULL, NULL, 1407 NULL, NULL, NULL, NULL, 1408 NULL, NULL, NULL, NULL, 1409 NULL, NULL, NULL, NULL, 1410 NULL, NULL, NULL, NULL, 1411 }, 1412 .msr = { 1413 .index = MSR_IA32_PERF_CAPABILITIES, 1414 }, 1415 }, 1416 1417 [FEAT_VMX_PROCBASED_CTLS] = { 1418 .type = MSR_FEATURE_WORD, 1419 .feat_names = { 1420 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1421 NULL, NULL, NULL, "vmx-hlt-exit", 1422 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1423 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1424 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1425 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1426 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1427 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1428 }, 1429 .msr = { 1430 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1431 } 1432 }, 1433 1434 [FEAT_VMX_SECONDARY_CTLS] = { 1435 .type = MSR_FEATURE_WORD, 1436 .feat_names = { 1437 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1438 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1439 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1440 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1441 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1442 "vmx-xsaves", NULL, NULL, NULL, 1443 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1444 NULL, NULL, NULL, NULL, 1445 }, 1446 .msr = { 1447 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1448 } 1449 }, 1450 1451 [FEAT_VMX_PINBASED_CTLS] = { 1452 .type = MSR_FEATURE_WORD, 1453 .feat_names = { 1454 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1455 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1456 NULL, NULL, NULL, NULL, 1457 NULL, NULL, NULL, NULL, 1458 NULL, NULL, NULL, NULL, 1459 NULL, NULL, NULL, NULL, 1460 NULL, NULL, NULL, NULL, 1461 NULL, NULL, NULL, NULL, 1462 }, 1463 .msr = { 1464 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1465 } 1466 }, 1467 1468 [FEAT_VMX_EXIT_CTLS] = { 1469 .type = MSR_FEATURE_WORD, 1470 /* 1471 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1472 * the LM CPUID bit. 1473 */ 1474 .feat_names = { 1475 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1476 NULL, NULL, NULL, NULL, 1477 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1478 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1479 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1480 "vmx-exit-save-efer", "vmx-exit-load-efer", 1481 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1482 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1483 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1484 }, 1485 .msr = { 1486 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1487 } 1488 }, 1489 1490 [FEAT_VMX_ENTRY_CTLS] = { 1491 .type = MSR_FEATURE_WORD, 1492 .feat_names = { 1493 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1494 NULL, NULL, NULL, NULL, 1495 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1496 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1497 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1498 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1499 NULL, NULL, NULL, NULL, 1500 NULL, NULL, NULL, NULL, 1501 }, 1502 .msr = { 1503 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1504 } 1505 }, 1506 1507 [FEAT_VMX_MISC] = { 1508 .type = MSR_FEATURE_WORD, 1509 .feat_names = { 1510 NULL, NULL, NULL, NULL, 1511 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1512 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1513 NULL, NULL, NULL, NULL, 1514 NULL, NULL, NULL, NULL, 1515 NULL, NULL, NULL, NULL, 1516 NULL, NULL, NULL, NULL, 1517 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1518 }, 1519 .msr = { 1520 .index = MSR_IA32_VMX_MISC, 1521 } 1522 }, 1523 1524 [FEAT_VMX_EPT_VPID_CAPS] = { 1525 .type = MSR_FEATURE_WORD, 1526 .feat_names = { 1527 "vmx-ept-execonly", NULL, NULL, NULL, 1528 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1529 NULL, NULL, NULL, NULL, 1530 NULL, NULL, NULL, NULL, 1531 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1532 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1533 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1534 NULL, NULL, NULL, NULL, 1535 "vmx-invvpid", NULL, NULL, NULL, 1536 NULL, NULL, NULL, NULL, 1537 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1538 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1539 NULL, NULL, NULL, NULL, 1540 NULL, NULL, NULL, NULL, 1541 NULL, NULL, NULL, NULL, 1542 NULL, NULL, NULL, NULL, 1543 NULL, NULL, NULL, NULL, 1544 }, 1545 .msr = { 1546 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1547 } 1548 }, 1549 1550 [FEAT_VMX_BASIC] = { 1551 .type = MSR_FEATURE_WORD, 1552 .feat_names = { 1553 [54] = "vmx-ins-outs", 1554 [55] = "vmx-true-ctls", 1555 [56] = "vmx-any-errcode", 1556 [58] = "vmx-nested-exception", 1557 }, 1558 .msr = { 1559 .index = MSR_IA32_VMX_BASIC, 1560 }, 1561 /* Just to be safe - we don't support setting the MSEG version field. */ 1562 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1563 }, 1564 1565 [FEAT_VMX_VMFUNC] = { 1566 .type = MSR_FEATURE_WORD, 1567 .feat_names = { 1568 [0] = "vmx-eptp-switching", 1569 }, 1570 .msr = { 1571 .index = MSR_IA32_VMX_VMFUNC, 1572 } 1573 }, 1574 1575 [FEAT_14_0_ECX] = { 1576 .type = CPUID_FEATURE_WORD, 1577 .feat_names = { 1578 NULL, NULL, NULL, NULL, 1579 NULL, NULL, NULL, NULL, 1580 NULL, NULL, NULL, NULL, 1581 NULL, NULL, NULL, NULL, 1582 NULL, NULL, NULL, NULL, 1583 NULL, NULL, NULL, NULL, 1584 NULL, NULL, NULL, NULL, 1585 NULL, NULL, NULL, "intel-pt-lip", 1586 }, 1587 .cpuid = { 1588 .eax = 0x14, 1589 .needs_ecx = true, .ecx = 0, 1590 .reg = R_ECX, 1591 }, 1592 .tcg_features = TCG_14_0_ECX_FEATURES, 1593 }, 1594 1595 [FEAT_SGX_12_0_EAX] = { 1596 .type = CPUID_FEATURE_WORD, 1597 .feat_names = { 1598 "sgx1", "sgx2", NULL, NULL, 1599 NULL, NULL, NULL, NULL, 1600 NULL, NULL, NULL, "sgx-edeccssa", 1601 NULL, NULL, NULL, NULL, 1602 NULL, NULL, NULL, NULL, 1603 NULL, NULL, NULL, NULL, 1604 NULL, NULL, NULL, NULL, 1605 NULL, NULL, NULL, NULL, 1606 }, 1607 .cpuid = { 1608 .eax = 0x12, 1609 .needs_ecx = true, .ecx = 0, 1610 .reg = R_EAX, 1611 }, 1612 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1613 }, 1614 1615 [FEAT_SGX_12_0_EBX] = { 1616 .type = CPUID_FEATURE_WORD, 1617 .feat_names = { 1618 "sgx-exinfo" , NULL, NULL, NULL, 1619 NULL, NULL, NULL, NULL, 1620 NULL, NULL, NULL, NULL, 1621 NULL, NULL, NULL, NULL, 1622 NULL, NULL, NULL, NULL, 1623 NULL, NULL, NULL, NULL, 1624 NULL, NULL, NULL, NULL, 1625 NULL, NULL, NULL, NULL, 1626 }, 1627 .cpuid = { 1628 .eax = 0x12, 1629 .needs_ecx = true, .ecx = 0, 1630 .reg = R_EBX, 1631 }, 1632 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1633 }, 1634 1635 [FEAT_SGX_12_1_EAX] = { 1636 .type = CPUID_FEATURE_WORD, 1637 .feat_names = { 1638 NULL, "sgx-debug", "sgx-mode64", NULL, 1639 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1640 NULL, NULL, "sgx-aex-notify", NULL, 1641 NULL, NULL, NULL, NULL, 1642 NULL, NULL, NULL, NULL, 1643 NULL, NULL, NULL, NULL, 1644 NULL, NULL, NULL, NULL, 1645 NULL, NULL, NULL, NULL, 1646 }, 1647 .cpuid = { 1648 .eax = 0x12, 1649 .needs_ecx = true, .ecx = 1, 1650 .reg = R_EAX, 1651 }, 1652 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1653 }, 1654 }; 1655 1656 typedef struct FeatureMask { 1657 FeatureWord index; 1658 uint64_t mask; 1659 } FeatureMask; 1660 1661 typedef struct FeatureDep { 1662 FeatureMask from, to; 1663 } FeatureDep; 1664 1665 static FeatureDep feature_dependencies[] = { 1666 { 1667 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1668 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1669 }, 1670 { 1671 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1672 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1673 }, 1674 { 1675 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1676 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1677 }, 1678 { 1679 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1680 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1681 }, 1682 { 1683 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1684 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1685 }, 1686 { 1687 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1688 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1689 }, 1690 { 1691 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1692 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1693 }, 1694 { 1695 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1696 .to = { FEAT_VMX_MISC, ~0ull }, 1697 }, 1698 { 1699 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1700 .to = { FEAT_VMX_BASIC, ~0ull }, 1701 }, 1702 { 1703 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1704 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1705 }, 1706 { 1707 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1708 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1709 }, 1710 { 1711 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1712 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1713 }, 1714 { 1715 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1716 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1717 }, 1718 { 1719 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1720 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1721 }, 1722 { 1723 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1724 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1725 }, 1726 { 1727 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1728 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1729 }, 1730 { 1731 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1732 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1733 }, 1734 { 1735 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1736 .to = { FEAT_14_0_ECX, ~0ull }, 1737 }, 1738 { 1739 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1740 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1741 }, 1742 { 1743 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1744 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1745 }, 1746 { 1747 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1748 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1749 }, 1750 { 1751 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1752 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1753 }, 1754 { 1755 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1756 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1757 }, 1758 { 1759 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1760 .to = { FEAT_SVM, ~0ull }, 1761 }, 1762 { 1763 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1764 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1765 }, 1766 { 1767 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1768 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1769 }, 1770 { 1771 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1772 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1773 }, 1774 { 1775 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1776 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1777 }, 1778 { 1779 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1780 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1781 }, 1782 { 1783 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1784 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1785 }, 1786 { 1787 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1788 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1789 }, 1790 { 1791 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1792 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1793 }, 1794 { 1795 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1796 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1797 }, 1798 { 1799 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1800 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1801 }, 1802 { 1803 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1804 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1805 }, 1806 { 1807 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1808 .to = { FEAT_24_0_EBX, ~0ull }, 1809 }, 1810 }; 1811 1812 typedef struct X86RegisterInfo32 { 1813 /* Name of register */ 1814 const char *name; 1815 /* QAPI enum value register */ 1816 X86CPURegister32 qapi_enum; 1817 } X86RegisterInfo32; 1818 1819 #define REGISTER(reg) \ 1820 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1821 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1822 REGISTER(EAX), 1823 REGISTER(ECX), 1824 REGISTER(EDX), 1825 REGISTER(EBX), 1826 REGISTER(ESP), 1827 REGISTER(EBP), 1828 REGISTER(ESI), 1829 REGISTER(EDI), 1830 }; 1831 #undef REGISTER 1832 1833 /* CPUID feature bits available in XSS */ 1834 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1835 1836 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1837 [XSTATE_FP_BIT] = { 1838 /* x87 FP state component is always enabled if XSAVE is supported */ 1839 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1840 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1841 }, 1842 [XSTATE_SSE_BIT] = { 1843 /* SSE state component is always enabled if XSAVE is supported */ 1844 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1845 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1846 }, 1847 [XSTATE_YMM_BIT] = 1848 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1849 .size = sizeof(XSaveAVX) }, 1850 [XSTATE_BNDREGS_BIT] = 1851 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1852 .size = sizeof(XSaveBNDREG) }, 1853 [XSTATE_BNDCSR_BIT] = 1854 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1855 .size = sizeof(XSaveBNDCSR) }, 1856 [XSTATE_OPMASK_BIT] = 1857 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1858 .size = sizeof(XSaveOpmask) }, 1859 [XSTATE_ZMM_Hi256_BIT] = 1860 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1861 .size = sizeof(XSaveZMM_Hi256) }, 1862 [XSTATE_Hi16_ZMM_BIT] = 1863 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1864 .size = sizeof(XSaveHi16_ZMM) }, 1865 [XSTATE_PKRU_BIT] = 1866 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1867 .size = sizeof(XSavePKRU) }, 1868 [XSTATE_ARCH_LBR_BIT] = { 1869 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1870 .offset = 0 /*supervisor mode component, offset = 0 */, 1871 .size = sizeof(XSavesArchLBR) }, 1872 [XSTATE_XTILE_CFG_BIT] = { 1873 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1874 .size = sizeof(XSaveXTILECFG), 1875 }, 1876 [XSTATE_XTILE_DATA_BIT] = { 1877 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1878 .size = sizeof(XSaveXTILEDATA) 1879 }, 1880 }; 1881 1882 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1883 { 1884 uint64_t ret = x86_ext_save_areas[0].size; 1885 const ExtSaveArea *esa; 1886 uint32_t offset = 0; 1887 int i; 1888 1889 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1890 esa = &x86_ext_save_areas[i]; 1891 if ((mask >> i) & 1) { 1892 offset = compacted ? ret : esa->offset; 1893 ret = MAX(ret, offset + esa->size); 1894 } 1895 } 1896 return ret; 1897 } 1898 1899 static inline bool accel_uses_host_cpuid(void) 1900 { 1901 return kvm_enabled() || hvf_enabled(); 1902 } 1903 1904 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1905 { 1906 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1907 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1908 } 1909 1910 /* Return name of 32-bit register, from a R_* constant */ 1911 static const char *get_register_name_32(unsigned int reg) 1912 { 1913 if (reg >= CPU_NB_REGS32) { 1914 return NULL; 1915 } 1916 return x86_reg_info_32[reg].name; 1917 } 1918 1919 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1920 { 1921 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1922 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1923 } 1924 1925 /* 1926 * Returns the set of feature flags that are supported and migratable by 1927 * QEMU, for a given FeatureWord. 1928 */ 1929 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1930 { 1931 FeatureWordInfo *wi = &feature_word_info[w]; 1932 CPUX86State *env = &cpu->env; 1933 uint64_t r = 0; 1934 int i; 1935 1936 for (i = 0; i < 64; i++) { 1937 uint64_t f = 1ULL << i; 1938 1939 /* If the feature name is known, it is implicitly considered migratable, 1940 * unless it is explicitly set in unmigratable_flags */ 1941 if ((wi->migratable_flags & f) || 1942 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1943 r |= f; 1944 } 1945 } 1946 1947 /* when tsc-khz is set explicitly, invtsc is migratable */ 1948 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1949 r |= CPUID_APM_INVTSC; 1950 } 1951 1952 return r; 1953 } 1954 1955 void host_cpuid(uint32_t function, uint32_t count, 1956 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1957 { 1958 uint32_t vec[4]; 1959 1960 #ifdef __x86_64__ 1961 asm volatile("cpuid" 1962 : "=a"(vec[0]), "=b"(vec[1]), 1963 "=c"(vec[2]), "=d"(vec[3]) 1964 : "0"(function), "c"(count) : "cc"); 1965 #elif defined(__i386__) 1966 asm volatile("pusha \n\t" 1967 "cpuid \n\t" 1968 "mov %%eax, 0(%2) \n\t" 1969 "mov %%ebx, 4(%2) \n\t" 1970 "mov %%ecx, 8(%2) \n\t" 1971 "mov %%edx, 12(%2) \n\t" 1972 "popa" 1973 : : "a"(function), "c"(count), "S"(vec) 1974 : "memory", "cc"); 1975 #else 1976 abort(); 1977 #endif 1978 1979 if (eax) 1980 *eax = vec[0]; 1981 if (ebx) 1982 *ebx = vec[1]; 1983 if (ecx) 1984 *ecx = vec[2]; 1985 if (edx) 1986 *edx = vec[3]; 1987 } 1988 1989 /* CPU class name definitions: */ 1990 1991 /* Return type name for a given CPU model name 1992 * Caller is responsible for freeing the returned string. 1993 */ 1994 static char *x86_cpu_type_name(const char *model_name) 1995 { 1996 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1997 } 1998 1999 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2000 { 2001 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2002 return object_class_by_name(typename); 2003 } 2004 2005 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2006 { 2007 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2008 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2009 return cpu_model_from_type(class_name); 2010 } 2011 2012 typedef struct X86CPUVersionDefinition { 2013 X86CPUVersion version; 2014 const char *alias; 2015 const char *note; 2016 PropValue *props; 2017 const CPUCaches *const cache_info; 2018 } X86CPUVersionDefinition; 2019 2020 /* Base definition for a CPU model */ 2021 typedef struct X86CPUDefinition { 2022 const char *name; 2023 uint32_t level; 2024 uint32_t xlevel; 2025 /* vendor is zero-terminated, 12 character ASCII string */ 2026 char vendor[CPUID_VENDOR_SZ + 1]; 2027 int family; 2028 int model; 2029 int stepping; 2030 uint8_t avx10_version; 2031 FeatureWordArray features; 2032 const char *model_id; 2033 const CPUCaches *const cache_info; 2034 /* 2035 * Definitions for alternative versions of CPU model. 2036 * List is terminated by item with version == 0. 2037 * If NULL, version 1 will be registered automatically. 2038 */ 2039 const X86CPUVersionDefinition *versions; 2040 const char *deprecation_note; 2041 } X86CPUDefinition; 2042 2043 /* Reference to a specific CPU model version */ 2044 struct X86CPUModel { 2045 /* Base CPU definition */ 2046 const X86CPUDefinition *cpudef; 2047 /* CPU model version */ 2048 X86CPUVersion version; 2049 const char *note; 2050 /* 2051 * If true, this is an alias CPU model. 2052 * This matters only for "-cpu help" and query-cpu-definitions 2053 */ 2054 bool is_alias; 2055 }; 2056 2057 /* Get full model name for CPU version */ 2058 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2059 X86CPUVersion version) 2060 { 2061 assert(version > 0); 2062 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2063 } 2064 2065 static const X86CPUVersionDefinition * 2066 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2067 { 2068 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2069 static const X86CPUVersionDefinition default_version_list[] = { 2070 { 1 }, 2071 { /* end of list */ } 2072 }; 2073 2074 return def->versions ?: default_version_list; 2075 } 2076 2077 static const CPUCaches epyc_cache_info = { 2078 .l1d_cache = &(CPUCacheInfo) { 2079 .type = DATA_CACHE, 2080 .level = 1, 2081 .size = 32 * KiB, 2082 .line_size = 64, 2083 .associativity = 8, 2084 .partitions = 1, 2085 .sets = 64, 2086 .lines_per_tag = 1, 2087 .self_init = 1, 2088 .no_invd_sharing = true, 2089 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2090 }, 2091 .l1i_cache = &(CPUCacheInfo) { 2092 .type = INSTRUCTION_CACHE, 2093 .level = 1, 2094 .size = 64 * KiB, 2095 .line_size = 64, 2096 .associativity = 4, 2097 .partitions = 1, 2098 .sets = 256, 2099 .lines_per_tag = 1, 2100 .self_init = 1, 2101 .no_invd_sharing = true, 2102 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2103 }, 2104 .l2_cache = &(CPUCacheInfo) { 2105 .type = UNIFIED_CACHE, 2106 .level = 2, 2107 .size = 512 * KiB, 2108 .line_size = 64, 2109 .associativity = 8, 2110 .partitions = 1, 2111 .sets = 1024, 2112 .lines_per_tag = 1, 2113 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2114 }, 2115 .l3_cache = &(CPUCacheInfo) { 2116 .type = UNIFIED_CACHE, 2117 .level = 3, 2118 .size = 8 * MiB, 2119 .line_size = 64, 2120 .associativity = 16, 2121 .partitions = 1, 2122 .sets = 8192, 2123 .lines_per_tag = 1, 2124 .self_init = true, 2125 .inclusive = true, 2126 .complex_indexing = true, 2127 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2128 }, 2129 }; 2130 2131 static CPUCaches epyc_v4_cache_info = { 2132 .l1d_cache = &(CPUCacheInfo) { 2133 .type = DATA_CACHE, 2134 .level = 1, 2135 .size = 32 * KiB, 2136 .line_size = 64, 2137 .associativity = 8, 2138 .partitions = 1, 2139 .sets = 64, 2140 .lines_per_tag = 1, 2141 .self_init = 1, 2142 .no_invd_sharing = true, 2143 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2144 }, 2145 .l1i_cache = &(CPUCacheInfo) { 2146 .type = INSTRUCTION_CACHE, 2147 .level = 1, 2148 .size = 64 * KiB, 2149 .line_size = 64, 2150 .associativity = 4, 2151 .partitions = 1, 2152 .sets = 256, 2153 .lines_per_tag = 1, 2154 .self_init = 1, 2155 .no_invd_sharing = true, 2156 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2157 }, 2158 .l2_cache = &(CPUCacheInfo) { 2159 .type = UNIFIED_CACHE, 2160 .level = 2, 2161 .size = 512 * KiB, 2162 .line_size = 64, 2163 .associativity = 8, 2164 .partitions = 1, 2165 .sets = 1024, 2166 .lines_per_tag = 1, 2167 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2168 }, 2169 .l3_cache = &(CPUCacheInfo) { 2170 .type = UNIFIED_CACHE, 2171 .level = 3, 2172 .size = 8 * MiB, 2173 .line_size = 64, 2174 .associativity = 16, 2175 .partitions = 1, 2176 .sets = 8192, 2177 .lines_per_tag = 1, 2178 .self_init = true, 2179 .inclusive = true, 2180 .complex_indexing = false, 2181 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2182 }, 2183 }; 2184 2185 static const CPUCaches epyc_rome_cache_info = { 2186 .l1d_cache = &(CPUCacheInfo) { 2187 .type = DATA_CACHE, 2188 .level = 1, 2189 .size = 32 * KiB, 2190 .line_size = 64, 2191 .associativity = 8, 2192 .partitions = 1, 2193 .sets = 64, 2194 .lines_per_tag = 1, 2195 .self_init = 1, 2196 .no_invd_sharing = true, 2197 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2198 }, 2199 .l1i_cache = &(CPUCacheInfo) { 2200 .type = INSTRUCTION_CACHE, 2201 .level = 1, 2202 .size = 32 * KiB, 2203 .line_size = 64, 2204 .associativity = 8, 2205 .partitions = 1, 2206 .sets = 64, 2207 .lines_per_tag = 1, 2208 .self_init = 1, 2209 .no_invd_sharing = true, 2210 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2211 }, 2212 .l2_cache = &(CPUCacheInfo) { 2213 .type = UNIFIED_CACHE, 2214 .level = 2, 2215 .size = 512 * KiB, 2216 .line_size = 64, 2217 .associativity = 8, 2218 .partitions = 1, 2219 .sets = 1024, 2220 .lines_per_tag = 1, 2221 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2222 }, 2223 .l3_cache = &(CPUCacheInfo) { 2224 .type = UNIFIED_CACHE, 2225 .level = 3, 2226 .size = 16 * MiB, 2227 .line_size = 64, 2228 .associativity = 16, 2229 .partitions = 1, 2230 .sets = 16384, 2231 .lines_per_tag = 1, 2232 .self_init = true, 2233 .inclusive = true, 2234 .complex_indexing = true, 2235 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2236 }, 2237 }; 2238 2239 static const CPUCaches epyc_rome_v3_cache_info = { 2240 .l1d_cache = &(CPUCacheInfo) { 2241 .type = DATA_CACHE, 2242 .level = 1, 2243 .size = 32 * KiB, 2244 .line_size = 64, 2245 .associativity = 8, 2246 .partitions = 1, 2247 .sets = 64, 2248 .lines_per_tag = 1, 2249 .self_init = 1, 2250 .no_invd_sharing = true, 2251 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2252 }, 2253 .l1i_cache = &(CPUCacheInfo) { 2254 .type = INSTRUCTION_CACHE, 2255 .level = 1, 2256 .size = 32 * KiB, 2257 .line_size = 64, 2258 .associativity = 8, 2259 .partitions = 1, 2260 .sets = 64, 2261 .lines_per_tag = 1, 2262 .self_init = 1, 2263 .no_invd_sharing = true, 2264 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2265 }, 2266 .l2_cache = &(CPUCacheInfo) { 2267 .type = UNIFIED_CACHE, 2268 .level = 2, 2269 .size = 512 * KiB, 2270 .line_size = 64, 2271 .associativity = 8, 2272 .partitions = 1, 2273 .sets = 1024, 2274 .lines_per_tag = 1, 2275 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2276 }, 2277 .l3_cache = &(CPUCacheInfo) { 2278 .type = UNIFIED_CACHE, 2279 .level = 3, 2280 .size = 16 * MiB, 2281 .line_size = 64, 2282 .associativity = 16, 2283 .partitions = 1, 2284 .sets = 16384, 2285 .lines_per_tag = 1, 2286 .self_init = true, 2287 .inclusive = true, 2288 .complex_indexing = false, 2289 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2290 }, 2291 }; 2292 2293 static const CPUCaches epyc_milan_cache_info = { 2294 .l1d_cache = &(CPUCacheInfo) { 2295 .type = DATA_CACHE, 2296 .level = 1, 2297 .size = 32 * KiB, 2298 .line_size = 64, 2299 .associativity = 8, 2300 .partitions = 1, 2301 .sets = 64, 2302 .lines_per_tag = 1, 2303 .self_init = 1, 2304 .no_invd_sharing = true, 2305 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2306 }, 2307 .l1i_cache = &(CPUCacheInfo) { 2308 .type = INSTRUCTION_CACHE, 2309 .level = 1, 2310 .size = 32 * KiB, 2311 .line_size = 64, 2312 .associativity = 8, 2313 .partitions = 1, 2314 .sets = 64, 2315 .lines_per_tag = 1, 2316 .self_init = 1, 2317 .no_invd_sharing = true, 2318 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2319 }, 2320 .l2_cache = &(CPUCacheInfo) { 2321 .type = UNIFIED_CACHE, 2322 .level = 2, 2323 .size = 512 * KiB, 2324 .line_size = 64, 2325 .associativity = 8, 2326 .partitions = 1, 2327 .sets = 1024, 2328 .lines_per_tag = 1, 2329 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2330 }, 2331 .l3_cache = &(CPUCacheInfo) { 2332 .type = UNIFIED_CACHE, 2333 .level = 3, 2334 .size = 32 * MiB, 2335 .line_size = 64, 2336 .associativity = 16, 2337 .partitions = 1, 2338 .sets = 32768, 2339 .lines_per_tag = 1, 2340 .self_init = true, 2341 .inclusive = true, 2342 .complex_indexing = true, 2343 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2344 }, 2345 }; 2346 2347 static const CPUCaches epyc_milan_v2_cache_info = { 2348 .l1d_cache = &(CPUCacheInfo) { 2349 .type = DATA_CACHE, 2350 .level = 1, 2351 .size = 32 * KiB, 2352 .line_size = 64, 2353 .associativity = 8, 2354 .partitions = 1, 2355 .sets = 64, 2356 .lines_per_tag = 1, 2357 .self_init = 1, 2358 .no_invd_sharing = true, 2359 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2360 }, 2361 .l1i_cache = &(CPUCacheInfo) { 2362 .type = INSTRUCTION_CACHE, 2363 .level = 1, 2364 .size = 32 * KiB, 2365 .line_size = 64, 2366 .associativity = 8, 2367 .partitions = 1, 2368 .sets = 64, 2369 .lines_per_tag = 1, 2370 .self_init = 1, 2371 .no_invd_sharing = true, 2372 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2373 }, 2374 .l2_cache = &(CPUCacheInfo) { 2375 .type = UNIFIED_CACHE, 2376 .level = 2, 2377 .size = 512 * KiB, 2378 .line_size = 64, 2379 .associativity = 8, 2380 .partitions = 1, 2381 .sets = 1024, 2382 .lines_per_tag = 1, 2383 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2384 }, 2385 .l3_cache = &(CPUCacheInfo) { 2386 .type = UNIFIED_CACHE, 2387 .level = 3, 2388 .size = 32 * MiB, 2389 .line_size = 64, 2390 .associativity = 16, 2391 .partitions = 1, 2392 .sets = 32768, 2393 .lines_per_tag = 1, 2394 .self_init = true, 2395 .inclusive = true, 2396 .complex_indexing = false, 2397 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2398 }, 2399 }; 2400 2401 static const CPUCaches epyc_genoa_cache_info = { 2402 .l1d_cache = &(CPUCacheInfo) { 2403 .type = DATA_CACHE, 2404 .level = 1, 2405 .size = 32 * KiB, 2406 .line_size = 64, 2407 .associativity = 8, 2408 .partitions = 1, 2409 .sets = 64, 2410 .lines_per_tag = 1, 2411 .self_init = 1, 2412 .no_invd_sharing = true, 2413 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2414 }, 2415 .l1i_cache = &(CPUCacheInfo) { 2416 .type = INSTRUCTION_CACHE, 2417 .level = 1, 2418 .size = 32 * KiB, 2419 .line_size = 64, 2420 .associativity = 8, 2421 .partitions = 1, 2422 .sets = 64, 2423 .lines_per_tag = 1, 2424 .self_init = 1, 2425 .no_invd_sharing = true, 2426 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2427 }, 2428 .l2_cache = &(CPUCacheInfo) { 2429 .type = UNIFIED_CACHE, 2430 .level = 2, 2431 .size = 1 * MiB, 2432 .line_size = 64, 2433 .associativity = 8, 2434 .partitions = 1, 2435 .sets = 2048, 2436 .lines_per_tag = 1, 2437 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2438 }, 2439 .l3_cache = &(CPUCacheInfo) { 2440 .type = UNIFIED_CACHE, 2441 .level = 3, 2442 .size = 32 * MiB, 2443 .line_size = 64, 2444 .associativity = 16, 2445 .partitions = 1, 2446 .sets = 32768, 2447 .lines_per_tag = 1, 2448 .self_init = true, 2449 .inclusive = true, 2450 .complex_indexing = false, 2451 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2452 }, 2453 }; 2454 2455 /* The following VMX features are not supported by KVM and are left out in the 2456 * CPU definitions: 2457 * 2458 * Dual-monitor support (all processors) 2459 * Entry to SMM 2460 * Deactivate dual-monitor treatment 2461 * Number of CR3-target values 2462 * Shutdown activity state 2463 * Wait-for-SIPI activity state 2464 * PAUSE-loop exiting (Westmere and newer) 2465 * EPT-violation #VE (Broadwell and newer) 2466 * Inject event with insn length=0 (Skylake and newer) 2467 * Conceal non-root operation from PT 2468 * Conceal VM exits from PT 2469 * Conceal VM entries from PT 2470 * Enable ENCLS exiting 2471 * Mode-based execute control (XS/XU) 2472 * TSC scaling (Skylake Server and newer) 2473 * GPA translation for PT (IceLake and newer) 2474 * User wait and pause 2475 * ENCLV exiting 2476 * Load IA32_RTIT_CTL 2477 * Clear IA32_RTIT_CTL 2478 * Advanced VM-exit information for EPT violations 2479 * Sub-page write permissions 2480 * PT in VMX operation 2481 */ 2482 2483 static const X86CPUDefinition builtin_x86_defs[] = { 2484 { 2485 .name = "qemu64", 2486 .level = 0xd, 2487 .vendor = CPUID_VENDOR_AMD, 2488 .family = 15, 2489 .model = 107, 2490 .stepping = 1, 2491 .features[FEAT_1_EDX] = 2492 PPRO_FEATURES | 2493 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2494 CPUID_PSE36, 2495 .features[FEAT_1_ECX] = 2496 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2497 .features[FEAT_8000_0001_EDX] = 2498 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2499 .features[FEAT_8000_0001_ECX] = 2500 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2501 .xlevel = 0x8000000A, 2502 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2503 }, 2504 { 2505 .name = "phenom", 2506 .level = 5, 2507 .vendor = CPUID_VENDOR_AMD, 2508 .family = 16, 2509 .model = 2, 2510 .stepping = 3, 2511 /* Missing: CPUID_HT */ 2512 .features[FEAT_1_EDX] = 2513 PPRO_FEATURES | 2514 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2515 CPUID_PSE36 | CPUID_VME, 2516 .features[FEAT_1_ECX] = 2517 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2518 CPUID_EXT_POPCNT, 2519 .features[FEAT_8000_0001_EDX] = 2520 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2521 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2522 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2523 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2524 CPUID_EXT3_CR8LEG, 2525 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2526 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2527 .features[FEAT_8000_0001_ECX] = 2528 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2529 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2530 /* Missing: CPUID_SVM_LBRV */ 2531 .features[FEAT_SVM] = 2532 CPUID_SVM_NPT, 2533 .xlevel = 0x8000001A, 2534 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2535 }, 2536 { 2537 .name = "core2duo", 2538 .level = 10, 2539 .vendor = CPUID_VENDOR_INTEL, 2540 .family = 6, 2541 .model = 15, 2542 .stepping = 11, 2543 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2544 .features[FEAT_1_EDX] = 2545 PPRO_FEATURES | 2546 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2547 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2548 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2549 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2550 .features[FEAT_1_ECX] = 2551 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2552 CPUID_EXT_CX16, 2553 .features[FEAT_8000_0001_EDX] = 2554 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2555 .features[FEAT_8000_0001_ECX] = 2556 CPUID_EXT3_LAHF_LM, 2557 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2558 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2559 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2560 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2561 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2562 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2563 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2564 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2565 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2566 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2567 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2568 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2569 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2570 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2571 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2572 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2573 .features[FEAT_VMX_SECONDARY_CTLS] = 2574 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2575 .xlevel = 0x80000008, 2576 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2577 }, 2578 { 2579 .name = "kvm64", 2580 .level = 0xd, 2581 .vendor = CPUID_VENDOR_INTEL, 2582 .family = 15, 2583 .model = 6, 2584 .stepping = 1, 2585 /* Missing: CPUID_HT */ 2586 .features[FEAT_1_EDX] = 2587 PPRO_FEATURES | CPUID_VME | 2588 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2589 CPUID_PSE36, 2590 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2591 .features[FEAT_1_ECX] = 2592 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2593 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2594 .features[FEAT_8000_0001_EDX] = 2595 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2596 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2597 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2598 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2599 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2600 .features[FEAT_8000_0001_ECX] = 2601 0, 2602 /* VMX features from Cedar Mill/Prescott */ 2603 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2604 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2605 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2606 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2607 VMX_PIN_BASED_NMI_EXITING, 2608 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2609 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2610 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2611 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2612 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2613 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2614 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2615 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2616 .xlevel = 0x80000008, 2617 .model_id = "Common KVM processor" 2618 }, 2619 { 2620 .name = "qemu32", 2621 .level = 4, 2622 .vendor = CPUID_VENDOR_INTEL, 2623 .family = 6, 2624 .model = 6, 2625 .stepping = 3, 2626 .features[FEAT_1_EDX] = 2627 PPRO_FEATURES, 2628 .features[FEAT_1_ECX] = 2629 CPUID_EXT_SSE3, 2630 .xlevel = 0x80000004, 2631 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2632 }, 2633 { 2634 .name = "kvm32", 2635 .level = 5, 2636 .vendor = CPUID_VENDOR_INTEL, 2637 .family = 15, 2638 .model = 6, 2639 .stepping = 1, 2640 .features[FEAT_1_EDX] = 2641 PPRO_FEATURES | CPUID_VME | 2642 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2643 .features[FEAT_1_ECX] = 2644 CPUID_EXT_SSE3, 2645 .features[FEAT_8000_0001_ECX] = 2646 0, 2647 /* VMX features from Yonah */ 2648 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2649 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2650 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2651 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2652 VMX_PIN_BASED_NMI_EXITING, 2653 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2654 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2655 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2656 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2657 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2658 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2659 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2660 .xlevel = 0x80000008, 2661 .model_id = "Common 32-bit KVM processor" 2662 }, 2663 { 2664 .name = "coreduo", 2665 .level = 10, 2666 .vendor = CPUID_VENDOR_INTEL, 2667 .family = 6, 2668 .model = 14, 2669 .stepping = 8, 2670 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2671 .features[FEAT_1_EDX] = 2672 PPRO_FEATURES | CPUID_VME | 2673 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2674 CPUID_SS, 2675 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2676 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2677 .features[FEAT_1_ECX] = 2678 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2679 .features[FEAT_8000_0001_EDX] = 2680 CPUID_EXT2_NX, 2681 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2682 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2683 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2684 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2685 VMX_PIN_BASED_NMI_EXITING, 2686 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2687 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2688 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2689 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2690 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2691 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2692 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2693 .xlevel = 0x80000008, 2694 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2695 }, 2696 { 2697 .name = "486", 2698 .level = 1, 2699 .vendor = CPUID_VENDOR_INTEL, 2700 .family = 4, 2701 .model = 8, 2702 .stepping = 0, 2703 .features[FEAT_1_EDX] = 2704 I486_FEATURES, 2705 .xlevel = 0, 2706 .model_id = "", 2707 }, 2708 { 2709 .name = "pentium", 2710 .level = 1, 2711 .vendor = CPUID_VENDOR_INTEL, 2712 .family = 5, 2713 .model = 4, 2714 .stepping = 3, 2715 .features[FEAT_1_EDX] = 2716 PENTIUM_FEATURES, 2717 .xlevel = 0, 2718 .model_id = "", 2719 }, 2720 { 2721 .name = "pentium2", 2722 .level = 2, 2723 .vendor = CPUID_VENDOR_INTEL, 2724 .family = 6, 2725 .model = 5, 2726 .stepping = 2, 2727 .features[FEAT_1_EDX] = 2728 PENTIUM2_FEATURES, 2729 .xlevel = 0, 2730 .model_id = "", 2731 }, 2732 { 2733 .name = "pentium3", 2734 .level = 3, 2735 .vendor = CPUID_VENDOR_INTEL, 2736 .family = 6, 2737 .model = 7, 2738 .stepping = 3, 2739 .features[FEAT_1_EDX] = 2740 PENTIUM3_FEATURES, 2741 .xlevel = 0, 2742 .model_id = "", 2743 }, 2744 { 2745 .name = "athlon", 2746 .level = 2, 2747 .vendor = CPUID_VENDOR_AMD, 2748 .family = 6, 2749 .model = 2, 2750 .stepping = 3, 2751 .features[FEAT_1_EDX] = 2752 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2753 CPUID_MCA, 2754 .features[FEAT_8000_0001_EDX] = 2755 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2756 .xlevel = 0x80000008, 2757 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2758 }, 2759 { 2760 .name = "n270", 2761 .level = 10, 2762 .vendor = CPUID_VENDOR_INTEL, 2763 .family = 6, 2764 .model = 28, 2765 .stepping = 2, 2766 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2767 .features[FEAT_1_EDX] = 2768 PPRO_FEATURES | 2769 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2770 CPUID_ACPI | CPUID_SS, 2771 /* Some CPUs got no CPUID_SEP */ 2772 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2773 * CPUID_EXT_XTPR */ 2774 .features[FEAT_1_ECX] = 2775 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2776 CPUID_EXT_MOVBE, 2777 .features[FEAT_8000_0001_EDX] = 2778 CPUID_EXT2_NX, 2779 .features[FEAT_8000_0001_ECX] = 2780 CPUID_EXT3_LAHF_LM, 2781 .xlevel = 0x80000008, 2782 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2783 }, 2784 { 2785 .name = "Conroe", 2786 .level = 10, 2787 .vendor = CPUID_VENDOR_INTEL, 2788 .family = 6, 2789 .model = 15, 2790 .stepping = 3, 2791 .features[FEAT_1_EDX] = 2792 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2793 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2794 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2795 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2796 CPUID_DE | CPUID_FP87, 2797 .features[FEAT_1_ECX] = 2798 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2799 .features[FEAT_8000_0001_EDX] = 2800 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2801 .features[FEAT_8000_0001_ECX] = 2802 CPUID_EXT3_LAHF_LM, 2803 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2804 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2805 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2806 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2807 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2808 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2809 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2810 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2811 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2812 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2813 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2814 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2815 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2816 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2817 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2818 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2819 .features[FEAT_VMX_SECONDARY_CTLS] = 2820 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2821 .xlevel = 0x80000008, 2822 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2823 }, 2824 { 2825 .name = "Penryn", 2826 .level = 10, 2827 .vendor = CPUID_VENDOR_INTEL, 2828 .family = 6, 2829 .model = 23, 2830 .stepping = 3, 2831 .features[FEAT_1_EDX] = 2832 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2833 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2834 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2835 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2836 CPUID_DE | CPUID_FP87, 2837 .features[FEAT_1_ECX] = 2838 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2839 CPUID_EXT_SSE3, 2840 .features[FEAT_8000_0001_EDX] = 2841 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2842 .features[FEAT_8000_0001_ECX] = 2843 CPUID_EXT3_LAHF_LM, 2844 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2845 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2846 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2847 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2848 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2849 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2850 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2851 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2852 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2853 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2854 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2855 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2856 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2857 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2858 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2859 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2860 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2861 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2862 .features[FEAT_VMX_SECONDARY_CTLS] = 2863 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2864 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2865 .xlevel = 0x80000008, 2866 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2867 }, 2868 { 2869 .name = "Nehalem", 2870 .level = 11, 2871 .vendor = CPUID_VENDOR_INTEL, 2872 .family = 6, 2873 .model = 26, 2874 .stepping = 3, 2875 .features[FEAT_1_EDX] = 2876 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2877 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2878 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2879 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2880 CPUID_DE | CPUID_FP87, 2881 .features[FEAT_1_ECX] = 2882 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2883 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2884 .features[FEAT_8000_0001_EDX] = 2885 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2886 .features[FEAT_8000_0001_ECX] = 2887 CPUID_EXT3_LAHF_LM, 2888 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2889 MSR_VMX_BASIC_TRUE_CTLS, 2890 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2891 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2892 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2893 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2894 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2895 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2896 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2897 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2898 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2899 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2900 .features[FEAT_VMX_EXIT_CTLS] = 2901 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2902 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2903 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2904 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2905 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2906 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2907 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2908 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2909 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2910 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2911 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2912 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2913 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2914 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2915 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2916 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2917 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2918 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2919 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2920 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2921 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2922 .features[FEAT_VMX_SECONDARY_CTLS] = 2923 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2924 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2925 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2926 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2927 VMX_SECONDARY_EXEC_ENABLE_VPID, 2928 .xlevel = 0x80000008, 2929 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2930 .versions = (X86CPUVersionDefinition[]) { 2931 { .version = 1 }, 2932 { 2933 .version = 2, 2934 .alias = "Nehalem-IBRS", 2935 .props = (PropValue[]) { 2936 { "spec-ctrl", "on" }, 2937 { "model-id", 2938 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2939 { /* end of list */ } 2940 } 2941 }, 2942 { /* end of list */ } 2943 } 2944 }, 2945 { 2946 .name = "Westmere", 2947 .level = 11, 2948 .vendor = CPUID_VENDOR_INTEL, 2949 .family = 6, 2950 .model = 44, 2951 .stepping = 1, 2952 .features[FEAT_1_EDX] = 2953 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2954 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2955 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2956 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2957 CPUID_DE | CPUID_FP87, 2958 .features[FEAT_1_ECX] = 2959 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2960 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2961 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2962 .features[FEAT_8000_0001_EDX] = 2963 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2964 .features[FEAT_8000_0001_ECX] = 2965 CPUID_EXT3_LAHF_LM, 2966 .features[FEAT_6_EAX] = 2967 CPUID_6_EAX_ARAT, 2968 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2969 MSR_VMX_BASIC_TRUE_CTLS, 2970 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2971 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2972 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2973 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2974 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2975 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2976 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2977 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2978 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2979 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2980 .features[FEAT_VMX_EXIT_CTLS] = 2981 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2982 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2983 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2984 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2985 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2986 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2987 MSR_VMX_MISC_STORE_LMA, 2988 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2989 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2990 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2991 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2992 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2993 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2994 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2995 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2996 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2997 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2998 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2999 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3000 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3001 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3002 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3003 .features[FEAT_VMX_SECONDARY_CTLS] = 3004 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3005 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3006 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3007 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3008 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3009 .xlevel = 0x80000008, 3010 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3011 .versions = (X86CPUVersionDefinition[]) { 3012 { .version = 1 }, 3013 { 3014 .version = 2, 3015 .alias = "Westmere-IBRS", 3016 .props = (PropValue[]) { 3017 { "spec-ctrl", "on" }, 3018 { "model-id", 3019 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3020 { /* end of list */ } 3021 } 3022 }, 3023 { /* end of list */ } 3024 } 3025 }, 3026 { 3027 .name = "SandyBridge", 3028 .level = 0xd, 3029 .vendor = CPUID_VENDOR_INTEL, 3030 .family = 6, 3031 .model = 42, 3032 .stepping = 1, 3033 .features[FEAT_1_EDX] = 3034 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3035 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3036 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3037 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3038 CPUID_DE | CPUID_FP87, 3039 .features[FEAT_1_ECX] = 3040 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3041 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3042 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3043 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3044 CPUID_EXT_SSE3, 3045 .features[FEAT_8000_0001_EDX] = 3046 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3047 CPUID_EXT2_SYSCALL, 3048 .features[FEAT_8000_0001_ECX] = 3049 CPUID_EXT3_LAHF_LM, 3050 .features[FEAT_XSAVE] = 3051 CPUID_XSAVE_XSAVEOPT, 3052 .features[FEAT_6_EAX] = 3053 CPUID_6_EAX_ARAT, 3054 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3055 MSR_VMX_BASIC_TRUE_CTLS, 3056 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3057 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3058 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3059 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3060 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3061 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3062 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3063 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3064 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3065 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3066 .features[FEAT_VMX_EXIT_CTLS] = 3067 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3068 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3069 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3070 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3071 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3072 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3073 MSR_VMX_MISC_STORE_LMA, 3074 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3075 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3076 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3077 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3078 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3079 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3080 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3081 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3082 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3083 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3084 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3085 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3086 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3087 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3088 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3089 .features[FEAT_VMX_SECONDARY_CTLS] = 3090 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3091 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3092 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3093 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3094 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3095 .xlevel = 0x80000008, 3096 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3097 .versions = (X86CPUVersionDefinition[]) { 3098 { .version = 1 }, 3099 { 3100 .version = 2, 3101 .alias = "SandyBridge-IBRS", 3102 .props = (PropValue[]) { 3103 { "spec-ctrl", "on" }, 3104 { "model-id", 3105 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3106 { /* end of list */ } 3107 } 3108 }, 3109 { /* end of list */ } 3110 } 3111 }, 3112 { 3113 .name = "IvyBridge", 3114 .level = 0xd, 3115 .vendor = CPUID_VENDOR_INTEL, 3116 .family = 6, 3117 .model = 58, 3118 .stepping = 9, 3119 .features[FEAT_1_EDX] = 3120 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3121 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3122 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3123 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3124 CPUID_DE | CPUID_FP87, 3125 .features[FEAT_1_ECX] = 3126 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3127 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3128 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3129 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3130 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3131 .features[FEAT_7_0_EBX] = 3132 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3133 CPUID_7_0_EBX_ERMS, 3134 .features[FEAT_8000_0001_EDX] = 3135 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3136 CPUID_EXT2_SYSCALL, 3137 .features[FEAT_8000_0001_ECX] = 3138 CPUID_EXT3_LAHF_LM, 3139 .features[FEAT_XSAVE] = 3140 CPUID_XSAVE_XSAVEOPT, 3141 .features[FEAT_6_EAX] = 3142 CPUID_6_EAX_ARAT, 3143 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3144 MSR_VMX_BASIC_TRUE_CTLS, 3145 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3146 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3147 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3148 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3149 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3150 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3151 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3152 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3153 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3154 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3155 .features[FEAT_VMX_EXIT_CTLS] = 3156 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3157 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3158 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3159 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3160 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3161 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3162 MSR_VMX_MISC_STORE_LMA, 3163 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3164 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3165 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3166 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3167 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3168 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3169 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3170 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3171 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3172 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3173 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3174 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3175 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3176 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3177 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3178 .features[FEAT_VMX_SECONDARY_CTLS] = 3179 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3180 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3181 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3182 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3183 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3184 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3185 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3186 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3187 .xlevel = 0x80000008, 3188 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3189 .versions = (X86CPUVersionDefinition[]) { 3190 { .version = 1 }, 3191 { 3192 .version = 2, 3193 .alias = "IvyBridge-IBRS", 3194 .props = (PropValue[]) { 3195 { "spec-ctrl", "on" }, 3196 { "model-id", 3197 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3198 { /* end of list */ } 3199 } 3200 }, 3201 { /* end of list */ } 3202 } 3203 }, 3204 { 3205 .name = "Haswell", 3206 .level = 0xd, 3207 .vendor = CPUID_VENDOR_INTEL, 3208 .family = 6, 3209 .model = 60, 3210 .stepping = 4, 3211 .features[FEAT_1_EDX] = 3212 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3213 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3214 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3215 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3216 CPUID_DE | CPUID_FP87, 3217 .features[FEAT_1_ECX] = 3218 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3219 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3220 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3221 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3222 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3223 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3224 .features[FEAT_8000_0001_EDX] = 3225 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3226 CPUID_EXT2_SYSCALL, 3227 .features[FEAT_8000_0001_ECX] = 3228 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3229 .features[FEAT_7_0_EBX] = 3230 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3231 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3232 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3233 CPUID_7_0_EBX_RTM, 3234 .features[FEAT_XSAVE] = 3235 CPUID_XSAVE_XSAVEOPT, 3236 .features[FEAT_6_EAX] = 3237 CPUID_6_EAX_ARAT, 3238 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3239 MSR_VMX_BASIC_TRUE_CTLS, 3240 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3241 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3242 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3243 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3244 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3245 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3246 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3247 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3248 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3249 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3250 .features[FEAT_VMX_EXIT_CTLS] = 3251 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3252 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3253 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3254 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3255 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3256 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3257 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3258 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3259 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3260 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3261 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3262 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3263 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3264 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3265 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3266 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3267 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3268 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3269 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3270 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3271 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3272 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3273 .features[FEAT_VMX_SECONDARY_CTLS] = 3274 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3275 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3276 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3277 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3278 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3279 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3280 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3281 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3282 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3283 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3284 .xlevel = 0x80000008, 3285 .model_id = "Intel Core Processor (Haswell)", 3286 .versions = (X86CPUVersionDefinition[]) { 3287 { .version = 1 }, 3288 { 3289 .version = 2, 3290 .alias = "Haswell-noTSX", 3291 .props = (PropValue[]) { 3292 { "hle", "off" }, 3293 { "rtm", "off" }, 3294 { "stepping", "1" }, 3295 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3296 { /* end of list */ } 3297 }, 3298 }, 3299 { 3300 .version = 3, 3301 .alias = "Haswell-IBRS", 3302 .props = (PropValue[]) { 3303 /* Restore TSX features removed by -v2 above */ 3304 { "hle", "on" }, 3305 { "rtm", "on" }, 3306 /* 3307 * Haswell and Haswell-IBRS had stepping=4 in 3308 * QEMU 4.0 and older 3309 */ 3310 { "stepping", "4" }, 3311 { "spec-ctrl", "on" }, 3312 { "model-id", 3313 "Intel Core Processor (Haswell, IBRS)" }, 3314 { /* end of list */ } 3315 } 3316 }, 3317 { 3318 .version = 4, 3319 .alias = "Haswell-noTSX-IBRS", 3320 .props = (PropValue[]) { 3321 { "hle", "off" }, 3322 { "rtm", "off" }, 3323 /* spec-ctrl was already enabled by -v3 above */ 3324 { "stepping", "1" }, 3325 { "model-id", 3326 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3327 { /* end of list */ } 3328 } 3329 }, 3330 { /* end of list */ } 3331 } 3332 }, 3333 { 3334 .name = "Broadwell", 3335 .level = 0xd, 3336 .vendor = CPUID_VENDOR_INTEL, 3337 .family = 6, 3338 .model = 61, 3339 .stepping = 2, 3340 .features[FEAT_1_EDX] = 3341 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3342 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3343 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3344 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3345 CPUID_DE | CPUID_FP87, 3346 .features[FEAT_1_ECX] = 3347 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3348 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3349 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3350 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3351 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3352 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3353 .features[FEAT_8000_0001_EDX] = 3354 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3355 CPUID_EXT2_SYSCALL, 3356 .features[FEAT_8000_0001_ECX] = 3357 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3358 .features[FEAT_7_0_EBX] = 3359 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3360 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3361 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3362 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3363 CPUID_7_0_EBX_SMAP, 3364 .features[FEAT_XSAVE] = 3365 CPUID_XSAVE_XSAVEOPT, 3366 .features[FEAT_6_EAX] = 3367 CPUID_6_EAX_ARAT, 3368 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3369 MSR_VMX_BASIC_TRUE_CTLS, 3370 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3371 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3372 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3373 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3374 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3375 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3376 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3377 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3378 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3379 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3380 .features[FEAT_VMX_EXIT_CTLS] = 3381 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3382 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3383 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3384 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3385 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3386 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3387 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3388 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3389 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3390 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3391 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3392 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3393 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3394 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3395 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3396 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3397 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3398 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3399 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3400 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3401 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3402 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3403 .features[FEAT_VMX_SECONDARY_CTLS] = 3404 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3405 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3406 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3407 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3408 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3409 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3410 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3411 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3412 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3413 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3414 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3415 .xlevel = 0x80000008, 3416 .model_id = "Intel Core Processor (Broadwell)", 3417 .versions = (X86CPUVersionDefinition[]) { 3418 { .version = 1 }, 3419 { 3420 .version = 2, 3421 .alias = "Broadwell-noTSX", 3422 .props = (PropValue[]) { 3423 { "hle", "off" }, 3424 { "rtm", "off" }, 3425 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3426 { /* end of list */ } 3427 }, 3428 }, 3429 { 3430 .version = 3, 3431 .alias = "Broadwell-IBRS", 3432 .props = (PropValue[]) { 3433 /* Restore TSX features removed by -v2 above */ 3434 { "hle", "on" }, 3435 { "rtm", "on" }, 3436 { "spec-ctrl", "on" }, 3437 { "model-id", 3438 "Intel Core Processor (Broadwell, IBRS)" }, 3439 { /* end of list */ } 3440 } 3441 }, 3442 { 3443 .version = 4, 3444 .alias = "Broadwell-noTSX-IBRS", 3445 .props = (PropValue[]) { 3446 { "hle", "off" }, 3447 { "rtm", "off" }, 3448 /* spec-ctrl was already enabled by -v3 above */ 3449 { "model-id", 3450 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3451 { /* end of list */ } 3452 } 3453 }, 3454 { /* end of list */ } 3455 } 3456 }, 3457 { 3458 .name = "Skylake-Client", 3459 .level = 0xd, 3460 .vendor = CPUID_VENDOR_INTEL, 3461 .family = 6, 3462 .model = 94, 3463 .stepping = 3, 3464 .features[FEAT_1_EDX] = 3465 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3466 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3467 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3468 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3469 CPUID_DE | CPUID_FP87, 3470 .features[FEAT_1_ECX] = 3471 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3472 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3473 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3474 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3475 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3476 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3477 .features[FEAT_8000_0001_EDX] = 3478 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3479 CPUID_EXT2_SYSCALL, 3480 .features[FEAT_8000_0001_ECX] = 3481 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3482 .features[FEAT_7_0_EBX] = 3483 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3484 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3485 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3486 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3487 CPUID_7_0_EBX_SMAP, 3488 /* XSAVES is added in version 4 */ 3489 .features[FEAT_XSAVE] = 3490 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3491 CPUID_XSAVE_XGETBV1, 3492 .features[FEAT_6_EAX] = 3493 CPUID_6_EAX_ARAT, 3494 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3495 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3496 MSR_VMX_BASIC_TRUE_CTLS, 3497 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3498 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3499 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3500 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3501 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3502 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3503 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3504 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3505 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3506 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3507 .features[FEAT_VMX_EXIT_CTLS] = 3508 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3509 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3510 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3511 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3512 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3513 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3514 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3515 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3516 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3517 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3518 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3519 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3520 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3521 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3522 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3523 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3524 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3525 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3526 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3527 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3528 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3529 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3530 .features[FEAT_VMX_SECONDARY_CTLS] = 3531 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3532 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3533 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3534 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3535 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3536 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3537 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3538 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3539 .xlevel = 0x80000008, 3540 .model_id = "Intel Core Processor (Skylake)", 3541 .versions = (X86CPUVersionDefinition[]) { 3542 { .version = 1 }, 3543 { 3544 .version = 2, 3545 .alias = "Skylake-Client-IBRS", 3546 .props = (PropValue[]) { 3547 { "spec-ctrl", "on" }, 3548 { "model-id", 3549 "Intel Core Processor (Skylake, IBRS)" }, 3550 { /* end of list */ } 3551 } 3552 }, 3553 { 3554 .version = 3, 3555 .alias = "Skylake-Client-noTSX-IBRS", 3556 .props = (PropValue[]) { 3557 { "hle", "off" }, 3558 { "rtm", "off" }, 3559 { "model-id", 3560 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3561 { /* end of list */ } 3562 } 3563 }, 3564 { 3565 .version = 4, 3566 .note = "IBRS, XSAVES, no TSX", 3567 .props = (PropValue[]) { 3568 { "xsaves", "on" }, 3569 { "vmx-xsaves", "on" }, 3570 { /* end of list */ } 3571 } 3572 }, 3573 { /* end of list */ } 3574 } 3575 }, 3576 { 3577 .name = "Skylake-Server", 3578 .level = 0xd, 3579 .vendor = CPUID_VENDOR_INTEL, 3580 .family = 6, 3581 .model = 85, 3582 .stepping = 4, 3583 .features[FEAT_1_EDX] = 3584 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3585 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3586 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3587 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3588 CPUID_DE | CPUID_FP87, 3589 .features[FEAT_1_ECX] = 3590 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3591 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3592 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3593 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3594 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3595 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3596 .features[FEAT_8000_0001_EDX] = 3597 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3598 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3599 .features[FEAT_8000_0001_ECX] = 3600 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3601 .features[FEAT_7_0_EBX] = 3602 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3603 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3604 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3605 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3606 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3607 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3608 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3609 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3610 .features[FEAT_7_0_ECX] = 3611 CPUID_7_0_ECX_PKU, 3612 /* XSAVES is added in version 5 */ 3613 .features[FEAT_XSAVE] = 3614 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3615 CPUID_XSAVE_XGETBV1, 3616 .features[FEAT_6_EAX] = 3617 CPUID_6_EAX_ARAT, 3618 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3619 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3620 MSR_VMX_BASIC_TRUE_CTLS, 3621 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3622 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3623 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3624 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3625 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3626 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3627 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3628 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3629 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3630 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3631 .features[FEAT_VMX_EXIT_CTLS] = 3632 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3633 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3634 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3635 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3636 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3637 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3638 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3639 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3640 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3641 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3642 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3643 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3644 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3645 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3646 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3647 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3648 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3649 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3650 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3651 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3652 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3653 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3654 .features[FEAT_VMX_SECONDARY_CTLS] = 3655 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3656 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3657 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3658 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3659 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3660 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3661 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3662 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3663 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3664 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3665 .xlevel = 0x80000008, 3666 .model_id = "Intel Xeon Processor (Skylake)", 3667 .versions = (X86CPUVersionDefinition[]) { 3668 { .version = 1 }, 3669 { 3670 .version = 2, 3671 .alias = "Skylake-Server-IBRS", 3672 .props = (PropValue[]) { 3673 /* clflushopt was not added to Skylake-Server-IBRS */ 3674 /* TODO: add -v3 including clflushopt */ 3675 { "clflushopt", "off" }, 3676 { "spec-ctrl", "on" }, 3677 { "model-id", 3678 "Intel Xeon Processor (Skylake, IBRS)" }, 3679 { /* end of list */ } 3680 } 3681 }, 3682 { 3683 .version = 3, 3684 .alias = "Skylake-Server-noTSX-IBRS", 3685 .props = (PropValue[]) { 3686 { "hle", "off" }, 3687 { "rtm", "off" }, 3688 { "model-id", 3689 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3690 { /* end of list */ } 3691 } 3692 }, 3693 { 3694 .version = 4, 3695 .note = "IBRS, EPT switching, no TSX", 3696 .props = (PropValue[]) { 3697 { "vmx-eptp-switching", "on" }, 3698 { /* end of list */ } 3699 } 3700 }, 3701 { 3702 .version = 5, 3703 .note = "IBRS, XSAVES, EPT switching, no TSX", 3704 .props = (PropValue[]) { 3705 { "xsaves", "on" }, 3706 { "vmx-xsaves", "on" }, 3707 { /* end of list */ } 3708 } 3709 }, 3710 { /* end of list */ } 3711 } 3712 }, 3713 { 3714 .name = "Cascadelake-Server", 3715 .level = 0xd, 3716 .vendor = CPUID_VENDOR_INTEL, 3717 .family = 6, 3718 .model = 85, 3719 .stepping = 6, 3720 .features[FEAT_1_EDX] = 3721 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3722 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3723 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3724 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3725 CPUID_DE | CPUID_FP87, 3726 .features[FEAT_1_ECX] = 3727 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3728 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3729 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3730 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3731 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3732 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3733 .features[FEAT_8000_0001_EDX] = 3734 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3735 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3736 .features[FEAT_8000_0001_ECX] = 3737 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3738 .features[FEAT_7_0_EBX] = 3739 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3740 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3741 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3742 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3743 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3744 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3745 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3746 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3747 .features[FEAT_7_0_ECX] = 3748 CPUID_7_0_ECX_PKU | 3749 CPUID_7_0_ECX_AVX512VNNI, 3750 .features[FEAT_7_0_EDX] = 3751 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3752 /* XSAVES is added in version 5 */ 3753 .features[FEAT_XSAVE] = 3754 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3755 CPUID_XSAVE_XGETBV1, 3756 .features[FEAT_6_EAX] = 3757 CPUID_6_EAX_ARAT, 3758 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3759 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3760 MSR_VMX_BASIC_TRUE_CTLS, 3761 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3762 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3763 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3764 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3765 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3766 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3767 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3768 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3769 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3770 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3771 .features[FEAT_VMX_EXIT_CTLS] = 3772 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3773 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3774 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3775 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3776 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3777 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3778 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3779 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3780 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3781 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3782 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3783 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3784 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3785 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3786 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3787 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3788 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3789 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3790 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3791 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3792 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3793 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3794 .features[FEAT_VMX_SECONDARY_CTLS] = 3795 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3796 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3797 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3798 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3799 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3800 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3801 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3802 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3803 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3804 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3805 .xlevel = 0x80000008, 3806 .model_id = "Intel Xeon Processor (Cascadelake)", 3807 .versions = (X86CPUVersionDefinition[]) { 3808 { .version = 1 }, 3809 { .version = 2, 3810 .note = "ARCH_CAPABILITIES", 3811 .props = (PropValue[]) { 3812 { "arch-capabilities", "on" }, 3813 { "rdctl-no", "on" }, 3814 { "ibrs-all", "on" }, 3815 { "skip-l1dfl-vmentry", "on" }, 3816 { "mds-no", "on" }, 3817 { /* end of list */ } 3818 }, 3819 }, 3820 { .version = 3, 3821 .alias = "Cascadelake-Server-noTSX", 3822 .note = "ARCH_CAPABILITIES, no TSX", 3823 .props = (PropValue[]) { 3824 { "hle", "off" }, 3825 { "rtm", "off" }, 3826 { /* end of list */ } 3827 }, 3828 }, 3829 { .version = 4, 3830 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 3831 .props = (PropValue[]) { 3832 { "vmx-eptp-switching", "on" }, 3833 { /* end of list */ } 3834 }, 3835 }, 3836 { .version = 5, 3837 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3838 .props = (PropValue[]) { 3839 { "xsaves", "on" }, 3840 { "vmx-xsaves", "on" }, 3841 { /* end of list */ } 3842 }, 3843 }, 3844 { /* end of list */ } 3845 } 3846 }, 3847 { 3848 .name = "Cooperlake", 3849 .level = 0xd, 3850 .vendor = CPUID_VENDOR_INTEL, 3851 .family = 6, 3852 .model = 85, 3853 .stepping = 10, 3854 .features[FEAT_1_EDX] = 3855 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3856 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3857 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3858 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3859 CPUID_DE | CPUID_FP87, 3860 .features[FEAT_1_ECX] = 3861 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3862 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3863 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3864 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3865 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3866 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3867 .features[FEAT_8000_0001_EDX] = 3868 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3869 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3870 .features[FEAT_8000_0001_ECX] = 3871 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3872 .features[FEAT_7_0_EBX] = 3873 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3874 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3875 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3876 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3877 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3878 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3879 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3880 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3881 .features[FEAT_7_0_ECX] = 3882 CPUID_7_0_ECX_PKU | 3883 CPUID_7_0_ECX_AVX512VNNI, 3884 .features[FEAT_7_0_EDX] = 3885 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3886 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3887 .features[FEAT_ARCH_CAPABILITIES] = 3888 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3889 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3890 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3891 .features[FEAT_7_1_EAX] = 3892 CPUID_7_1_EAX_AVX512_BF16, 3893 /* XSAVES is added in version 2 */ 3894 .features[FEAT_XSAVE] = 3895 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3896 CPUID_XSAVE_XGETBV1, 3897 .features[FEAT_6_EAX] = 3898 CPUID_6_EAX_ARAT, 3899 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3900 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3901 MSR_VMX_BASIC_TRUE_CTLS, 3902 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3903 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3904 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3905 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3906 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3907 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3908 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3909 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3910 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3911 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3912 .features[FEAT_VMX_EXIT_CTLS] = 3913 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3914 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3915 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3916 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3917 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3918 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3919 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3920 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3921 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3922 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3923 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3924 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3925 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3926 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3927 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3928 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3929 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3930 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3931 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3932 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3933 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3934 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3935 .features[FEAT_VMX_SECONDARY_CTLS] = 3936 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3937 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3938 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3939 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3940 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3941 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3942 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3943 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3944 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3945 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3946 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3947 .xlevel = 0x80000008, 3948 .model_id = "Intel Xeon Processor (Cooperlake)", 3949 .versions = (X86CPUVersionDefinition[]) { 3950 { .version = 1 }, 3951 { .version = 2, 3952 .note = "XSAVES", 3953 .props = (PropValue[]) { 3954 { "xsaves", "on" }, 3955 { "vmx-xsaves", "on" }, 3956 { /* end of list */ } 3957 }, 3958 }, 3959 { /* end of list */ } 3960 } 3961 }, 3962 { 3963 .name = "Icelake-Server", 3964 .level = 0xd, 3965 .vendor = CPUID_VENDOR_INTEL, 3966 .family = 6, 3967 .model = 134, 3968 .stepping = 0, 3969 .features[FEAT_1_EDX] = 3970 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3971 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3972 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3973 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3974 CPUID_DE | CPUID_FP87, 3975 .features[FEAT_1_ECX] = 3976 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3977 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3978 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3979 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3980 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3981 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3982 .features[FEAT_8000_0001_EDX] = 3983 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3984 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3985 .features[FEAT_8000_0001_ECX] = 3986 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3987 .features[FEAT_8000_0008_EBX] = 3988 CPUID_8000_0008_EBX_WBNOINVD, 3989 .features[FEAT_7_0_EBX] = 3990 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3991 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3992 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3993 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3994 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3995 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3996 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3997 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3998 .features[FEAT_7_0_ECX] = 3999 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4000 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4001 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4002 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4003 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4004 .features[FEAT_7_0_EDX] = 4005 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4006 /* XSAVES is added in version 5 */ 4007 .features[FEAT_XSAVE] = 4008 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4009 CPUID_XSAVE_XGETBV1, 4010 .features[FEAT_6_EAX] = 4011 CPUID_6_EAX_ARAT, 4012 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4013 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4014 MSR_VMX_BASIC_TRUE_CTLS, 4015 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4016 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4017 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4018 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4019 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4020 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4021 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4022 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4023 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4024 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4025 .features[FEAT_VMX_EXIT_CTLS] = 4026 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4027 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4028 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4029 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4030 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4031 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4032 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4033 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4034 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4035 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4036 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4037 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4038 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4039 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4040 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4041 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4042 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4043 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4044 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4045 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4046 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4047 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4048 .features[FEAT_VMX_SECONDARY_CTLS] = 4049 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4050 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4051 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4052 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4053 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4054 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4055 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4056 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4057 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4058 .xlevel = 0x80000008, 4059 .model_id = "Intel Xeon Processor (Icelake)", 4060 .versions = (X86CPUVersionDefinition[]) { 4061 { .version = 1 }, 4062 { 4063 .version = 2, 4064 .note = "no TSX", 4065 .alias = "Icelake-Server-noTSX", 4066 .props = (PropValue[]) { 4067 { "hle", "off" }, 4068 { "rtm", "off" }, 4069 { /* end of list */ } 4070 }, 4071 }, 4072 { 4073 .version = 3, 4074 .props = (PropValue[]) { 4075 { "arch-capabilities", "on" }, 4076 { "rdctl-no", "on" }, 4077 { "ibrs-all", "on" }, 4078 { "skip-l1dfl-vmentry", "on" }, 4079 { "mds-no", "on" }, 4080 { "pschange-mc-no", "on" }, 4081 { "taa-no", "on" }, 4082 { /* end of list */ } 4083 }, 4084 }, 4085 { 4086 .version = 4, 4087 .props = (PropValue[]) { 4088 { "sha-ni", "on" }, 4089 { "avx512ifma", "on" }, 4090 { "rdpid", "on" }, 4091 { "fsrm", "on" }, 4092 { "vmx-rdseed-exit", "on" }, 4093 { "vmx-pml", "on" }, 4094 { "vmx-eptp-switching", "on" }, 4095 { "model", "106" }, 4096 { /* end of list */ } 4097 }, 4098 }, 4099 { 4100 .version = 5, 4101 .note = "XSAVES", 4102 .props = (PropValue[]) { 4103 { "xsaves", "on" }, 4104 { "vmx-xsaves", "on" }, 4105 { /* end of list */ } 4106 }, 4107 }, 4108 { 4109 .version = 6, 4110 .note = "5-level EPT", 4111 .props = (PropValue[]) { 4112 { "vmx-page-walk-5", "on" }, 4113 { /* end of list */ } 4114 }, 4115 }, 4116 { 4117 .version = 7, 4118 .note = "TSX, taa-no", 4119 .props = (PropValue[]) { 4120 /* Restore TSX features removed by -v2 above */ 4121 { "hle", "on" }, 4122 { "rtm", "on" }, 4123 { /* end of list */ } 4124 }, 4125 }, 4126 { /* end of list */ } 4127 } 4128 }, 4129 { 4130 .name = "SapphireRapids", 4131 .level = 0x20, 4132 .vendor = CPUID_VENDOR_INTEL, 4133 .family = 6, 4134 .model = 143, 4135 .stepping = 4, 4136 /* 4137 * please keep the ascending order so that we can have a clear view of 4138 * bit position of each feature. 4139 */ 4140 .features[FEAT_1_EDX] = 4141 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4142 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4143 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4144 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4145 CPUID_SSE | CPUID_SSE2, 4146 .features[FEAT_1_ECX] = 4147 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4148 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4149 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4150 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4151 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4152 .features[FEAT_8000_0001_EDX] = 4153 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4154 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4155 .features[FEAT_8000_0001_ECX] = 4156 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4157 .features[FEAT_8000_0008_EBX] = 4158 CPUID_8000_0008_EBX_WBNOINVD, 4159 .features[FEAT_7_0_EBX] = 4160 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4161 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4162 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4163 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4164 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4165 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4166 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4167 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4168 .features[FEAT_7_0_ECX] = 4169 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4170 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4171 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4172 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4173 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4174 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4175 .features[FEAT_7_0_EDX] = 4176 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4177 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4178 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4179 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4180 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4181 .features[FEAT_ARCH_CAPABILITIES] = 4182 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4183 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4184 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4185 .features[FEAT_XSAVE] = 4186 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4187 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4188 .features[FEAT_6_EAX] = 4189 CPUID_6_EAX_ARAT, 4190 .features[FEAT_7_1_EAX] = 4191 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4192 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4193 .features[FEAT_VMX_BASIC] = 4194 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4195 .features[FEAT_VMX_ENTRY_CTLS] = 4196 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4197 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4198 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4199 .features[FEAT_VMX_EPT_VPID_CAPS] = 4200 MSR_VMX_EPT_EXECONLY | 4201 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4202 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4203 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4204 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4205 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4206 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4207 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4208 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4209 .features[FEAT_VMX_EXIT_CTLS] = 4210 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4211 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4212 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4213 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4214 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4215 .features[FEAT_VMX_MISC] = 4216 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4217 MSR_VMX_MISC_VMWRITE_VMEXIT, 4218 .features[FEAT_VMX_PINBASED_CTLS] = 4219 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4220 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4221 VMX_PIN_BASED_POSTED_INTR, 4222 .features[FEAT_VMX_PROCBASED_CTLS] = 4223 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4224 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4225 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4226 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4227 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4228 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4229 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4230 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4231 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4232 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4233 VMX_CPU_BASED_PAUSE_EXITING | 4234 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4235 .features[FEAT_VMX_SECONDARY_CTLS] = 4236 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4237 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4238 VMX_SECONDARY_EXEC_RDTSCP | 4239 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4240 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4241 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4242 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4243 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4244 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4245 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4246 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4247 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4248 VMX_SECONDARY_EXEC_XSAVES, 4249 .features[FEAT_VMX_VMFUNC] = 4250 MSR_VMX_VMFUNC_EPT_SWITCHING, 4251 .xlevel = 0x80000008, 4252 .model_id = "Intel Xeon Processor (SapphireRapids)", 4253 .versions = (X86CPUVersionDefinition[]) { 4254 { .version = 1 }, 4255 { 4256 .version = 2, 4257 .props = (PropValue[]) { 4258 { "sbdr-ssdp-no", "on" }, 4259 { "fbsdp-no", "on" }, 4260 { "psdp-no", "on" }, 4261 { /* end of list */ } 4262 } 4263 }, 4264 { 4265 .version = 3, 4266 .props = (PropValue[]) { 4267 { "ss", "on" }, 4268 { "tsc-adjust", "on" }, 4269 { "cldemote", "on" }, 4270 { "movdiri", "on" }, 4271 { "movdir64b", "on" }, 4272 { /* end of list */ } 4273 } 4274 }, 4275 { /* end of list */ } 4276 } 4277 }, 4278 { 4279 .name = "GraniteRapids", 4280 .level = 0x20, 4281 .vendor = CPUID_VENDOR_INTEL, 4282 .family = 6, 4283 .model = 173, 4284 .stepping = 0, 4285 /* 4286 * please keep the ascending order so that we can have a clear view of 4287 * bit position of each feature. 4288 */ 4289 .features[FEAT_1_EDX] = 4290 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4291 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4292 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4293 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4294 CPUID_SSE | CPUID_SSE2, 4295 .features[FEAT_1_ECX] = 4296 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4297 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4298 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4299 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4300 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4301 .features[FEAT_8000_0001_EDX] = 4302 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4303 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4304 .features[FEAT_8000_0001_ECX] = 4305 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4306 .features[FEAT_8000_0008_EBX] = 4307 CPUID_8000_0008_EBX_WBNOINVD, 4308 .features[FEAT_7_0_EBX] = 4309 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4310 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4311 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4312 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4313 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4314 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4315 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4316 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4317 .features[FEAT_7_0_ECX] = 4318 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4319 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4320 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4321 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4322 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4323 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4324 .features[FEAT_7_0_EDX] = 4325 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4326 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4327 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4328 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4329 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4330 .features[FEAT_ARCH_CAPABILITIES] = 4331 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4332 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4333 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4334 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4335 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4336 .features[FEAT_XSAVE] = 4337 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4338 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4339 .features[FEAT_6_EAX] = 4340 CPUID_6_EAX_ARAT, 4341 .features[FEAT_7_1_EAX] = 4342 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4343 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4344 CPUID_7_1_EAX_AMX_FP16, 4345 .features[FEAT_7_1_EDX] = 4346 CPUID_7_1_EDX_PREFETCHITI, 4347 .features[FEAT_7_2_EDX] = 4348 CPUID_7_2_EDX_MCDT_NO, 4349 .features[FEAT_VMX_BASIC] = 4350 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4351 .features[FEAT_VMX_ENTRY_CTLS] = 4352 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4353 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4354 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4355 .features[FEAT_VMX_EPT_VPID_CAPS] = 4356 MSR_VMX_EPT_EXECONLY | 4357 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4358 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4359 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4360 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4361 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4362 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4363 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4364 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4365 .features[FEAT_VMX_EXIT_CTLS] = 4366 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4367 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4368 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4369 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4370 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4371 .features[FEAT_VMX_MISC] = 4372 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4373 MSR_VMX_MISC_VMWRITE_VMEXIT, 4374 .features[FEAT_VMX_PINBASED_CTLS] = 4375 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4376 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4377 VMX_PIN_BASED_POSTED_INTR, 4378 .features[FEAT_VMX_PROCBASED_CTLS] = 4379 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4380 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4381 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4382 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4383 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4384 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4385 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4386 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4387 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4388 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4389 VMX_CPU_BASED_PAUSE_EXITING | 4390 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4391 .features[FEAT_VMX_SECONDARY_CTLS] = 4392 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4393 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4394 VMX_SECONDARY_EXEC_RDTSCP | 4395 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4396 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4397 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4398 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4399 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4400 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4401 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4402 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4403 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4404 VMX_SECONDARY_EXEC_XSAVES, 4405 .features[FEAT_VMX_VMFUNC] = 4406 MSR_VMX_VMFUNC_EPT_SWITCHING, 4407 .xlevel = 0x80000008, 4408 .model_id = "Intel Xeon Processor (GraniteRapids)", 4409 .versions = (X86CPUVersionDefinition[]) { 4410 { .version = 1 }, 4411 { 4412 .version = 2, 4413 .props = (PropValue[]) { 4414 { "ss", "on" }, 4415 { "tsc-adjust", "on" }, 4416 { "cldemote", "on" }, 4417 { "movdiri", "on" }, 4418 { "movdir64b", "on" }, 4419 { "avx10", "on" }, 4420 { "avx10-128", "on" }, 4421 { "avx10-256", "on" }, 4422 { "avx10-512", "on" }, 4423 { "avx10-version", "1" }, 4424 { "stepping", "1" }, 4425 { /* end of list */ } 4426 } 4427 }, 4428 { /* end of list */ }, 4429 }, 4430 }, 4431 { 4432 .name = "SierraForest", 4433 .level = 0x23, 4434 .vendor = CPUID_VENDOR_INTEL, 4435 .family = 6, 4436 .model = 175, 4437 .stepping = 0, 4438 /* 4439 * please keep the ascending order so that we can have a clear view of 4440 * bit position of each feature. 4441 */ 4442 .features[FEAT_1_EDX] = 4443 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4444 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4445 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4446 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4447 CPUID_SSE | CPUID_SSE2, 4448 .features[FEAT_1_ECX] = 4449 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4450 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4451 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4452 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4453 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4454 .features[FEAT_8000_0001_EDX] = 4455 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4456 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4457 .features[FEAT_8000_0001_ECX] = 4458 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4459 .features[FEAT_8000_0008_EBX] = 4460 CPUID_8000_0008_EBX_WBNOINVD, 4461 .features[FEAT_7_0_EBX] = 4462 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4463 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4464 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4465 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4466 CPUID_7_0_EBX_SHA_NI, 4467 .features[FEAT_7_0_ECX] = 4468 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4469 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4470 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4471 .features[FEAT_7_0_EDX] = 4472 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4473 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4474 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4475 .features[FEAT_ARCH_CAPABILITIES] = 4476 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4477 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4478 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4479 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4480 MSR_ARCH_CAP_PBRSB_NO, 4481 .features[FEAT_XSAVE] = 4482 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4483 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4484 .features[FEAT_6_EAX] = 4485 CPUID_6_EAX_ARAT, 4486 .features[FEAT_7_1_EAX] = 4487 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4488 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4489 .features[FEAT_7_1_EDX] = 4490 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4491 .features[FEAT_7_2_EDX] = 4492 CPUID_7_2_EDX_MCDT_NO, 4493 .features[FEAT_VMX_BASIC] = 4494 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4495 .features[FEAT_VMX_ENTRY_CTLS] = 4496 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4497 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4498 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4499 .features[FEAT_VMX_EPT_VPID_CAPS] = 4500 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4501 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4502 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4503 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4504 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4505 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4506 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4507 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4508 .features[FEAT_VMX_EXIT_CTLS] = 4509 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4510 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4511 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4512 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4513 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4514 .features[FEAT_VMX_MISC] = 4515 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4516 MSR_VMX_MISC_VMWRITE_VMEXIT, 4517 .features[FEAT_VMX_PINBASED_CTLS] = 4518 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4519 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4520 VMX_PIN_BASED_POSTED_INTR, 4521 .features[FEAT_VMX_PROCBASED_CTLS] = 4522 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4523 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4524 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4525 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4526 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4527 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4528 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4529 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4530 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4531 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4532 VMX_CPU_BASED_PAUSE_EXITING | 4533 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4534 .features[FEAT_VMX_SECONDARY_CTLS] = 4535 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4536 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4537 VMX_SECONDARY_EXEC_RDTSCP | 4538 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4539 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4540 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4541 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4542 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4543 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4544 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4545 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4546 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4547 VMX_SECONDARY_EXEC_XSAVES, 4548 .features[FEAT_VMX_VMFUNC] = 4549 MSR_VMX_VMFUNC_EPT_SWITCHING, 4550 .xlevel = 0x80000008, 4551 .model_id = "Intel Xeon Processor (SierraForest)", 4552 .versions = (X86CPUVersionDefinition[]) { 4553 { .version = 1 }, 4554 { /* end of list */ }, 4555 }, 4556 }, 4557 { 4558 .name = "Denverton", 4559 .level = 21, 4560 .vendor = CPUID_VENDOR_INTEL, 4561 .family = 6, 4562 .model = 95, 4563 .stepping = 1, 4564 .features[FEAT_1_EDX] = 4565 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4566 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4567 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4568 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4569 CPUID_SSE | CPUID_SSE2, 4570 .features[FEAT_1_ECX] = 4571 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4572 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4573 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4574 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4575 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4576 .features[FEAT_8000_0001_EDX] = 4577 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4578 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4579 .features[FEAT_8000_0001_ECX] = 4580 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4581 .features[FEAT_7_0_EBX] = 4582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4583 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4584 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4585 .features[FEAT_7_0_EDX] = 4586 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4587 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4588 /* XSAVES is added in version 3 */ 4589 .features[FEAT_XSAVE] = 4590 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4591 .features[FEAT_6_EAX] = 4592 CPUID_6_EAX_ARAT, 4593 .features[FEAT_ARCH_CAPABILITIES] = 4594 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4595 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4596 MSR_VMX_BASIC_TRUE_CTLS, 4597 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4598 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4599 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4600 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4601 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4602 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4603 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4604 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4605 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4606 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4607 .features[FEAT_VMX_EXIT_CTLS] = 4608 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4609 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4610 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4611 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4612 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4613 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4614 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4615 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4616 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4617 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4618 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4619 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4620 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4621 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4622 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4623 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4624 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4625 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4626 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4627 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4628 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4629 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4630 .features[FEAT_VMX_SECONDARY_CTLS] = 4631 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4632 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4633 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4634 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4635 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4636 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4637 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4638 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4639 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4640 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4641 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4642 .xlevel = 0x80000008, 4643 .model_id = "Intel Atom Processor (Denverton)", 4644 .versions = (X86CPUVersionDefinition[]) { 4645 { .version = 1 }, 4646 { 4647 .version = 2, 4648 .note = "no MPX, no MONITOR", 4649 .props = (PropValue[]) { 4650 { "monitor", "off" }, 4651 { "mpx", "off" }, 4652 { /* end of list */ }, 4653 }, 4654 }, 4655 { 4656 .version = 3, 4657 .note = "XSAVES, no MPX, no MONITOR", 4658 .props = (PropValue[]) { 4659 { "xsaves", "on" }, 4660 { "vmx-xsaves", "on" }, 4661 { /* end of list */ }, 4662 }, 4663 }, 4664 { /* end of list */ }, 4665 }, 4666 }, 4667 { 4668 .name = "Snowridge", 4669 .level = 27, 4670 .vendor = CPUID_VENDOR_INTEL, 4671 .family = 6, 4672 .model = 134, 4673 .stepping = 1, 4674 .features[FEAT_1_EDX] = 4675 /* missing: CPUID_PN CPUID_IA64 */ 4676 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4677 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4678 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4679 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4680 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4681 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4682 CPUID_MMX | 4683 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4684 .features[FEAT_1_ECX] = 4685 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4686 CPUID_EXT_SSSE3 | 4687 CPUID_EXT_CX16 | 4688 CPUID_EXT_SSE41 | 4689 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4690 CPUID_EXT_POPCNT | 4691 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4692 CPUID_EXT_RDRAND, 4693 .features[FEAT_8000_0001_EDX] = 4694 CPUID_EXT2_SYSCALL | 4695 CPUID_EXT2_NX | 4696 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4697 CPUID_EXT2_LM, 4698 .features[FEAT_8000_0001_ECX] = 4699 CPUID_EXT3_LAHF_LM | 4700 CPUID_EXT3_3DNOWPREFETCH, 4701 .features[FEAT_7_0_EBX] = 4702 CPUID_7_0_EBX_FSGSBASE | 4703 CPUID_7_0_EBX_SMEP | 4704 CPUID_7_0_EBX_ERMS | 4705 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4706 CPUID_7_0_EBX_RDSEED | 4707 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4708 CPUID_7_0_EBX_CLWB | 4709 CPUID_7_0_EBX_SHA_NI, 4710 .features[FEAT_7_0_ECX] = 4711 CPUID_7_0_ECX_UMIP | 4712 /* missing bit 5 */ 4713 CPUID_7_0_ECX_GFNI | 4714 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4715 CPUID_7_0_ECX_MOVDIR64B, 4716 .features[FEAT_7_0_EDX] = 4717 CPUID_7_0_EDX_SPEC_CTRL | 4718 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4719 CPUID_7_0_EDX_CORE_CAPABILITY, 4720 .features[FEAT_CORE_CAPABILITY] = 4721 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4722 /* XSAVES is added in version 3 */ 4723 .features[FEAT_XSAVE] = 4724 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4725 CPUID_XSAVE_XGETBV1, 4726 .features[FEAT_6_EAX] = 4727 CPUID_6_EAX_ARAT, 4728 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4729 MSR_VMX_BASIC_TRUE_CTLS, 4730 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4731 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4732 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4733 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4734 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4735 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4736 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4737 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4738 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4739 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4740 .features[FEAT_VMX_EXIT_CTLS] = 4741 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4742 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4743 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4744 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4745 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4746 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4747 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4748 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4749 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4750 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4751 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4752 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4753 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4754 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4755 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4756 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4757 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4758 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4759 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4760 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4761 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4762 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4763 .features[FEAT_VMX_SECONDARY_CTLS] = 4764 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4765 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4766 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4767 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4768 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4769 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4770 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4771 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4772 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4773 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4774 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4775 .xlevel = 0x80000008, 4776 .model_id = "Intel Atom Processor (SnowRidge)", 4777 .versions = (X86CPUVersionDefinition[]) { 4778 { .version = 1 }, 4779 { 4780 .version = 2, 4781 .props = (PropValue[]) { 4782 { "mpx", "off" }, 4783 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4784 { /* end of list */ }, 4785 }, 4786 }, 4787 { 4788 .version = 3, 4789 .note = "XSAVES, no MPX", 4790 .props = (PropValue[]) { 4791 { "xsaves", "on" }, 4792 { "vmx-xsaves", "on" }, 4793 { /* end of list */ }, 4794 }, 4795 }, 4796 { 4797 .version = 4, 4798 .note = "no split lock detect, no core-capability", 4799 .props = (PropValue[]) { 4800 { "split-lock-detect", "off" }, 4801 { "core-capability", "off" }, 4802 { /* end of list */ }, 4803 }, 4804 }, 4805 { /* end of list */ }, 4806 }, 4807 }, 4808 { 4809 .name = "KnightsMill", 4810 .level = 0xd, 4811 .vendor = CPUID_VENDOR_INTEL, 4812 .family = 6, 4813 .model = 133, 4814 .stepping = 0, 4815 .features[FEAT_1_EDX] = 4816 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4817 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4818 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4819 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4820 CPUID_PSE | CPUID_DE | CPUID_FP87, 4821 .features[FEAT_1_ECX] = 4822 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4823 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4824 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4825 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4826 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4827 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4828 .features[FEAT_8000_0001_EDX] = 4829 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4830 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4831 .features[FEAT_8000_0001_ECX] = 4832 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4833 .features[FEAT_7_0_EBX] = 4834 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4835 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4836 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4837 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4838 CPUID_7_0_EBX_AVX512ER, 4839 .features[FEAT_7_0_ECX] = 4840 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4841 .features[FEAT_7_0_EDX] = 4842 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4843 .features[FEAT_XSAVE] = 4844 CPUID_XSAVE_XSAVEOPT, 4845 .features[FEAT_6_EAX] = 4846 CPUID_6_EAX_ARAT, 4847 .xlevel = 0x80000008, 4848 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4849 }, 4850 { 4851 .name = "Opteron_G1", 4852 .level = 5, 4853 .vendor = CPUID_VENDOR_AMD, 4854 .family = 15, 4855 .model = 6, 4856 .stepping = 1, 4857 .features[FEAT_1_EDX] = 4858 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4859 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4860 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4861 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4862 CPUID_DE | CPUID_FP87, 4863 .features[FEAT_1_ECX] = 4864 CPUID_EXT_SSE3, 4865 .features[FEAT_8000_0001_EDX] = 4866 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4867 .xlevel = 0x80000008, 4868 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4869 }, 4870 { 4871 .name = "Opteron_G2", 4872 .level = 5, 4873 .vendor = CPUID_VENDOR_AMD, 4874 .family = 15, 4875 .model = 6, 4876 .stepping = 1, 4877 .features[FEAT_1_EDX] = 4878 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4879 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4880 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4881 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4882 CPUID_DE | CPUID_FP87, 4883 .features[FEAT_1_ECX] = 4884 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4885 .features[FEAT_8000_0001_EDX] = 4886 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4887 .features[FEAT_8000_0001_ECX] = 4888 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4889 .xlevel = 0x80000008, 4890 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4891 }, 4892 { 4893 .name = "Opteron_G3", 4894 .level = 5, 4895 .vendor = CPUID_VENDOR_AMD, 4896 .family = 16, 4897 .model = 2, 4898 .stepping = 3, 4899 .features[FEAT_1_EDX] = 4900 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4901 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4902 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4903 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4904 CPUID_DE | CPUID_FP87, 4905 .features[FEAT_1_ECX] = 4906 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4907 CPUID_EXT_SSE3, 4908 .features[FEAT_8000_0001_EDX] = 4909 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4910 CPUID_EXT2_RDTSCP, 4911 .features[FEAT_8000_0001_ECX] = 4912 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4913 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4914 .xlevel = 0x80000008, 4915 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4916 }, 4917 { 4918 .name = "Opteron_G4", 4919 .level = 0xd, 4920 .vendor = CPUID_VENDOR_AMD, 4921 .family = 21, 4922 .model = 1, 4923 .stepping = 2, 4924 .features[FEAT_1_EDX] = 4925 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4926 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4927 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4928 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4929 CPUID_DE | CPUID_FP87, 4930 .features[FEAT_1_ECX] = 4931 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4932 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4933 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4934 CPUID_EXT_SSE3, 4935 .features[FEAT_8000_0001_EDX] = 4936 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4937 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4938 .features[FEAT_8000_0001_ECX] = 4939 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4940 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4941 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4942 CPUID_EXT3_LAHF_LM, 4943 .features[FEAT_SVM] = 4944 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4945 /* no xsaveopt! */ 4946 .xlevel = 0x8000001A, 4947 .model_id = "AMD Opteron 62xx class CPU", 4948 }, 4949 { 4950 .name = "Opteron_G5", 4951 .level = 0xd, 4952 .vendor = CPUID_VENDOR_AMD, 4953 .family = 21, 4954 .model = 2, 4955 .stepping = 0, 4956 .features[FEAT_1_EDX] = 4957 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4958 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4959 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4960 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4961 CPUID_DE | CPUID_FP87, 4962 .features[FEAT_1_ECX] = 4963 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4964 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4965 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4966 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4967 .features[FEAT_8000_0001_EDX] = 4968 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4969 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4970 .features[FEAT_8000_0001_ECX] = 4971 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4972 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4973 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4974 CPUID_EXT3_LAHF_LM, 4975 .features[FEAT_SVM] = 4976 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4977 /* no xsaveopt! */ 4978 .xlevel = 0x8000001A, 4979 .model_id = "AMD Opteron 63xx class CPU", 4980 }, 4981 { 4982 .name = "EPYC", 4983 .level = 0xd, 4984 .vendor = CPUID_VENDOR_AMD, 4985 .family = 23, 4986 .model = 1, 4987 .stepping = 2, 4988 .features[FEAT_1_EDX] = 4989 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4990 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4991 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4992 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4993 CPUID_VME | CPUID_FP87, 4994 .features[FEAT_1_ECX] = 4995 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4996 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4997 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4998 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4999 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5000 .features[FEAT_8000_0001_EDX] = 5001 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5002 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5003 CPUID_EXT2_SYSCALL, 5004 .features[FEAT_8000_0001_ECX] = 5005 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5006 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5007 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5008 CPUID_EXT3_TOPOEXT, 5009 .features[FEAT_7_0_EBX] = 5010 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5011 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5012 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5013 CPUID_7_0_EBX_SHA_NI, 5014 .features[FEAT_XSAVE] = 5015 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5016 CPUID_XSAVE_XGETBV1, 5017 .features[FEAT_6_EAX] = 5018 CPUID_6_EAX_ARAT, 5019 .features[FEAT_SVM] = 5020 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5021 .xlevel = 0x8000001E, 5022 .model_id = "AMD EPYC Processor", 5023 .cache_info = &epyc_cache_info, 5024 .versions = (X86CPUVersionDefinition[]) { 5025 { .version = 1 }, 5026 { 5027 .version = 2, 5028 .alias = "EPYC-IBPB", 5029 .props = (PropValue[]) { 5030 { "ibpb", "on" }, 5031 { "model-id", 5032 "AMD EPYC Processor (with IBPB)" }, 5033 { /* end of list */ } 5034 } 5035 }, 5036 { 5037 .version = 3, 5038 .props = (PropValue[]) { 5039 { "ibpb", "on" }, 5040 { "perfctr-core", "on" }, 5041 { "clzero", "on" }, 5042 { "xsaveerptr", "on" }, 5043 { "xsaves", "on" }, 5044 { "model-id", 5045 "AMD EPYC Processor" }, 5046 { /* end of list */ } 5047 } 5048 }, 5049 { 5050 .version = 4, 5051 .props = (PropValue[]) { 5052 { "model-id", 5053 "AMD EPYC-v4 Processor" }, 5054 { /* end of list */ } 5055 }, 5056 .cache_info = &epyc_v4_cache_info 5057 }, 5058 { /* end of list */ } 5059 } 5060 }, 5061 { 5062 .name = "Dhyana", 5063 .level = 0xd, 5064 .vendor = CPUID_VENDOR_HYGON, 5065 .family = 24, 5066 .model = 0, 5067 .stepping = 1, 5068 .features[FEAT_1_EDX] = 5069 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5070 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5071 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5072 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5073 CPUID_VME | CPUID_FP87, 5074 .features[FEAT_1_ECX] = 5075 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5076 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5077 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5078 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5079 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5080 .features[FEAT_8000_0001_EDX] = 5081 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5082 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5083 CPUID_EXT2_SYSCALL, 5084 .features[FEAT_8000_0001_ECX] = 5085 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5086 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5087 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5088 CPUID_EXT3_TOPOEXT, 5089 .features[FEAT_8000_0008_EBX] = 5090 CPUID_8000_0008_EBX_IBPB, 5091 .features[FEAT_7_0_EBX] = 5092 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5093 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5094 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5095 /* XSAVES is added in version 2 */ 5096 .features[FEAT_XSAVE] = 5097 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5098 CPUID_XSAVE_XGETBV1, 5099 .features[FEAT_6_EAX] = 5100 CPUID_6_EAX_ARAT, 5101 .features[FEAT_SVM] = 5102 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5103 .xlevel = 0x8000001E, 5104 .model_id = "Hygon Dhyana Processor", 5105 .cache_info = &epyc_cache_info, 5106 .versions = (X86CPUVersionDefinition[]) { 5107 { .version = 1 }, 5108 { .version = 2, 5109 .note = "XSAVES", 5110 .props = (PropValue[]) { 5111 { "xsaves", "on" }, 5112 { /* end of list */ } 5113 }, 5114 }, 5115 { /* end of list */ } 5116 } 5117 }, 5118 { 5119 .name = "EPYC-Rome", 5120 .level = 0xd, 5121 .vendor = CPUID_VENDOR_AMD, 5122 .family = 23, 5123 .model = 49, 5124 .stepping = 0, 5125 .features[FEAT_1_EDX] = 5126 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5127 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5128 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5129 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5130 CPUID_VME | CPUID_FP87, 5131 .features[FEAT_1_ECX] = 5132 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5133 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5134 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5135 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5136 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5137 .features[FEAT_8000_0001_EDX] = 5138 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5139 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5140 CPUID_EXT2_SYSCALL, 5141 .features[FEAT_8000_0001_ECX] = 5142 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5143 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5144 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5145 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5146 .features[FEAT_8000_0008_EBX] = 5147 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5148 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5149 CPUID_8000_0008_EBX_STIBP, 5150 .features[FEAT_7_0_EBX] = 5151 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5152 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5153 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5154 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5155 .features[FEAT_7_0_ECX] = 5156 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5157 .features[FEAT_XSAVE] = 5158 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5159 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5160 .features[FEAT_6_EAX] = 5161 CPUID_6_EAX_ARAT, 5162 .features[FEAT_SVM] = 5163 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5164 .xlevel = 0x8000001E, 5165 .model_id = "AMD EPYC-Rome Processor", 5166 .cache_info = &epyc_rome_cache_info, 5167 .versions = (X86CPUVersionDefinition[]) { 5168 { .version = 1 }, 5169 { 5170 .version = 2, 5171 .props = (PropValue[]) { 5172 { "ibrs", "on" }, 5173 { "amd-ssbd", "on" }, 5174 { /* end of list */ } 5175 } 5176 }, 5177 { 5178 .version = 3, 5179 .props = (PropValue[]) { 5180 { "model-id", 5181 "AMD EPYC-Rome-v3 Processor" }, 5182 { /* end of list */ } 5183 }, 5184 .cache_info = &epyc_rome_v3_cache_info 5185 }, 5186 { 5187 .version = 4, 5188 .props = (PropValue[]) { 5189 /* Erratum 1386 */ 5190 { "model-id", 5191 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5192 { "xsaves", "off" }, 5193 { /* end of list */ } 5194 }, 5195 }, 5196 { /* end of list */ } 5197 } 5198 }, 5199 { 5200 .name = "EPYC-Milan", 5201 .level = 0xd, 5202 .vendor = CPUID_VENDOR_AMD, 5203 .family = 25, 5204 .model = 1, 5205 .stepping = 1, 5206 .features[FEAT_1_EDX] = 5207 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5208 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5209 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5210 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5211 CPUID_VME | CPUID_FP87, 5212 .features[FEAT_1_ECX] = 5213 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5214 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5215 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5216 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5217 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5218 CPUID_EXT_PCID, 5219 .features[FEAT_8000_0001_EDX] = 5220 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5221 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5222 CPUID_EXT2_SYSCALL, 5223 .features[FEAT_8000_0001_ECX] = 5224 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5225 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5226 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5227 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5228 .features[FEAT_8000_0008_EBX] = 5229 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5230 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5231 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5232 CPUID_8000_0008_EBX_AMD_SSBD, 5233 .features[FEAT_7_0_EBX] = 5234 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5235 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5236 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5237 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5238 CPUID_7_0_EBX_INVPCID, 5239 .features[FEAT_7_0_ECX] = 5240 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5241 .features[FEAT_7_0_EDX] = 5242 CPUID_7_0_EDX_FSRM, 5243 .features[FEAT_XSAVE] = 5244 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5245 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5246 .features[FEAT_6_EAX] = 5247 CPUID_6_EAX_ARAT, 5248 .features[FEAT_SVM] = 5249 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5250 .xlevel = 0x8000001E, 5251 .model_id = "AMD EPYC-Milan Processor", 5252 .cache_info = &epyc_milan_cache_info, 5253 .versions = (X86CPUVersionDefinition[]) { 5254 { .version = 1 }, 5255 { 5256 .version = 2, 5257 .props = (PropValue[]) { 5258 { "model-id", 5259 "AMD EPYC-Milan-v2 Processor" }, 5260 { "vaes", "on" }, 5261 { "vpclmulqdq", "on" }, 5262 { "stibp-always-on", "on" }, 5263 { "amd-psfd", "on" }, 5264 { "no-nested-data-bp", "on" }, 5265 { "lfence-always-serializing", "on" }, 5266 { "null-sel-clr-base", "on" }, 5267 { /* end of list */ } 5268 }, 5269 .cache_info = &epyc_milan_v2_cache_info 5270 }, 5271 { /* end of list */ } 5272 } 5273 }, 5274 { 5275 .name = "EPYC-Genoa", 5276 .level = 0xd, 5277 .vendor = CPUID_VENDOR_AMD, 5278 .family = 25, 5279 .model = 17, 5280 .stepping = 0, 5281 .features[FEAT_1_EDX] = 5282 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5283 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5284 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5285 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5286 CPUID_VME | CPUID_FP87, 5287 .features[FEAT_1_ECX] = 5288 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5289 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5290 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5291 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5292 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5293 CPUID_EXT_SSE3, 5294 .features[FEAT_8000_0001_EDX] = 5295 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5296 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5297 CPUID_EXT2_SYSCALL, 5298 .features[FEAT_8000_0001_ECX] = 5299 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5300 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5301 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5302 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5303 .features[FEAT_8000_0008_EBX] = 5304 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5305 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5306 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5307 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5308 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5309 .features[FEAT_8000_0021_EAX] = 5310 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5311 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5312 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5313 CPUID_8000_0021_EAX_AUTO_IBRS, 5314 .features[FEAT_7_0_EBX] = 5315 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5316 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5317 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5318 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5319 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5320 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5321 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5322 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5323 .features[FEAT_7_0_ECX] = 5324 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5325 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5326 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5327 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5328 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5329 CPUID_7_0_ECX_RDPID, 5330 .features[FEAT_7_0_EDX] = 5331 CPUID_7_0_EDX_FSRM, 5332 .features[FEAT_7_1_EAX] = 5333 CPUID_7_1_EAX_AVX512_BF16, 5334 .features[FEAT_XSAVE] = 5335 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5336 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5337 .features[FEAT_6_EAX] = 5338 CPUID_6_EAX_ARAT, 5339 .features[FEAT_SVM] = 5340 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5341 CPUID_SVM_SVME_ADDR_CHK, 5342 .xlevel = 0x80000022, 5343 .model_id = "AMD EPYC-Genoa Processor", 5344 .cache_info = &epyc_genoa_cache_info, 5345 }, 5346 }; 5347 5348 /* 5349 * We resolve CPU model aliases using -v1 when using "-machine 5350 * none", but this is just for compatibility while libvirt isn't 5351 * adapted to resolve CPU model versions before creating VMs. 5352 * See "Runnability guarantee of CPU models" at 5353 * docs/about/deprecated.rst. 5354 */ 5355 X86CPUVersion default_cpu_version = 1; 5356 5357 void x86_cpu_set_default_version(X86CPUVersion version) 5358 { 5359 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5360 assert(version != CPU_VERSION_AUTO); 5361 default_cpu_version = version; 5362 } 5363 5364 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5365 { 5366 int v = 0; 5367 const X86CPUVersionDefinition *vdef = 5368 x86_cpu_def_get_versions(model->cpudef); 5369 while (vdef->version) { 5370 v = vdef->version; 5371 vdef++; 5372 } 5373 return v; 5374 } 5375 5376 /* Return the actual version being used for a specific CPU model */ 5377 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5378 { 5379 X86CPUVersion v = model->version; 5380 if (v == CPU_VERSION_AUTO) { 5381 v = default_cpu_version; 5382 } 5383 if (v == CPU_VERSION_LATEST) { 5384 return x86_cpu_model_last_version(model); 5385 } 5386 return v; 5387 } 5388 5389 static const Property max_x86_cpu_properties[] = { 5390 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5391 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5392 }; 5393 5394 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5395 { 5396 Object *obj = OBJECT(dev); 5397 5398 if (!object_property_get_int(obj, "family", &error_abort)) { 5399 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5400 object_property_set_int(obj, "family", 15, &error_abort); 5401 object_property_set_int(obj, "model", 107, &error_abort); 5402 object_property_set_int(obj, "stepping", 1, &error_abort); 5403 } else { 5404 object_property_set_int(obj, "family", 6, &error_abort); 5405 object_property_set_int(obj, "model", 6, &error_abort); 5406 object_property_set_int(obj, "stepping", 3, &error_abort); 5407 } 5408 } 5409 5410 x86_cpu_realizefn(dev, errp); 5411 } 5412 5413 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5414 { 5415 DeviceClass *dc = DEVICE_CLASS(oc); 5416 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5417 5418 xcc->ordering = 9; 5419 5420 xcc->model_description = 5421 "Enables all features supported by the accelerator in the current host"; 5422 5423 device_class_set_props(dc, max_x86_cpu_properties); 5424 dc->realize = max_x86_cpu_realize; 5425 } 5426 5427 static void max_x86_cpu_initfn(Object *obj) 5428 { 5429 X86CPU *cpu = X86_CPU(obj); 5430 5431 /* We can't fill the features array here because we don't know yet if 5432 * "migratable" is true or false. 5433 */ 5434 cpu->max_features = true; 5435 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5436 5437 /* 5438 * these defaults are used for TCG and all other accelerators 5439 * besides KVM and HVF, which overwrite these values 5440 */ 5441 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5442 &error_abort); 5443 object_property_set_str(OBJECT(cpu), "model-id", 5444 "QEMU TCG CPU version " QEMU_HW_VERSION, 5445 &error_abort); 5446 } 5447 5448 static const TypeInfo max_x86_cpu_type_info = { 5449 .name = X86_CPU_TYPE_NAME("max"), 5450 .parent = TYPE_X86_CPU, 5451 .instance_init = max_x86_cpu_initfn, 5452 .class_init = max_x86_cpu_class_init, 5453 }; 5454 5455 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5456 { 5457 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5458 5459 switch (f->type) { 5460 case CPUID_FEATURE_WORD: 5461 { 5462 const char *reg = get_register_name_32(f->cpuid.reg); 5463 assert(reg); 5464 return g_strdup_printf("CPUID.%02XH:%s", 5465 f->cpuid.eax, reg); 5466 } 5467 case MSR_FEATURE_WORD: 5468 return g_strdup_printf("MSR(%02XH)", 5469 f->msr.index); 5470 } 5471 5472 return NULL; 5473 } 5474 5475 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5476 { 5477 FeatureWord w; 5478 5479 for (w = 0; w < FEATURE_WORDS; w++) { 5480 if (cpu->filtered_features[w]) { 5481 return true; 5482 } 5483 } 5484 5485 return false; 5486 } 5487 5488 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5489 const char *verbose_prefix) 5490 { 5491 CPUX86State *env = &cpu->env; 5492 FeatureWordInfo *f = &feature_word_info[w]; 5493 int i; 5494 5495 if (!cpu->force_features) { 5496 env->features[w] &= ~mask; 5497 } 5498 cpu->filtered_features[w] |= mask; 5499 5500 if (!verbose_prefix) { 5501 return; 5502 } 5503 5504 for (i = 0; i < 64; ++i) { 5505 if ((1ULL << i) & mask) { 5506 g_autofree char *feat_word_str = feature_word_description(f, i); 5507 warn_report("%s: %s%s%s [bit %d]", 5508 verbose_prefix, 5509 feat_word_str, 5510 f->feat_names[i] ? "." : "", 5511 f->feat_names[i] ? f->feat_names[i] : "", i); 5512 } 5513 } 5514 } 5515 5516 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5517 const char *name, void *opaque, 5518 Error **errp) 5519 { 5520 X86CPU *cpu = X86_CPU(obj); 5521 CPUX86State *env = &cpu->env; 5522 uint64_t value; 5523 5524 value = (env->cpuid_version >> 8) & 0xf; 5525 if (value == 0xf) { 5526 value += (env->cpuid_version >> 20) & 0xff; 5527 } 5528 visit_type_uint64(v, name, &value, errp); 5529 } 5530 5531 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5532 const char *name, void *opaque, 5533 Error **errp) 5534 { 5535 X86CPU *cpu = X86_CPU(obj); 5536 CPUX86State *env = &cpu->env; 5537 const uint64_t max = 0xff + 0xf; 5538 uint64_t value; 5539 5540 if (!visit_type_uint64(v, name, &value, errp)) { 5541 return; 5542 } 5543 if (value > max) { 5544 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5545 name ? name : "null", max); 5546 return; 5547 } 5548 5549 env->cpuid_version &= ~0xff00f00; 5550 if (value > 0x0f) { 5551 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5552 } else { 5553 env->cpuid_version |= value << 8; 5554 } 5555 } 5556 5557 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5558 const char *name, void *opaque, 5559 Error **errp) 5560 { 5561 X86CPU *cpu = X86_CPU(obj); 5562 CPUX86State *env = &cpu->env; 5563 uint64_t value; 5564 5565 value = (env->cpuid_version >> 4) & 0xf; 5566 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5567 visit_type_uint64(v, name, &value, errp); 5568 } 5569 5570 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5571 const char *name, void *opaque, 5572 Error **errp) 5573 { 5574 X86CPU *cpu = X86_CPU(obj); 5575 CPUX86State *env = &cpu->env; 5576 const uint64_t max = 0xff; 5577 uint64_t value; 5578 5579 if (!visit_type_uint64(v, name, &value, errp)) { 5580 return; 5581 } 5582 if (value > max) { 5583 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5584 name ? name : "null", max); 5585 return; 5586 } 5587 5588 env->cpuid_version &= ~0xf00f0; 5589 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5590 } 5591 5592 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5593 const char *name, void *opaque, 5594 Error **errp) 5595 { 5596 X86CPU *cpu = X86_CPU(obj); 5597 CPUX86State *env = &cpu->env; 5598 uint64_t value; 5599 5600 value = env->cpuid_version & 0xf; 5601 visit_type_uint64(v, name, &value, errp); 5602 } 5603 5604 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5605 const char *name, void *opaque, 5606 Error **errp) 5607 { 5608 X86CPU *cpu = X86_CPU(obj); 5609 CPUX86State *env = &cpu->env; 5610 const uint64_t max = 0xf; 5611 uint64_t value; 5612 5613 if (!visit_type_uint64(v, name, &value, errp)) { 5614 return; 5615 } 5616 if (value > max) { 5617 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5618 name ? name : "null", max); 5619 return; 5620 } 5621 5622 env->cpuid_version &= ~0xf; 5623 env->cpuid_version |= value & 0xf; 5624 } 5625 5626 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5627 { 5628 X86CPU *cpu = X86_CPU(obj); 5629 CPUX86State *env = &cpu->env; 5630 char *value; 5631 5632 value = g_malloc(CPUID_VENDOR_SZ + 1); 5633 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5634 env->cpuid_vendor3); 5635 return value; 5636 } 5637 5638 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5639 Error **errp) 5640 { 5641 X86CPU *cpu = X86_CPU(obj); 5642 CPUX86State *env = &cpu->env; 5643 int i; 5644 5645 if (strlen(value) != CPUID_VENDOR_SZ) { 5646 error_setg(errp, "value of property 'vendor' must consist of" 5647 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5648 return; 5649 } 5650 5651 env->cpuid_vendor1 = 0; 5652 env->cpuid_vendor2 = 0; 5653 env->cpuid_vendor3 = 0; 5654 for (i = 0; i < 4; i++) { 5655 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5656 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5657 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5658 } 5659 } 5660 5661 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5662 { 5663 X86CPU *cpu = X86_CPU(obj); 5664 CPUX86State *env = &cpu->env; 5665 char *value; 5666 int i; 5667 5668 value = g_malloc(48 + 1); 5669 for (i = 0; i < 48; i++) { 5670 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5671 } 5672 value[48] = '\0'; 5673 return value; 5674 } 5675 5676 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5677 Error **errp) 5678 { 5679 X86CPU *cpu = X86_CPU(obj); 5680 CPUX86State *env = &cpu->env; 5681 int c, len, i; 5682 5683 if (model_id == NULL) { 5684 model_id = ""; 5685 } 5686 len = strlen(model_id); 5687 memset(env->cpuid_model, 0, 48); 5688 for (i = 0; i < 48; i++) { 5689 if (i >= len) { 5690 c = '\0'; 5691 } else { 5692 c = (uint8_t)model_id[i]; 5693 } 5694 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5695 } 5696 } 5697 5698 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5699 void *opaque, Error **errp) 5700 { 5701 X86CPU *cpu = X86_CPU(obj); 5702 int64_t value; 5703 5704 value = cpu->env.tsc_khz * 1000; 5705 visit_type_int(v, name, &value, errp); 5706 } 5707 5708 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5709 void *opaque, Error **errp) 5710 { 5711 X86CPU *cpu = X86_CPU(obj); 5712 const int64_t max = INT64_MAX; 5713 int64_t value; 5714 5715 if (!visit_type_int(v, name, &value, errp)) { 5716 return; 5717 } 5718 if (value < 0 || value > max) { 5719 error_setg(errp, "parameter '%s' can be at most %" PRId64, 5720 name ? name : "null", max); 5721 return; 5722 } 5723 5724 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5725 } 5726 5727 /* Generic getter for "feature-words" and "filtered-features" properties */ 5728 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5729 const char *name, void *opaque, 5730 Error **errp) 5731 { 5732 uint64_t *array = (uint64_t *)opaque; 5733 FeatureWord w; 5734 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5735 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5736 X86CPUFeatureWordInfoList *list = NULL; 5737 5738 for (w = 0; w < FEATURE_WORDS; w++) { 5739 FeatureWordInfo *wi = &feature_word_info[w]; 5740 /* 5741 * We didn't have MSR features when "feature-words" was 5742 * introduced. Therefore skipped other type entries. 5743 */ 5744 if (wi->type != CPUID_FEATURE_WORD) { 5745 continue; 5746 } 5747 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5748 qwi->cpuid_input_eax = wi->cpuid.eax; 5749 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5750 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5751 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5752 qwi->features = array[w]; 5753 5754 /* List will be in reverse order, but order shouldn't matter */ 5755 list_entries[w].next = list; 5756 list_entries[w].value = &word_infos[w]; 5757 list = &list_entries[w]; 5758 } 5759 5760 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5761 } 5762 5763 /* Convert all '_' in a feature string option name to '-', to make feature 5764 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5765 */ 5766 static inline void feat2prop(char *s) 5767 { 5768 while ((s = strchr(s, '_'))) { 5769 *s = '-'; 5770 } 5771 } 5772 5773 /* Return the feature property name for a feature flag bit */ 5774 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5775 { 5776 const char *name; 5777 /* XSAVE components are automatically enabled by other features, 5778 * so return the original feature name instead 5779 */ 5780 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5781 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5782 5783 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5784 x86_ext_save_areas[comp].bits) { 5785 w = x86_ext_save_areas[comp].feature; 5786 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5787 } 5788 } 5789 5790 assert(bitnr < 64); 5791 assert(w < FEATURE_WORDS); 5792 name = feature_word_info[w].feat_names[bitnr]; 5793 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5794 return name; 5795 } 5796 5797 /* Compatibility hack to maintain legacy +-feat semantic, 5798 * where +-feat overwrites any feature set by 5799 * feat=on|feat even if the later is parsed after +-feat 5800 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5801 */ 5802 static GList *plus_features, *minus_features; 5803 5804 static gint compare_string(gconstpointer a, gconstpointer b) 5805 { 5806 return g_strcmp0(a, b); 5807 } 5808 5809 /* Parse "+feature,-feature,feature=foo" CPU feature string 5810 */ 5811 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5812 Error **errp) 5813 { 5814 char *featurestr; /* Single 'key=value" string being parsed */ 5815 static bool cpu_globals_initialized; 5816 bool ambiguous = false; 5817 5818 if (cpu_globals_initialized) { 5819 return; 5820 } 5821 cpu_globals_initialized = true; 5822 5823 if (!features) { 5824 return; 5825 } 5826 5827 for (featurestr = strtok(features, ","); 5828 featurestr; 5829 featurestr = strtok(NULL, ",")) { 5830 const char *name; 5831 const char *val = NULL; 5832 char *eq = NULL; 5833 char num[32]; 5834 GlobalProperty *prop; 5835 5836 /* Compatibility syntax: */ 5837 if (featurestr[0] == '+') { 5838 plus_features = g_list_append(plus_features, 5839 g_strdup(featurestr + 1)); 5840 continue; 5841 } else if (featurestr[0] == '-') { 5842 minus_features = g_list_append(minus_features, 5843 g_strdup(featurestr + 1)); 5844 continue; 5845 } 5846 5847 eq = strchr(featurestr, '='); 5848 if (eq) { 5849 *eq++ = 0; 5850 val = eq; 5851 } else { 5852 val = "on"; 5853 } 5854 5855 feat2prop(featurestr); 5856 name = featurestr; 5857 5858 if (g_list_find_custom(plus_features, name, compare_string)) { 5859 warn_report("Ambiguous CPU model string. " 5860 "Don't mix both \"+%s\" and \"%s=%s\"", 5861 name, name, val); 5862 ambiguous = true; 5863 } 5864 if (g_list_find_custom(minus_features, name, compare_string)) { 5865 warn_report("Ambiguous CPU model string. " 5866 "Don't mix both \"-%s\" and \"%s=%s\"", 5867 name, name, val); 5868 ambiguous = true; 5869 } 5870 5871 /* Special case: */ 5872 if (!strcmp(name, "tsc-freq")) { 5873 int ret; 5874 uint64_t tsc_freq; 5875 5876 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5877 if (ret < 0 || tsc_freq > INT64_MAX) { 5878 error_setg(errp, "bad numerical value %s", val); 5879 return; 5880 } 5881 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5882 val = num; 5883 name = "tsc-frequency"; 5884 } 5885 5886 prop = g_new0(typeof(*prop), 1); 5887 prop->driver = typename; 5888 prop->property = g_strdup(name); 5889 prop->value = g_strdup(val); 5890 qdev_prop_register_global(prop); 5891 } 5892 5893 if (ambiguous) { 5894 warn_report("Compatibility of ambiguous CPU model " 5895 "strings won't be kept on future QEMU versions"); 5896 } 5897 } 5898 5899 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5900 5901 /* Build a list with the name of all features on a feature word array */ 5902 static void x86_cpu_list_feature_names(FeatureWordArray features, 5903 strList **list) 5904 { 5905 strList **tail = list; 5906 FeatureWord w; 5907 5908 for (w = 0; w < FEATURE_WORDS; w++) { 5909 uint64_t filtered = features[w]; 5910 int i; 5911 for (i = 0; i < 64; i++) { 5912 if (filtered & (1ULL << i)) { 5913 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5914 } 5915 } 5916 } 5917 } 5918 5919 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5920 const char *name, void *opaque, 5921 Error **errp) 5922 { 5923 X86CPU *xc = X86_CPU(obj); 5924 strList *result = NULL; 5925 5926 x86_cpu_list_feature_names(xc->filtered_features, &result); 5927 visit_type_strList(v, "unavailable-features", &result, errp); 5928 } 5929 5930 /* Print all cpuid feature names in featureset 5931 */ 5932 static void listflags(GList *features) 5933 { 5934 size_t len = 0; 5935 GList *tmp; 5936 5937 for (tmp = features; tmp; tmp = tmp->next) { 5938 const char *name = tmp->data; 5939 if ((len + strlen(name) + 1) >= 75) { 5940 qemu_printf("\n"); 5941 len = 0; 5942 } 5943 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5944 len += strlen(name) + 1; 5945 } 5946 qemu_printf("\n"); 5947 } 5948 5949 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5950 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5951 { 5952 ObjectClass *class_a = (ObjectClass *)a; 5953 ObjectClass *class_b = (ObjectClass *)b; 5954 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5955 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5956 int ret; 5957 5958 if (cc_a->ordering != cc_b->ordering) { 5959 ret = cc_a->ordering - cc_b->ordering; 5960 } else { 5961 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5962 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5963 ret = strcmp(name_a, name_b); 5964 } 5965 return ret; 5966 } 5967 5968 static GSList *get_sorted_cpu_model_list(void) 5969 { 5970 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5971 list = g_slist_sort(list, x86_cpu_list_compare); 5972 return list; 5973 } 5974 5975 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5976 { 5977 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5978 char *r = object_property_get_str(obj, "model-id", &error_abort); 5979 object_unref(obj); 5980 return r; 5981 } 5982 5983 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5984 { 5985 X86CPUVersion version; 5986 5987 if (!cc->model || !cc->model->is_alias) { 5988 return NULL; 5989 } 5990 version = x86_cpu_model_resolve_version(cc->model); 5991 if (version <= 0) { 5992 return NULL; 5993 } 5994 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5995 } 5996 5997 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5998 { 5999 ObjectClass *oc = data; 6000 X86CPUClass *cc = X86_CPU_CLASS(oc); 6001 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6002 g_autofree char *desc = g_strdup(cc->model_description); 6003 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6004 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6005 6006 if (!desc && alias_of) { 6007 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6008 desc = g_strdup("(alias configured by machine type)"); 6009 } else { 6010 desc = g_strdup_printf("(alias of %s)", alias_of); 6011 } 6012 } 6013 if (!desc && cc->model && cc->model->note) { 6014 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6015 } 6016 if (!desc) { 6017 desc = g_strdup_printf("%s", model_id); 6018 } 6019 6020 if (cc->model && cc->model->cpudef->deprecation_note) { 6021 g_autofree char *olddesc = desc; 6022 desc = g_strdup_printf("%s (deprecated)", olddesc); 6023 } 6024 6025 qemu_printf(" %-20s %s\n", name, desc); 6026 } 6027 6028 /* list available CPU models and flags */ 6029 void x86_cpu_list(void) 6030 { 6031 int i, j; 6032 GSList *list; 6033 GList *names = NULL; 6034 6035 qemu_printf("Available CPUs:\n"); 6036 list = get_sorted_cpu_model_list(); 6037 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6038 g_slist_free(list); 6039 6040 names = NULL; 6041 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6042 FeatureWordInfo *fw = &feature_word_info[i]; 6043 for (j = 0; j < 64; j++) { 6044 if (fw->feat_names[j]) { 6045 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6046 } 6047 } 6048 } 6049 6050 names = g_list_sort(names, (GCompareFunc)strcmp); 6051 6052 qemu_printf("\nRecognized CPUID flags:\n"); 6053 listflags(names); 6054 qemu_printf("\n"); 6055 g_list_free(names); 6056 } 6057 6058 #ifndef CONFIG_USER_ONLY 6059 6060 /* Check for missing features that may prevent the CPU class from 6061 * running using the current machine and accelerator. 6062 */ 6063 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6064 strList **list) 6065 { 6066 strList **tail = list; 6067 X86CPU *xc; 6068 Error *err = NULL; 6069 6070 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6071 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6072 return; 6073 } 6074 6075 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6076 6077 x86_cpu_expand_features(xc, &err); 6078 if (err) { 6079 /* Errors at x86_cpu_expand_features should never happen, 6080 * but in case it does, just report the model as not 6081 * runnable at all using the "type" property. 6082 */ 6083 QAPI_LIST_APPEND(tail, g_strdup("type")); 6084 error_free(err); 6085 } 6086 6087 x86_cpu_filter_features(xc, false); 6088 6089 x86_cpu_list_feature_names(xc->filtered_features, tail); 6090 6091 object_unref(OBJECT(xc)); 6092 } 6093 6094 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6095 { 6096 ObjectClass *oc = data; 6097 X86CPUClass *cc = X86_CPU_CLASS(oc); 6098 CpuDefinitionInfoList **cpu_list = user_data; 6099 CpuDefinitionInfo *info; 6100 6101 info = g_malloc0(sizeof(*info)); 6102 info->name = x86_cpu_class_get_model_name(cc); 6103 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6104 info->has_unavailable_features = true; 6105 info->q_typename = g_strdup(object_class_get_name(oc)); 6106 info->migration_safe = cc->migration_safe; 6107 info->has_migration_safe = true; 6108 info->q_static = cc->static_model; 6109 if (cc->model && cc->model->cpudef->deprecation_note) { 6110 info->deprecated = true; 6111 } else { 6112 info->deprecated = false; 6113 } 6114 /* 6115 * Old machine types won't report aliases, so that alias translation 6116 * doesn't break compatibility with previous QEMU versions. 6117 */ 6118 if (default_cpu_version != CPU_VERSION_LEGACY) { 6119 info->alias_of = x86_cpu_class_get_alias_of(cc); 6120 } 6121 6122 QAPI_LIST_PREPEND(*cpu_list, info); 6123 } 6124 6125 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6126 { 6127 CpuDefinitionInfoList *cpu_list = NULL; 6128 GSList *list = get_sorted_cpu_model_list(); 6129 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6130 g_slist_free(list); 6131 return cpu_list; 6132 } 6133 6134 #endif /* !CONFIG_USER_ONLY */ 6135 6136 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6137 { 6138 FeatureWordInfo *wi = &feature_word_info[w]; 6139 uint64_t r = 0; 6140 uint64_t unavail = 0; 6141 6142 if (kvm_enabled()) { 6143 switch (wi->type) { 6144 case CPUID_FEATURE_WORD: 6145 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6146 wi->cpuid.ecx, 6147 wi->cpuid.reg); 6148 break; 6149 case MSR_FEATURE_WORD: 6150 r = kvm_arch_get_supported_msr_feature(kvm_state, 6151 wi->msr.index); 6152 break; 6153 } 6154 } else if (hvf_enabled()) { 6155 if (wi->type != CPUID_FEATURE_WORD) { 6156 return 0; 6157 } 6158 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6159 wi->cpuid.ecx, 6160 wi->cpuid.reg); 6161 } else if (tcg_enabled()) { 6162 r = wi->tcg_features; 6163 } else { 6164 return ~0; 6165 } 6166 6167 switch (w) { 6168 #ifndef TARGET_X86_64 6169 case FEAT_8000_0001_EDX: 6170 /* 6171 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6172 * way for userspace to get out of its 32-bit jail, we can leave 6173 * the LM bit set. 6174 */ 6175 unavail = tcg_enabled() 6176 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6177 : CPUID_EXT2_LM; 6178 break; 6179 #endif 6180 6181 case FEAT_8000_0007_EBX: 6182 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6183 /* Disable AMD machine check architecture for Intel CPU. */ 6184 unavail = ~0; 6185 } 6186 break; 6187 6188 case FEAT_7_0_EBX: 6189 #ifndef CONFIG_USER_ONLY 6190 if (!check_sgx_support()) { 6191 unavail = CPUID_7_0_EBX_SGX; 6192 } 6193 #endif 6194 break; 6195 case FEAT_7_0_ECX: 6196 #ifndef CONFIG_USER_ONLY 6197 if (!check_sgx_support()) { 6198 unavail = CPUID_7_0_ECX_SGX_LC; 6199 } 6200 #endif 6201 break; 6202 6203 default: 6204 break; 6205 } 6206 6207 r &= ~unavail; 6208 if (cpu && cpu->migratable) { 6209 r &= x86_cpu_get_migratable_flags(cpu, w); 6210 } 6211 return r; 6212 } 6213 6214 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6215 uint32_t *eax, uint32_t *ebx, 6216 uint32_t *ecx, uint32_t *edx) 6217 { 6218 if (kvm_enabled()) { 6219 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6220 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6221 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6222 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6223 } else if (hvf_enabled()) { 6224 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6225 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6226 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6227 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6228 } else { 6229 *eax = 0; 6230 *ebx = 0; 6231 *ecx = 0; 6232 *edx = 0; 6233 } 6234 } 6235 6236 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6237 uint32_t *eax, uint32_t *ebx, 6238 uint32_t *ecx, uint32_t *edx) 6239 { 6240 uint32_t level, unused; 6241 6242 /* Only return valid host leaves. */ 6243 switch (func) { 6244 case 2: 6245 case 4: 6246 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6247 break; 6248 case 0x80000005: 6249 case 0x80000006: 6250 case 0x8000001d: 6251 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6252 break; 6253 default: 6254 return; 6255 } 6256 6257 if (func > level) { 6258 *eax = 0; 6259 *ebx = 0; 6260 *ecx = 0; 6261 *edx = 0; 6262 } else { 6263 host_cpuid(func, index, eax, ebx, ecx, edx); 6264 } 6265 } 6266 6267 /* 6268 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6269 */ 6270 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6271 { 6272 PropValue *pv; 6273 for (pv = props; pv->prop; pv++) { 6274 if (!pv->value) { 6275 continue; 6276 } 6277 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6278 &error_abort); 6279 } 6280 } 6281 6282 /* 6283 * Apply properties for the CPU model version specified in model. 6284 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6285 */ 6286 6287 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6288 { 6289 const X86CPUVersionDefinition *vdef; 6290 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6291 6292 if (version == CPU_VERSION_LEGACY) { 6293 return; 6294 } 6295 6296 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6297 PropValue *p; 6298 6299 for (p = vdef->props; p && p->prop; p++) { 6300 object_property_parse(OBJECT(cpu), p->prop, p->value, 6301 &error_abort); 6302 } 6303 6304 if (vdef->version == version) { 6305 break; 6306 } 6307 } 6308 6309 /* 6310 * If we reached the end of the list, version number was invalid 6311 */ 6312 assert(vdef->version == version); 6313 } 6314 6315 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6316 X86CPUModel *model) 6317 { 6318 const X86CPUVersionDefinition *vdef; 6319 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6320 const CPUCaches *cache_info = model->cpudef->cache_info; 6321 6322 if (version == CPU_VERSION_LEGACY) { 6323 return cache_info; 6324 } 6325 6326 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6327 if (vdef->cache_info) { 6328 cache_info = vdef->cache_info; 6329 } 6330 6331 if (vdef->version == version) { 6332 break; 6333 } 6334 } 6335 6336 assert(vdef->version == version); 6337 return cache_info; 6338 } 6339 6340 /* 6341 * Load data from X86CPUDefinition into a X86CPU object. 6342 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6343 */ 6344 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6345 { 6346 const X86CPUDefinition *def = model->cpudef; 6347 CPUX86State *env = &cpu->env; 6348 FeatureWord w; 6349 6350 /*NOTE: any property set by this function should be returned by 6351 * x86_cpu_static_props(), so static expansion of 6352 * query-cpu-model-expansion is always complete. 6353 */ 6354 6355 /* CPU models only set _minimum_ values for level/xlevel: */ 6356 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6357 &error_abort); 6358 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6359 &error_abort); 6360 6361 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6362 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6363 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6364 &error_abort); 6365 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6366 &error_abort); 6367 for (w = 0; w < FEATURE_WORDS; w++) { 6368 env->features[w] = def->features[w]; 6369 } 6370 6371 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6372 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6373 6374 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6375 6376 /* sysenter isn't supported in compatibility mode on AMD, 6377 * syscall isn't supported in compatibility mode on Intel. 6378 * Normally we advertise the actual CPU vendor, but you can 6379 * override this using the 'vendor' property if you want to use 6380 * KVM's sysenter/syscall emulation in compatibility mode and 6381 * when doing cross vendor migration 6382 */ 6383 6384 /* 6385 * vendor property is set here but then overloaded with the 6386 * host cpu vendor for KVM and HVF. 6387 */ 6388 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6389 6390 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 6391 &error_abort); 6392 6393 x86_cpu_apply_version_props(cpu, model); 6394 6395 /* 6396 * Properties in versioned CPU model are not user specified features. 6397 * We can simply clear env->user_features here since it will be filled later 6398 * in x86_cpu_expand_features() based on plus_features and minus_features. 6399 */ 6400 memset(&env->user_features, 0, sizeof(env->user_features)); 6401 } 6402 6403 static const gchar *x86_gdb_arch_name(CPUState *cs) 6404 { 6405 #ifdef TARGET_X86_64 6406 return "i386:x86-64"; 6407 #else 6408 return "i386"; 6409 #endif 6410 } 6411 6412 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6413 { 6414 X86CPUModel *model = data; 6415 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6416 CPUClass *cc = CPU_CLASS(oc); 6417 6418 xcc->model = model; 6419 xcc->migration_safe = true; 6420 cc->deprecation_note = model->cpudef->deprecation_note; 6421 } 6422 6423 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6424 { 6425 g_autofree char *typename = x86_cpu_type_name(name); 6426 TypeInfo ti = { 6427 .name = typename, 6428 .parent = TYPE_X86_CPU, 6429 .class_init = x86_cpu_cpudef_class_init, 6430 .class_data = model, 6431 }; 6432 6433 type_register_static(&ti); 6434 } 6435 6436 6437 /* 6438 * register builtin_x86_defs; 6439 * "max", "base" and subclasses ("host") are not registered here. 6440 * See x86_cpu_register_types for all model registrations. 6441 */ 6442 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6443 { 6444 X86CPUModel *m; 6445 const X86CPUVersionDefinition *vdef; 6446 6447 /* AMD aliases are handled at runtime based on CPUID vendor, so 6448 * they shouldn't be set on the CPU model table. 6449 */ 6450 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6451 /* catch mistakes instead of silently truncating model_id when too long */ 6452 assert(def->model_id && strlen(def->model_id) <= 48); 6453 6454 /* Unversioned model: */ 6455 m = g_new0(X86CPUModel, 1); 6456 m->cpudef = def; 6457 m->version = CPU_VERSION_AUTO; 6458 m->is_alias = true; 6459 x86_register_cpu_model_type(def->name, m); 6460 6461 /* Versioned models: */ 6462 6463 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6464 g_autofree char *name = 6465 x86_cpu_versioned_model_name(def, vdef->version); 6466 6467 m = g_new0(X86CPUModel, 1); 6468 m->cpudef = def; 6469 m->version = vdef->version; 6470 m->note = vdef->note; 6471 x86_register_cpu_model_type(name, m); 6472 6473 if (vdef->alias) { 6474 X86CPUModel *am = g_new0(X86CPUModel, 1); 6475 am->cpudef = def; 6476 am->version = vdef->version; 6477 am->is_alias = true; 6478 x86_register_cpu_model_type(vdef->alias, am); 6479 } 6480 } 6481 6482 } 6483 6484 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6485 { 6486 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6487 return 57; /* 57 bits virtual */ 6488 } else { 6489 return 48; /* 48 bits virtual */ 6490 } 6491 } 6492 6493 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6494 uint32_t *eax, uint32_t *ebx, 6495 uint32_t *ecx, uint32_t *edx) 6496 { 6497 X86CPU *cpu = env_archcpu(env); 6498 CPUState *cs = env_cpu(env); 6499 uint32_t limit; 6500 uint32_t signature[3]; 6501 X86CPUTopoInfo topo_info; 6502 uint32_t cores_per_pkg; 6503 uint32_t threads_per_pkg; 6504 6505 topo_info.dies_per_pkg = env->nr_dies; 6506 topo_info.modules_per_die = env->nr_modules; 6507 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; 6508 topo_info.threads_per_core = cs->nr_threads; 6509 6510 cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * 6511 topo_info.dies_per_pkg; 6512 threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; 6513 6514 /* Calculate & apply limits for different index ranges */ 6515 if (index >= 0xC0000000) { 6516 limit = env->cpuid_xlevel2; 6517 } else if (index >= 0x80000000) { 6518 limit = env->cpuid_xlevel; 6519 } else if (index >= 0x40000000) { 6520 limit = 0x40000001; 6521 } else { 6522 limit = env->cpuid_level; 6523 } 6524 6525 if (index > limit) { 6526 /* Intel documentation states that invalid EAX input will 6527 * return the same information as EAX=cpuid_level 6528 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6529 */ 6530 index = env->cpuid_level; 6531 } 6532 6533 switch(index) { 6534 case 0: 6535 *eax = env->cpuid_level; 6536 *ebx = env->cpuid_vendor1; 6537 *edx = env->cpuid_vendor2; 6538 *ecx = env->cpuid_vendor3; 6539 break; 6540 case 1: 6541 *eax = env->cpuid_version; 6542 *ebx = (cpu->apic_id << 24) | 6543 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6544 *ecx = env->features[FEAT_1_ECX]; 6545 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6546 *ecx |= CPUID_EXT_OSXSAVE; 6547 } 6548 *edx = env->features[FEAT_1_EDX]; 6549 if (threads_per_pkg > 1) { 6550 *ebx |= threads_per_pkg << 16; 6551 *edx |= CPUID_HT; 6552 } 6553 if (!cpu->enable_pmu) { 6554 *ecx &= ~CPUID_EXT_PDCM; 6555 } 6556 break; 6557 case 2: 6558 /* cache info: needed for Pentium Pro compatibility */ 6559 if (cpu->cache_info_passthrough) { 6560 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6561 break; 6562 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6563 *eax = *ebx = *ecx = *edx = 0; 6564 break; 6565 } 6566 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6567 *ebx = 0; 6568 if (!cpu->enable_l3_cache) { 6569 *ecx = 0; 6570 } else { 6571 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6572 } 6573 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6574 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6575 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6576 break; 6577 case 4: 6578 /* cache info: needed for Core compatibility */ 6579 if (cpu->cache_info_passthrough) { 6580 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6581 /* 6582 * QEMU has its own number of cores/logical cpus, 6583 * set 24..14, 31..26 bit to configured values 6584 */ 6585 if (*eax & 31) { 6586 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6587 6588 *eax &= ~0xFC000000; 6589 *eax |= max_core_ids_in_package(&topo_info) << 26; 6590 if (host_vcpus_per_cache > threads_per_pkg) { 6591 *eax &= ~0x3FFC000; 6592 6593 /* Share the cache at package level. */ 6594 *eax |= max_thread_ids_for_cache(&topo_info, 6595 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 6596 } 6597 } 6598 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6599 *eax = *ebx = *ecx = *edx = 0; 6600 } else { 6601 *eax = 0; 6602 6603 switch (count) { 6604 case 0: /* L1 dcache info */ 6605 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6606 &topo_info, 6607 eax, ebx, ecx, edx); 6608 if (!cpu->l1_cache_per_core) { 6609 *eax &= ~MAKE_64BIT_MASK(14, 12); 6610 } 6611 break; 6612 case 1: /* L1 icache info */ 6613 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6614 &topo_info, 6615 eax, ebx, ecx, edx); 6616 if (!cpu->l1_cache_per_core) { 6617 *eax &= ~MAKE_64BIT_MASK(14, 12); 6618 } 6619 break; 6620 case 2: /* L2 cache info */ 6621 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6622 &topo_info, 6623 eax, ebx, ecx, edx); 6624 break; 6625 case 3: /* L3 cache info */ 6626 if (cpu->enable_l3_cache) { 6627 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6628 &topo_info, 6629 eax, ebx, ecx, edx); 6630 break; 6631 } 6632 /* fall through */ 6633 default: /* end of info */ 6634 *eax = *ebx = *ecx = *edx = 0; 6635 break; 6636 } 6637 } 6638 break; 6639 case 5: 6640 /* MONITOR/MWAIT Leaf */ 6641 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6642 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6643 *ecx = cpu->mwait.ecx; /* flags */ 6644 *edx = cpu->mwait.edx; /* mwait substates */ 6645 break; 6646 case 6: 6647 /* Thermal and Power Leaf */ 6648 *eax = env->features[FEAT_6_EAX]; 6649 *ebx = 0; 6650 *ecx = 0; 6651 *edx = 0; 6652 break; 6653 case 7: 6654 /* Structured Extended Feature Flags Enumeration Leaf */ 6655 if (count == 0) { 6656 /* Maximum ECX value for sub-leaves */ 6657 *eax = env->cpuid_level_func7; 6658 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6659 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6660 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6661 *ecx |= CPUID_7_0_ECX_OSPKE; 6662 } 6663 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6664 } else if (count == 1) { 6665 *eax = env->features[FEAT_7_1_EAX]; 6666 *edx = env->features[FEAT_7_1_EDX]; 6667 *ebx = 0; 6668 *ecx = 0; 6669 } else if (count == 2) { 6670 *edx = env->features[FEAT_7_2_EDX]; 6671 *eax = 0; 6672 *ebx = 0; 6673 *ecx = 0; 6674 } else { 6675 *eax = 0; 6676 *ebx = 0; 6677 *ecx = 0; 6678 *edx = 0; 6679 } 6680 break; 6681 case 9: 6682 /* Direct Cache Access Information Leaf */ 6683 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6684 *ebx = 0; 6685 *ecx = 0; 6686 *edx = 0; 6687 break; 6688 case 0xA: 6689 /* Architectural Performance Monitoring Leaf */ 6690 if (cpu->enable_pmu) { 6691 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6692 } else { 6693 *eax = 0; 6694 *ebx = 0; 6695 *ecx = 0; 6696 *edx = 0; 6697 } 6698 break; 6699 case 0xB: 6700 /* Extended Topology Enumeration Leaf */ 6701 if (!cpu->enable_cpuid_0xb) { 6702 *eax = *ebx = *ecx = *edx = 0; 6703 break; 6704 } 6705 6706 *ecx = count & 0xff; 6707 *edx = cpu->apic_id; 6708 6709 switch (count) { 6710 case 0: 6711 *eax = apicid_core_offset(&topo_info); 6712 *ebx = topo_info.threads_per_core; 6713 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6714 break; 6715 case 1: 6716 *eax = apicid_pkg_offset(&topo_info); 6717 *ebx = threads_per_pkg; 6718 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6719 break; 6720 default: 6721 *eax = 0; 6722 *ebx = 0; 6723 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6724 } 6725 6726 assert(!(*eax & ~0x1f)); 6727 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6728 break; 6729 case 0x1C: 6730 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6731 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6732 *edx = 0; 6733 } 6734 break; 6735 case 0x1F: 6736 /* V2 Extended Topology Enumeration Leaf */ 6737 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6738 *eax = *ebx = *ecx = *edx = 0; 6739 break; 6740 } 6741 6742 encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); 6743 break; 6744 case 0xD: { 6745 /* Processor Extended State */ 6746 *eax = 0; 6747 *ebx = 0; 6748 *ecx = 0; 6749 *edx = 0; 6750 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6751 break; 6752 } 6753 6754 if (count == 0) { 6755 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6756 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6757 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6758 /* 6759 * The initial value of xcr0 and ebx == 0, On host without kvm 6760 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6761 * even through guest update xcr0, this will crash some legacy guest 6762 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6763 */ 6764 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6765 } else if (count == 1) { 6766 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6767 x86_cpu_xsave_xss_components(cpu); 6768 6769 *eax = env->features[FEAT_XSAVE]; 6770 *ebx = xsave_area_size(xstate, true); 6771 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6772 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6773 if (kvm_enabled() && cpu->enable_pmu && 6774 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6775 (*eax & CPUID_XSAVE_XSAVES)) { 6776 *ecx |= XSTATE_ARCH_LBR_MASK; 6777 } else { 6778 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6779 } 6780 } else if (count == 0xf && cpu->enable_pmu 6781 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6782 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6783 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6784 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6785 6786 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6787 *eax = esa->size; 6788 *ebx = esa->offset; 6789 *ecx = esa->ecx & 6790 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6791 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6792 *eax = esa->size; 6793 *ebx = 0; 6794 *ecx = 1; 6795 } 6796 } 6797 break; 6798 } 6799 case 0x12: 6800 #ifndef CONFIG_USER_ONLY 6801 if (!kvm_enabled() || 6802 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6803 *eax = *ebx = *ecx = *edx = 0; 6804 break; 6805 } 6806 6807 /* 6808 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6809 * the EPC properties, e.g. confidentiality and integrity, from the 6810 * host's first EPC section, i.e. assume there is one EPC section or 6811 * that all EPC sections have the same security properties. 6812 */ 6813 if (count > 1) { 6814 uint64_t epc_addr, epc_size; 6815 6816 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6817 *eax = *ebx = *ecx = *edx = 0; 6818 break; 6819 } 6820 host_cpuid(index, 2, eax, ebx, ecx, edx); 6821 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6822 *ebx = (uint32_t)(epc_addr >> 32); 6823 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6824 *edx = (uint32_t)(epc_size >> 32); 6825 break; 6826 } 6827 6828 /* 6829 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6830 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6831 * supports. Features can be further restricted by userspace, but not 6832 * made more permissive. 6833 */ 6834 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6835 6836 if (count == 0) { 6837 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6838 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6839 } else { 6840 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6841 *ebx &= 0; /* ebx reserve */ 6842 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6843 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6844 6845 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6846 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6847 6848 /* Access to PROVISIONKEY requires additional credentials. */ 6849 if ((*eax & (1U << 4)) && 6850 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6851 *eax &= ~(1U << 4); 6852 } 6853 } 6854 #endif 6855 break; 6856 case 0x14: { 6857 /* Intel Processor Trace Enumeration */ 6858 *eax = 0; 6859 *ebx = 0; 6860 *ecx = 0; 6861 *edx = 0; 6862 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6863 !kvm_enabled()) { 6864 break; 6865 } 6866 6867 /* 6868 * If these are changed, they should stay in sync with 6869 * x86_cpu_filter_features(). 6870 */ 6871 if (count == 0) { 6872 *eax = INTEL_PT_MAX_SUBLEAF; 6873 *ebx = INTEL_PT_MINIMAL_EBX; 6874 *ecx = INTEL_PT_MINIMAL_ECX; 6875 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6876 *ecx |= CPUID_14_0_ECX_LIP; 6877 } 6878 } else if (count == 1) { 6879 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6880 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6881 } 6882 break; 6883 } 6884 case 0x1D: { 6885 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6886 *eax = 0; 6887 *ebx = 0; 6888 *ecx = 0; 6889 *edx = 0; 6890 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6891 break; 6892 } 6893 6894 if (count == 0) { 6895 /* Highest numbered palette subleaf */ 6896 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6897 } else if (count == 1) { 6898 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6899 (INTEL_AMX_BYTES_PER_TILE << 16); 6900 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6901 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6902 } 6903 break; 6904 } 6905 case 0x1E: { 6906 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6907 *eax = 0; 6908 *ebx = 0; 6909 *ecx = 0; 6910 *edx = 0; 6911 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6912 break; 6913 } 6914 6915 if (count == 0) { 6916 /* Highest numbered palette subleaf */ 6917 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6918 } 6919 break; 6920 } 6921 case 0x24: { 6922 *eax = 0; 6923 *ebx = 0; 6924 *ecx = 0; 6925 *edx = 0; 6926 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 6927 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 6928 } 6929 break; 6930 } 6931 case 0x40000000: 6932 /* 6933 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6934 * set here, but we restrict to TCG none the less. 6935 */ 6936 if (tcg_enabled() && cpu->expose_tcg) { 6937 memcpy(signature, "TCGTCGTCGTCG", 12); 6938 *eax = 0x40000001; 6939 *ebx = signature[0]; 6940 *ecx = signature[1]; 6941 *edx = signature[2]; 6942 } else { 6943 *eax = 0; 6944 *ebx = 0; 6945 *ecx = 0; 6946 *edx = 0; 6947 } 6948 break; 6949 case 0x40000001: 6950 *eax = 0; 6951 *ebx = 0; 6952 *ecx = 0; 6953 *edx = 0; 6954 break; 6955 case 0x80000000: 6956 *eax = env->cpuid_xlevel; 6957 *ebx = env->cpuid_vendor1; 6958 *edx = env->cpuid_vendor2; 6959 *ecx = env->cpuid_vendor3; 6960 break; 6961 case 0x80000001: 6962 *eax = env->cpuid_version; 6963 *ebx = 0; 6964 *ecx = env->features[FEAT_8000_0001_ECX]; 6965 *edx = env->features[FEAT_8000_0001_EDX]; 6966 6967 /* The Linux kernel checks for the CMPLegacy bit and 6968 * discards multiple thread information if it is set. 6969 * So don't set it here for Intel to make Linux guests happy. 6970 */ 6971 if (threads_per_pkg > 1) { 6972 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6973 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6974 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6975 *ecx |= 1 << 1; /* CmpLegacy bit */ 6976 } 6977 } 6978 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6979 !(env->hflags & HF_LMA_MASK)) { 6980 *edx &= ~CPUID_EXT2_SYSCALL; 6981 } 6982 break; 6983 case 0x80000002: 6984 case 0x80000003: 6985 case 0x80000004: 6986 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6987 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6988 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6989 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6990 break; 6991 case 0x80000005: 6992 /* cache info (L1 cache) */ 6993 if (cpu->cache_info_passthrough) { 6994 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6995 break; 6996 } 6997 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6998 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6999 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 7000 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7001 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7002 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7003 break; 7004 case 0x80000006: 7005 /* cache info (L2 cache) */ 7006 if (cpu->cache_info_passthrough) { 7007 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7008 break; 7009 } 7010 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7011 (L2_DTLB_2M_ENTRIES << 16) | 7012 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7013 (L2_ITLB_2M_ENTRIES); 7014 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7015 (L2_DTLB_4K_ENTRIES << 16) | 7016 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7017 (L2_ITLB_4K_ENTRIES); 7018 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7019 cpu->enable_l3_cache ? 7020 env->cache_info_amd.l3_cache : NULL, 7021 ecx, edx); 7022 break; 7023 case 0x80000007: 7024 *eax = 0; 7025 *ebx = env->features[FEAT_8000_0007_EBX]; 7026 *ecx = 0; 7027 *edx = env->features[FEAT_8000_0007_EDX]; 7028 break; 7029 case 0x80000008: 7030 /* virtual & phys address size in low 2 bytes. */ 7031 *eax = cpu->phys_bits; 7032 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7033 /* 64 bit processor */ 7034 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7035 *eax |= (cpu->guest_phys_bits << 16); 7036 } 7037 *ebx = env->features[FEAT_8000_0008_EBX]; 7038 if (threads_per_pkg > 1) { 7039 /* 7040 * Bits 15:12 is "The number of bits in the initial 7041 * Core::X86::Apic::ApicId[ApicId] value that indicate 7042 * thread ID within a package". 7043 * Bits 7:0 is "The number of threads in the package is NC+1" 7044 */ 7045 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 7046 (threads_per_pkg - 1); 7047 } else { 7048 *ecx = 0; 7049 } 7050 *edx = 0; 7051 break; 7052 case 0x8000000A: 7053 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7054 *eax = 0x00000001; /* SVM Revision */ 7055 *ebx = 0x00000010; /* nr of ASIDs */ 7056 *ecx = 0; 7057 *edx = env->features[FEAT_SVM]; /* optional features */ 7058 } else { 7059 *eax = 0; 7060 *ebx = 0; 7061 *ecx = 0; 7062 *edx = 0; 7063 } 7064 break; 7065 case 0x8000001D: 7066 *eax = 0; 7067 if (cpu->cache_info_passthrough) { 7068 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7069 break; 7070 } 7071 switch (count) { 7072 case 0: /* L1 dcache info */ 7073 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7074 &topo_info, eax, ebx, ecx, edx); 7075 break; 7076 case 1: /* L1 icache info */ 7077 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7078 &topo_info, eax, ebx, ecx, edx); 7079 break; 7080 case 2: /* L2 cache info */ 7081 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7082 &topo_info, eax, ebx, ecx, edx); 7083 break; 7084 case 3: /* L3 cache info */ 7085 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7086 &topo_info, eax, ebx, ecx, edx); 7087 break; 7088 default: /* end of info */ 7089 *eax = *ebx = *ecx = *edx = 0; 7090 break; 7091 } 7092 if (cpu->amd_topoext_features_only) { 7093 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7094 } 7095 break; 7096 case 0x8000001E: 7097 if (cpu->core_id <= 255) { 7098 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 7099 } else { 7100 *eax = 0; 7101 *ebx = 0; 7102 *ecx = 0; 7103 *edx = 0; 7104 } 7105 break; 7106 case 0x80000022: 7107 *eax = *ebx = *ecx = *edx = 0; 7108 /* AMD Extended Performance Monitoring and Debug */ 7109 if (kvm_enabled() && cpu->enable_pmu && 7110 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7111 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7112 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7113 R_EBX) & 0xf; 7114 } 7115 break; 7116 case 0xC0000000: 7117 *eax = env->cpuid_xlevel2; 7118 *ebx = 0; 7119 *ecx = 0; 7120 *edx = 0; 7121 break; 7122 case 0xC0000001: 7123 /* Support for VIA CPU's CPUID instruction */ 7124 *eax = env->cpuid_version; 7125 *ebx = 0; 7126 *ecx = 0; 7127 *edx = env->features[FEAT_C000_0001_EDX]; 7128 break; 7129 case 0xC0000002: 7130 case 0xC0000003: 7131 case 0xC0000004: 7132 /* Reserved for the future, and now filled with zero */ 7133 *eax = 0; 7134 *ebx = 0; 7135 *ecx = 0; 7136 *edx = 0; 7137 break; 7138 case 0x8000001F: 7139 *eax = *ebx = *ecx = *edx = 0; 7140 if (sev_enabled()) { 7141 *eax = 0x2; 7142 *eax |= sev_es_enabled() ? 0x8 : 0; 7143 *eax |= sev_snp_enabled() ? 0x10 : 0; 7144 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7145 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7146 } 7147 break; 7148 case 0x80000021: 7149 *eax = *ebx = *ecx = *edx = 0; 7150 *eax = env->features[FEAT_8000_0021_EAX]; 7151 *ebx = env->features[FEAT_8000_0021_EBX]; 7152 break; 7153 default: 7154 /* reserved values: zero */ 7155 *eax = 0; 7156 *ebx = 0; 7157 *ecx = 0; 7158 *edx = 0; 7159 break; 7160 } 7161 } 7162 7163 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7164 { 7165 #ifndef CONFIG_USER_ONLY 7166 /* Those default values are defined in Skylake HW */ 7167 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7168 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7169 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7170 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7171 #endif 7172 } 7173 7174 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7175 { 7176 if (!esa->size) { 7177 return false; 7178 } 7179 7180 if (env->features[esa->feature] & esa->bits) { 7181 return true; 7182 } 7183 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7184 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7185 return true; 7186 } 7187 7188 return false; 7189 } 7190 7191 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7192 { 7193 CPUState *cs = CPU(obj); 7194 X86CPU *cpu = X86_CPU(cs); 7195 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7196 CPUX86State *env = &cpu->env; 7197 target_ulong cr4; 7198 uint64_t xcr0; 7199 int i; 7200 7201 if (xcc->parent_phases.hold) { 7202 xcc->parent_phases.hold(obj, type); 7203 } 7204 7205 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7206 7207 if (tcg_enabled()) { 7208 cpu_init_fp_statuses(env); 7209 } 7210 7211 env->old_exception = -1; 7212 7213 /* init to reset state */ 7214 env->int_ctl = 0; 7215 env->hflags2 |= HF2_GIF_MASK; 7216 env->hflags2 |= HF2_VGIF_MASK; 7217 env->hflags &= ~HF_GUEST_MASK; 7218 7219 cpu_x86_update_cr0(env, 0x60000010); 7220 env->a20_mask = ~0x0; 7221 env->smbase = 0x30000; 7222 env->msr_smi_count = 0; 7223 7224 env->idt.limit = 0xffff; 7225 env->gdt.limit = 0xffff; 7226 env->ldt.limit = 0xffff; 7227 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7228 env->tr.limit = 0xffff; 7229 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7230 7231 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7232 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7233 DESC_R_MASK | DESC_A_MASK); 7234 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7235 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7236 DESC_A_MASK); 7237 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7238 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7239 DESC_A_MASK); 7240 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7241 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7242 DESC_A_MASK); 7243 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7244 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7245 DESC_A_MASK); 7246 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7247 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7248 DESC_A_MASK); 7249 7250 env->eip = 0xfff0; 7251 env->regs[R_EDX] = env->cpuid_version; 7252 7253 env->eflags = 0x2; 7254 7255 /* FPU init */ 7256 for (i = 0; i < 8; i++) { 7257 env->fptags[i] = 1; 7258 } 7259 cpu_set_fpuc(env, 0x37f); 7260 7261 env->mxcsr = 0x1f80; 7262 /* All units are in INIT state. */ 7263 env->xstate_bv = 0; 7264 7265 env->pat = 0x0007040600070406ULL; 7266 7267 if (kvm_enabled()) { 7268 /* 7269 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7270 * a new CPU, use 1 instead to force a reset. 7271 */ 7272 if (env->tsc != 0) { 7273 env->tsc = 1; 7274 } 7275 } else { 7276 env->tsc = 0; 7277 } 7278 7279 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7280 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7281 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7282 } 7283 7284 memset(env->dr, 0, sizeof(env->dr)); 7285 env->dr[6] = DR6_FIXED_1; 7286 env->dr[7] = DR7_FIXED_1; 7287 cpu_breakpoint_remove_all(cs, BP_CPU); 7288 cpu_watchpoint_remove_all(cs, BP_CPU); 7289 7290 cr4 = 0; 7291 xcr0 = XSTATE_FP_MASK; 7292 7293 #ifdef CONFIG_USER_ONLY 7294 /* Enable all the features for user-mode. */ 7295 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7296 xcr0 |= XSTATE_SSE_MASK; 7297 } 7298 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7299 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7300 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7301 continue; 7302 } 7303 if (cpuid_has_xsave_feature(env, esa)) { 7304 xcr0 |= 1ull << i; 7305 } 7306 } 7307 7308 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7309 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7310 } 7311 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7312 cr4 |= CR4_FSGSBASE_MASK; 7313 } 7314 #endif 7315 7316 env->xcr0 = xcr0; 7317 cpu_x86_update_cr4(env, cr4); 7318 7319 /* 7320 * SDM 11.11.5 requires: 7321 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7322 * - IA32_MTRR_PHYSMASKn.V = 0 7323 * All other bits are undefined. For simplification, zero it all. 7324 */ 7325 env->mtrr_deftype = 0; 7326 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7327 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7328 7329 env->interrupt_injected = -1; 7330 env->exception_nr = -1; 7331 env->exception_pending = 0; 7332 env->exception_injected = 0; 7333 env->exception_has_payload = false; 7334 env->exception_payload = 0; 7335 env->nmi_injected = false; 7336 env->triple_fault_pending = false; 7337 #if !defined(CONFIG_USER_ONLY) 7338 /* We hard-wire the BSP to the first CPU. */ 7339 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7340 7341 cs->halted = !cpu_is_bsp(cpu); 7342 7343 if (kvm_enabled()) { 7344 kvm_arch_reset_vcpu(cpu); 7345 } 7346 7347 x86_cpu_set_sgxlepubkeyhash(env); 7348 7349 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7350 7351 #endif 7352 } 7353 7354 void x86_cpu_after_reset(X86CPU *cpu) 7355 { 7356 #ifndef CONFIG_USER_ONLY 7357 if (kvm_enabled()) { 7358 kvm_arch_after_reset_vcpu(cpu); 7359 } 7360 7361 if (cpu->apic_state) { 7362 device_cold_reset(cpu->apic_state); 7363 } 7364 #endif 7365 } 7366 7367 static void mce_init(X86CPU *cpu) 7368 { 7369 CPUX86State *cenv = &cpu->env; 7370 unsigned int bank; 7371 7372 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7373 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7374 (CPUID_MCE | CPUID_MCA)) { 7375 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7376 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7377 cenv->mcg_ctl = ~(uint64_t)0; 7378 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7379 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7380 } 7381 } 7382 } 7383 7384 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7385 { 7386 if (*min < value) { 7387 *min = value; 7388 } 7389 } 7390 7391 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7392 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7393 { 7394 CPUX86State *env = &cpu->env; 7395 FeatureWordInfo *fi = &feature_word_info[w]; 7396 uint32_t eax = fi->cpuid.eax; 7397 uint32_t region = eax & 0xF0000000; 7398 7399 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7400 if (!env->features[w]) { 7401 return; 7402 } 7403 7404 switch (region) { 7405 case 0x00000000: 7406 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7407 break; 7408 case 0x80000000: 7409 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7410 break; 7411 case 0xC0000000: 7412 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7413 break; 7414 } 7415 7416 if (eax == 7) { 7417 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7418 fi->cpuid.ecx); 7419 } 7420 } 7421 7422 /* Calculate XSAVE components based on the configured CPU feature flags */ 7423 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7424 { 7425 CPUX86State *env = &cpu->env; 7426 int i; 7427 uint64_t mask; 7428 static bool request_perm; 7429 7430 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7431 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7432 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7433 env->features[FEAT_XSAVE_XSS_LO] = 0; 7434 env->features[FEAT_XSAVE_XSS_HI] = 0; 7435 return; 7436 } 7437 7438 mask = 0; 7439 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7440 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7441 if (cpuid_has_xsave_feature(env, esa)) { 7442 mask |= (1ULL << i); 7443 } 7444 } 7445 7446 /* Only request permission for first vcpu */ 7447 if (kvm_enabled() && !request_perm) { 7448 kvm_request_xsave_components(cpu, mask); 7449 request_perm = true; 7450 } 7451 7452 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7453 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7454 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7455 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7456 } 7457 7458 /***** Steps involved on loading and filtering CPUID data 7459 * 7460 * When initializing and realizing a CPU object, the steps 7461 * involved in setting up CPUID data are: 7462 * 7463 * 1) Loading CPU model definition (X86CPUDefinition). This is 7464 * implemented by x86_cpu_load_model() and should be completely 7465 * transparent, as it is done automatically by instance_init. 7466 * No code should need to look at X86CPUDefinition structs 7467 * outside instance_init. 7468 * 7469 * 2) CPU expansion. This is done by realize before CPUID 7470 * filtering, and will make sure host/accelerator data is 7471 * loaded for CPU models that depend on host capabilities 7472 * (e.g. "host"). Done by x86_cpu_expand_features(). 7473 * 7474 * 3) CPUID filtering. This initializes extra data related to 7475 * CPUID, and checks if the host supports all capabilities 7476 * required by the CPU. Runnability of a CPU model is 7477 * determined at this step. Done by x86_cpu_filter_features(). 7478 * 7479 * Some operations don't require all steps to be performed. 7480 * More precisely: 7481 * 7482 * - CPU instance creation (instance_init) will run only CPU 7483 * model loading. CPU expansion can't run at instance_init-time 7484 * because host/accelerator data may be not available yet. 7485 * - CPU realization will perform both CPU model expansion and CPUID 7486 * filtering, and return an error in case one of them fails. 7487 * - query-cpu-definitions needs to run all 3 steps. It needs 7488 * to run CPUID filtering, as the 'unavailable-features' 7489 * field is set based on the filtering results. 7490 * - The query-cpu-model-expansion QMP command only needs to run 7491 * CPU model loading and CPU expansion. It should not filter 7492 * any CPUID data based on host capabilities. 7493 */ 7494 7495 /* Expand CPU configuration data, based on configured features 7496 * and host/accelerator capabilities when appropriate. 7497 */ 7498 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7499 { 7500 CPUX86State *env = &cpu->env; 7501 FeatureWord w; 7502 int i; 7503 GList *l; 7504 7505 for (l = plus_features; l; l = l->next) { 7506 const char *prop = l->data; 7507 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7508 return; 7509 } 7510 } 7511 7512 for (l = minus_features; l; l = l->next) { 7513 const char *prop = l->data; 7514 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7515 return; 7516 } 7517 } 7518 7519 /*TODO: Now cpu->max_features doesn't overwrite features 7520 * set using QOM properties, and we can convert 7521 * plus_features & minus_features to global properties 7522 * inside x86_cpu_parse_featurestr() too. 7523 */ 7524 if (cpu->max_features) { 7525 for (w = 0; w < FEATURE_WORDS; w++) { 7526 /* Override only features that weren't set explicitly 7527 * by the user. 7528 */ 7529 env->features[w] |= 7530 x86_cpu_get_supported_feature_word(cpu, w) & 7531 ~env->user_features[w] & 7532 ~feature_word_info[w].no_autoenable_flags; 7533 } 7534 7535 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 7536 uint32_t eax, ebx, ecx, edx; 7537 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 7538 env->avx10_version = ebx & 0xff; 7539 } 7540 } 7541 7542 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7543 FeatureDep *d = &feature_dependencies[i]; 7544 if (!(env->features[d->from.index] & d->from.mask)) { 7545 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7546 7547 /* Not an error unless the dependent feature was added explicitly. */ 7548 mark_unavailable_features(cpu, d->to.index, 7549 unavailable_features & env->user_features[d->to.index], 7550 "This feature depends on other features that were not requested"); 7551 7552 env->features[d->to.index] &= ~unavailable_features; 7553 } 7554 } 7555 7556 if (!kvm_enabled() || !cpu->expose_kvm) { 7557 env->features[FEAT_KVM] = 0; 7558 } 7559 7560 x86_cpu_enable_xsave_components(cpu); 7561 7562 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7563 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7564 if (cpu->full_cpuid_auto_level) { 7565 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7566 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7567 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7568 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7569 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7570 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7571 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7572 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7573 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7574 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7575 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7576 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7577 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7578 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7579 7580 /* Intel Processor Trace requires CPUID[0x14] */ 7581 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7582 if (cpu->intel_pt_auto_level) { 7583 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7584 } else if (cpu->env.cpuid_min_level < 0x14) { 7585 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7586 CPUID_7_0_EBX_INTEL_PT, 7587 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7588 } 7589 } 7590 7591 /* 7592 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7593 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7594 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7595 * cpu->vendor_cpuid_only has been unset for compatibility with older 7596 * machine types. 7597 */ 7598 if (x86_has_extended_topo(env->avail_cpu_topo) && 7599 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7600 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7601 } 7602 7603 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 7604 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7605 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 7606 } 7607 7608 /* SVM requires CPUID[0x8000000A] */ 7609 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7610 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7611 } 7612 7613 /* SEV requires CPUID[0x8000001F] */ 7614 if (sev_enabled()) { 7615 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7616 } 7617 7618 if (env->features[FEAT_8000_0021_EAX]) { 7619 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7620 } 7621 7622 /* SGX requires CPUID[0x12] for EPC enumeration */ 7623 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7624 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7625 } 7626 } 7627 7628 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7629 if (env->cpuid_level_func7 == UINT32_MAX) { 7630 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7631 } 7632 if (env->cpuid_level == UINT32_MAX) { 7633 env->cpuid_level = env->cpuid_min_level; 7634 } 7635 if (env->cpuid_xlevel == UINT32_MAX) { 7636 env->cpuid_xlevel = env->cpuid_min_xlevel; 7637 } 7638 if (env->cpuid_xlevel2 == UINT32_MAX) { 7639 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7640 } 7641 7642 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7643 return; 7644 } 7645 } 7646 7647 /* 7648 * Finishes initialization of CPUID data, filters CPU feature 7649 * words based on host availability of each feature. 7650 * 7651 * Returns: true if any flag is not supported by the host, false otherwise. 7652 */ 7653 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7654 { 7655 CPUX86State *env = &cpu->env; 7656 FeatureWord w; 7657 const char *prefix = NULL; 7658 bool have_filtered_features; 7659 7660 uint32_t eax_0, ebx_0, ecx_0, edx_0; 7661 uint32_t eax_1, ebx_1, ecx_1, edx_1; 7662 7663 if (verbose) { 7664 prefix = accel_uses_host_cpuid() 7665 ? "host doesn't support requested feature" 7666 : "TCG doesn't support requested feature"; 7667 } 7668 7669 for (w = 0; w < FEATURE_WORDS; w++) { 7670 uint64_t host_feat = 7671 x86_cpu_get_supported_feature_word(NULL, w); 7672 uint64_t requested_features = env->features[w]; 7673 uint64_t unavailable_features = requested_features & ~host_feat; 7674 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7675 } 7676 7677 /* 7678 * Check that KVM actually allows the processor tracing features that 7679 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7680 */ 7681 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7682 kvm_enabled()) { 7683 x86_cpu_get_supported_cpuid(0x14, 0, 7684 &eax_0, &ebx_0, &ecx_0, &edx_0); 7685 x86_cpu_get_supported_cpuid(0x14, 1, 7686 &eax_1, &ebx_1, &ecx_1, &edx_1); 7687 7688 if (!eax_0 || 7689 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7690 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7691 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7692 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7693 INTEL_PT_ADDR_RANGES_NUM) || 7694 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7695 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7696 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7697 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7698 /* 7699 * Processor Trace capabilities aren't configurable, so if the 7700 * host can't emulate the capabilities we report on 7701 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7702 */ 7703 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7704 } 7705 } 7706 7707 have_filtered_features = x86_cpu_have_filtered_features(cpu); 7708 7709 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7710 x86_cpu_get_supported_cpuid(0x24, 0, 7711 &eax_0, &ebx_0, &ecx_0, &edx_0); 7712 uint8_t version = ebx_0 & 0xff; 7713 7714 if (version < env->avx10_version) { 7715 if (prefix) { 7716 warn_report("%s: avx10.%d. Adjust to avx10.%d", 7717 prefix, env->avx10_version, version); 7718 } 7719 env->avx10_version = version; 7720 have_filtered_features = true; 7721 } 7722 } else if (env->avx10_version && prefix) { 7723 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 7724 have_filtered_features = true; 7725 } 7726 7727 return have_filtered_features; 7728 } 7729 7730 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7731 { 7732 size_t len; 7733 7734 /* Hyper-V vendor id */ 7735 if (!cpu->hyperv_vendor) { 7736 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7737 &error_abort); 7738 } 7739 len = strlen(cpu->hyperv_vendor); 7740 if (len > 12) { 7741 warn_report("hv-vendor-id truncated to 12 characters"); 7742 len = 12; 7743 } 7744 memset(cpu->hyperv_vendor_id, 0, 12); 7745 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7746 7747 /* 'Hv#1' interface identification*/ 7748 cpu->hyperv_interface_id[0] = 0x31237648; 7749 cpu->hyperv_interface_id[1] = 0; 7750 cpu->hyperv_interface_id[2] = 0; 7751 cpu->hyperv_interface_id[3] = 0; 7752 7753 /* Hypervisor implementation limits */ 7754 cpu->hyperv_limits[0] = 64; 7755 cpu->hyperv_limits[1] = 0; 7756 cpu->hyperv_limits[2] = 0; 7757 } 7758 7759 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7760 { 7761 CPUState *cs = CPU(dev); 7762 X86CPU *cpu = X86_CPU(dev); 7763 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7764 CPUX86State *env = &cpu->env; 7765 Error *local_err = NULL; 7766 unsigned requested_lbr_fmt; 7767 7768 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7769 /* Use pc-relative instructions in system-mode */ 7770 tcg_cflags_set(cs, CF_PCREL); 7771 #endif 7772 7773 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7774 error_setg(errp, "apic-id property was not initialized properly"); 7775 return; 7776 } 7777 7778 /* 7779 * Process Hyper-V enlightenments. 7780 * Note: this currently has to happen before the expansion of CPU features. 7781 */ 7782 x86_cpu_hyperv_realize(cpu); 7783 7784 x86_cpu_expand_features(cpu, &local_err); 7785 if (local_err) { 7786 goto out; 7787 } 7788 7789 /* 7790 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7791 * with user-provided setting. 7792 */ 7793 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7794 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7795 error_setg(errp, "invalid lbr-fmt"); 7796 return; 7797 } 7798 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7799 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7800 } 7801 7802 /* 7803 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7804 * 3)vPMU LBR format matches that of host setting. 7805 */ 7806 requested_lbr_fmt = 7807 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7808 if (requested_lbr_fmt && kvm_enabled()) { 7809 uint64_t host_perf_cap = 7810 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 7811 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7812 7813 if (!cpu->enable_pmu) { 7814 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7815 return; 7816 } 7817 if (requested_lbr_fmt != host_lbr_fmt) { 7818 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7819 "the host value (0x%x).", 7820 requested_lbr_fmt, host_lbr_fmt); 7821 return; 7822 } 7823 } 7824 7825 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 7826 if (cpu->enforce_cpuid) { 7827 error_setg(&local_err, 7828 accel_uses_host_cpuid() ? 7829 "Host doesn't support requested features" : 7830 "TCG doesn't support requested features"); 7831 goto out; 7832 } 7833 } 7834 7835 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7836 * CPUID[1].EDX. 7837 */ 7838 if (IS_AMD_CPU(env)) { 7839 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7840 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7841 & CPUID_EXT2_AMD_ALIASES); 7842 } 7843 7844 x86_cpu_set_sgxlepubkeyhash(env); 7845 7846 /* 7847 * note: the call to the framework needs to happen after feature expansion, 7848 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7849 * These may be set by the accel-specific code, 7850 * and the results are subsequently checked / assumed in this function. 7851 */ 7852 cpu_exec_realizefn(cs, &local_err); 7853 if (local_err != NULL) { 7854 error_propagate(errp, local_err); 7855 return; 7856 } 7857 7858 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7859 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7860 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7861 goto out; 7862 } 7863 7864 if (cpu->guest_phys_bits == -1) { 7865 /* 7866 * If it was not set by the user, or by the accelerator via 7867 * cpu_exec_realizefn, clear. 7868 */ 7869 cpu->guest_phys_bits = 0; 7870 } 7871 7872 if (cpu->ucode_rev == 0) { 7873 /* 7874 * The default is the same as KVM's. Note that this check 7875 * needs to happen after the evenual setting of ucode_rev in 7876 * accel-specific code in cpu_exec_realizefn. 7877 */ 7878 if (IS_AMD_CPU(env)) { 7879 cpu->ucode_rev = 0x01000065; 7880 } else { 7881 cpu->ucode_rev = 0x100000000ULL; 7882 } 7883 } 7884 7885 /* 7886 * mwait extended info: needed for Core compatibility 7887 * We always wake on interrupt even if host does not have the capability. 7888 * 7889 * requires the accel-specific code in cpu_exec_realizefn to 7890 * have already acquired the CPUID data into cpu->mwait. 7891 */ 7892 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7893 7894 /* For 64bit systems think about the number of physical bits to present. 7895 * ideally this should be the same as the host; anything other than matching 7896 * the host can cause incorrect guest behaviour. 7897 * QEMU used to pick the magic value of 40 bits that corresponds to 7898 * consumer AMD devices but nothing else. 7899 * 7900 * Note that this code assumes features expansion has already been done 7901 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7902 * phys_bits adjustments to match the host have been already done in 7903 * accel-specific code in cpu_exec_realizefn. 7904 */ 7905 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7906 if (cpu->phys_bits && 7907 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7908 cpu->phys_bits < 32)) { 7909 error_setg(errp, "phys-bits should be between 32 and %u " 7910 " (but is %u)", 7911 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7912 return; 7913 } 7914 /* 7915 * 0 means it was not explicitly set by the user (or by machine 7916 * compat_props or by the host code in host-cpu.c). 7917 * In this case, the default is the value used by TCG (40). 7918 */ 7919 if (cpu->phys_bits == 0) { 7920 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7921 } 7922 if (cpu->guest_phys_bits && 7923 (cpu->guest_phys_bits > cpu->phys_bits || 7924 cpu->guest_phys_bits < 32)) { 7925 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7926 " (but is %u)", 7927 cpu->phys_bits, cpu->guest_phys_bits); 7928 return; 7929 } 7930 } else { 7931 /* For 32 bit systems don't use the user set value, but keep 7932 * phys_bits consistent with what we tell the guest. 7933 */ 7934 if (cpu->phys_bits != 0) { 7935 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7936 return; 7937 } 7938 if (cpu->guest_phys_bits != 0) { 7939 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7940 return; 7941 } 7942 7943 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7944 cpu->phys_bits = 36; 7945 } else { 7946 cpu->phys_bits = 32; 7947 } 7948 } 7949 7950 /* Cache information initialization */ 7951 if (!cpu->legacy_cache) { 7952 const CPUCaches *cache_info = 7953 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7954 7955 if (!xcc->model || !cache_info) { 7956 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7957 error_setg(errp, 7958 "CPU model '%s' doesn't support legacy-cache=off", name); 7959 return; 7960 } 7961 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7962 *cache_info; 7963 } else { 7964 /* Build legacy cache information */ 7965 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7966 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7967 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7968 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7969 7970 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7971 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7972 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7973 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7974 7975 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7976 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7977 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7978 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7979 } 7980 7981 #ifndef CONFIG_USER_ONLY 7982 MachineState *ms = MACHINE(qdev_get_machine()); 7983 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7984 7985 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7986 x86_cpu_apic_create(cpu, &local_err); 7987 if (local_err != NULL) { 7988 goto out; 7989 } 7990 } 7991 #endif 7992 7993 mce_init(cpu); 7994 7995 x86_cpu_gdb_init(cs); 7996 qemu_init_vcpu(cs); 7997 7998 /* 7999 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 8000 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8001 * based on inputs (sockets,cores,threads), it is still better to give 8002 * users a warning. 8003 * 8004 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 8005 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 8006 */ 8007 if (IS_AMD_CPU(env) && 8008 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8009 cs->nr_threads > 1) { 8010 warn_report_once("This family of AMD CPU doesn't support " 8011 "hyperthreading(%d). Please configure -smp " 8012 "options properly or try enabling topoext " 8013 "feature.", cs->nr_threads); 8014 } 8015 8016 #ifndef CONFIG_USER_ONLY 8017 x86_cpu_apic_realize(cpu, &local_err); 8018 if (local_err != NULL) { 8019 goto out; 8020 } 8021 #endif /* !CONFIG_USER_ONLY */ 8022 cpu_reset(cs); 8023 8024 xcc->parent_realize(dev, &local_err); 8025 8026 out: 8027 if (local_err != NULL) { 8028 error_propagate(errp, local_err); 8029 return; 8030 } 8031 } 8032 8033 static void x86_cpu_unrealizefn(DeviceState *dev) 8034 { 8035 X86CPU *cpu = X86_CPU(dev); 8036 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8037 8038 #ifndef CONFIG_USER_ONLY 8039 cpu_remove_sync(CPU(dev)); 8040 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8041 #endif 8042 8043 if (cpu->apic_state) { 8044 object_unparent(OBJECT(cpu->apic_state)); 8045 cpu->apic_state = NULL; 8046 } 8047 8048 xcc->parent_unrealize(dev); 8049 } 8050 8051 typedef struct BitProperty { 8052 FeatureWord w; 8053 uint64_t mask; 8054 } BitProperty; 8055 8056 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8057 void *opaque, Error **errp) 8058 { 8059 X86CPU *cpu = X86_CPU(obj); 8060 BitProperty *fp = opaque; 8061 uint64_t f = cpu->env.features[fp->w]; 8062 bool value = (f & fp->mask) == fp->mask; 8063 visit_type_bool(v, name, &value, errp); 8064 } 8065 8066 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8067 void *opaque, Error **errp) 8068 { 8069 DeviceState *dev = DEVICE(obj); 8070 X86CPU *cpu = X86_CPU(obj); 8071 BitProperty *fp = opaque; 8072 bool value; 8073 8074 if (dev->realized) { 8075 qdev_prop_set_after_realize(dev, name, errp); 8076 return; 8077 } 8078 8079 if (!visit_type_bool(v, name, &value, errp)) { 8080 return; 8081 } 8082 8083 if (value) { 8084 cpu->env.features[fp->w] |= fp->mask; 8085 } else { 8086 cpu->env.features[fp->w] &= ~fp->mask; 8087 } 8088 cpu->env.user_features[fp->w] |= fp->mask; 8089 } 8090 8091 /* Register a boolean property to get/set a single bit in a uint32_t field. 8092 * 8093 * The same property name can be registered multiple times to make it affect 8094 * multiple bits in the same FeatureWord. In that case, the getter will return 8095 * true only if all bits are set. 8096 */ 8097 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8098 const char *prop_name, 8099 FeatureWord w, 8100 int bitnr) 8101 { 8102 ObjectClass *oc = OBJECT_CLASS(xcc); 8103 BitProperty *fp; 8104 ObjectProperty *op; 8105 uint64_t mask = (1ULL << bitnr); 8106 8107 op = object_class_property_find(oc, prop_name); 8108 if (op) { 8109 fp = op->opaque; 8110 assert(fp->w == w); 8111 fp->mask |= mask; 8112 } else { 8113 fp = g_new0(BitProperty, 1); 8114 fp->w = w; 8115 fp->mask = mask; 8116 object_class_property_add(oc, prop_name, "bool", 8117 x86_cpu_get_bit_prop, 8118 x86_cpu_set_bit_prop, 8119 NULL, fp); 8120 } 8121 } 8122 8123 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8124 FeatureWord w, 8125 int bitnr) 8126 { 8127 FeatureWordInfo *fi = &feature_word_info[w]; 8128 const char *name = fi->feat_names[bitnr]; 8129 8130 if (!name) { 8131 return; 8132 } 8133 8134 /* Property names should use "-" instead of "_". 8135 * Old names containing underscores are registered as aliases 8136 * using object_property_add_alias() 8137 */ 8138 assert(!strchr(name, '_')); 8139 /* aliases don't use "|" delimiters anymore, they are registered 8140 * manually using object_property_add_alias() */ 8141 assert(!strchr(name, '|')); 8142 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8143 } 8144 8145 static void x86_cpu_post_initfn(Object *obj) 8146 { 8147 static bool first = true; 8148 uint64_t supported_xcr0; 8149 int i; 8150 8151 if (first) { 8152 first = false; 8153 8154 supported_xcr0 = 8155 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 8156 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 8157 8158 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 8159 ExtSaveArea *esa = &x86_ext_save_areas[i]; 8160 8161 if (!(supported_xcr0 & (1 << i))) { 8162 esa->size = 0; 8163 } 8164 } 8165 } 8166 8167 accel_cpu_instance_init(CPU(obj)); 8168 } 8169 8170 static void x86_cpu_init_default_topo(X86CPU *cpu) 8171 { 8172 CPUX86State *env = &cpu->env; 8173 8174 env->nr_modules = 1; 8175 env->nr_dies = 1; 8176 8177 /* thread, core and socket levels are set by default. */ 8178 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 8179 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 8180 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 8181 } 8182 8183 static void x86_cpu_initfn(Object *obj) 8184 { 8185 X86CPU *cpu = X86_CPU(obj); 8186 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8187 CPUX86State *env = &cpu->env; 8188 8189 x86_cpu_init_default_topo(cpu); 8190 8191 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8192 x86_cpu_get_feature_words, 8193 NULL, NULL, (void *)env->features); 8194 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8195 x86_cpu_get_feature_words, 8196 NULL, NULL, (void *)cpu->filtered_features); 8197 8198 object_property_add_alias(obj, "sse3", obj, "pni"); 8199 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8200 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8201 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8202 object_property_add_alias(obj, "xd", obj, "nx"); 8203 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8204 object_property_add_alias(obj, "i64", obj, "lm"); 8205 8206 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8207 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8208 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8209 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8210 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8211 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8212 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8213 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8214 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8215 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8216 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8217 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8218 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8219 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8220 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8221 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8222 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8223 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8224 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8225 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8226 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8227 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8228 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8229 8230 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8231 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8232 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8233 8234 if (xcc->model) { 8235 x86_cpu_load_model(cpu, xcc->model); 8236 } 8237 } 8238 8239 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8240 { 8241 X86CPU *cpu = X86_CPU(cs); 8242 8243 return cpu->apic_id; 8244 } 8245 8246 #if !defined(CONFIG_USER_ONLY) 8247 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8248 { 8249 X86CPU *cpu = X86_CPU(cs); 8250 8251 return cpu->env.cr[0] & CR0_PG_MASK; 8252 } 8253 #endif /* !CONFIG_USER_ONLY */ 8254 8255 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8256 { 8257 X86CPU *cpu = X86_CPU(cs); 8258 8259 cpu->env.eip = value; 8260 } 8261 8262 static vaddr x86_cpu_get_pc(CPUState *cs) 8263 { 8264 X86CPU *cpu = X86_CPU(cs); 8265 8266 /* Match cpu_get_tb_cpu_state. */ 8267 return cpu->env.eip + cpu->env.segs[R_CS].base; 8268 } 8269 8270 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8271 { 8272 X86CPU *cpu = X86_CPU(cs); 8273 CPUX86State *env = &cpu->env; 8274 8275 #if !defined(CONFIG_USER_ONLY) 8276 if (interrupt_request & CPU_INTERRUPT_POLL) { 8277 return CPU_INTERRUPT_POLL; 8278 } 8279 #endif 8280 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8281 return CPU_INTERRUPT_SIPI; 8282 } 8283 8284 if (env->hflags2 & HF2_GIF_MASK) { 8285 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8286 !(env->hflags & HF_SMM_MASK)) { 8287 return CPU_INTERRUPT_SMI; 8288 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8289 !(env->hflags2 & HF2_NMI_MASK)) { 8290 return CPU_INTERRUPT_NMI; 8291 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8292 return CPU_INTERRUPT_MCE; 8293 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8294 (((env->hflags2 & HF2_VINTR_MASK) && 8295 (env->hflags2 & HF2_HIF_MASK)) || 8296 (!(env->hflags2 & HF2_VINTR_MASK) && 8297 (env->eflags & IF_MASK && 8298 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8299 return CPU_INTERRUPT_HARD; 8300 #if !defined(CONFIG_USER_ONLY) 8301 } else if (env->hflags2 & HF2_VGIF_MASK) { 8302 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8303 (env->eflags & IF_MASK) && 8304 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8305 return CPU_INTERRUPT_VIRQ; 8306 } 8307 #endif 8308 } 8309 } 8310 8311 return 0; 8312 } 8313 8314 static bool x86_cpu_has_work(CPUState *cs) 8315 { 8316 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8317 } 8318 8319 int x86_mmu_index_pl(CPUX86State *env, unsigned pl) 8320 { 8321 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8322 int mmu_index_base = 8323 pl == 3 ? MMU_USER64_IDX : 8324 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8325 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8326 8327 return mmu_index_base + mmu_index_32; 8328 } 8329 8330 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8331 { 8332 CPUX86State *env = cpu_env(cs); 8333 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); 8334 } 8335 8336 static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) 8337 { 8338 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; 8339 int mmu_index_base = 8340 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8341 (pl < 3 && (env->eflags & AC_MASK) 8342 ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); 8343 8344 return mmu_index_base + mmu_index_32; 8345 } 8346 8347 int cpu_mmu_index_kernel(CPUX86State *env) 8348 { 8349 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); 8350 } 8351 8352 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8353 { 8354 X86CPU *cpu = X86_CPU(cs); 8355 CPUX86State *env = &cpu->env; 8356 8357 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8358 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8359 : bfd_mach_i386_i8086); 8360 8361 info->cap_arch = CS_ARCH_X86; 8362 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8363 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8364 : CS_MODE_16); 8365 info->cap_insn_unit = 1; 8366 info->cap_insn_split = 8; 8367 } 8368 8369 void x86_update_hflags(CPUX86State *env) 8370 { 8371 uint32_t hflags; 8372 #define HFLAG_COPY_MASK \ 8373 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8374 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8375 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8376 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8377 8378 hflags = env->hflags & HFLAG_COPY_MASK; 8379 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8380 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8381 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8382 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8383 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8384 8385 if (env->cr[4] & CR4_OSFXSR_MASK) { 8386 hflags |= HF_OSFXSR_MASK; 8387 } 8388 8389 if (env->efer & MSR_EFER_LMA) { 8390 hflags |= HF_LMA_MASK; 8391 } 8392 8393 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8394 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8395 } else { 8396 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8397 (DESC_B_SHIFT - HF_CS32_SHIFT); 8398 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8399 (DESC_B_SHIFT - HF_SS32_SHIFT); 8400 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8401 !(hflags & HF_CS32_MASK)) { 8402 hflags |= HF_ADDSEG_MASK; 8403 } else { 8404 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8405 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8406 } 8407 } 8408 env->hflags = hflags; 8409 } 8410 8411 static const Property x86_cpu_properties[] = { 8412 #ifdef CONFIG_USER_ONLY 8413 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8414 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8415 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8416 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8417 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8418 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8419 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8420 #else 8421 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8422 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8423 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8424 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8425 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8426 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8427 #endif 8428 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8429 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8430 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8431 8432 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8433 HYPERV_SPINLOCK_NEVER_NOTIFY), 8434 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8435 HYPERV_FEAT_RELAXED, 0), 8436 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8437 HYPERV_FEAT_VAPIC, 0), 8438 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8439 HYPERV_FEAT_TIME, 0), 8440 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8441 HYPERV_FEAT_CRASH, 0), 8442 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8443 HYPERV_FEAT_RESET, 0), 8444 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8445 HYPERV_FEAT_VPINDEX, 0), 8446 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8447 HYPERV_FEAT_RUNTIME, 0), 8448 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8449 HYPERV_FEAT_SYNIC, 0), 8450 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8451 HYPERV_FEAT_STIMER, 0), 8452 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8453 HYPERV_FEAT_FREQUENCIES, 0), 8454 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8455 HYPERV_FEAT_REENLIGHTENMENT, 0), 8456 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8457 HYPERV_FEAT_TLBFLUSH, 0), 8458 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8459 HYPERV_FEAT_EVMCS, 0), 8460 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8461 HYPERV_FEAT_IPI, 0), 8462 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8463 HYPERV_FEAT_STIMER_DIRECT, 0), 8464 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8465 HYPERV_FEAT_AVIC, 0), 8466 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8467 HYPERV_FEAT_MSR_BITMAP, 0), 8468 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8469 HYPERV_FEAT_XMM_INPUT, 0), 8470 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8471 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8472 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8473 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8474 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8475 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8476 #ifdef CONFIG_SYNDBG 8477 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8478 HYPERV_FEAT_SYNDBG, 0), 8479 #endif 8480 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8481 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8482 8483 /* WS2008R2 identify by default */ 8484 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8485 0x3839), 8486 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8487 0x000A), 8488 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8489 0x0000), 8490 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8491 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8492 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8493 8494 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8495 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8496 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8497 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8498 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8499 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8500 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8501 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8502 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8503 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8504 UINT32_MAX), 8505 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8506 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8507 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8508 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8509 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8510 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8511 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 8512 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8513 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8514 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8515 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8516 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8517 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8518 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8519 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8520 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8521 false), 8522 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8523 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8524 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8525 true), 8526 /* 8527 * lecacy_cache defaults to true unless the CPU model provides its 8528 * own cache information (see x86_cpu_load_def()). 8529 */ 8530 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8531 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8532 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8533 8534 /* 8535 * From "Requirements for Implementing the Microsoft 8536 * Hypervisor Interface": 8537 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8538 * 8539 * "Starting with Windows Server 2012 and Windows 8, if 8540 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8541 * the hypervisor imposes no specific limit to the number of VPs. 8542 * In this case, Windows Server 2012 guest VMs may use more than 8543 * 64 VPs, up to the maximum supported number of processors applicable 8544 * to the specific Windows version being used." 8545 */ 8546 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8547 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8548 false), 8549 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8550 true), 8551 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8552 }; 8553 8554 #ifndef CONFIG_USER_ONLY 8555 #include "hw/core/sysemu-cpu-ops.h" 8556 8557 static const struct SysemuCPUOps i386_sysemu_ops = { 8558 .get_memory_mapping = x86_cpu_get_memory_mapping, 8559 .get_paging_enabled = x86_cpu_get_paging_enabled, 8560 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8561 .asidx_from_attrs = x86_asidx_from_attrs, 8562 .get_crash_info = x86_cpu_get_crash_info, 8563 .write_elf32_note = x86_cpu_write_elf32_note, 8564 .write_elf64_note = x86_cpu_write_elf64_note, 8565 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8566 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8567 .legacy_vmsd = &vmstate_x86_cpu, 8568 }; 8569 #endif 8570 8571 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8572 { 8573 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8574 CPUClass *cc = CPU_CLASS(oc); 8575 DeviceClass *dc = DEVICE_CLASS(oc); 8576 ResettableClass *rc = RESETTABLE_CLASS(oc); 8577 FeatureWord w; 8578 8579 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8580 &xcc->parent_realize); 8581 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8582 &xcc->parent_unrealize); 8583 device_class_set_props(dc, x86_cpu_properties); 8584 8585 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8586 &xcc->parent_phases); 8587 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8588 8589 cc->class_by_name = x86_cpu_class_by_name; 8590 cc->parse_features = x86_cpu_parse_featurestr; 8591 cc->has_work = x86_cpu_has_work; 8592 cc->mmu_index = x86_cpu_mmu_index; 8593 cc->dump_state = x86_cpu_dump_state; 8594 cc->set_pc = x86_cpu_set_pc; 8595 cc->get_pc = x86_cpu_get_pc; 8596 cc->gdb_read_register = x86_cpu_gdb_read_register; 8597 cc->gdb_write_register = x86_cpu_gdb_write_register; 8598 cc->get_arch_id = x86_cpu_get_arch_id; 8599 8600 #ifndef CONFIG_USER_ONLY 8601 cc->sysemu_ops = &i386_sysemu_ops; 8602 #endif /* !CONFIG_USER_ONLY */ 8603 8604 cc->gdb_arch_name = x86_gdb_arch_name; 8605 #ifdef TARGET_X86_64 8606 cc->gdb_core_xml_file = "i386-64bit.xml"; 8607 #else 8608 cc->gdb_core_xml_file = "i386-32bit.xml"; 8609 #endif 8610 cc->disas_set_info = x86_disas_set_info; 8611 8612 dc->user_creatable = true; 8613 8614 object_class_property_add(oc, "family", "int", 8615 x86_cpuid_version_get_family, 8616 x86_cpuid_version_set_family, NULL, NULL); 8617 object_class_property_add(oc, "model", "int", 8618 x86_cpuid_version_get_model, 8619 x86_cpuid_version_set_model, NULL, NULL); 8620 object_class_property_add(oc, "stepping", "int", 8621 x86_cpuid_version_get_stepping, 8622 x86_cpuid_version_set_stepping, NULL, NULL); 8623 object_class_property_add_str(oc, "vendor", 8624 x86_cpuid_get_vendor, 8625 x86_cpuid_set_vendor); 8626 object_class_property_add_str(oc, "model-id", 8627 x86_cpuid_get_model_id, 8628 x86_cpuid_set_model_id); 8629 object_class_property_add(oc, "tsc-frequency", "int", 8630 x86_cpuid_get_tsc_freq, 8631 x86_cpuid_set_tsc_freq, NULL, NULL); 8632 /* 8633 * The "unavailable-features" property has the same semantics as 8634 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8635 * QMP command: they list the features that would have prevented the 8636 * CPU from running if the "enforce" flag was set. 8637 */ 8638 object_class_property_add(oc, "unavailable-features", "strList", 8639 x86_cpu_get_unavailable_features, 8640 NULL, NULL, NULL); 8641 8642 #if !defined(CONFIG_USER_ONLY) 8643 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8644 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8645 #endif 8646 8647 for (w = 0; w < FEATURE_WORDS; w++) { 8648 int bitnr; 8649 for (bitnr = 0; bitnr < 64; bitnr++) { 8650 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8651 } 8652 } 8653 } 8654 8655 static const TypeInfo x86_cpu_type_info = { 8656 .name = TYPE_X86_CPU, 8657 .parent = TYPE_CPU, 8658 .instance_size = sizeof(X86CPU), 8659 .instance_align = __alignof(X86CPU), 8660 .instance_init = x86_cpu_initfn, 8661 .instance_post_init = x86_cpu_post_initfn, 8662 8663 .abstract = true, 8664 .class_size = sizeof(X86CPUClass), 8665 .class_init = x86_cpu_common_class_init, 8666 }; 8667 8668 /* "base" CPU model, used by query-cpu-model-expansion */ 8669 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8670 { 8671 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8672 8673 xcc->static_model = true; 8674 xcc->migration_safe = true; 8675 xcc->model_description = "base CPU model type with no features enabled"; 8676 xcc->ordering = 8; 8677 } 8678 8679 static const TypeInfo x86_base_cpu_type_info = { 8680 .name = X86_CPU_TYPE_NAME("base"), 8681 .parent = TYPE_X86_CPU, 8682 .class_init = x86_cpu_base_class_init, 8683 }; 8684 8685 static void x86_cpu_register_types(void) 8686 { 8687 int i; 8688 8689 type_register_static(&x86_cpu_type_info); 8690 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8691 x86_register_cpudef_types(&builtin_x86_defs[i]); 8692 } 8693 type_register_static(&max_x86_cpu_type_info); 8694 type_register_static(&x86_base_cpu_type_info); 8695 } 8696 8697 type_init(x86_cpu_register_types) 8698