1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #include "exec/watchpoint.h" 39 #ifndef CONFIG_USER_ONLY 40 #include "system/reset.h" 41 #include "qapi/qapi-commands-machine-target.h" 42 #include "system/address-spaces.h" 43 #include "hw/boards.h" 44 #include "hw/i386/sgx-epc.h" 45 #endif 46 #include "tcg/tcg-cpu.h" 47 48 #include "disas/capstone.h" 49 #include "cpu-internal.h" 50 51 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 52 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 53 uint32_t *eax, uint32_t *ebx, 54 uint32_t *ecx, uint32_t *edx); 55 56 /* Helpers for building CPUID[2] descriptors: */ 57 58 struct CPUID2CacheDescriptorInfo { 59 enum CacheType type; 60 int level; 61 int size; 62 int line_size; 63 int associativity; 64 }; 65 66 /* 67 * Known CPUID 2 cache descriptors. 68 * From Intel SDM Volume 2A, CPUID instruction 69 */ 70 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 71 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 72 .associativity = 4, .line_size = 32, }, 73 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 76 .associativity = 4, .line_size = 64, }, 77 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 78 .associativity = 2, .line_size = 32, }, 79 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 80 .associativity = 4, .line_size = 32, }, 81 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 82 .associativity = 4, .line_size = 64, }, 83 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 84 .associativity = 6, .line_size = 64, }, 85 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 86 .associativity = 2, .line_size = 64, }, 87 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 88 .associativity = 8, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x22, 0x23 are not included 91 */ 92 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 93 .associativity = 16, .line_size = 64, }, 94 /* lines per sector is not supported cpuid2_cache_descriptor(), 95 * so descriptors 0x25, 0x20 are not included 96 */ 97 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 98 .associativity = 8, .line_size = 64, }, 99 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 100 .associativity = 8, .line_size = 64, }, 101 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 106 .associativity = 4, .line_size = 32, }, 107 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 108 .associativity = 4, .line_size = 32, }, 109 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 110 .associativity = 4, .line_size = 32, }, 111 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 112 .associativity = 4, .line_size = 64, }, 113 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 114 .associativity = 8, .line_size = 64, }, 115 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 116 .associativity = 12, .line_size = 64, }, 117 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 118 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 119 .associativity = 12, .line_size = 64, }, 120 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 121 .associativity = 16, .line_size = 64, }, 122 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 123 .associativity = 12, .line_size = 64, }, 124 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 125 .associativity = 16, .line_size = 64, }, 126 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 127 .associativity = 24, .line_size = 64, }, 128 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 129 .associativity = 8, .line_size = 64, }, 130 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 131 .associativity = 4, .line_size = 64, }, 132 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 133 .associativity = 4, .line_size = 64, }, 134 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 135 .associativity = 4, .line_size = 64, }, 136 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 137 .associativity = 4, .line_size = 64, }, 138 /* lines per sector is not supported cpuid2_cache_descriptor(), 139 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 140 */ 141 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 142 .associativity = 8, .line_size = 64, }, 143 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 2, .line_size = 64, }, 145 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 146 .associativity = 8, .line_size = 64, }, 147 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 150 .associativity = 8, .line_size = 32, }, 151 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 152 .associativity = 8, .line_size = 32, }, 153 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 154 .associativity = 8, .line_size = 32, }, 155 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 156 .associativity = 4, .line_size = 64, }, 157 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 158 .associativity = 8, .line_size = 64, }, 159 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 160 .associativity = 4, .line_size = 64, }, 161 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 162 .associativity = 4, .line_size = 64, }, 163 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 164 .associativity = 4, .line_size = 64, }, 165 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 166 .associativity = 8, .line_size = 64, }, 167 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 168 .associativity = 8, .line_size = 64, }, 169 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 170 .associativity = 8, .line_size = 64, }, 171 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 172 .associativity = 12, .line_size = 64, }, 173 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 174 .associativity = 12, .line_size = 64, }, 175 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 176 .associativity = 12, .line_size = 64, }, 177 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 178 .associativity = 16, .line_size = 64, }, 179 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 180 .associativity = 16, .line_size = 64, }, 181 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 182 .associativity = 16, .line_size = 64, }, 183 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 184 .associativity = 24, .line_size = 64, }, 185 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 186 .associativity = 24, .line_size = 64, }, 187 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 188 .associativity = 24, .line_size = 64, }, 189 }; 190 191 /* 192 * "CPUID leaf 2 does not report cache descriptor information, 193 * use CPUID leaf 4 to query cache parameters" 194 */ 195 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 196 197 /* 198 * Return a CPUID 2 cache descriptor for a given cache. 199 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 200 */ 201 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 202 { 203 int i; 204 205 assert(cache->size > 0); 206 assert(cache->level > 0); 207 assert(cache->line_size > 0); 208 assert(cache->associativity > 0); 209 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 210 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 211 if (d->level == cache->level && d->type == cache->type && 212 d->size == cache->size && d->line_size == cache->line_size && 213 d->associativity == cache->associativity) { 214 return i; 215 } 216 } 217 218 return CACHE_DESCRIPTOR_UNAVAILABLE; 219 } 220 221 /* CPUID Leaf 4 constants: */ 222 223 /* EAX: */ 224 #define CACHE_TYPE_D 1 225 #define CACHE_TYPE_I 2 226 #define CACHE_TYPE_UNIFIED 3 227 228 #define CACHE_LEVEL(l) (l << 5) 229 230 #define CACHE_SELF_INIT_LEVEL (1 << 8) 231 232 /* EDX: */ 233 #define CACHE_NO_INVD_SHARING (1 << 0) 234 #define CACHE_INCLUSIVE (1 << 1) 235 #define CACHE_COMPLEX_IDX (1 << 2) 236 237 /* Encode CacheType for CPUID[4].EAX */ 238 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 239 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 240 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 241 0 /* Invalid value */) 242 243 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 244 enum CpuTopologyLevel share_level) 245 { 246 uint32_t num_ids = 0; 247 248 switch (share_level) { 249 case CPU_TOPOLOGY_LEVEL_CORE: 250 num_ids = 1 << apicid_core_offset(topo_info); 251 break; 252 case CPU_TOPOLOGY_LEVEL_MODULE: 253 num_ids = 1 << apicid_module_offset(topo_info); 254 break; 255 case CPU_TOPOLOGY_LEVEL_DIE: 256 num_ids = 1 << apicid_die_offset(topo_info); 257 break; 258 case CPU_TOPOLOGY_LEVEL_SOCKET: 259 num_ids = 1 << apicid_pkg_offset(topo_info); 260 break; 261 default: 262 /* 263 * Currently there is no use case for THREAD, so use 264 * assert directly to facilitate debugging. 265 */ 266 g_assert_not_reached(); 267 } 268 269 return num_ids - 1; 270 } 271 272 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 273 { 274 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 275 apicid_core_offset(topo_info)); 276 return num_cores - 1; 277 } 278 279 /* Encode cache info for CPUID[4] */ 280 static void encode_cache_cpuid4(CPUCacheInfo *cache, 281 X86CPUTopoInfo *topo_info, 282 uint32_t *eax, uint32_t *ebx, 283 uint32_t *ecx, uint32_t *edx) 284 { 285 assert(cache->size == cache->line_size * cache->associativity * 286 cache->partitions * cache->sets); 287 288 *eax = CACHE_TYPE(cache->type) | 289 CACHE_LEVEL(cache->level) | 290 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 291 (max_core_ids_in_package(topo_info) << 26) | 292 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 293 294 assert(cache->line_size > 0); 295 assert(cache->partitions > 0); 296 assert(cache->associativity > 0); 297 /* We don't implement fully-associative caches */ 298 assert(cache->associativity < cache->sets); 299 *ebx = (cache->line_size - 1) | 300 ((cache->partitions - 1) << 12) | 301 ((cache->associativity - 1) << 22); 302 303 assert(cache->sets > 0); 304 *ecx = cache->sets - 1; 305 306 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 307 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 308 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 309 } 310 311 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 312 enum CpuTopologyLevel topo_level) 313 { 314 switch (topo_level) { 315 case CPU_TOPOLOGY_LEVEL_THREAD: 316 return 1; 317 case CPU_TOPOLOGY_LEVEL_CORE: 318 return topo_info->threads_per_core; 319 case CPU_TOPOLOGY_LEVEL_MODULE: 320 return x86_threads_per_module(topo_info); 321 case CPU_TOPOLOGY_LEVEL_DIE: 322 return x86_threads_per_die(topo_info); 323 case CPU_TOPOLOGY_LEVEL_SOCKET: 324 return x86_threads_per_pkg(topo_info); 325 default: 326 g_assert_not_reached(); 327 } 328 return 0; 329 } 330 331 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 332 enum CpuTopologyLevel topo_level) 333 { 334 switch (topo_level) { 335 case CPU_TOPOLOGY_LEVEL_THREAD: 336 return 0; 337 case CPU_TOPOLOGY_LEVEL_CORE: 338 return apicid_core_offset(topo_info); 339 case CPU_TOPOLOGY_LEVEL_MODULE: 340 return apicid_module_offset(topo_info); 341 case CPU_TOPOLOGY_LEVEL_DIE: 342 return apicid_die_offset(topo_info); 343 case CPU_TOPOLOGY_LEVEL_SOCKET: 344 return apicid_pkg_offset(topo_info); 345 default: 346 g_assert_not_reached(); 347 } 348 return 0; 349 } 350 351 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 352 { 353 switch (topo_level) { 354 case CPU_TOPOLOGY_LEVEL_INVALID: 355 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 356 case CPU_TOPOLOGY_LEVEL_THREAD: 357 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 358 case CPU_TOPOLOGY_LEVEL_CORE: 359 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 360 case CPU_TOPOLOGY_LEVEL_MODULE: 361 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 362 case CPU_TOPOLOGY_LEVEL_DIE: 363 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 364 default: 365 /* Other types are not supported in QEMU. */ 366 g_assert_not_reached(); 367 } 368 return 0; 369 } 370 371 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 372 X86CPUTopoInfo *topo_info, 373 uint32_t *eax, uint32_t *ebx, 374 uint32_t *ecx, uint32_t *edx) 375 { 376 X86CPU *cpu = env_archcpu(env); 377 unsigned long level, base_level, next_level; 378 uint32_t num_threads_next_level, offset_next_level; 379 380 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 381 382 /* 383 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 384 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 385 */ 386 level = CPU_TOPOLOGY_LEVEL_THREAD; 387 base_level = level; 388 for (int i = 0; i <= count; i++) { 389 level = find_next_bit(env->avail_cpu_topo, 390 CPU_TOPOLOGY_LEVEL_SOCKET, 391 base_level); 392 393 /* 394 * CPUID[0x1f] doesn't explicitly encode the package level, 395 * and it just encodes the invalid level (all fields are 0) 396 * into the last subleaf of 0x1f. 397 */ 398 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 399 level = CPU_TOPOLOGY_LEVEL_INVALID; 400 break; 401 } 402 /* Search the next level. */ 403 base_level = level + 1; 404 } 405 406 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 407 num_threads_next_level = 0; 408 offset_next_level = 0; 409 } else { 410 next_level = find_next_bit(env->avail_cpu_topo, 411 CPU_TOPOLOGY_LEVEL_SOCKET, 412 level + 1); 413 num_threads_next_level = num_threads_by_topo_level(topo_info, 414 next_level); 415 offset_next_level = apicid_offset_by_topo_level(topo_info, 416 next_level); 417 } 418 419 *eax = offset_next_level; 420 /* The count (bits 15-00) doesn't need to be reliable. */ 421 *ebx = num_threads_next_level & 0xffff; 422 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 423 *edx = cpu->apic_id; 424 425 assert(!(*eax & ~0x1f)); 426 } 427 428 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 429 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 430 { 431 assert(cache->size % 1024 == 0); 432 assert(cache->lines_per_tag > 0); 433 assert(cache->associativity > 0); 434 assert(cache->line_size > 0); 435 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 436 (cache->lines_per_tag << 8) | (cache->line_size); 437 } 438 439 #define ASSOC_FULL 0xFF 440 441 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 442 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 443 a == 2 ? 0x2 : \ 444 a == 4 ? 0x4 : \ 445 a == 8 ? 0x6 : \ 446 a == 16 ? 0x8 : \ 447 a == 32 ? 0xA : \ 448 a == 48 ? 0xB : \ 449 a == 64 ? 0xC : \ 450 a == 96 ? 0xD : \ 451 a == 128 ? 0xE : \ 452 a == ASSOC_FULL ? 0xF : \ 453 0 /* invalid value */) 454 455 /* 456 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 457 * @l3 can be NULL. 458 */ 459 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 460 CPUCacheInfo *l3, 461 uint32_t *ecx, uint32_t *edx) 462 { 463 assert(l2->size % 1024 == 0); 464 assert(l2->associativity > 0); 465 assert(l2->lines_per_tag > 0); 466 assert(l2->line_size > 0); 467 *ecx = ((l2->size / 1024) << 16) | 468 (AMD_ENC_ASSOC(l2->associativity) << 12) | 469 (l2->lines_per_tag << 8) | (l2->line_size); 470 471 if (l3) { 472 assert(l3->size % (512 * 1024) == 0); 473 assert(l3->associativity > 0); 474 assert(l3->lines_per_tag > 0); 475 assert(l3->line_size > 0); 476 *edx = ((l3->size / (512 * 1024)) << 18) | 477 (AMD_ENC_ASSOC(l3->associativity) << 12) | 478 (l3->lines_per_tag << 8) | (l3->line_size); 479 } else { 480 *edx = 0; 481 } 482 } 483 484 /* Encode cache info for CPUID[8000001D] */ 485 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 486 X86CPUTopoInfo *topo_info, 487 uint32_t *eax, uint32_t *ebx, 488 uint32_t *ecx, uint32_t *edx) 489 { 490 assert(cache->size == cache->line_size * cache->associativity * 491 cache->partitions * cache->sets); 492 493 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 494 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 495 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 496 497 assert(cache->line_size > 0); 498 assert(cache->partitions > 0); 499 assert(cache->associativity > 0); 500 /* We don't implement fully-associative caches */ 501 assert(cache->associativity < cache->sets); 502 *ebx = (cache->line_size - 1) | 503 ((cache->partitions - 1) << 12) | 504 ((cache->associativity - 1) << 22); 505 506 assert(cache->sets > 0); 507 *ecx = cache->sets - 1; 508 509 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 510 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 511 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 512 } 513 514 /* Encode cache info for CPUID[8000001E] */ 515 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 516 uint32_t *eax, uint32_t *ebx, 517 uint32_t *ecx, uint32_t *edx) 518 { 519 X86CPUTopoIDs topo_ids; 520 521 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 522 523 *eax = cpu->apic_id; 524 525 /* 526 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 527 * Read-only. Reset: 0000_XXXXh. 528 * See Core::X86::Cpuid::ExtApicId. 529 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 530 * Bits Description 531 * 31:16 Reserved. 532 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 533 * The number of threads per core is ThreadsPerCore+1. 534 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 535 * 536 * NOTE: CoreId is already part of apic_id. Just use it. We can 537 * use all the 8 bits to represent the core_id here. 538 */ 539 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 540 541 /* 542 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 543 * Read-only. Reset: 0000_0XXXh. 544 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 545 * Bits Description 546 * 31:11 Reserved. 547 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 548 * ValidValues: 549 * Value Description 550 * 0h 1 node per processor. 551 * 7h-1h Reserved. 552 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 553 * 554 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 555 * But users can create more nodes than the actual hardware can 556 * support. To genaralize we can use all the upper 8 bits for nodes. 557 * NodeId is combination of node and socket_id which is already decoded 558 * in apic_id. Just use it by shifting. 559 */ 560 if (cpu->legacy_multi_node) { 561 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 562 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 563 } else { 564 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 565 } 566 567 *edx = 0; 568 } 569 570 /* 571 * Definitions of the hardcoded cache entries we expose: 572 * These are legacy cache values. If there is a need to change any 573 * of these values please use builtin_x86_defs 574 */ 575 576 /* L1 data cache: */ 577 static CPUCacheInfo legacy_l1d_cache = { 578 .type = DATA_CACHE, 579 .level = 1, 580 .size = 32 * KiB, 581 .self_init = 1, 582 .line_size = 64, 583 .associativity = 8, 584 .sets = 64, 585 .partitions = 1, 586 .no_invd_sharing = true, 587 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 588 }; 589 590 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 591 static CPUCacheInfo legacy_l1d_cache_amd = { 592 .type = DATA_CACHE, 593 .level = 1, 594 .size = 64 * KiB, 595 .self_init = 1, 596 .line_size = 64, 597 .associativity = 2, 598 .sets = 512, 599 .partitions = 1, 600 .lines_per_tag = 1, 601 .no_invd_sharing = true, 602 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 603 }; 604 605 /* L1 instruction cache: */ 606 static CPUCacheInfo legacy_l1i_cache = { 607 .type = INSTRUCTION_CACHE, 608 .level = 1, 609 .size = 32 * KiB, 610 .self_init = 1, 611 .line_size = 64, 612 .associativity = 8, 613 .sets = 64, 614 .partitions = 1, 615 .no_invd_sharing = true, 616 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 617 }; 618 619 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 620 static CPUCacheInfo legacy_l1i_cache_amd = { 621 .type = INSTRUCTION_CACHE, 622 .level = 1, 623 .size = 64 * KiB, 624 .self_init = 1, 625 .line_size = 64, 626 .associativity = 2, 627 .sets = 512, 628 .partitions = 1, 629 .lines_per_tag = 1, 630 .no_invd_sharing = true, 631 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 632 }; 633 634 /* Level 2 unified cache: */ 635 static CPUCacheInfo legacy_l2_cache = { 636 .type = UNIFIED_CACHE, 637 .level = 2, 638 .size = 4 * MiB, 639 .self_init = 1, 640 .line_size = 64, 641 .associativity = 16, 642 .sets = 4096, 643 .partitions = 1, 644 .no_invd_sharing = true, 645 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 646 }; 647 648 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 649 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 650 .type = UNIFIED_CACHE, 651 .level = 2, 652 .size = 2 * MiB, 653 .line_size = 64, 654 .associativity = 8, 655 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 656 }; 657 658 659 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 660 static CPUCacheInfo legacy_l2_cache_amd = { 661 .type = UNIFIED_CACHE, 662 .level = 2, 663 .size = 512 * KiB, 664 .line_size = 64, 665 .lines_per_tag = 1, 666 .associativity = 16, 667 .sets = 512, 668 .partitions = 1, 669 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 670 }; 671 672 /* Level 3 unified cache: */ 673 static CPUCacheInfo legacy_l3_cache = { 674 .type = UNIFIED_CACHE, 675 .level = 3, 676 .size = 16 * MiB, 677 .line_size = 64, 678 .associativity = 16, 679 .sets = 16384, 680 .partitions = 1, 681 .lines_per_tag = 1, 682 .self_init = true, 683 .inclusive = true, 684 .complex_indexing = true, 685 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 686 }; 687 688 /* TLB definitions: */ 689 690 #define L1_DTLB_2M_ASSOC 1 691 #define L1_DTLB_2M_ENTRIES 255 692 #define L1_DTLB_4K_ASSOC 1 693 #define L1_DTLB_4K_ENTRIES 255 694 695 #define L1_ITLB_2M_ASSOC 1 696 #define L1_ITLB_2M_ENTRIES 255 697 #define L1_ITLB_4K_ASSOC 1 698 #define L1_ITLB_4K_ENTRIES 255 699 700 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 701 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 702 #define L2_DTLB_4K_ASSOC 4 703 #define L2_DTLB_4K_ENTRIES 512 704 705 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 706 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 707 #define L2_ITLB_4K_ASSOC 4 708 #define L2_ITLB_4K_ENTRIES 512 709 710 /* CPUID Leaf 0x14 constants: */ 711 #define INTEL_PT_MAX_SUBLEAF 0x1 712 /* 713 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 714 * MSR can be accessed; 715 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 716 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 717 * of Intel PT MSRs across warm reset; 718 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 719 */ 720 #define INTEL_PT_MINIMAL_EBX 0xf 721 /* 722 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 723 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 724 * accessed; 725 * bit[01]: ToPA tables can hold any number of output entries, up to the 726 * maximum allowed by the MaskOrTableOffset field of 727 * IA32_RTIT_OUTPUT_MASK_PTRS; 728 * bit[02]: Support Single-Range Output scheme; 729 */ 730 #define INTEL_PT_MINIMAL_ECX 0x7 731 /* generated packets which contain IP payloads have LIP values */ 732 #define INTEL_PT_IP_LIP (1 << 31) 733 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 734 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 735 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 736 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 737 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 738 739 /* CPUID Leaf 0x1D constants: */ 740 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 741 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 742 #define INTEL_AMX_BYTES_PER_TILE 0x400 743 #define INTEL_AMX_BYTES_PER_ROW 0x40 744 #define INTEL_AMX_TILE_MAX_NAMES 0x8 745 #define INTEL_AMX_TILE_MAX_ROWS 0x10 746 747 /* CPUID Leaf 0x1E constants: */ 748 #define INTEL_AMX_TMUL_MAX_K 0x10 749 #define INTEL_AMX_TMUL_MAX_N 0x40 750 751 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 752 uint32_t vendor2, uint32_t vendor3) 753 { 754 int i; 755 for (i = 0; i < 4; i++) { 756 dst[i] = vendor1 >> (8 * i); 757 dst[i + 4] = vendor2 >> (8 * i); 758 dst[i + 8] = vendor3 >> (8 * i); 759 } 760 dst[CPUID_VENDOR_SZ] = '\0'; 761 } 762 763 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 764 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 765 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 766 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 767 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 768 CPUID_PSE36 | CPUID_FXSR) 769 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 770 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 771 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 772 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 773 CPUID_PAE | CPUID_SEP | CPUID_APIC) 774 775 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 776 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 777 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 778 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 779 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE | \ 780 CPUID_HT) 781 /* partly implemented: 782 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 783 /* missing: 784 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_TM, CPUID_PBE */ 785 786 /* 787 * Kernel-only features that can be shown to usermode programs even if 788 * they aren't actually supported by TCG, because qemu-user only runs 789 * in CPL=3; remove them if they are ever implemented for system emulation. 790 */ 791 #if defined CONFIG_USER_ONLY 792 #define CPUID_EXT_KERNEL_FEATURES \ 793 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 794 #else 795 #define CPUID_EXT_KERNEL_FEATURES 0 796 #endif 797 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 798 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 799 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 800 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 801 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 802 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 803 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 804 /* missing: 805 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 806 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 807 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 808 CPUID_EXT_TSC_DEADLINE_TIMER 809 */ 810 811 #ifdef TARGET_X86_64 812 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 813 #else 814 #define TCG_EXT2_X86_64_FEATURES 0 815 #endif 816 817 /* 818 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 819 * in usermode or by 32-bit programs. Those are added to supported 820 * TCG features unconditionally in user-mode emulation mode. This may 821 * indeed seem strange or incorrect, but it works because code running 822 * under usermode emulation cannot access them. 823 * 824 * Even for long mode, qemu-i386 is not running "a userspace program on a 825 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 826 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 827 * but again the difference is only visible in kernel mode. 828 */ 829 #if defined CONFIG_LINUX_USER 830 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 831 #elif defined CONFIG_USER_ONLY 832 /* FIXME: Long mode not yet supported for i386 bsd-user */ 833 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 834 #else 835 #define CPUID_EXT2_KERNEL_FEATURES 0 836 #endif 837 838 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 839 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 840 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 841 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 842 CPUID_EXT2_KERNEL_FEATURES) 843 844 #if defined CONFIG_USER_ONLY 845 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 846 #else 847 #define CPUID_EXT3_KERNEL_FEATURES 0 848 #endif 849 850 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 851 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 852 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES | \ 853 CPUID_EXT3_CMP_LEG) 854 855 #define TCG_EXT4_FEATURES 0 856 857 #if defined CONFIG_USER_ONLY 858 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 859 #else 860 #define CPUID_SVM_KERNEL_FEATURES 0 861 #endif 862 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 863 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 864 865 #define TCG_KVM_FEATURES 0 866 867 #if defined CONFIG_USER_ONLY 868 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 869 #else 870 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 871 #endif 872 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 873 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 874 CPUID_7_0_EBX_CLFLUSHOPT | \ 875 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 876 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 877 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 878 /* missing: 879 CPUID_7_0_EBX_HLE 880 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 881 882 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 883 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 884 #else 885 #define TCG_7_0_ECX_RDPID 0 886 #endif 887 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 888 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 889 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 890 TCG_7_0_ECX_RDPID) 891 892 #if defined CONFIG_USER_ONLY 893 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 894 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 895 #else 896 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 897 #endif 898 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 899 900 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 901 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 902 #define TCG_7_1_EDX_FEATURES 0 903 #define TCG_7_2_EDX_FEATURES 0 904 #define TCG_APM_FEATURES 0 905 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 906 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 907 /* missing: 908 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 909 #define TCG_14_0_ECX_FEATURES 0 910 #define TCG_SGX_12_0_EAX_FEATURES 0 911 #define TCG_SGX_12_0_EBX_FEATURES 0 912 #define TCG_SGX_12_1_EAX_FEATURES 0 913 #define TCG_24_0_EBX_FEATURES 0 914 915 #if defined CONFIG_USER_ONLY 916 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 917 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 918 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 919 CPUID_8000_0008_EBX_AMD_PSFD) 920 #else 921 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 922 #endif 923 924 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 925 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 926 927 #if defined CONFIG_USER_ONLY 928 #define CPUID_8000_0021_EAX_KERNEL_FEATURES CPUID_8000_0021_EAX_AUTO_IBRS 929 #else 930 #define CPUID_8000_0021_EAX_KERNEL_FEATURES 0 931 #endif 932 933 #define TCG_8000_0021_EAX_FEATURES ( \ 934 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | \ 935 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | \ 936 CPUID_8000_0021_EAX_KERNEL_FEATURES) 937 938 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 939 [FEAT_1_EDX] = { 940 .type = CPUID_FEATURE_WORD, 941 .feat_names = { 942 "fpu", "vme", "de", "pse", 943 "tsc", "msr", "pae", "mce", 944 "cx8", "apic", NULL, "sep", 945 "mtrr", "pge", "mca", "cmov", 946 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 947 NULL, "ds" /* Intel dts */, "acpi", "mmx", 948 "fxsr", "sse", "sse2", "ss", 949 "ht" /* Intel htt */, "tm", "ia64", "pbe", 950 }, 951 .cpuid = {.eax = 1, .reg = R_EDX, }, 952 .tcg_features = TCG_FEATURES, 953 .no_autoenable_flags = CPUID_HT, 954 }, 955 [FEAT_1_ECX] = { 956 .type = CPUID_FEATURE_WORD, 957 .feat_names = { 958 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 959 "ds-cpl", "vmx", "smx", "est", 960 "tm2", "ssse3", "cid", NULL, 961 "fma", "cx16", "xtpr", "pdcm", 962 NULL, "pcid", "dca", "sse4.1", 963 "sse4.2", "x2apic", "movbe", "popcnt", 964 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 965 "avx", "f16c", "rdrand", "hypervisor", 966 }, 967 .cpuid = { .eax = 1, .reg = R_ECX, }, 968 .tcg_features = TCG_EXT_FEATURES, 969 }, 970 /* Feature names that are already defined on feature_name[] but 971 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 972 * names on feat_names below. They are copied automatically 973 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 974 */ 975 [FEAT_8000_0001_EDX] = { 976 .type = CPUID_FEATURE_WORD, 977 .feat_names = { 978 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 979 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 980 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 981 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 982 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 983 "nx", NULL, "mmxext", NULL /* mmx */, 984 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 985 NULL, "lm", "3dnowext", "3dnow", 986 }, 987 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 988 .tcg_features = TCG_EXT2_FEATURES, 989 }, 990 [FEAT_8000_0001_ECX] = { 991 .type = CPUID_FEATURE_WORD, 992 .feat_names = { 993 "lahf-lm", "cmp-legacy", "svm", "extapic", 994 "cr8legacy", "abm", "sse4a", "misalignsse", 995 "3dnowprefetch", "osvw", "ibs", "xop", 996 "skinit", "wdt", NULL, "lwp", 997 "fma4", "tce", NULL, "nodeid-msr", 998 NULL, "tbm", "topoext", "perfctr-core", 999 "perfctr-nb", NULL, NULL, NULL, 1000 NULL, NULL, NULL, NULL, 1001 }, 1002 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 1003 .tcg_features = TCG_EXT3_FEATURES, 1004 /* 1005 * TOPOEXT is always allowed but can't be enabled blindly by 1006 * "-cpu host", as it requires consistent cache topology info 1007 * to be provided so it doesn't confuse guests. 1008 */ 1009 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 1010 }, 1011 [FEAT_C000_0001_EDX] = { 1012 .type = CPUID_FEATURE_WORD, 1013 .feat_names = { 1014 NULL, NULL, "xstore", "xstore-en", 1015 NULL, NULL, "xcrypt", "xcrypt-en", 1016 "ace2", "ace2-en", "phe", "phe-en", 1017 "pmm", "pmm-en", NULL, NULL, 1018 NULL, NULL, NULL, NULL, 1019 NULL, NULL, NULL, NULL, 1020 NULL, NULL, NULL, NULL, 1021 NULL, NULL, NULL, NULL, 1022 }, 1023 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1024 .tcg_features = TCG_EXT4_FEATURES, 1025 }, 1026 [FEAT_KVM] = { 1027 .type = CPUID_FEATURE_WORD, 1028 .feat_names = { 1029 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1030 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1031 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1032 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1033 NULL, NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 "kvmclock-stable-bit", NULL, NULL, NULL, 1036 NULL, NULL, NULL, NULL, 1037 }, 1038 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1039 .tcg_features = TCG_KVM_FEATURES, 1040 }, 1041 [FEAT_KVM_HINTS] = { 1042 .type = CPUID_FEATURE_WORD, 1043 .feat_names = { 1044 "kvm-hint-dedicated", NULL, NULL, NULL, 1045 NULL, NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 NULL, NULL, NULL, NULL, 1051 NULL, NULL, NULL, NULL, 1052 }, 1053 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1054 .tcg_features = TCG_KVM_FEATURES, 1055 /* 1056 * KVM hints aren't auto-enabled by -cpu host, they need to be 1057 * explicitly enabled in the command-line. 1058 */ 1059 .no_autoenable_flags = ~0U, 1060 }, 1061 [FEAT_SVM] = { 1062 .type = CPUID_FEATURE_WORD, 1063 .feat_names = { 1064 "npt", "lbrv", "svm-lock", "nrip-save", 1065 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1066 NULL, NULL, "pause-filter", NULL, 1067 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1068 "vgif", NULL, NULL, NULL, 1069 NULL, NULL, NULL, NULL, 1070 NULL, "vnmi", NULL, NULL, 1071 "svme-addr-chk", NULL, NULL, NULL, 1072 }, 1073 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1074 .tcg_features = TCG_SVM_FEATURES, 1075 }, 1076 [FEAT_7_0_EBX] = { 1077 .type = CPUID_FEATURE_WORD, 1078 .feat_names = { 1079 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1080 "hle", "avx2", "fdp-excptn-only", "smep", 1081 "bmi2", "erms", "invpcid", "rtm", 1082 NULL, "zero-fcs-fds", "mpx", NULL, 1083 "avx512f", "avx512dq", "rdseed", "adx", 1084 "smap", "avx512ifma", "pcommit", "clflushopt", 1085 "clwb", "intel-pt", "avx512pf", "avx512er", 1086 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1087 }, 1088 .cpuid = { 1089 .eax = 7, 1090 .needs_ecx = true, .ecx = 0, 1091 .reg = R_EBX, 1092 }, 1093 .tcg_features = TCG_7_0_EBX_FEATURES, 1094 }, 1095 [FEAT_7_0_ECX] = { 1096 .type = CPUID_FEATURE_WORD, 1097 .feat_names = { 1098 NULL, "avx512vbmi", "umip", "pku", 1099 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1100 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1101 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1102 "la57", NULL, NULL, NULL, 1103 NULL, NULL, "rdpid", NULL, 1104 "bus-lock-detect", "cldemote", NULL, "movdiri", 1105 "movdir64b", NULL, "sgxlc", "pks", 1106 }, 1107 .cpuid = { 1108 .eax = 7, 1109 .needs_ecx = true, .ecx = 0, 1110 .reg = R_ECX, 1111 }, 1112 .tcg_features = TCG_7_0_ECX_FEATURES, 1113 }, 1114 [FEAT_7_0_EDX] = { 1115 .type = CPUID_FEATURE_WORD, 1116 .feat_names = { 1117 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1118 "fsrm", NULL, NULL, NULL, 1119 "avx512-vp2intersect", NULL, "md-clear", NULL, 1120 NULL, NULL, "serialize", NULL, 1121 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1122 NULL, NULL, "amx-bf16", "avx512-fp16", 1123 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1124 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1125 }, 1126 .cpuid = { 1127 .eax = 7, 1128 .needs_ecx = true, .ecx = 0, 1129 .reg = R_EDX, 1130 }, 1131 .tcg_features = TCG_7_0_EDX_FEATURES, 1132 }, 1133 [FEAT_7_1_EAX] = { 1134 .type = CPUID_FEATURE_WORD, 1135 .feat_names = { 1136 "sha512", "sm3", "sm4", NULL, 1137 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1138 NULL, NULL, "fzrm", "fsrs", 1139 "fsrc", NULL, NULL, NULL, 1140 NULL, "fred", "lkgs", "wrmsrns", 1141 NULL, "amx-fp16", NULL, "avx-ifma", 1142 NULL, NULL, "lam", NULL, 1143 NULL, NULL, NULL, NULL, 1144 }, 1145 .cpuid = { 1146 .eax = 7, 1147 .needs_ecx = true, .ecx = 1, 1148 .reg = R_EAX, 1149 }, 1150 .tcg_features = TCG_7_1_EAX_FEATURES, 1151 }, 1152 [FEAT_7_1_EDX] = { 1153 .type = CPUID_FEATURE_WORD, 1154 .feat_names = { 1155 NULL, NULL, NULL, NULL, 1156 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1157 "amx-complex", NULL, "avx-vnni-int16", NULL, 1158 NULL, NULL, "prefetchiti", NULL, 1159 NULL, NULL, NULL, "avx10", 1160 NULL, NULL, NULL, NULL, 1161 NULL, NULL, NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 }, 1164 .cpuid = { 1165 .eax = 7, 1166 .needs_ecx = true, .ecx = 1, 1167 .reg = R_EDX, 1168 }, 1169 .tcg_features = TCG_7_1_EDX_FEATURES, 1170 }, 1171 [FEAT_7_2_EDX] = { 1172 .type = CPUID_FEATURE_WORD, 1173 .feat_names = { 1174 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1175 "bhi-ctrl", "mcdt-no", NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 NULL, NULL, NULL, NULL, 1180 NULL, NULL, NULL, NULL, 1181 NULL, NULL, NULL, NULL, 1182 }, 1183 .cpuid = { 1184 .eax = 7, 1185 .needs_ecx = true, .ecx = 2, 1186 .reg = R_EDX, 1187 }, 1188 .tcg_features = TCG_7_2_EDX_FEATURES, 1189 }, 1190 [FEAT_24_0_EBX] = { 1191 .type = CPUID_FEATURE_WORD, 1192 .feat_names = { 1193 [16] = "avx10-128", 1194 [17] = "avx10-256", 1195 [18] = "avx10-512", 1196 }, 1197 .cpuid = { 1198 .eax = 0x24, 1199 .needs_ecx = true, .ecx = 0, 1200 .reg = R_EBX, 1201 }, 1202 .tcg_features = TCG_24_0_EBX_FEATURES, 1203 }, 1204 [FEAT_8000_0007_EDX] = { 1205 .type = CPUID_FEATURE_WORD, 1206 .feat_names = { 1207 NULL, NULL, NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 "invtsc", NULL, NULL, NULL, 1210 NULL, NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 }, 1216 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1217 .tcg_features = TCG_APM_FEATURES, 1218 .unmigratable_flags = CPUID_APM_INVTSC, 1219 }, 1220 [FEAT_8000_0007_EBX] = { 1221 .type = CPUID_FEATURE_WORD, 1222 .feat_names = { 1223 "overflow-recov", "succor", NULL, NULL, 1224 NULL, NULL, NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 NULL, NULL, NULL, NULL, 1227 NULL, NULL, NULL, NULL, 1228 NULL, NULL, NULL, NULL, 1229 NULL, NULL, NULL, NULL, 1230 NULL, NULL, NULL, NULL, 1231 }, 1232 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1233 .tcg_features = 0, 1234 .unmigratable_flags = 0, 1235 }, 1236 [FEAT_8000_0008_EBX] = { 1237 .type = CPUID_FEATURE_WORD, 1238 .feat_names = { 1239 "clzero", NULL, "xsaveerptr", NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, "wbnoinvd", NULL, NULL, 1242 "ibpb", NULL, "ibrs", "amd-stibp", 1243 NULL, "stibp-always-on", NULL, NULL, 1244 NULL, NULL, NULL, NULL, 1245 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1246 "amd-psfd", NULL, NULL, NULL, 1247 }, 1248 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1249 .tcg_features = TCG_8000_0008_EBX, 1250 .unmigratable_flags = 0, 1251 }, 1252 [FEAT_8000_0021_EAX] = { 1253 .type = CPUID_FEATURE_WORD, 1254 .feat_names = { 1255 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1256 NULL, NULL, "null-sel-clr-base", NULL, 1257 "auto-ibrs", NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 NULL, NULL, NULL, NULL, 1261 "eraps", NULL, NULL, "sbpb", 1262 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1263 }, 1264 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1265 .tcg_features = TCG_8000_0021_EAX_FEATURES, 1266 .unmigratable_flags = 0, 1267 }, 1268 [FEAT_8000_0021_EBX] = { 1269 .type = CPUID_FEATURE_WORD, 1270 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1271 .tcg_features = 0, 1272 .unmigratable_flags = 0, 1273 }, 1274 [FEAT_8000_0022_EAX] = { 1275 .type = CPUID_FEATURE_WORD, 1276 .feat_names = { 1277 "perfmon-v2", NULL, NULL, NULL, 1278 NULL, NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 }, 1286 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1287 .tcg_features = 0, 1288 .unmigratable_flags = 0, 1289 }, 1290 [FEAT_XSAVE] = { 1291 .type = CPUID_FEATURE_WORD, 1292 .feat_names = { 1293 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1294 "xfd", NULL, NULL, NULL, 1295 NULL, NULL, NULL, NULL, 1296 NULL, NULL, NULL, NULL, 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 NULL, NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 }, 1302 .cpuid = { 1303 .eax = 0xd, 1304 .needs_ecx = true, .ecx = 1, 1305 .reg = R_EAX, 1306 }, 1307 .tcg_features = TCG_XSAVE_FEATURES, 1308 }, 1309 [FEAT_XSAVE_XSS_LO] = { 1310 .type = CPUID_FEATURE_WORD, 1311 .feat_names = { 1312 NULL, NULL, NULL, NULL, 1313 NULL, NULL, NULL, NULL, 1314 NULL, NULL, NULL, NULL, 1315 NULL, NULL, NULL, NULL, 1316 NULL, NULL, NULL, NULL, 1317 NULL, NULL, NULL, NULL, 1318 NULL, NULL, NULL, NULL, 1319 NULL, NULL, NULL, NULL, 1320 }, 1321 .cpuid = { 1322 .eax = 0xD, 1323 .needs_ecx = true, 1324 .ecx = 1, 1325 .reg = R_ECX, 1326 }, 1327 }, 1328 [FEAT_XSAVE_XSS_HI] = { 1329 .type = CPUID_FEATURE_WORD, 1330 .cpuid = { 1331 .eax = 0xD, 1332 .needs_ecx = true, 1333 .ecx = 1, 1334 .reg = R_EDX 1335 }, 1336 }, 1337 [FEAT_6_EAX] = { 1338 .type = CPUID_FEATURE_WORD, 1339 .feat_names = { 1340 NULL, NULL, "arat", NULL, 1341 NULL, NULL, NULL, NULL, 1342 NULL, NULL, NULL, NULL, 1343 NULL, NULL, NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 }, 1349 .cpuid = { .eax = 6, .reg = R_EAX, }, 1350 .tcg_features = TCG_6_EAX_FEATURES, 1351 }, 1352 [FEAT_XSAVE_XCR0_LO] = { 1353 .type = CPUID_FEATURE_WORD, 1354 .cpuid = { 1355 .eax = 0xD, 1356 .needs_ecx = true, .ecx = 0, 1357 .reg = R_EAX, 1358 }, 1359 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1360 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1361 XSTATE_PKRU_MASK, 1362 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1363 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1364 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1365 XSTATE_PKRU_MASK, 1366 }, 1367 [FEAT_XSAVE_XCR0_HI] = { 1368 .type = CPUID_FEATURE_WORD, 1369 .cpuid = { 1370 .eax = 0xD, 1371 .needs_ecx = true, .ecx = 0, 1372 .reg = R_EDX, 1373 }, 1374 .tcg_features = 0U, 1375 }, 1376 /*Below are MSR exposed features*/ 1377 [FEAT_ARCH_CAPABILITIES] = { 1378 .type = MSR_FEATURE_WORD, 1379 .feat_names = { 1380 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1381 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1382 "taa-no", NULL, NULL, NULL, 1383 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1384 NULL, "fb-clear", NULL, NULL, 1385 "bhi-no", NULL, NULL, NULL, 1386 "pbrsb-no", NULL, "gds-no", "rfds-no", 1387 "rfds-clear", NULL, NULL, NULL, 1388 NULL, NULL, NULL, NULL, 1389 NULL, NULL, NULL, NULL, 1390 NULL, NULL, NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 NULL, NULL, NULL, NULL, 1395 NULL, NULL, "its-no", NULL, 1396 }, 1397 .msr = { 1398 .index = MSR_IA32_ARCH_CAPABILITIES, 1399 }, 1400 /* 1401 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1402 * cannot be read from user mode. Therefore, it has no impact 1403 > on any user-mode operation, and warnings about unsupported 1404 * features do not matter. 1405 */ 1406 .tcg_features = ~0U, 1407 }, 1408 [FEAT_CORE_CAPABILITY] = { 1409 .type = MSR_FEATURE_WORD, 1410 .feat_names = { 1411 NULL, NULL, NULL, NULL, 1412 NULL, "split-lock-detect", NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 NULL, NULL, NULL, NULL, 1417 NULL, NULL, NULL, NULL, 1418 NULL, NULL, NULL, NULL, 1419 }, 1420 .msr = { 1421 .index = MSR_IA32_CORE_CAPABILITY, 1422 }, 1423 }, 1424 [FEAT_PERF_CAPABILITIES] = { 1425 .type = MSR_FEATURE_WORD, 1426 .feat_names = { 1427 NULL, NULL, NULL, NULL, 1428 NULL, NULL, NULL, NULL, 1429 NULL, NULL, NULL, NULL, 1430 NULL, "full-width-write", NULL, NULL, 1431 NULL, NULL, NULL, NULL, 1432 NULL, NULL, NULL, NULL, 1433 NULL, NULL, NULL, NULL, 1434 NULL, NULL, NULL, NULL, 1435 }, 1436 .msr = { 1437 .index = MSR_IA32_PERF_CAPABILITIES, 1438 }, 1439 }, 1440 1441 [FEAT_VMX_PROCBASED_CTLS] = { 1442 .type = MSR_FEATURE_WORD, 1443 .feat_names = { 1444 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1445 NULL, NULL, NULL, "vmx-hlt-exit", 1446 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1447 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1448 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1449 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1450 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1451 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1452 }, 1453 .msr = { 1454 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1455 } 1456 }, 1457 1458 [FEAT_VMX_SECONDARY_CTLS] = { 1459 .type = MSR_FEATURE_WORD, 1460 .feat_names = { 1461 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1462 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1463 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1464 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1465 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1466 "vmx-xsaves", NULL, NULL, NULL, 1467 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1468 NULL, NULL, NULL, NULL, 1469 }, 1470 .msr = { 1471 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1472 } 1473 }, 1474 1475 [FEAT_VMX_PINBASED_CTLS] = { 1476 .type = MSR_FEATURE_WORD, 1477 .feat_names = { 1478 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1479 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1480 NULL, NULL, NULL, NULL, 1481 NULL, NULL, NULL, NULL, 1482 NULL, NULL, NULL, NULL, 1483 NULL, NULL, NULL, NULL, 1484 NULL, NULL, NULL, NULL, 1485 NULL, NULL, NULL, NULL, 1486 }, 1487 .msr = { 1488 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1489 } 1490 }, 1491 1492 [FEAT_VMX_EXIT_CTLS] = { 1493 .type = MSR_FEATURE_WORD, 1494 /* 1495 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1496 * the LM CPUID bit. 1497 */ 1498 .feat_names = { 1499 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1500 NULL, NULL, NULL, NULL, 1501 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1502 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1503 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1504 "vmx-exit-save-efer", "vmx-exit-load-efer", 1505 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1506 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1507 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1508 }, 1509 .msr = { 1510 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1511 } 1512 }, 1513 1514 [FEAT_VMX_ENTRY_CTLS] = { 1515 .type = MSR_FEATURE_WORD, 1516 .feat_names = { 1517 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1518 NULL, NULL, NULL, NULL, 1519 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1520 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1521 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1522 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1523 NULL, NULL, NULL, NULL, 1524 NULL, NULL, NULL, NULL, 1525 }, 1526 .msr = { 1527 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1528 } 1529 }, 1530 1531 [FEAT_VMX_MISC] = { 1532 .type = MSR_FEATURE_WORD, 1533 .feat_names = { 1534 NULL, NULL, NULL, NULL, 1535 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1536 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1537 NULL, NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, NULL, NULL, 1540 NULL, NULL, NULL, NULL, 1541 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1542 }, 1543 .msr = { 1544 .index = MSR_IA32_VMX_MISC, 1545 } 1546 }, 1547 1548 [FEAT_VMX_EPT_VPID_CAPS] = { 1549 .type = MSR_FEATURE_WORD, 1550 .feat_names = { 1551 "vmx-ept-execonly", NULL, NULL, NULL, 1552 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1553 NULL, NULL, NULL, NULL, 1554 NULL, NULL, NULL, NULL, 1555 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1556 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1557 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1558 NULL, NULL, NULL, NULL, 1559 "vmx-invvpid", NULL, NULL, NULL, 1560 NULL, NULL, NULL, NULL, 1561 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1562 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1563 NULL, NULL, NULL, NULL, 1564 NULL, NULL, NULL, NULL, 1565 NULL, NULL, NULL, NULL, 1566 NULL, NULL, NULL, NULL, 1567 NULL, NULL, NULL, NULL, 1568 }, 1569 .msr = { 1570 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1571 } 1572 }, 1573 1574 [FEAT_VMX_BASIC] = { 1575 .type = MSR_FEATURE_WORD, 1576 .feat_names = { 1577 [54] = "vmx-ins-outs", 1578 [55] = "vmx-true-ctls", 1579 [56] = "vmx-any-errcode", 1580 [58] = "vmx-nested-exception", 1581 }, 1582 .msr = { 1583 .index = MSR_IA32_VMX_BASIC, 1584 }, 1585 /* Just to be safe - we don't support setting the MSEG version field. */ 1586 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1587 }, 1588 1589 [FEAT_VMX_VMFUNC] = { 1590 .type = MSR_FEATURE_WORD, 1591 .feat_names = { 1592 [0] = "vmx-eptp-switching", 1593 }, 1594 .msr = { 1595 .index = MSR_IA32_VMX_VMFUNC, 1596 } 1597 }, 1598 1599 [FEAT_14_0_ECX] = { 1600 .type = CPUID_FEATURE_WORD, 1601 .feat_names = { 1602 NULL, NULL, NULL, NULL, 1603 NULL, NULL, NULL, NULL, 1604 NULL, NULL, NULL, NULL, 1605 NULL, NULL, NULL, NULL, 1606 NULL, NULL, NULL, NULL, 1607 NULL, NULL, NULL, NULL, 1608 NULL, NULL, NULL, NULL, 1609 NULL, NULL, NULL, "intel-pt-lip", 1610 }, 1611 .cpuid = { 1612 .eax = 0x14, 1613 .needs_ecx = true, .ecx = 0, 1614 .reg = R_ECX, 1615 }, 1616 .tcg_features = TCG_14_0_ECX_FEATURES, 1617 }, 1618 1619 [FEAT_SGX_12_0_EAX] = { 1620 .type = CPUID_FEATURE_WORD, 1621 .feat_names = { 1622 "sgx1", "sgx2", NULL, NULL, 1623 NULL, NULL, NULL, NULL, 1624 NULL, NULL, NULL, "sgx-edeccssa", 1625 NULL, NULL, NULL, NULL, 1626 NULL, NULL, NULL, NULL, 1627 NULL, NULL, NULL, NULL, 1628 NULL, NULL, NULL, NULL, 1629 NULL, NULL, NULL, NULL, 1630 }, 1631 .cpuid = { 1632 .eax = 0x12, 1633 .needs_ecx = true, .ecx = 0, 1634 .reg = R_EAX, 1635 }, 1636 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1637 }, 1638 1639 [FEAT_SGX_12_0_EBX] = { 1640 .type = CPUID_FEATURE_WORD, 1641 .feat_names = { 1642 "sgx-exinfo" , NULL, NULL, NULL, 1643 NULL, NULL, NULL, NULL, 1644 NULL, NULL, NULL, NULL, 1645 NULL, NULL, NULL, NULL, 1646 NULL, NULL, NULL, NULL, 1647 NULL, NULL, NULL, NULL, 1648 NULL, NULL, NULL, NULL, 1649 NULL, NULL, NULL, NULL, 1650 }, 1651 .cpuid = { 1652 .eax = 0x12, 1653 .needs_ecx = true, .ecx = 0, 1654 .reg = R_EBX, 1655 }, 1656 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1657 }, 1658 1659 [FEAT_SGX_12_1_EAX] = { 1660 .type = CPUID_FEATURE_WORD, 1661 .feat_names = { 1662 NULL, "sgx-debug", "sgx-mode64", NULL, 1663 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1664 NULL, NULL, "sgx-aex-notify", NULL, 1665 NULL, NULL, NULL, NULL, 1666 NULL, NULL, NULL, NULL, 1667 NULL, NULL, NULL, NULL, 1668 NULL, NULL, NULL, NULL, 1669 NULL, NULL, NULL, NULL, 1670 }, 1671 .cpuid = { 1672 .eax = 0x12, 1673 .needs_ecx = true, .ecx = 1, 1674 .reg = R_EAX, 1675 }, 1676 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1677 }, 1678 }; 1679 1680 typedef struct FeatureMask { 1681 FeatureWord index; 1682 uint64_t mask; 1683 } FeatureMask; 1684 1685 typedef struct FeatureDep { 1686 FeatureMask from, to; 1687 } FeatureDep; 1688 1689 static FeatureDep feature_dependencies[] = { 1690 { 1691 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1692 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1693 }, 1694 { 1695 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1696 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1697 }, 1698 { 1699 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1700 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1701 }, 1702 { 1703 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1704 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1705 }, 1706 { 1707 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1708 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1709 }, 1710 { 1711 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1712 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1713 }, 1714 { 1715 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1716 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1717 }, 1718 { 1719 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1720 .to = { FEAT_VMX_MISC, ~0ull }, 1721 }, 1722 { 1723 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1724 .to = { FEAT_VMX_BASIC, ~0ull }, 1725 }, 1726 { 1727 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1728 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1729 }, 1730 { 1731 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1732 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1733 }, 1734 { 1735 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1736 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1737 }, 1738 { 1739 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1740 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1741 }, 1742 { 1743 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1744 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1745 }, 1746 { 1747 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1748 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1749 }, 1750 { 1751 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1752 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1753 }, 1754 { 1755 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1756 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1757 }, 1758 { 1759 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1760 .to = { FEAT_14_0_ECX, ~0ull }, 1761 }, 1762 { 1763 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1764 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1765 }, 1766 { 1767 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1768 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1769 }, 1770 { 1771 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1772 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1773 }, 1774 { 1775 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1776 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1777 }, 1778 { 1779 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1780 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1781 }, 1782 { 1783 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1784 .to = { FEAT_SVM, ~0ull }, 1785 }, 1786 { 1787 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1788 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1789 }, 1790 { 1791 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1792 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1793 }, 1794 { 1795 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1796 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1797 }, 1798 { 1799 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1800 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1801 }, 1802 { 1803 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1804 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1805 }, 1806 { 1807 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1808 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1809 }, 1810 { 1811 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1812 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1813 }, 1814 { 1815 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1816 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1817 }, 1818 { 1819 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1820 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1821 }, 1822 { 1823 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1824 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1825 }, 1826 { 1827 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1828 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1829 }, 1830 { 1831 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1832 .to = { FEAT_24_0_EBX, ~0ull }, 1833 }, 1834 }; 1835 1836 typedef struct X86RegisterInfo32 { 1837 /* Name of register */ 1838 const char *name; 1839 /* QAPI enum value register */ 1840 X86CPURegister32 qapi_enum; 1841 } X86RegisterInfo32; 1842 1843 #define REGISTER(reg) \ 1844 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1845 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1846 REGISTER(EAX), 1847 REGISTER(ECX), 1848 REGISTER(EDX), 1849 REGISTER(EBX), 1850 REGISTER(ESP), 1851 REGISTER(EBP), 1852 REGISTER(ESI), 1853 REGISTER(EDI), 1854 }; 1855 #undef REGISTER 1856 1857 /* CPUID feature bits available in XSS */ 1858 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1859 1860 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1861 [XSTATE_FP_BIT] = { 1862 /* x87 FP state component is always enabled if XSAVE is supported */ 1863 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1864 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1865 }, 1866 [XSTATE_SSE_BIT] = { 1867 /* SSE state component is always enabled if XSAVE is supported */ 1868 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1869 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1870 }, 1871 [XSTATE_YMM_BIT] = 1872 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1873 .size = sizeof(XSaveAVX) }, 1874 [XSTATE_BNDREGS_BIT] = 1875 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1876 .size = sizeof(XSaveBNDREG) }, 1877 [XSTATE_BNDCSR_BIT] = 1878 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1879 .size = sizeof(XSaveBNDCSR) }, 1880 [XSTATE_OPMASK_BIT] = 1881 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1882 .size = sizeof(XSaveOpmask) }, 1883 [XSTATE_ZMM_Hi256_BIT] = 1884 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1885 .size = sizeof(XSaveZMM_Hi256) }, 1886 [XSTATE_Hi16_ZMM_BIT] = 1887 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1888 .size = sizeof(XSaveHi16_ZMM) }, 1889 [XSTATE_PKRU_BIT] = 1890 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1891 .size = sizeof(XSavePKRU) }, 1892 [XSTATE_ARCH_LBR_BIT] = { 1893 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1894 .offset = 0 /*supervisor mode component, offset = 0 */, 1895 .size = sizeof(XSavesArchLBR) }, 1896 [XSTATE_XTILE_CFG_BIT] = { 1897 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1898 .size = sizeof(XSaveXTILECFG), 1899 }, 1900 [XSTATE_XTILE_DATA_BIT] = { 1901 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1902 .size = sizeof(XSaveXTILEDATA) 1903 }, 1904 }; 1905 1906 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1907 { 1908 uint64_t ret = x86_ext_save_areas[0].size; 1909 const ExtSaveArea *esa; 1910 uint32_t offset = 0; 1911 int i; 1912 1913 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1914 esa = &x86_ext_save_areas[i]; 1915 if ((mask >> i) & 1) { 1916 offset = compacted ? ret : esa->offset; 1917 ret = MAX(ret, offset + esa->size); 1918 } 1919 } 1920 return ret; 1921 } 1922 1923 static inline bool accel_uses_host_cpuid(void) 1924 { 1925 return kvm_enabled() || hvf_enabled(); 1926 } 1927 1928 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1929 { 1930 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1931 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1932 } 1933 1934 /* Return name of 32-bit register, from a R_* constant */ 1935 static const char *get_register_name_32(unsigned int reg) 1936 { 1937 if (reg >= CPU_NB_REGS32) { 1938 return NULL; 1939 } 1940 return x86_reg_info_32[reg].name; 1941 } 1942 1943 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1944 { 1945 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1946 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1947 } 1948 1949 /* 1950 * Returns the set of feature flags that are supported and migratable by 1951 * QEMU, for a given FeatureWord. 1952 */ 1953 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1954 { 1955 FeatureWordInfo *wi = &feature_word_info[w]; 1956 CPUX86State *env = &cpu->env; 1957 uint64_t r = 0; 1958 int i; 1959 1960 for (i = 0; i < 64; i++) { 1961 uint64_t f = 1ULL << i; 1962 1963 /* If the feature name is known, it is implicitly considered migratable, 1964 * unless it is explicitly set in unmigratable_flags */ 1965 if ((wi->migratable_flags & f) || 1966 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1967 r |= f; 1968 } 1969 } 1970 1971 /* when tsc-khz is set explicitly, invtsc is migratable */ 1972 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1973 r |= CPUID_APM_INVTSC; 1974 } 1975 1976 return r; 1977 } 1978 1979 void host_cpuid(uint32_t function, uint32_t count, 1980 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1981 { 1982 uint32_t vec[4]; 1983 1984 #ifdef __x86_64__ 1985 asm volatile("cpuid" 1986 : "=a"(vec[0]), "=b"(vec[1]), 1987 "=c"(vec[2]), "=d"(vec[3]) 1988 : "0"(function), "c"(count) : "cc"); 1989 #elif defined(__i386__) 1990 asm volatile("pusha \n\t" 1991 "cpuid \n\t" 1992 "mov %%eax, 0(%2) \n\t" 1993 "mov %%ebx, 4(%2) \n\t" 1994 "mov %%ecx, 8(%2) \n\t" 1995 "mov %%edx, 12(%2) \n\t" 1996 "popa" 1997 : : "a"(function), "c"(count), "S"(vec) 1998 : "memory", "cc"); 1999 #else 2000 abort(); 2001 #endif 2002 2003 if (eax) 2004 *eax = vec[0]; 2005 if (ebx) 2006 *ebx = vec[1]; 2007 if (ecx) 2008 *ecx = vec[2]; 2009 if (edx) 2010 *edx = vec[3]; 2011 } 2012 2013 /* CPU class name definitions: */ 2014 2015 /* Return type name for a given CPU model name 2016 * Caller is responsible for freeing the returned string. 2017 */ 2018 static char *x86_cpu_type_name(const char *model_name) 2019 { 2020 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 2021 } 2022 2023 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2024 { 2025 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2026 return object_class_by_name(typename); 2027 } 2028 2029 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2030 { 2031 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2032 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2033 return cpu_model_from_type(class_name); 2034 } 2035 2036 typedef struct X86CPUVersionDefinition { 2037 X86CPUVersion version; 2038 const char *alias; 2039 const char *note; 2040 PropValue *props; 2041 const CPUCaches *const cache_info; 2042 } X86CPUVersionDefinition; 2043 2044 /* Base definition for a CPU model */ 2045 typedef struct X86CPUDefinition { 2046 const char *name; 2047 uint32_t level; 2048 uint32_t xlevel; 2049 /* vendor is zero-terminated, 12 character ASCII string */ 2050 char vendor[CPUID_VENDOR_SZ + 1]; 2051 int family; 2052 int model; 2053 int stepping; 2054 uint8_t avx10_version; 2055 FeatureWordArray features; 2056 const char *model_id; 2057 const CPUCaches *const cache_info; 2058 /* 2059 * Definitions for alternative versions of CPU model. 2060 * List is terminated by item with version == 0. 2061 * If NULL, version 1 will be registered automatically. 2062 */ 2063 const X86CPUVersionDefinition *versions; 2064 const char *deprecation_note; 2065 } X86CPUDefinition; 2066 2067 /* Reference to a specific CPU model version */ 2068 struct X86CPUModel { 2069 /* Base CPU definition */ 2070 const X86CPUDefinition *cpudef; 2071 /* CPU model version */ 2072 X86CPUVersion version; 2073 const char *note; 2074 /* 2075 * If true, this is an alias CPU model. 2076 * This matters only for "-cpu help" and query-cpu-definitions 2077 */ 2078 bool is_alias; 2079 }; 2080 2081 /* Get full model name for CPU version */ 2082 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2083 X86CPUVersion version) 2084 { 2085 assert(version > 0); 2086 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2087 } 2088 2089 static const X86CPUVersionDefinition * 2090 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2091 { 2092 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2093 static const X86CPUVersionDefinition default_version_list[] = { 2094 { 1 }, 2095 { /* end of list */ } 2096 }; 2097 2098 return def->versions ?: default_version_list; 2099 } 2100 2101 static const CPUCaches epyc_cache_info = { 2102 .l1d_cache = &(CPUCacheInfo) { 2103 .type = DATA_CACHE, 2104 .level = 1, 2105 .size = 32 * KiB, 2106 .line_size = 64, 2107 .associativity = 8, 2108 .partitions = 1, 2109 .sets = 64, 2110 .lines_per_tag = 1, 2111 .self_init = 1, 2112 .no_invd_sharing = true, 2113 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2114 }, 2115 .l1i_cache = &(CPUCacheInfo) { 2116 .type = INSTRUCTION_CACHE, 2117 .level = 1, 2118 .size = 64 * KiB, 2119 .line_size = 64, 2120 .associativity = 4, 2121 .partitions = 1, 2122 .sets = 256, 2123 .lines_per_tag = 1, 2124 .self_init = 1, 2125 .no_invd_sharing = true, 2126 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2127 }, 2128 .l2_cache = &(CPUCacheInfo) { 2129 .type = UNIFIED_CACHE, 2130 .level = 2, 2131 .size = 512 * KiB, 2132 .line_size = 64, 2133 .associativity = 8, 2134 .partitions = 1, 2135 .sets = 1024, 2136 .lines_per_tag = 1, 2137 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2138 }, 2139 .l3_cache = &(CPUCacheInfo) { 2140 .type = UNIFIED_CACHE, 2141 .level = 3, 2142 .size = 8 * MiB, 2143 .line_size = 64, 2144 .associativity = 16, 2145 .partitions = 1, 2146 .sets = 8192, 2147 .lines_per_tag = 1, 2148 .self_init = true, 2149 .inclusive = true, 2150 .complex_indexing = true, 2151 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2152 }, 2153 }; 2154 2155 static CPUCaches epyc_v4_cache_info = { 2156 .l1d_cache = &(CPUCacheInfo) { 2157 .type = DATA_CACHE, 2158 .level = 1, 2159 .size = 32 * KiB, 2160 .line_size = 64, 2161 .associativity = 8, 2162 .partitions = 1, 2163 .sets = 64, 2164 .lines_per_tag = 1, 2165 .self_init = 1, 2166 .no_invd_sharing = true, 2167 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2168 }, 2169 .l1i_cache = &(CPUCacheInfo) { 2170 .type = INSTRUCTION_CACHE, 2171 .level = 1, 2172 .size = 64 * KiB, 2173 .line_size = 64, 2174 .associativity = 4, 2175 .partitions = 1, 2176 .sets = 256, 2177 .lines_per_tag = 1, 2178 .self_init = 1, 2179 .no_invd_sharing = true, 2180 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2181 }, 2182 .l2_cache = &(CPUCacheInfo) { 2183 .type = UNIFIED_CACHE, 2184 .level = 2, 2185 .size = 512 * KiB, 2186 .line_size = 64, 2187 .associativity = 8, 2188 .partitions = 1, 2189 .sets = 1024, 2190 .lines_per_tag = 1, 2191 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2192 }, 2193 .l3_cache = &(CPUCacheInfo) { 2194 .type = UNIFIED_CACHE, 2195 .level = 3, 2196 .size = 8 * MiB, 2197 .line_size = 64, 2198 .associativity = 16, 2199 .partitions = 1, 2200 .sets = 8192, 2201 .lines_per_tag = 1, 2202 .self_init = true, 2203 .inclusive = true, 2204 .complex_indexing = false, 2205 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2206 }, 2207 }; 2208 2209 static const CPUCaches epyc_rome_cache_info = { 2210 .l1d_cache = &(CPUCacheInfo) { 2211 .type = DATA_CACHE, 2212 .level = 1, 2213 .size = 32 * KiB, 2214 .line_size = 64, 2215 .associativity = 8, 2216 .partitions = 1, 2217 .sets = 64, 2218 .lines_per_tag = 1, 2219 .self_init = 1, 2220 .no_invd_sharing = true, 2221 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2222 }, 2223 .l1i_cache = &(CPUCacheInfo) { 2224 .type = INSTRUCTION_CACHE, 2225 .level = 1, 2226 .size = 32 * KiB, 2227 .line_size = 64, 2228 .associativity = 8, 2229 .partitions = 1, 2230 .sets = 64, 2231 .lines_per_tag = 1, 2232 .self_init = 1, 2233 .no_invd_sharing = true, 2234 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2235 }, 2236 .l2_cache = &(CPUCacheInfo) { 2237 .type = UNIFIED_CACHE, 2238 .level = 2, 2239 .size = 512 * KiB, 2240 .line_size = 64, 2241 .associativity = 8, 2242 .partitions = 1, 2243 .sets = 1024, 2244 .lines_per_tag = 1, 2245 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2246 }, 2247 .l3_cache = &(CPUCacheInfo) { 2248 .type = UNIFIED_CACHE, 2249 .level = 3, 2250 .size = 16 * MiB, 2251 .line_size = 64, 2252 .associativity = 16, 2253 .partitions = 1, 2254 .sets = 16384, 2255 .lines_per_tag = 1, 2256 .self_init = true, 2257 .inclusive = true, 2258 .complex_indexing = true, 2259 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2260 }, 2261 }; 2262 2263 static const CPUCaches epyc_rome_v3_cache_info = { 2264 .l1d_cache = &(CPUCacheInfo) { 2265 .type = DATA_CACHE, 2266 .level = 1, 2267 .size = 32 * KiB, 2268 .line_size = 64, 2269 .associativity = 8, 2270 .partitions = 1, 2271 .sets = 64, 2272 .lines_per_tag = 1, 2273 .self_init = 1, 2274 .no_invd_sharing = true, 2275 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2276 }, 2277 .l1i_cache = &(CPUCacheInfo) { 2278 .type = INSTRUCTION_CACHE, 2279 .level = 1, 2280 .size = 32 * KiB, 2281 .line_size = 64, 2282 .associativity = 8, 2283 .partitions = 1, 2284 .sets = 64, 2285 .lines_per_tag = 1, 2286 .self_init = 1, 2287 .no_invd_sharing = true, 2288 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2289 }, 2290 .l2_cache = &(CPUCacheInfo) { 2291 .type = UNIFIED_CACHE, 2292 .level = 2, 2293 .size = 512 * KiB, 2294 .line_size = 64, 2295 .associativity = 8, 2296 .partitions = 1, 2297 .sets = 1024, 2298 .lines_per_tag = 1, 2299 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2300 }, 2301 .l3_cache = &(CPUCacheInfo) { 2302 .type = UNIFIED_CACHE, 2303 .level = 3, 2304 .size = 16 * MiB, 2305 .line_size = 64, 2306 .associativity = 16, 2307 .partitions = 1, 2308 .sets = 16384, 2309 .lines_per_tag = 1, 2310 .self_init = true, 2311 .inclusive = true, 2312 .complex_indexing = false, 2313 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2314 }, 2315 }; 2316 2317 static const CPUCaches epyc_milan_cache_info = { 2318 .l1d_cache = &(CPUCacheInfo) { 2319 .type = DATA_CACHE, 2320 .level = 1, 2321 .size = 32 * KiB, 2322 .line_size = 64, 2323 .associativity = 8, 2324 .partitions = 1, 2325 .sets = 64, 2326 .lines_per_tag = 1, 2327 .self_init = 1, 2328 .no_invd_sharing = true, 2329 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2330 }, 2331 .l1i_cache = &(CPUCacheInfo) { 2332 .type = INSTRUCTION_CACHE, 2333 .level = 1, 2334 .size = 32 * KiB, 2335 .line_size = 64, 2336 .associativity = 8, 2337 .partitions = 1, 2338 .sets = 64, 2339 .lines_per_tag = 1, 2340 .self_init = 1, 2341 .no_invd_sharing = true, 2342 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2343 }, 2344 .l2_cache = &(CPUCacheInfo) { 2345 .type = UNIFIED_CACHE, 2346 .level = 2, 2347 .size = 512 * KiB, 2348 .line_size = 64, 2349 .associativity = 8, 2350 .partitions = 1, 2351 .sets = 1024, 2352 .lines_per_tag = 1, 2353 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2354 }, 2355 .l3_cache = &(CPUCacheInfo) { 2356 .type = UNIFIED_CACHE, 2357 .level = 3, 2358 .size = 32 * MiB, 2359 .line_size = 64, 2360 .associativity = 16, 2361 .partitions = 1, 2362 .sets = 32768, 2363 .lines_per_tag = 1, 2364 .self_init = true, 2365 .inclusive = true, 2366 .complex_indexing = true, 2367 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2368 }, 2369 }; 2370 2371 static const CPUCaches epyc_milan_v2_cache_info = { 2372 .l1d_cache = &(CPUCacheInfo) { 2373 .type = DATA_CACHE, 2374 .level = 1, 2375 .size = 32 * KiB, 2376 .line_size = 64, 2377 .associativity = 8, 2378 .partitions = 1, 2379 .sets = 64, 2380 .lines_per_tag = 1, 2381 .self_init = 1, 2382 .no_invd_sharing = true, 2383 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2384 }, 2385 .l1i_cache = &(CPUCacheInfo) { 2386 .type = INSTRUCTION_CACHE, 2387 .level = 1, 2388 .size = 32 * KiB, 2389 .line_size = 64, 2390 .associativity = 8, 2391 .partitions = 1, 2392 .sets = 64, 2393 .lines_per_tag = 1, 2394 .self_init = 1, 2395 .no_invd_sharing = true, 2396 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2397 }, 2398 .l2_cache = &(CPUCacheInfo) { 2399 .type = UNIFIED_CACHE, 2400 .level = 2, 2401 .size = 512 * KiB, 2402 .line_size = 64, 2403 .associativity = 8, 2404 .partitions = 1, 2405 .sets = 1024, 2406 .lines_per_tag = 1, 2407 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2408 }, 2409 .l3_cache = &(CPUCacheInfo) { 2410 .type = UNIFIED_CACHE, 2411 .level = 3, 2412 .size = 32 * MiB, 2413 .line_size = 64, 2414 .associativity = 16, 2415 .partitions = 1, 2416 .sets = 32768, 2417 .lines_per_tag = 1, 2418 .self_init = true, 2419 .inclusive = true, 2420 .complex_indexing = false, 2421 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2422 }, 2423 }; 2424 2425 static const CPUCaches epyc_genoa_cache_info = { 2426 .l1d_cache = &(CPUCacheInfo) { 2427 .type = DATA_CACHE, 2428 .level = 1, 2429 .size = 32 * KiB, 2430 .line_size = 64, 2431 .associativity = 8, 2432 .partitions = 1, 2433 .sets = 64, 2434 .lines_per_tag = 1, 2435 .self_init = 1, 2436 .no_invd_sharing = true, 2437 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2438 }, 2439 .l1i_cache = &(CPUCacheInfo) { 2440 .type = INSTRUCTION_CACHE, 2441 .level = 1, 2442 .size = 32 * KiB, 2443 .line_size = 64, 2444 .associativity = 8, 2445 .partitions = 1, 2446 .sets = 64, 2447 .lines_per_tag = 1, 2448 .self_init = 1, 2449 .no_invd_sharing = true, 2450 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2451 }, 2452 .l2_cache = &(CPUCacheInfo) { 2453 .type = UNIFIED_CACHE, 2454 .level = 2, 2455 .size = 1 * MiB, 2456 .line_size = 64, 2457 .associativity = 8, 2458 .partitions = 1, 2459 .sets = 2048, 2460 .lines_per_tag = 1, 2461 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2462 }, 2463 .l3_cache = &(CPUCacheInfo) { 2464 .type = UNIFIED_CACHE, 2465 .level = 3, 2466 .size = 32 * MiB, 2467 .line_size = 64, 2468 .associativity = 16, 2469 .partitions = 1, 2470 .sets = 32768, 2471 .lines_per_tag = 1, 2472 .self_init = true, 2473 .inclusive = true, 2474 .complex_indexing = false, 2475 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2476 }, 2477 }; 2478 2479 /* The following VMX features are not supported by KVM and are left out in the 2480 * CPU definitions: 2481 * 2482 * Dual-monitor support (all processors) 2483 * Entry to SMM 2484 * Deactivate dual-monitor treatment 2485 * Number of CR3-target values 2486 * Shutdown activity state 2487 * Wait-for-SIPI activity state 2488 * PAUSE-loop exiting (Westmere and newer) 2489 * EPT-violation #VE (Broadwell and newer) 2490 * Inject event with insn length=0 (Skylake and newer) 2491 * Conceal non-root operation from PT 2492 * Conceal VM exits from PT 2493 * Conceal VM entries from PT 2494 * Enable ENCLS exiting 2495 * Mode-based execute control (XS/XU) 2496 * TSC scaling (Skylake Server and newer) 2497 * GPA translation for PT (IceLake and newer) 2498 * User wait and pause 2499 * ENCLV exiting 2500 * Load IA32_RTIT_CTL 2501 * Clear IA32_RTIT_CTL 2502 * Advanced VM-exit information for EPT violations 2503 * Sub-page write permissions 2504 * PT in VMX operation 2505 */ 2506 2507 static const X86CPUDefinition builtin_x86_defs[] = { 2508 { 2509 .name = "qemu64", 2510 .level = 0xd, 2511 .vendor = CPUID_VENDOR_AMD, 2512 .family = 15, 2513 .model = 107, 2514 .stepping = 1, 2515 .features[FEAT_1_EDX] = 2516 PPRO_FEATURES | 2517 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2518 CPUID_PSE36, 2519 .features[FEAT_1_ECX] = 2520 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2521 .features[FEAT_8000_0001_EDX] = 2522 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2523 .features[FEAT_8000_0001_ECX] = 2524 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2525 .xlevel = 0x8000000A, 2526 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2527 }, 2528 { 2529 .name = "phenom", 2530 .level = 5, 2531 .vendor = CPUID_VENDOR_AMD, 2532 .family = 16, 2533 .model = 2, 2534 .stepping = 3, 2535 /* Missing: CPUID_HT */ 2536 .features[FEAT_1_EDX] = 2537 PPRO_FEATURES | 2538 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2539 CPUID_PSE36 | CPUID_VME, 2540 .features[FEAT_1_ECX] = 2541 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2542 CPUID_EXT_POPCNT, 2543 .features[FEAT_8000_0001_EDX] = 2544 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2545 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2546 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2547 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2548 CPUID_EXT3_CR8LEG, 2549 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2550 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2551 .features[FEAT_8000_0001_ECX] = 2552 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2553 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2554 /* Missing: CPUID_SVM_LBRV */ 2555 .features[FEAT_SVM] = 2556 CPUID_SVM_NPT, 2557 .xlevel = 0x8000001A, 2558 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2559 }, 2560 { 2561 .name = "core2duo", 2562 .level = 10, 2563 .vendor = CPUID_VENDOR_INTEL, 2564 .family = 6, 2565 .model = 15, 2566 .stepping = 11, 2567 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2568 .features[FEAT_1_EDX] = 2569 PPRO_FEATURES | 2570 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2571 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2572 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2573 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2574 .features[FEAT_1_ECX] = 2575 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2576 CPUID_EXT_CX16, 2577 .features[FEAT_8000_0001_EDX] = 2578 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2579 .features[FEAT_8000_0001_ECX] = 2580 CPUID_EXT3_LAHF_LM, 2581 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2582 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2583 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2584 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2585 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2586 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2587 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2588 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2589 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2590 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2591 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2592 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2593 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2594 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2595 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2596 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2597 .features[FEAT_VMX_SECONDARY_CTLS] = 2598 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2599 .xlevel = 0x80000008, 2600 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2601 }, 2602 { 2603 .name = "kvm64", 2604 .level = 0xd, 2605 .vendor = CPUID_VENDOR_INTEL, 2606 .family = 15, 2607 .model = 6, 2608 .stepping = 1, 2609 /* Missing: CPUID_HT */ 2610 .features[FEAT_1_EDX] = 2611 PPRO_FEATURES | CPUID_VME | 2612 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2613 CPUID_PSE36, 2614 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2615 .features[FEAT_1_ECX] = 2616 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2617 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2618 .features[FEAT_8000_0001_EDX] = 2619 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2620 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2621 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2622 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2623 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2624 .features[FEAT_8000_0001_ECX] = 2625 0, 2626 /* VMX features from Cedar Mill/Prescott */ 2627 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2628 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2629 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2630 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2631 VMX_PIN_BASED_NMI_EXITING, 2632 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2633 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2634 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2635 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2636 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2637 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2638 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2639 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2640 .xlevel = 0x80000008, 2641 .model_id = "Common KVM processor" 2642 }, 2643 { 2644 .name = "qemu32", 2645 .level = 4, 2646 .vendor = CPUID_VENDOR_INTEL, 2647 .family = 6, 2648 .model = 6, 2649 .stepping = 3, 2650 .features[FEAT_1_EDX] = 2651 PPRO_FEATURES, 2652 .features[FEAT_1_ECX] = 2653 CPUID_EXT_SSE3, 2654 .xlevel = 0x80000004, 2655 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2656 }, 2657 { 2658 .name = "kvm32", 2659 .level = 5, 2660 .vendor = CPUID_VENDOR_INTEL, 2661 .family = 15, 2662 .model = 6, 2663 .stepping = 1, 2664 .features[FEAT_1_EDX] = 2665 PPRO_FEATURES | CPUID_VME | 2666 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2667 .features[FEAT_1_ECX] = 2668 CPUID_EXT_SSE3, 2669 .features[FEAT_8000_0001_ECX] = 2670 0, 2671 /* VMX features from Yonah */ 2672 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2673 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2674 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2675 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2676 VMX_PIN_BASED_NMI_EXITING, 2677 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2678 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2679 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2680 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2681 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2682 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2683 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2684 .xlevel = 0x80000008, 2685 .model_id = "Common 32-bit KVM processor" 2686 }, 2687 { 2688 .name = "coreduo", 2689 .level = 10, 2690 .vendor = CPUID_VENDOR_INTEL, 2691 .family = 6, 2692 .model = 14, 2693 .stepping = 8, 2694 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2695 .features[FEAT_1_EDX] = 2696 PPRO_FEATURES | CPUID_VME | 2697 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2698 CPUID_SS, 2699 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2700 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2701 .features[FEAT_1_ECX] = 2702 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2703 .features[FEAT_8000_0001_EDX] = 2704 CPUID_EXT2_NX, 2705 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2706 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2707 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2708 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2709 VMX_PIN_BASED_NMI_EXITING, 2710 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2711 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2712 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2713 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2714 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2715 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2716 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2717 .xlevel = 0x80000008, 2718 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2719 }, 2720 { 2721 .name = "486", 2722 .level = 1, 2723 .vendor = CPUID_VENDOR_INTEL, 2724 .family = 4, 2725 .model = 8, 2726 .stepping = 0, 2727 .features[FEAT_1_EDX] = 2728 I486_FEATURES, 2729 .xlevel = 0, 2730 .model_id = "", 2731 }, 2732 { 2733 .name = "pentium", 2734 .level = 1, 2735 .vendor = CPUID_VENDOR_INTEL, 2736 .family = 5, 2737 .model = 4, 2738 .stepping = 3, 2739 .features[FEAT_1_EDX] = 2740 PENTIUM_FEATURES, 2741 .xlevel = 0, 2742 .model_id = "", 2743 }, 2744 { 2745 .name = "pentium2", 2746 .level = 2, 2747 .vendor = CPUID_VENDOR_INTEL, 2748 .family = 6, 2749 .model = 5, 2750 .stepping = 2, 2751 .features[FEAT_1_EDX] = 2752 PENTIUM2_FEATURES, 2753 .xlevel = 0, 2754 .model_id = "", 2755 }, 2756 { 2757 .name = "pentium3", 2758 .level = 3, 2759 .vendor = CPUID_VENDOR_INTEL, 2760 .family = 6, 2761 .model = 7, 2762 .stepping = 3, 2763 .features[FEAT_1_EDX] = 2764 PENTIUM3_FEATURES, 2765 .xlevel = 0, 2766 .model_id = "", 2767 }, 2768 { 2769 .name = "athlon", 2770 .level = 2, 2771 .vendor = CPUID_VENDOR_AMD, 2772 .family = 6, 2773 .model = 2, 2774 .stepping = 3, 2775 .features[FEAT_1_EDX] = 2776 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2777 CPUID_MCA, 2778 .features[FEAT_8000_0001_EDX] = 2779 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2780 .xlevel = 0x80000008, 2781 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2782 }, 2783 { 2784 .name = "n270", 2785 .level = 10, 2786 .vendor = CPUID_VENDOR_INTEL, 2787 .family = 6, 2788 .model = 28, 2789 .stepping = 2, 2790 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2791 .features[FEAT_1_EDX] = 2792 PPRO_FEATURES | 2793 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2794 CPUID_ACPI | CPUID_SS, 2795 /* Some CPUs got no CPUID_SEP */ 2796 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2797 * CPUID_EXT_XTPR */ 2798 .features[FEAT_1_ECX] = 2799 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2800 CPUID_EXT_MOVBE, 2801 .features[FEAT_8000_0001_EDX] = 2802 CPUID_EXT2_NX, 2803 .features[FEAT_8000_0001_ECX] = 2804 CPUID_EXT3_LAHF_LM, 2805 .xlevel = 0x80000008, 2806 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2807 }, 2808 { 2809 .name = "Conroe", 2810 .level = 10, 2811 .vendor = CPUID_VENDOR_INTEL, 2812 .family = 6, 2813 .model = 15, 2814 .stepping = 3, 2815 .features[FEAT_1_EDX] = 2816 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2817 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2818 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2819 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2820 CPUID_DE | CPUID_FP87, 2821 .features[FEAT_1_ECX] = 2822 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2823 .features[FEAT_8000_0001_EDX] = 2824 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2825 .features[FEAT_8000_0001_ECX] = 2826 CPUID_EXT3_LAHF_LM, 2827 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2828 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2829 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2830 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2831 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2832 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2833 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2834 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2835 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2836 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2837 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2838 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2839 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2840 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2841 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2842 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2843 .features[FEAT_VMX_SECONDARY_CTLS] = 2844 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2845 .xlevel = 0x80000008, 2846 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2847 }, 2848 { 2849 .name = "Penryn", 2850 .level = 10, 2851 .vendor = CPUID_VENDOR_INTEL, 2852 .family = 6, 2853 .model = 23, 2854 .stepping = 3, 2855 .features[FEAT_1_EDX] = 2856 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2857 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2858 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2859 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2860 CPUID_DE | CPUID_FP87, 2861 .features[FEAT_1_ECX] = 2862 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2863 CPUID_EXT_SSE3, 2864 .features[FEAT_8000_0001_EDX] = 2865 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2866 .features[FEAT_8000_0001_ECX] = 2867 CPUID_EXT3_LAHF_LM, 2868 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2869 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2870 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2871 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2872 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2873 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2874 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2875 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2876 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2877 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2878 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2879 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2880 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2881 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2882 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2883 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2884 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2885 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2886 .features[FEAT_VMX_SECONDARY_CTLS] = 2887 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2888 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2889 .xlevel = 0x80000008, 2890 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2891 }, 2892 { 2893 .name = "Nehalem", 2894 .level = 11, 2895 .vendor = CPUID_VENDOR_INTEL, 2896 .family = 6, 2897 .model = 26, 2898 .stepping = 3, 2899 .features[FEAT_1_EDX] = 2900 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2901 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2902 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2903 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2904 CPUID_DE | CPUID_FP87, 2905 .features[FEAT_1_ECX] = 2906 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2907 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2908 .features[FEAT_8000_0001_EDX] = 2909 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2910 .features[FEAT_8000_0001_ECX] = 2911 CPUID_EXT3_LAHF_LM, 2912 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2913 MSR_VMX_BASIC_TRUE_CTLS, 2914 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2915 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2916 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2917 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2918 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2919 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2920 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2921 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2922 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2923 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2924 .features[FEAT_VMX_EXIT_CTLS] = 2925 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2926 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2927 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2928 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2929 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2930 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2931 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2932 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2933 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2934 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2935 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2936 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2937 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2938 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2939 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2940 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2941 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2942 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2943 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2944 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2945 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2946 .features[FEAT_VMX_SECONDARY_CTLS] = 2947 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2948 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2949 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2950 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2951 VMX_SECONDARY_EXEC_ENABLE_VPID, 2952 .xlevel = 0x80000008, 2953 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2954 .versions = (X86CPUVersionDefinition[]) { 2955 { .version = 1 }, 2956 { 2957 .version = 2, 2958 .alias = "Nehalem-IBRS", 2959 .props = (PropValue[]) { 2960 { "spec-ctrl", "on" }, 2961 { "model-id", 2962 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2963 { /* end of list */ } 2964 } 2965 }, 2966 { /* end of list */ } 2967 } 2968 }, 2969 { 2970 .name = "Westmere", 2971 .level = 11, 2972 .vendor = CPUID_VENDOR_INTEL, 2973 .family = 6, 2974 .model = 44, 2975 .stepping = 1, 2976 .features[FEAT_1_EDX] = 2977 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2978 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2979 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2980 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2981 CPUID_DE | CPUID_FP87, 2982 .features[FEAT_1_ECX] = 2983 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2984 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2985 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2986 .features[FEAT_8000_0001_EDX] = 2987 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2988 .features[FEAT_8000_0001_ECX] = 2989 CPUID_EXT3_LAHF_LM, 2990 .features[FEAT_6_EAX] = 2991 CPUID_6_EAX_ARAT, 2992 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2993 MSR_VMX_BASIC_TRUE_CTLS, 2994 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2995 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2996 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2997 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2998 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2999 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3000 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3001 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3002 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3003 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3004 .features[FEAT_VMX_EXIT_CTLS] = 3005 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3006 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3007 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3008 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3009 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3010 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3011 MSR_VMX_MISC_STORE_LMA, 3012 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3013 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3014 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3015 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3016 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3017 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3018 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3019 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3020 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3021 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3022 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3023 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3024 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3025 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3026 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3027 .features[FEAT_VMX_SECONDARY_CTLS] = 3028 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3029 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3030 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3031 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3032 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3033 .xlevel = 0x80000008, 3034 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3035 .versions = (X86CPUVersionDefinition[]) { 3036 { .version = 1 }, 3037 { 3038 .version = 2, 3039 .alias = "Westmere-IBRS", 3040 .props = (PropValue[]) { 3041 { "spec-ctrl", "on" }, 3042 { "model-id", 3043 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3044 { /* end of list */ } 3045 } 3046 }, 3047 { /* end of list */ } 3048 } 3049 }, 3050 { 3051 .name = "SandyBridge", 3052 .level = 0xd, 3053 .vendor = CPUID_VENDOR_INTEL, 3054 .family = 6, 3055 .model = 42, 3056 .stepping = 1, 3057 .features[FEAT_1_EDX] = 3058 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3059 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3060 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3061 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3062 CPUID_DE | CPUID_FP87, 3063 .features[FEAT_1_ECX] = 3064 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3065 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3066 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3067 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3068 CPUID_EXT_SSE3, 3069 .features[FEAT_8000_0001_EDX] = 3070 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3071 CPUID_EXT2_SYSCALL, 3072 .features[FEAT_8000_0001_ECX] = 3073 CPUID_EXT3_LAHF_LM, 3074 .features[FEAT_XSAVE] = 3075 CPUID_XSAVE_XSAVEOPT, 3076 .features[FEAT_6_EAX] = 3077 CPUID_6_EAX_ARAT, 3078 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3079 MSR_VMX_BASIC_TRUE_CTLS, 3080 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3081 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3082 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3083 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3084 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3085 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3086 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3087 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3088 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3089 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3090 .features[FEAT_VMX_EXIT_CTLS] = 3091 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3092 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3093 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3094 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3095 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3096 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3097 MSR_VMX_MISC_STORE_LMA, 3098 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3099 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3100 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3101 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3102 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3103 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3104 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3105 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3106 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3107 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3108 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3109 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3110 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3111 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3112 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3113 .features[FEAT_VMX_SECONDARY_CTLS] = 3114 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3115 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3116 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3117 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3118 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3119 .xlevel = 0x80000008, 3120 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3121 .versions = (X86CPUVersionDefinition[]) { 3122 { .version = 1 }, 3123 { 3124 .version = 2, 3125 .alias = "SandyBridge-IBRS", 3126 .props = (PropValue[]) { 3127 { "spec-ctrl", "on" }, 3128 { "model-id", 3129 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3130 { /* end of list */ } 3131 } 3132 }, 3133 { /* end of list */ } 3134 } 3135 }, 3136 { 3137 .name = "IvyBridge", 3138 .level = 0xd, 3139 .vendor = CPUID_VENDOR_INTEL, 3140 .family = 6, 3141 .model = 58, 3142 .stepping = 9, 3143 .features[FEAT_1_EDX] = 3144 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3145 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3146 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3147 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3148 CPUID_DE | CPUID_FP87, 3149 .features[FEAT_1_ECX] = 3150 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3151 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3152 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3153 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3154 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3155 .features[FEAT_7_0_EBX] = 3156 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3157 CPUID_7_0_EBX_ERMS, 3158 .features[FEAT_8000_0001_EDX] = 3159 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3160 CPUID_EXT2_SYSCALL, 3161 .features[FEAT_8000_0001_ECX] = 3162 CPUID_EXT3_LAHF_LM, 3163 .features[FEAT_XSAVE] = 3164 CPUID_XSAVE_XSAVEOPT, 3165 .features[FEAT_6_EAX] = 3166 CPUID_6_EAX_ARAT, 3167 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3168 MSR_VMX_BASIC_TRUE_CTLS, 3169 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3170 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3171 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3172 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3173 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3174 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3175 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3176 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3177 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3178 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3179 .features[FEAT_VMX_EXIT_CTLS] = 3180 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3181 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3182 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3183 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3184 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3185 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3186 MSR_VMX_MISC_STORE_LMA, 3187 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3188 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3189 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3190 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3191 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3192 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3193 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3194 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3195 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3196 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3197 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3198 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3199 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3200 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3201 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3202 .features[FEAT_VMX_SECONDARY_CTLS] = 3203 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3204 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3205 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3206 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3207 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3208 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3209 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3210 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3211 .xlevel = 0x80000008, 3212 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3213 .versions = (X86CPUVersionDefinition[]) { 3214 { .version = 1 }, 3215 { 3216 .version = 2, 3217 .alias = "IvyBridge-IBRS", 3218 .props = (PropValue[]) { 3219 { "spec-ctrl", "on" }, 3220 { "model-id", 3221 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3222 { /* end of list */ } 3223 } 3224 }, 3225 { /* end of list */ } 3226 } 3227 }, 3228 { 3229 .name = "Haswell", 3230 .level = 0xd, 3231 .vendor = CPUID_VENDOR_INTEL, 3232 .family = 6, 3233 .model = 60, 3234 .stepping = 4, 3235 .features[FEAT_1_EDX] = 3236 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3237 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3238 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3239 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3240 CPUID_DE | CPUID_FP87, 3241 .features[FEAT_1_ECX] = 3242 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3243 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3244 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3245 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3246 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3247 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3248 .features[FEAT_8000_0001_EDX] = 3249 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3250 CPUID_EXT2_SYSCALL, 3251 .features[FEAT_8000_0001_ECX] = 3252 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3253 .features[FEAT_7_0_EBX] = 3254 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3255 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3256 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3257 CPUID_7_0_EBX_RTM, 3258 .features[FEAT_XSAVE] = 3259 CPUID_XSAVE_XSAVEOPT, 3260 .features[FEAT_6_EAX] = 3261 CPUID_6_EAX_ARAT, 3262 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3263 MSR_VMX_BASIC_TRUE_CTLS, 3264 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3265 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3266 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3267 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3268 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3269 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3270 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3271 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3272 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3273 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3274 .features[FEAT_VMX_EXIT_CTLS] = 3275 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3276 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3277 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3278 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3279 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3280 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3281 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3282 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3283 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3284 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3285 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3286 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3287 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3288 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3289 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3290 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3291 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3292 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3293 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3294 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3295 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3296 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3297 .features[FEAT_VMX_SECONDARY_CTLS] = 3298 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3299 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3300 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3301 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3302 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3303 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3304 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3305 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3306 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3307 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3308 .xlevel = 0x80000008, 3309 .model_id = "Intel Core Processor (Haswell)", 3310 .versions = (X86CPUVersionDefinition[]) { 3311 { .version = 1 }, 3312 { 3313 .version = 2, 3314 .alias = "Haswell-noTSX", 3315 .props = (PropValue[]) { 3316 { "hle", "off" }, 3317 { "rtm", "off" }, 3318 { "stepping", "1" }, 3319 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3320 { /* end of list */ } 3321 }, 3322 }, 3323 { 3324 .version = 3, 3325 .alias = "Haswell-IBRS", 3326 .props = (PropValue[]) { 3327 /* Restore TSX features removed by -v2 above */ 3328 { "hle", "on" }, 3329 { "rtm", "on" }, 3330 /* 3331 * Haswell and Haswell-IBRS had stepping=4 in 3332 * QEMU 4.0 and older 3333 */ 3334 { "stepping", "4" }, 3335 { "spec-ctrl", "on" }, 3336 { "model-id", 3337 "Intel Core Processor (Haswell, IBRS)" }, 3338 { /* end of list */ } 3339 } 3340 }, 3341 { 3342 .version = 4, 3343 .alias = "Haswell-noTSX-IBRS", 3344 .props = (PropValue[]) { 3345 { "hle", "off" }, 3346 { "rtm", "off" }, 3347 /* spec-ctrl was already enabled by -v3 above */ 3348 { "stepping", "1" }, 3349 { "model-id", 3350 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3351 { /* end of list */ } 3352 } 3353 }, 3354 { /* end of list */ } 3355 } 3356 }, 3357 { 3358 .name = "Broadwell", 3359 .level = 0xd, 3360 .vendor = CPUID_VENDOR_INTEL, 3361 .family = 6, 3362 .model = 61, 3363 .stepping = 2, 3364 .features[FEAT_1_EDX] = 3365 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3366 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3367 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3368 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3369 CPUID_DE | CPUID_FP87, 3370 .features[FEAT_1_ECX] = 3371 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3372 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3373 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3374 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3375 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3376 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3377 .features[FEAT_8000_0001_EDX] = 3378 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3379 CPUID_EXT2_SYSCALL, 3380 .features[FEAT_8000_0001_ECX] = 3381 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3382 .features[FEAT_7_0_EBX] = 3383 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3384 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3385 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3386 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3387 CPUID_7_0_EBX_SMAP, 3388 .features[FEAT_XSAVE] = 3389 CPUID_XSAVE_XSAVEOPT, 3390 .features[FEAT_6_EAX] = 3391 CPUID_6_EAX_ARAT, 3392 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3393 MSR_VMX_BASIC_TRUE_CTLS, 3394 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3395 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3396 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3397 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3398 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3399 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3400 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3401 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3402 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3403 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3404 .features[FEAT_VMX_EXIT_CTLS] = 3405 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3406 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3407 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3408 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3409 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3410 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3411 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3412 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3413 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3414 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3415 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3416 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3417 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3418 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3419 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3420 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3421 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3422 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3423 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3424 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3425 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3426 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3427 .features[FEAT_VMX_SECONDARY_CTLS] = 3428 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3429 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3430 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3431 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3432 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3433 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3434 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3435 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3436 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3437 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3438 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3439 .xlevel = 0x80000008, 3440 .model_id = "Intel Core Processor (Broadwell)", 3441 .versions = (X86CPUVersionDefinition[]) { 3442 { .version = 1 }, 3443 { 3444 .version = 2, 3445 .alias = "Broadwell-noTSX", 3446 .props = (PropValue[]) { 3447 { "hle", "off" }, 3448 { "rtm", "off" }, 3449 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3450 { /* end of list */ } 3451 }, 3452 }, 3453 { 3454 .version = 3, 3455 .alias = "Broadwell-IBRS", 3456 .props = (PropValue[]) { 3457 /* Restore TSX features removed by -v2 above */ 3458 { "hle", "on" }, 3459 { "rtm", "on" }, 3460 { "spec-ctrl", "on" }, 3461 { "model-id", 3462 "Intel Core Processor (Broadwell, IBRS)" }, 3463 { /* end of list */ } 3464 } 3465 }, 3466 { 3467 .version = 4, 3468 .alias = "Broadwell-noTSX-IBRS", 3469 .props = (PropValue[]) { 3470 { "hle", "off" }, 3471 { "rtm", "off" }, 3472 /* spec-ctrl was already enabled by -v3 above */ 3473 { "model-id", 3474 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3475 { /* end of list */ } 3476 } 3477 }, 3478 { /* end of list */ } 3479 } 3480 }, 3481 { 3482 .name = "Skylake-Client", 3483 .level = 0xd, 3484 .vendor = CPUID_VENDOR_INTEL, 3485 .family = 6, 3486 .model = 94, 3487 .stepping = 3, 3488 .features[FEAT_1_EDX] = 3489 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3490 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3491 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3492 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3493 CPUID_DE | CPUID_FP87, 3494 .features[FEAT_1_ECX] = 3495 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3496 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3497 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3498 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3499 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3500 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3501 .features[FEAT_8000_0001_EDX] = 3502 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3503 CPUID_EXT2_SYSCALL, 3504 .features[FEAT_8000_0001_ECX] = 3505 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3506 .features[FEAT_7_0_EBX] = 3507 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3508 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3509 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3510 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3511 CPUID_7_0_EBX_SMAP, 3512 /* XSAVES is added in version 4 */ 3513 .features[FEAT_XSAVE] = 3514 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3515 CPUID_XSAVE_XGETBV1, 3516 .features[FEAT_6_EAX] = 3517 CPUID_6_EAX_ARAT, 3518 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3519 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3520 MSR_VMX_BASIC_TRUE_CTLS, 3521 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3522 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3523 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3524 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3525 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3526 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3527 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3528 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3529 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3530 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3531 .features[FEAT_VMX_EXIT_CTLS] = 3532 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3533 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3534 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3535 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3536 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3537 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3538 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3539 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3540 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3541 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3542 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3543 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3544 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3545 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3546 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3547 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3548 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3549 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3550 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3551 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3552 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3553 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3554 .features[FEAT_VMX_SECONDARY_CTLS] = 3555 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3556 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3557 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3558 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3559 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3560 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3561 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3562 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3563 .xlevel = 0x80000008, 3564 .model_id = "Intel Core Processor (Skylake)", 3565 .versions = (X86CPUVersionDefinition[]) { 3566 { .version = 1 }, 3567 { 3568 .version = 2, 3569 .alias = "Skylake-Client-IBRS", 3570 .props = (PropValue[]) { 3571 { "spec-ctrl", "on" }, 3572 { "model-id", 3573 "Intel Core Processor (Skylake, IBRS)" }, 3574 { /* end of list */ } 3575 } 3576 }, 3577 { 3578 .version = 3, 3579 .alias = "Skylake-Client-noTSX-IBRS", 3580 .props = (PropValue[]) { 3581 { "hle", "off" }, 3582 { "rtm", "off" }, 3583 { "model-id", 3584 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3585 { /* end of list */ } 3586 } 3587 }, 3588 { 3589 .version = 4, 3590 .note = "IBRS, XSAVES, no TSX", 3591 .props = (PropValue[]) { 3592 { "xsaves", "on" }, 3593 { "vmx-xsaves", "on" }, 3594 { /* end of list */ } 3595 } 3596 }, 3597 { /* end of list */ } 3598 } 3599 }, 3600 { 3601 .name = "Skylake-Server", 3602 .level = 0xd, 3603 .vendor = CPUID_VENDOR_INTEL, 3604 .family = 6, 3605 .model = 85, 3606 .stepping = 4, 3607 .features[FEAT_1_EDX] = 3608 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3609 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3610 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3611 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3612 CPUID_DE | CPUID_FP87, 3613 .features[FEAT_1_ECX] = 3614 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3615 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3616 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3617 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3618 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3619 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3620 .features[FEAT_8000_0001_EDX] = 3621 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3622 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3623 .features[FEAT_8000_0001_ECX] = 3624 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3625 .features[FEAT_7_0_EBX] = 3626 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3627 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3628 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3629 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3630 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3631 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3632 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3633 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3634 .features[FEAT_7_0_ECX] = 3635 CPUID_7_0_ECX_PKU, 3636 /* XSAVES is added in version 5 */ 3637 .features[FEAT_XSAVE] = 3638 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3639 CPUID_XSAVE_XGETBV1, 3640 .features[FEAT_6_EAX] = 3641 CPUID_6_EAX_ARAT, 3642 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3643 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3644 MSR_VMX_BASIC_TRUE_CTLS, 3645 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3646 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3647 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3648 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3649 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3650 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3651 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3652 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3653 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3654 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3655 .features[FEAT_VMX_EXIT_CTLS] = 3656 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3657 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3658 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3659 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3660 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3661 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3662 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3663 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3664 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3665 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3666 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3667 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3668 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3669 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3670 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3671 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3672 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3673 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3674 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3675 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3676 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3677 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3678 .features[FEAT_VMX_SECONDARY_CTLS] = 3679 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3680 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3681 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3682 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3683 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3684 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3685 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3686 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3687 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3688 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3689 .xlevel = 0x80000008, 3690 .model_id = "Intel Xeon Processor (Skylake)", 3691 .versions = (X86CPUVersionDefinition[]) { 3692 { .version = 1 }, 3693 { 3694 .version = 2, 3695 .alias = "Skylake-Server-IBRS", 3696 .props = (PropValue[]) { 3697 /* clflushopt was not added to Skylake-Server-IBRS */ 3698 /* TODO: add -v3 including clflushopt */ 3699 { "clflushopt", "off" }, 3700 { "spec-ctrl", "on" }, 3701 { "model-id", 3702 "Intel Xeon Processor (Skylake, IBRS)" }, 3703 { /* end of list */ } 3704 } 3705 }, 3706 { 3707 .version = 3, 3708 .alias = "Skylake-Server-noTSX-IBRS", 3709 .props = (PropValue[]) { 3710 { "hle", "off" }, 3711 { "rtm", "off" }, 3712 { "model-id", 3713 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3714 { /* end of list */ } 3715 } 3716 }, 3717 { 3718 .version = 4, 3719 .note = "IBRS, EPT switching, no TSX", 3720 .props = (PropValue[]) { 3721 { "vmx-eptp-switching", "on" }, 3722 { /* end of list */ } 3723 } 3724 }, 3725 { 3726 .version = 5, 3727 .note = "IBRS, XSAVES, EPT switching, no TSX", 3728 .props = (PropValue[]) { 3729 { "xsaves", "on" }, 3730 { "vmx-xsaves", "on" }, 3731 { /* end of list */ } 3732 } 3733 }, 3734 { /* end of list */ } 3735 } 3736 }, 3737 { 3738 .name = "Cascadelake-Server", 3739 .level = 0xd, 3740 .vendor = CPUID_VENDOR_INTEL, 3741 .family = 6, 3742 .model = 85, 3743 .stepping = 6, 3744 .features[FEAT_1_EDX] = 3745 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3746 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3747 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3748 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3749 CPUID_DE | CPUID_FP87, 3750 .features[FEAT_1_ECX] = 3751 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3752 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3753 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3754 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3755 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3756 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3757 .features[FEAT_8000_0001_EDX] = 3758 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3759 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3760 .features[FEAT_8000_0001_ECX] = 3761 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3762 .features[FEAT_7_0_EBX] = 3763 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3764 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3765 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3766 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3767 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3768 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3769 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3770 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3771 .features[FEAT_7_0_ECX] = 3772 CPUID_7_0_ECX_PKU | 3773 CPUID_7_0_ECX_AVX512VNNI, 3774 .features[FEAT_7_0_EDX] = 3775 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3776 /* XSAVES is added in version 5 */ 3777 .features[FEAT_XSAVE] = 3778 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3779 CPUID_XSAVE_XGETBV1, 3780 .features[FEAT_6_EAX] = 3781 CPUID_6_EAX_ARAT, 3782 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3783 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3784 MSR_VMX_BASIC_TRUE_CTLS, 3785 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3786 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3787 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3788 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3789 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3790 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3791 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3792 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3793 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3794 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3795 .features[FEAT_VMX_EXIT_CTLS] = 3796 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3797 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3798 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3799 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3800 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3801 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3802 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3803 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3804 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3805 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3806 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3807 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3808 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3809 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3810 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3811 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3812 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3813 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3814 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3815 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3816 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3817 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3818 .features[FEAT_VMX_SECONDARY_CTLS] = 3819 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3820 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3821 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3822 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3823 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3824 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3825 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3826 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3827 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3828 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3829 .xlevel = 0x80000008, 3830 .model_id = "Intel Xeon Processor (Cascadelake)", 3831 .versions = (X86CPUVersionDefinition[]) { 3832 { .version = 1 }, 3833 { .version = 2, 3834 .note = "ARCH_CAPABILITIES", 3835 .props = (PropValue[]) { 3836 { "arch-capabilities", "on" }, 3837 { "rdctl-no", "on" }, 3838 { "ibrs-all", "on" }, 3839 { "skip-l1dfl-vmentry", "on" }, 3840 { "mds-no", "on" }, 3841 { /* end of list */ } 3842 }, 3843 }, 3844 { .version = 3, 3845 .alias = "Cascadelake-Server-noTSX", 3846 .note = "ARCH_CAPABILITIES, no TSX", 3847 .props = (PropValue[]) { 3848 { "hle", "off" }, 3849 { "rtm", "off" }, 3850 { /* end of list */ } 3851 }, 3852 }, 3853 { .version = 4, 3854 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 3855 .props = (PropValue[]) { 3856 { "vmx-eptp-switching", "on" }, 3857 { /* end of list */ } 3858 }, 3859 }, 3860 { .version = 5, 3861 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3862 .props = (PropValue[]) { 3863 { "xsaves", "on" }, 3864 { "vmx-xsaves", "on" }, 3865 { /* end of list */ } 3866 }, 3867 }, 3868 { /* end of list */ } 3869 } 3870 }, 3871 { 3872 .name = "Cooperlake", 3873 .level = 0xd, 3874 .vendor = CPUID_VENDOR_INTEL, 3875 .family = 6, 3876 .model = 85, 3877 .stepping = 10, 3878 .features[FEAT_1_EDX] = 3879 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3880 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3881 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3882 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3883 CPUID_DE | CPUID_FP87, 3884 .features[FEAT_1_ECX] = 3885 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3886 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3887 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3888 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3889 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3890 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3891 .features[FEAT_8000_0001_EDX] = 3892 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3893 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3894 .features[FEAT_8000_0001_ECX] = 3895 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3896 .features[FEAT_7_0_EBX] = 3897 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3898 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3899 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3900 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3901 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3902 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3903 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3904 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3905 .features[FEAT_7_0_ECX] = 3906 CPUID_7_0_ECX_PKU | 3907 CPUID_7_0_ECX_AVX512VNNI, 3908 .features[FEAT_7_0_EDX] = 3909 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3910 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3911 .features[FEAT_ARCH_CAPABILITIES] = 3912 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3913 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3914 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3915 .features[FEAT_7_1_EAX] = 3916 CPUID_7_1_EAX_AVX512_BF16, 3917 /* XSAVES is added in version 2 */ 3918 .features[FEAT_XSAVE] = 3919 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3920 CPUID_XSAVE_XGETBV1, 3921 .features[FEAT_6_EAX] = 3922 CPUID_6_EAX_ARAT, 3923 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3924 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3925 MSR_VMX_BASIC_TRUE_CTLS, 3926 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3927 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3928 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3929 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3930 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3931 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3932 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3933 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3934 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3935 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3936 .features[FEAT_VMX_EXIT_CTLS] = 3937 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3938 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3939 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3940 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3941 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3942 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3943 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3944 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3945 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3946 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3947 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3948 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3949 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3950 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3951 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3952 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3953 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3954 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3955 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3956 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3957 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3958 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3959 .features[FEAT_VMX_SECONDARY_CTLS] = 3960 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3961 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3962 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3963 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3964 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3965 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3966 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3967 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3968 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3969 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3970 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3971 .xlevel = 0x80000008, 3972 .model_id = "Intel Xeon Processor (Cooperlake)", 3973 .versions = (X86CPUVersionDefinition[]) { 3974 { .version = 1 }, 3975 { .version = 2, 3976 .note = "XSAVES", 3977 .props = (PropValue[]) { 3978 { "xsaves", "on" }, 3979 { "vmx-xsaves", "on" }, 3980 { /* end of list */ } 3981 }, 3982 }, 3983 { /* end of list */ } 3984 } 3985 }, 3986 { 3987 .name = "Icelake-Server", 3988 .level = 0xd, 3989 .vendor = CPUID_VENDOR_INTEL, 3990 .family = 6, 3991 .model = 134, 3992 .stepping = 0, 3993 .features[FEAT_1_EDX] = 3994 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3995 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3996 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3997 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3998 CPUID_DE | CPUID_FP87, 3999 .features[FEAT_1_ECX] = 4000 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4001 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4002 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4003 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4004 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4005 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4006 .features[FEAT_8000_0001_EDX] = 4007 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4008 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4009 .features[FEAT_8000_0001_ECX] = 4010 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4011 .features[FEAT_8000_0008_EBX] = 4012 CPUID_8000_0008_EBX_WBNOINVD, 4013 .features[FEAT_7_0_EBX] = 4014 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4015 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4016 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4017 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4018 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4019 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4020 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4021 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4022 .features[FEAT_7_0_ECX] = 4023 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4024 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4025 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4026 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4027 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4028 .features[FEAT_7_0_EDX] = 4029 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4030 /* XSAVES is added in version 5 */ 4031 .features[FEAT_XSAVE] = 4032 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4033 CPUID_XSAVE_XGETBV1, 4034 .features[FEAT_6_EAX] = 4035 CPUID_6_EAX_ARAT, 4036 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4037 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4038 MSR_VMX_BASIC_TRUE_CTLS, 4039 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4040 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4041 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4042 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4043 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4044 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4045 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4046 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4047 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4048 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4049 .features[FEAT_VMX_EXIT_CTLS] = 4050 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4051 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4052 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4053 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4054 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4055 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4056 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4057 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4058 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4059 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4060 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4061 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4062 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4063 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4064 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4065 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4066 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4067 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4068 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4069 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4070 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4071 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4072 .features[FEAT_VMX_SECONDARY_CTLS] = 4073 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4074 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4075 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4076 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4077 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4078 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4079 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4080 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4081 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4082 .xlevel = 0x80000008, 4083 .model_id = "Intel Xeon Processor (Icelake)", 4084 .versions = (X86CPUVersionDefinition[]) { 4085 { .version = 1 }, 4086 { 4087 .version = 2, 4088 .note = "no TSX", 4089 .alias = "Icelake-Server-noTSX", 4090 .props = (PropValue[]) { 4091 { "hle", "off" }, 4092 { "rtm", "off" }, 4093 { /* end of list */ } 4094 }, 4095 }, 4096 { 4097 .version = 3, 4098 .props = (PropValue[]) { 4099 { "arch-capabilities", "on" }, 4100 { "rdctl-no", "on" }, 4101 { "ibrs-all", "on" }, 4102 { "skip-l1dfl-vmentry", "on" }, 4103 { "mds-no", "on" }, 4104 { "pschange-mc-no", "on" }, 4105 { "taa-no", "on" }, 4106 { /* end of list */ } 4107 }, 4108 }, 4109 { 4110 .version = 4, 4111 .props = (PropValue[]) { 4112 { "sha-ni", "on" }, 4113 { "avx512ifma", "on" }, 4114 { "rdpid", "on" }, 4115 { "fsrm", "on" }, 4116 { "vmx-rdseed-exit", "on" }, 4117 { "vmx-pml", "on" }, 4118 { "vmx-eptp-switching", "on" }, 4119 { "model", "106" }, 4120 { /* end of list */ } 4121 }, 4122 }, 4123 { 4124 .version = 5, 4125 .note = "XSAVES", 4126 .props = (PropValue[]) { 4127 { "xsaves", "on" }, 4128 { "vmx-xsaves", "on" }, 4129 { /* end of list */ } 4130 }, 4131 }, 4132 { 4133 .version = 6, 4134 .note = "5-level EPT", 4135 .props = (PropValue[]) { 4136 { "vmx-page-walk-5", "on" }, 4137 { /* end of list */ } 4138 }, 4139 }, 4140 { 4141 .version = 7, 4142 .note = "TSX, taa-no", 4143 .props = (PropValue[]) { 4144 /* Restore TSX features removed by -v2 above */ 4145 { "hle", "on" }, 4146 { "rtm", "on" }, 4147 { /* end of list */ } 4148 }, 4149 }, 4150 { /* end of list */ } 4151 } 4152 }, 4153 { 4154 .name = "SapphireRapids", 4155 .level = 0x20, 4156 .vendor = CPUID_VENDOR_INTEL, 4157 .family = 6, 4158 .model = 143, 4159 .stepping = 4, 4160 /* 4161 * please keep the ascending order so that we can have a clear view of 4162 * bit position of each feature. 4163 */ 4164 .features[FEAT_1_EDX] = 4165 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4166 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4167 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4168 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4169 CPUID_SSE | CPUID_SSE2, 4170 .features[FEAT_1_ECX] = 4171 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4172 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4173 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4174 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4175 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4176 .features[FEAT_8000_0001_EDX] = 4177 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4178 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4179 .features[FEAT_8000_0001_ECX] = 4180 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4181 .features[FEAT_8000_0008_EBX] = 4182 CPUID_8000_0008_EBX_WBNOINVD, 4183 .features[FEAT_7_0_EBX] = 4184 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4185 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4186 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4187 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4188 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4189 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4190 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4191 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4192 .features[FEAT_7_0_ECX] = 4193 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4194 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4195 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4196 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4197 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4198 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4199 .features[FEAT_7_0_EDX] = 4200 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4201 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4202 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4203 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4204 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4205 .features[FEAT_ARCH_CAPABILITIES] = 4206 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4207 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4208 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4209 .features[FEAT_XSAVE] = 4210 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4211 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4212 .features[FEAT_6_EAX] = 4213 CPUID_6_EAX_ARAT, 4214 .features[FEAT_7_1_EAX] = 4215 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4216 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4217 .features[FEAT_VMX_BASIC] = 4218 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4219 .features[FEAT_VMX_ENTRY_CTLS] = 4220 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4221 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4222 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4223 .features[FEAT_VMX_EPT_VPID_CAPS] = 4224 MSR_VMX_EPT_EXECONLY | 4225 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4226 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4227 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4228 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4229 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4230 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4231 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4232 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4233 .features[FEAT_VMX_EXIT_CTLS] = 4234 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4235 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4236 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4237 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4238 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4239 .features[FEAT_VMX_MISC] = 4240 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4241 MSR_VMX_MISC_VMWRITE_VMEXIT, 4242 .features[FEAT_VMX_PINBASED_CTLS] = 4243 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4244 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4245 VMX_PIN_BASED_POSTED_INTR, 4246 .features[FEAT_VMX_PROCBASED_CTLS] = 4247 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4248 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4249 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4250 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4251 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4252 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4253 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4254 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4255 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4256 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4257 VMX_CPU_BASED_PAUSE_EXITING | 4258 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4259 .features[FEAT_VMX_SECONDARY_CTLS] = 4260 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4261 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4262 VMX_SECONDARY_EXEC_RDTSCP | 4263 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4264 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4265 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4266 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4267 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4268 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4269 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4270 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4271 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4272 VMX_SECONDARY_EXEC_XSAVES, 4273 .features[FEAT_VMX_VMFUNC] = 4274 MSR_VMX_VMFUNC_EPT_SWITCHING, 4275 .xlevel = 0x80000008, 4276 .model_id = "Intel Xeon Processor (SapphireRapids)", 4277 .versions = (X86CPUVersionDefinition[]) { 4278 { .version = 1 }, 4279 { 4280 .version = 2, 4281 .props = (PropValue[]) { 4282 { "sbdr-ssdp-no", "on" }, 4283 { "fbsdp-no", "on" }, 4284 { "psdp-no", "on" }, 4285 { /* end of list */ } 4286 } 4287 }, 4288 { 4289 .version = 3, 4290 .props = (PropValue[]) { 4291 { "ss", "on" }, 4292 { "tsc-adjust", "on" }, 4293 { "cldemote", "on" }, 4294 { "movdiri", "on" }, 4295 { "movdir64b", "on" }, 4296 { /* end of list */ } 4297 } 4298 }, 4299 { /* end of list */ } 4300 } 4301 }, 4302 { 4303 .name = "GraniteRapids", 4304 .level = 0x20, 4305 .vendor = CPUID_VENDOR_INTEL, 4306 .family = 6, 4307 .model = 173, 4308 .stepping = 0, 4309 /* 4310 * please keep the ascending order so that we can have a clear view of 4311 * bit position of each feature. 4312 */ 4313 .features[FEAT_1_EDX] = 4314 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4315 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4316 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4317 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4318 CPUID_SSE | CPUID_SSE2, 4319 .features[FEAT_1_ECX] = 4320 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4321 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4322 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4323 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4324 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4325 .features[FEAT_8000_0001_EDX] = 4326 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4327 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4328 .features[FEAT_8000_0001_ECX] = 4329 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4330 .features[FEAT_8000_0008_EBX] = 4331 CPUID_8000_0008_EBX_WBNOINVD, 4332 .features[FEAT_7_0_EBX] = 4333 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4334 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4335 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4336 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4337 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4338 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4339 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4340 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4341 .features[FEAT_7_0_ECX] = 4342 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4343 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4344 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4345 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4346 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4347 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4348 .features[FEAT_7_0_EDX] = 4349 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4350 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4351 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4352 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4353 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4354 .features[FEAT_ARCH_CAPABILITIES] = 4355 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4356 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4357 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4358 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4359 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4360 .features[FEAT_XSAVE] = 4361 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4362 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4363 .features[FEAT_6_EAX] = 4364 CPUID_6_EAX_ARAT, 4365 .features[FEAT_7_1_EAX] = 4366 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4367 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4368 CPUID_7_1_EAX_AMX_FP16, 4369 .features[FEAT_7_1_EDX] = 4370 CPUID_7_1_EDX_PREFETCHITI, 4371 .features[FEAT_7_2_EDX] = 4372 CPUID_7_2_EDX_MCDT_NO, 4373 .features[FEAT_VMX_BASIC] = 4374 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4375 .features[FEAT_VMX_ENTRY_CTLS] = 4376 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4377 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4378 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4379 .features[FEAT_VMX_EPT_VPID_CAPS] = 4380 MSR_VMX_EPT_EXECONLY | 4381 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4382 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4383 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4384 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4385 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4386 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4387 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4388 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4389 .features[FEAT_VMX_EXIT_CTLS] = 4390 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4391 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4392 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4393 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4394 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4395 .features[FEAT_VMX_MISC] = 4396 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4397 MSR_VMX_MISC_VMWRITE_VMEXIT, 4398 .features[FEAT_VMX_PINBASED_CTLS] = 4399 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4400 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4401 VMX_PIN_BASED_POSTED_INTR, 4402 .features[FEAT_VMX_PROCBASED_CTLS] = 4403 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4404 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4405 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4406 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4407 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4408 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4409 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4410 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4411 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4412 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4413 VMX_CPU_BASED_PAUSE_EXITING | 4414 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4415 .features[FEAT_VMX_SECONDARY_CTLS] = 4416 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4417 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4418 VMX_SECONDARY_EXEC_RDTSCP | 4419 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4420 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4421 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4422 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4423 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4424 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4425 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4426 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4427 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4428 VMX_SECONDARY_EXEC_XSAVES, 4429 .features[FEAT_VMX_VMFUNC] = 4430 MSR_VMX_VMFUNC_EPT_SWITCHING, 4431 .xlevel = 0x80000008, 4432 .model_id = "Intel Xeon Processor (GraniteRapids)", 4433 .versions = (X86CPUVersionDefinition[]) { 4434 { .version = 1 }, 4435 { 4436 .version = 2, 4437 .props = (PropValue[]) { 4438 { "ss", "on" }, 4439 { "tsc-adjust", "on" }, 4440 { "cldemote", "on" }, 4441 { "movdiri", "on" }, 4442 { "movdir64b", "on" }, 4443 { "avx10", "on" }, 4444 { "avx10-128", "on" }, 4445 { "avx10-256", "on" }, 4446 { "avx10-512", "on" }, 4447 { "avx10-version", "1" }, 4448 { "stepping", "1" }, 4449 { /* end of list */ } 4450 } 4451 }, 4452 { /* end of list */ }, 4453 }, 4454 }, 4455 { 4456 .name = "SierraForest", 4457 .level = 0x23, 4458 .vendor = CPUID_VENDOR_INTEL, 4459 .family = 6, 4460 .model = 175, 4461 .stepping = 0, 4462 /* 4463 * please keep the ascending order so that we can have a clear view of 4464 * bit position of each feature. 4465 */ 4466 .features[FEAT_1_EDX] = 4467 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4468 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4469 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4470 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4471 CPUID_SSE | CPUID_SSE2, 4472 .features[FEAT_1_ECX] = 4473 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4474 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4475 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4476 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4477 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4478 .features[FEAT_8000_0001_EDX] = 4479 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4480 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4481 .features[FEAT_8000_0001_ECX] = 4482 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4483 .features[FEAT_8000_0008_EBX] = 4484 CPUID_8000_0008_EBX_WBNOINVD, 4485 .features[FEAT_7_0_EBX] = 4486 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4487 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4488 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4489 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4490 CPUID_7_0_EBX_SHA_NI, 4491 .features[FEAT_7_0_ECX] = 4492 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4493 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4494 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4495 .features[FEAT_7_0_EDX] = 4496 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4497 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4498 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4499 .features[FEAT_ARCH_CAPABILITIES] = 4500 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4501 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4502 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4503 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4504 MSR_ARCH_CAP_PBRSB_NO, 4505 .features[FEAT_XSAVE] = 4506 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4507 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4508 .features[FEAT_6_EAX] = 4509 CPUID_6_EAX_ARAT, 4510 .features[FEAT_7_1_EAX] = 4511 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4512 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4513 .features[FEAT_7_1_EDX] = 4514 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4515 .features[FEAT_7_2_EDX] = 4516 CPUID_7_2_EDX_MCDT_NO, 4517 .features[FEAT_VMX_BASIC] = 4518 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4519 .features[FEAT_VMX_ENTRY_CTLS] = 4520 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4521 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4522 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4523 .features[FEAT_VMX_EPT_VPID_CAPS] = 4524 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4525 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4526 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4527 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4528 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4529 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4530 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4531 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4532 .features[FEAT_VMX_EXIT_CTLS] = 4533 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4534 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4535 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4536 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4537 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4538 .features[FEAT_VMX_MISC] = 4539 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4540 MSR_VMX_MISC_VMWRITE_VMEXIT, 4541 .features[FEAT_VMX_PINBASED_CTLS] = 4542 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4543 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4544 VMX_PIN_BASED_POSTED_INTR, 4545 .features[FEAT_VMX_PROCBASED_CTLS] = 4546 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4547 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4548 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4549 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4550 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4551 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4552 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4553 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4554 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4555 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4556 VMX_CPU_BASED_PAUSE_EXITING | 4557 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4558 .features[FEAT_VMX_SECONDARY_CTLS] = 4559 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4560 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4561 VMX_SECONDARY_EXEC_RDTSCP | 4562 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4563 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4564 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4565 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4566 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4567 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4568 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4569 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4570 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4571 VMX_SECONDARY_EXEC_XSAVES, 4572 .features[FEAT_VMX_VMFUNC] = 4573 MSR_VMX_VMFUNC_EPT_SWITCHING, 4574 .xlevel = 0x80000008, 4575 .model_id = "Intel Xeon Processor (SierraForest)", 4576 .versions = (X86CPUVersionDefinition[]) { 4577 { .version = 1 }, 4578 { 4579 .version = 2, 4580 .props = (PropValue[]) { 4581 { "ss", "on" }, 4582 { "tsc-adjust", "on" }, 4583 { "cldemote", "on" }, 4584 { "movdiri", "on" }, 4585 { "movdir64b", "on" }, 4586 { "gds-no", "on" }, 4587 { "rfds-no", "on" }, 4588 { "lam", "on" }, 4589 { "intel-psfd", "on"}, 4590 { "ipred-ctrl", "on"}, 4591 { "rrsba-ctrl", "on"}, 4592 { "bhi-ctrl", "on"}, 4593 { "stepping", "3" }, 4594 { /* end of list */ } 4595 } 4596 }, 4597 { /* end of list */ }, 4598 }, 4599 }, 4600 { 4601 .name = "ClearwaterForest", 4602 .level = 0x23, 4603 .xlevel = 0x80000008, 4604 .vendor = CPUID_VENDOR_INTEL, 4605 .family = 6, 4606 .model = 221, 4607 .stepping = 0, 4608 /* 4609 * please keep the ascending order so that we can have a clear view of 4610 * bit position of each feature. 4611 */ 4612 .features[FEAT_1_EDX] = 4613 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4614 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4615 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4616 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4617 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 4618 .features[FEAT_1_ECX] = 4619 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4620 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4621 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4622 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4623 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4624 .features[FEAT_8000_0001_EDX] = 4625 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4626 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4627 .features[FEAT_8000_0001_ECX] = 4628 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4629 .features[FEAT_8000_0008_EBX] = 4630 CPUID_8000_0008_EBX_WBNOINVD, 4631 .features[FEAT_7_0_EBX] = 4632 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 4633 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4634 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4635 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4636 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4637 CPUID_7_0_EBX_SHA_NI, 4638 .features[FEAT_7_0_ECX] = 4639 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4640 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4641 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 4642 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 4643 CPUID_7_0_ECX_MOVDIR64B, 4644 .features[FEAT_7_0_EDX] = 4645 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4646 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4647 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4648 .features[FEAT_ARCH_CAPABILITIES] = 4649 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4650 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4651 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4652 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4653 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 4654 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 4655 .features[FEAT_XSAVE] = 4656 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4657 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4658 .features[FEAT_6_EAX] = 4659 CPUID_6_EAX_ARAT, 4660 .features[FEAT_7_1_EAX] = 4661 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 4662 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4663 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 4664 CPUID_7_1_EAX_LAM, 4665 .features[FEAT_7_1_EDX] = 4666 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 4667 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 4668 .features[FEAT_7_2_EDX] = 4669 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 4670 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 4671 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 4672 .features[FEAT_VMX_BASIC] = 4673 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4674 .features[FEAT_VMX_ENTRY_CTLS] = 4675 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4676 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4677 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4678 .features[FEAT_VMX_EPT_VPID_CAPS] = 4679 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4680 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4681 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4682 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4683 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4684 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4685 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4686 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4687 .features[FEAT_VMX_EXIT_CTLS] = 4688 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4689 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4690 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4691 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4692 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4693 .features[FEAT_VMX_MISC] = 4694 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4695 MSR_VMX_MISC_VMWRITE_VMEXIT, 4696 .features[FEAT_VMX_PINBASED_CTLS] = 4697 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4698 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4699 VMX_PIN_BASED_POSTED_INTR, 4700 .features[FEAT_VMX_PROCBASED_CTLS] = 4701 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4702 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4703 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4704 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4705 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4706 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4707 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4708 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4709 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4710 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4711 VMX_CPU_BASED_PAUSE_EXITING | 4712 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4713 .features[FEAT_VMX_SECONDARY_CTLS] = 4714 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4715 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4716 VMX_SECONDARY_EXEC_RDTSCP | 4717 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4718 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4719 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4720 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4721 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4722 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4723 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4724 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4725 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4726 VMX_SECONDARY_EXEC_XSAVES, 4727 .features[FEAT_VMX_VMFUNC] = 4728 MSR_VMX_VMFUNC_EPT_SWITCHING, 4729 .model_id = "Intel Xeon Processor (ClearwaterForest)", 4730 .versions = (X86CPUVersionDefinition[]) { 4731 { .version = 1 }, 4732 { /* end of list */ }, 4733 }, 4734 }, 4735 { 4736 .name = "Denverton", 4737 .level = 21, 4738 .vendor = CPUID_VENDOR_INTEL, 4739 .family = 6, 4740 .model = 95, 4741 .stepping = 1, 4742 .features[FEAT_1_EDX] = 4743 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4744 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4745 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4746 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4747 CPUID_SSE | CPUID_SSE2, 4748 .features[FEAT_1_ECX] = 4749 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4750 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4751 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4752 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4753 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4754 .features[FEAT_8000_0001_EDX] = 4755 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4756 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4757 .features[FEAT_8000_0001_ECX] = 4758 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4759 .features[FEAT_7_0_EBX] = 4760 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4761 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4762 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4763 .features[FEAT_7_0_EDX] = 4764 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4765 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4766 /* XSAVES is added in version 3 */ 4767 .features[FEAT_XSAVE] = 4768 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4769 .features[FEAT_6_EAX] = 4770 CPUID_6_EAX_ARAT, 4771 .features[FEAT_ARCH_CAPABILITIES] = 4772 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4773 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4774 MSR_VMX_BASIC_TRUE_CTLS, 4775 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4776 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4777 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4778 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4779 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4780 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4781 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4782 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4783 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4784 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4785 .features[FEAT_VMX_EXIT_CTLS] = 4786 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4787 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4788 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4789 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4790 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4791 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4792 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4793 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4794 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4795 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4796 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4797 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4798 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4799 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4800 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4801 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4802 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4803 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4804 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4805 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4806 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4807 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4808 .features[FEAT_VMX_SECONDARY_CTLS] = 4809 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4810 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4811 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4812 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4813 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4814 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4815 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4816 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4817 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4818 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4819 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4820 .xlevel = 0x80000008, 4821 .model_id = "Intel Atom Processor (Denverton)", 4822 .versions = (X86CPUVersionDefinition[]) { 4823 { .version = 1 }, 4824 { 4825 .version = 2, 4826 .note = "no MPX, no MONITOR", 4827 .props = (PropValue[]) { 4828 { "monitor", "off" }, 4829 { "mpx", "off" }, 4830 { /* end of list */ }, 4831 }, 4832 }, 4833 { 4834 .version = 3, 4835 .note = "XSAVES, no MPX, no MONITOR", 4836 .props = (PropValue[]) { 4837 { "xsaves", "on" }, 4838 { "vmx-xsaves", "on" }, 4839 { /* end of list */ }, 4840 }, 4841 }, 4842 { /* end of list */ }, 4843 }, 4844 }, 4845 { 4846 .name = "Snowridge", 4847 .level = 27, 4848 .vendor = CPUID_VENDOR_INTEL, 4849 .family = 6, 4850 .model = 134, 4851 .stepping = 1, 4852 .features[FEAT_1_EDX] = 4853 /* missing: CPUID_PN CPUID_IA64 */ 4854 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4855 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4856 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4857 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4858 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4859 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4860 CPUID_MMX | 4861 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4862 .features[FEAT_1_ECX] = 4863 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4864 CPUID_EXT_SSSE3 | 4865 CPUID_EXT_CX16 | 4866 CPUID_EXT_SSE41 | 4867 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4868 CPUID_EXT_POPCNT | 4869 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4870 CPUID_EXT_RDRAND, 4871 .features[FEAT_8000_0001_EDX] = 4872 CPUID_EXT2_SYSCALL | 4873 CPUID_EXT2_NX | 4874 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4875 CPUID_EXT2_LM, 4876 .features[FEAT_8000_0001_ECX] = 4877 CPUID_EXT3_LAHF_LM | 4878 CPUID_EXT3_3DNOWPREFETCH, 4879 .features[FEAT_7_0_EBX] = 4880 CPUID_7_0_EBX_FSGSBASE | 4881 CPUID_7_0_EBX_SMEP | 4882 CPUID_7_0_EBX_ERMS | 4883 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4884 CPUID_7_0_EBX_RDSEED | 4885 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4886 CPUID_7_0_EBX_CLWB | 4887 CPUID_7_0_EBX_SHA_NI, 4888 .features[FEAT_7_0_ECX] = 4889 CPUID_7_0_ECX_UMIP | 4890 /* missing bit 5 */ 4891 CPUID_7_0_ECX_GFNI | 4892 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4893 CPUID_7_0_ECX_MOVDIR64B, 4894 .features[FEAT_7_0_EDX] = 4895 CPUID_7_0_EDX_SPEC_CTRL | 4896 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4897 CPUID_7_0_EDX_CORE_CAPABILITY, 4898 .features[FEAT_CORE_CAPABILITY] = 4899 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4900 /* XSAVES is added in version 3 */ 4901 .features[FEAT_XSAVE] = 4902 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4903 CPUID_XSAVE_XGETBV1, 4904 .features[FEAT_6_EAX] = 4905 CPUID_6_EAX_ARAT, 4906 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4907 MSR_VMX_BASIC_TRUE_CTLS, 4908 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4909 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4910 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4911 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4912 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4913 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4914 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4915 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4916 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4917 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4918 .features[FEAT_VMX_EXIT_CTLS] = 4919 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4920 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4921 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4922 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4923 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4924 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4925 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4926 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4927 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4928 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4929 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4930 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4931 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4932 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4933 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4934 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4935 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4936 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4937 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4938 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4939 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4940 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4941 .features[FEAT_VMX_SECONDARY_CTLS] = 4942 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4943 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4944 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4945 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4946 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4947 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4948 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4949 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4950 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4951 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4952 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4953 .xlevel = 0x80000008, 4954 .model_id = "Intel Atom Processor (SnowRidge)", 4955 .versions = (X86CPUVersionDefinition[]) { 4956 { .version = 1 }, 4957 { 4958 .version = 2, 4959 .props = (PropValue[]) { 4960 { "mpx", "off" }, 4961 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4962 { /* end of list */ }, 4963 }, 4964 }, 4965 { 4966 .version = 3, 4967 .note = "XSAVES, no MPX", 4968 .props = (PropValue[]) { 4969 { "xsaves", "on" }, 4970 { "vmx-xsaves", "on" }, 4971 { /* end of list */ }, 4972 }, 4973 }, 4974 { 4975 .version = 4, 4976 .note = "no split lock detect, no core-capability", 4977 .props = (PropValue[]) { 4978 { "split-lock-detect", "off" }, 4979 { "core-capability", "off" }, 4980 { /* end of list */ }, 4981 }, 4982 }, 4983 { /* end of list */ }, 4984 }, 4985 }, 4986 { 4987 .name = "KnightsMill", 4988 .level = 0xd, 4989 .vendor = CPUID_VENDOR_INTEL, 4990 .family = 6, 4991 .model = 133, 4992 .stepping = 0, 4993 .features[FEAT_1_EDX] = 4994 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4995 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4996 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4997 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4998 CPUID_PSE | CPUID_DE | CPUID_FP87, 4999 .features[FEAT_1_ECX] = 5000 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5001 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 5002 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 5003 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5004 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 5005 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5006 .features[FEAT_8000_0001_EDX] = 5007 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5008 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5009 .features[FEAT_8000_0001_ECX] = 5010 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5011 .features[FEAT_7_0_EBX] = 5012 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5013 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5014 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 5015 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 5016 CPUID_7_0_EBX_AVX512ER, 5017 .features[FEAT_7_0_ECX] = 5018 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 5019 .features[FEAT_7_0_EDX] = 5020 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 5021 .features[FEAT_XSAVE] = 5022 CPUID_XSAVE_XSAVEOPT, 5023 .features[FEAT_6_EAX] = 5024 CPUID_6_EAX_ARAT, 5025 .xlevel = 0x80000008, 5026 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5027 }, 5028 { 5029 .name = "Opteron_G1", 5030 .level = 5, 5031 .vendor = CPUID_VENDOR_AMD, 5032 .family = 15, 5033 .model = 6, 5034 .stepping = 1, 5035 .features[FEAT_1_EDX] = 5036 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5037 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5038 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5039 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5040 CPUID_DE | CPUID_FP87, 5041 .features[FEAT_1_ECX] = 5042 CPUID_EXT_SSE3, 5043 .features[FEAT_8000_0001_EDX] = 5044 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5045 .xlevel = 0x80000008, 5046 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5047 }, 5048 { 5049 .name = "Opteron_G2", 5050 .level = 5, 5051 .vendor = CPUID_VENDOR_AMD, 5052 .family = 15, 5053 .model = 6, 5054 .stepping = 1, 5055 .features[FEAT_1_EDX] = 5056 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5057 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5058 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5059 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5060 CPUID_DE | CPUID_FP87, 5061 .features[FEAT_1_ECX] = 5062 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5063 .features[FEAT_8000_0001_EDX] = 5064 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5065 .features[FEAT_8000_0001_ECX] = 5066 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5067 .xlevel = 0x80000008, 5068 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5069 }, 5070 { 5071 .name = "Opteron_G3", 5072 .level = 5, 5073 .vendor = CPUID_VENDOR_AMD, 5074 .family = 16, 5075 .model = 2, 5076 .stepping = 3, 5077 .features[FEAT_1_EDX] = 5078 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5079 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5080 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5081 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5082 CPUID_DE | CPUID_FP87, 5083 .features[FEAT_1_ECX] = 5084 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5085 CPUID_EXT_SSE3, 5086 .features[FEAT_8000_0001_EDX] = 5087 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5088 CPUID_EXT2_RDTSCP, 5089 .features[FEAT_8000_0001_ECX] = 5090 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5091 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5092 .xlevel = 0x80000008, 5093 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5094 }, 5095 { 5096 .name = "Opteron_G4", 5097 .level = 0xd, 5098 .vendor = CPUID_VENDOR_AMD, 5099 .family = 21, 5100 .model = 1, 5101 .stepping = 2, 5102 .features[FEAT_1_EDX] = 5103 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5104 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5105 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5106 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5107 CPUID_DE | CPUID_FP87, 5108 .features[FEAT_1_ECX] = 5109 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5110 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5111 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5112 CPUID_EXT_SSE3, 5113 .features[FEAT_8000_0001_EDX] = 5114 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5115 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5116 .features[FEAT_8000_0001_ECX] = 5117 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5118 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5119 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5120 CPUID_EXT3_LAHF_LM, 5121 .features[FEAT_SVM] = 5122 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5123 /* no xsaveopt! */ 5124 .xlevel = 0x8000001A, 5125 .model_id = "AMD Opteron 62xx class CPU", 5126 }, 5127 { 5128 .name = "Opteron_G5", 5129 .level = 0xd, 5130 .vendor = CPUID_VENDOR_AMD, 5131 .family = 21, 5132 .model = 2, 5133 .stepping = 0, 5134 .features[FEAT_1_EDX] = 5135 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5136 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5137 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5138 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5139 CPUID_DE | CPUID_FP87, 5140 .features[FEAT_1_ECX] = 5141 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5142 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5143 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5144 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5145 .features[FEAT_8000_0001_EDX] = 5146 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5147 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5148 .features[FEAT_8000_0001_ECX] = 5149 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5150 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5151 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5152 CPUID_EXT3_LAHF_LM, 5153 .features[FEAT_SVM] = 5154 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5155 /* no xsaveopt! */ 5156 .xlevel = 0x8000001A, 5157 .model_id = "AMD Opteron 63xx class CPU", 5158 }, 5159 { 5160 .name = "EPYC", 5161 .level = 0xd, 5162 .vendor = CPUID_VENDOR_AMD, 5163 .family = 23, 5164 .model = 1, 5165 .stepping = 2, 5166 .features[FEAT_1_EDX] = 5167 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5168 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5169 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5170 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5171 CPUID_VME | CPUID_FP87, 5172 .features[FEAT_1_ECX] = 5173 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5174 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5175 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5176 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5177 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5178 .features[FEAT_8000_0001_EDX] = 5179 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5180 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5181 CPUID_EXT2_SYSCALL, 5182 .features[FEAT_8000_0001_ECX] = 5183 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5184 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5185 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5186 CPUID_EXT3_TOPOEXT, 5187 .features[FEAT_7_0_EBX] = 5188 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5189 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5190 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5191 CPUID_7_0_EBX_SHA_NI, 5192 .features[FEAT_XSAVE] = 5193 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5194 CPUID_XSAVE_XGETBV1, 5195 .features[FEAT_6_EAX] = 5196 CPUID_6_EAX_ARAT, 5197 .features[FEAT_SVM] = 5198 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5199 .xlevel = 0x8000001E, 5200 .model_id = "AMD EPYC Processor", 5201 .cache_info = &epyc_cache_info, 5202 .versions = (X86CPUVersionDefinition[]) { 5203 { .version = 1 }, 5204 { 5205 .version = 2, 5206 .alias = "EPYC-IBPB", 5207 .props = (PropValue[]) { 5208 { "ibpb", "on" }, 5209 { "model-id", 5210 "AMD EPYC Processor (with IBPB)" }, 5211 { /* end of list */ } 5212 } 5213 }, 5214 { 5215 .version = 3, 5216 .props = (PropValue[]) { 5217 { "ibpb", "on" }, 5218 { "perfctr-core", "on" }, 5219 { "clzero", "on" }, 5220 { "xsaveerptr", "on" }, 5221 { "xsaves", "on" }, 5222 { "model-id", 5223 "AMD EPYC Processor" }, 5224 { /* end of list */ } 5225 } 5226 }, 5227 { 5228 .version = 4, 5229 .props = (PropValue[]) { 5230 { "model-id", 5231 "AMD EPYC-v4 Processor" }, 5232 { /* end of list */ } 5233 }, 5234 .cache_info = &epyc_v4_cache_info 5235 }, 5236 { /* end of list */ } 5237 } 5238 }, 5239 { 5240 .name = "Dhyana", 5241 .level = 0xd, 5242 .vendor = CPUID_VENDOR_HYGON, 5243 .family = 24, 5244 .model = 0, 5245 .stepping = 1, 5246 .features[FEAT_1_EDX] = 5247 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5248 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5249 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5250 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5251 CPUID_VME | CPUID_FP87, 5252 .features[FEAT_1_ECX] = 5253 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5254 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5255 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5256 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5257 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5258 .features[FEAT_8000_0001_EDX] = 5259 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5260 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5261 CPUID_EXT2_SYSCALL, 5262 .features[FEAT_8000_0001_ECX] = 5263 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5264 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5265 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5266 CPUID_EXT3_TOPOEXT, 5267 .features[FEAT_8000_0008_EBX] = 5268 CPUID_8000_0008_EBX_IBPB, 5269 .features[FEAT_7_0_EBX] = 5270 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5271 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5272 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5273 /* XSAVES is added in version 2 */ 5274 .features[FEAT_XSAVE] = 5275 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5276 CPUID_XSAVE_XGETBV1, 5277 .features[FEAT_6_EAX] = 5278 CPUID_6_EAX_ARAT, 5279 .features[FEAT_SVM] = 5280 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5281 .xlevel = 0x8000001E, 5282 .model_id = "Hygon Dhyana Processor", 5283 .cache_info = &epyc_cache_info, 5284 .versions = (X86CPUVersionDefinition[]) { 5285 { .version = 1 }, 5286 { .version = 2, 5287 .note = "XSAVES", 5288 .props = (PropValue[]) { 5289 { "xsaves", "on" }, 5290 { /* end of list */ } 5291 }, 5292 }, 5293 { /* end of list */ } 5294 } 5295 }, 5296 { 5297 .name = "EPYC-Rome", 5298 .level = 0xd, 5299 .vendor = CPUID_VENDOR_AMD, 5300 .family = 23, 5301 .model = 49, 5302 .stepping = 0, 5303 .features[FEAT_1_EDX] = 5304 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5305 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5306 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5307 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5308 CPUID_VME | CPUID_FP87, 5309 .features[FEAT_1_ECX] = 5310 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5311 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5312 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5313 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5314 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5315 .features[FEAT_8000_0001_EDX] = 5316 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5317 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5318 CPUID_EXT2_SYSCALL, 5319 .features[FEAT_8000_0001_ECX] = 5320 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5321 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5322 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5323 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5324 .features[FEAT_8000_0008_EBX] = 5325 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5326 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5327 CPUID_8000_0008_EBX_STIBP, 5328 .features[FEAT_7_0_EBX] = 5329 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5330 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5331 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5332 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5333 .features[FEAT_7_0_ECX] = 5334 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5335 .features[FEAT_XSAVE] = 5336 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5337 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5338 .features[FEAT_6_EAX] = 5339 CPUID_6_EAX_ARAT, 5340 .features[FEAT_SVM] = 5341 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5342 .xlevel = 0x8000001E, 5343 .model_id = "AMD EPYC-Rome Processor", 5344 .cache_info = &epyc_rome_cache_info, 5345 .versions = (X86CPUVersionDefinition[]) { 5346 { .version = 1 }, 5347 { 5348 .version = 2, 5349 .props = (PropValue[]) { 5350 { "ibrs", "on" }, 5351 { "amd-ssbd", "on" }, 5352 { /* end of list */ } 5353 } 5354 }, 5355 { 5356 .version = 3, 5357 .props = (PropValue[]) { 5358 { "model-id", 5359 "AMD EPYC-Rome-v3 Processor" }, 5360 { /* end of list */ } 5361 }, 5362 .cache_info = &epyc_rome_v3_cache_info 5363 }, 5364 { 5365 .version = 4, 5366 .props = (PropValue[]) { 5367 /* Erratum 1386 */ 5368 { "model-id", 5369 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5370 { "xsaves", "off" }, 5371 { /* end of list */ } 5372 }, 5373 }, 5374 { /* end of list */ } 5375 } 5376 }, 5377 { 5378 .name = "EPYC-Milan", 5379 .level = 0xd, 5380 .vendor = CPUID_VENDOR_AMD, 5381 .family = 25, 5382 .model = 1, 5383 .stepping = 1, 5384 .features[FEAT_1_EDX] = 5385 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5386 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5387 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5388 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5389 CPUID_VME | CPUID_FP87, 5390 .features[FEAT_1_ECX] = 5391 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5392 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5393 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5394 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5395 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5396 CPUID_EXT_PCID, 5397 .features[FEAT_8000_0001_EDX] = 5398 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5399 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5400 CPUID_EXT2_SYSCALL, 5401 .features[FEAT_8000_0001_ECX] = 5402 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5403 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5404 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5405 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5406 .features[FEAT_8000_0008_EBX] = 5407 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5408 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5409 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5410 CPUID_8000_0008_EBX_AMD_SSBD, 5411 .features[FEAT_7_0_EBX] = 5412 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5413 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5414 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5415 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5416 CPUID_7_0_EBX_INVPCID, 5417 .features[FEAT_7_0_ECX] = 5418 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5419 .features[FEAT_7_0_EDX] = 5420 CPUID_7_0_EDX_FSRM, 5421 .features[FEAT_XSAVE] = 5422 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5423 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5424 .features[FEAT_6_EAX] = 5425 CPUID_6_EAX_ARAT, 5426 .features[FEAT_SVM] = 5427 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5428 .xlevel = 0x8000001E, 5429 .model_id = "AMD EPYC-Milan Processor", 5430 .cache_info = &epyc_milan_cache_info, 5431 .versions = (X86CPUVersionDefinition[]) { 5432 { .version = 1 }, 5433 { 5434 .version = 2, 5435 .props = (PropValue[]) { 5436 { "model-id", 5437 "AMD EPYC-Milan-v2 Processor" }, 5438 { "vaes", "on" }, 5439 { "vpclmulqdq", "on" }, 5440 { "stibp-always-on", "on" }, 5441 { "amd-psfd", "on" }, 5442 { "no-nested-data-bp", "on" }, 5443 { "lfence-always-serializing", "on" }, 5444 { "null-sel-clr-base", "on" }, 5445 { /* end of list */ } 5446 }, 5447 .cache_info = &epyc_milan_v2_cache_info 5448 }, 5449 { /* end of list */ } 5450 } 5451 }, 5452 { 5453 .name = "EPYC-Genoa", 5454 .level = 0xd, 5455 .vendor = CPUID_VENDOR_AMD, 5456 .family = 25, 5457 .model = 17, 5458 .stepping = 0, 5459 .features[FEAT_1_EDX] = 5460 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5461 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5462 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5463 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5464 CPUID_VME | CPUID_FP87, 5465 .features[FEAT_1_ECX] = 5466 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5467 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5468 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5469 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5470 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5471 CPUID_EXT_SSE3, 5472 .features[FEAT_8000_0001_EDX] = 5473 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5474 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5475 CPUID_EXT2_SYSCALL, 5476 .features[FEAT_8000_0001_ECX] = 5477 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5478 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5479 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5480 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5481 .features[FEAT_8000_0008_EBX] = 5482 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5483 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5484 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5485 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5486 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5487 .features[FEAT_8000_0021_EAX] = 5488 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5489 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5490 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5491 CPUID_8000_0021_EAX_AUTO_IBRS, 5492 .features[FEAT_7_0_EBX] = 5493 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5494 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5495 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5496 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5497 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5498 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5499 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5500 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5501 .features[FEAT_7_0_ECX] = 5502 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5503 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5504 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5505 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5506 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5507 CPUID_7_0_ECX_RDPID, 5508 .features[FEAT_7_0_EDX] = 5509 CPUID_7_0_EDX_FSRM, 5510 .features[FEAT_7_1_EAX] = 5511 CPUID_7_1_EAX_AVX512_BF16, 5512 .features[FEAT_XSAVE] = 5513 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5514 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5515 .features[FEAT_6_EAX] = 5516 CPUID_6_EAX_ARAT, 5517 .features[FEAT_SVM] = 5518 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5519 CPUID_SVM_SVME_ADDR_CHK, 5520 .xlevel = 0x80000022, 5521 .model_id = "AMD EPYC-Genoa Processor", 5522 .cache_info = &epyc_genoa_cache_info, 5523 }, 5524 { 5525 .name = "YongFeng", 5526 .level = 0x1F, 5527 .vendor = CPUID_VENDOR_ZHAOXIN1, 5528 .family = 7, 5529 .model = 11, 5530 .stepping = 3, 5531 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 5532 .features[FEAT_1_EDX] = 5533 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5534 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5535 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5536 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5537 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 5538 /* 5539 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 5540 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 5541 */ 5542 .features[FEAT_1_ECX] = 5543 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5544 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 5545 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 5546 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 5547 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5548 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5549 .features[FEAT_7_0_EBX] = 5550 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 5551 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 5552 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 5553 CPUID_7_0_EBX_FSGSBASE, 5554 /* missing: CPUID_7_0_ECX_OSPKE */ 5555 .features[FEAT_7_0_ECX] = 5556 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 5557 .features[FEAT_7_0_EDX] = 5558 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 5559 .features[FEAT_8000_0001_EDX] = 5560 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5561 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5562 .features[FEAT_8000_0001_ECX] = 5563 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 5564 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 5565 /* 5566 * TODO: When the Linux kernel introduces other existing definitions 5567 * for this leaf, remember to update the definitions here. 5568 */ 5569 .features[FEAT_C000_0001_EDX] = 5570 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 5571 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 5572 CPUID_C000_0001_EDX_ACE2 | 5573 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 5574 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 5575 .features[FEAT_XSAVE] = 5576 CPUID_XSAVE_XSAVEOPT, 5577 .features[FEAT_ARCH_CAPABILITIES] = 5578 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 5579 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 5580 MSR_ARCH_CAP_SSB_NO, 5581 .features[FEAT_VMX_PROCBASED_CTLS] = 5582 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 5583 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 5584 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 5585 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 5586 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 5587 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 5588 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 5589 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5590 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 5591 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5592 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5593 /* 5594 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 5595 * VMX_SECONDARY_EXEC_TSC_SCALING 5596 */ 5597 .features[FEAT_VMX_SECONDARY_CTLS] = 5598 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5599 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5600 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 5601 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5602 VMX_SECONDARY_EXEC_WBINVD_EXITING | 5603 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5604 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5605 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5606 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5607 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5608 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 5609 VMX_SECONDARY_EXEC_SHADOW_VMCS | 5610 VMX_SECONDARY_EXEC_ENABLE_PML, 5611 .features[FEAT_VMX_PINBASED_CTLS] = 5612 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5613 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5614 VMX_PIN_BASED_POSTED_INTR, 5615 .features[FEAT_VMX_EXIT_CTLS] = 5616 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 5617 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5618 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5619 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5620 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5621 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 5622 .features[FEAT_VMX_ENTRY_CTLS] = 5623 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5624 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5625 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5626 /* 5627 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 5628 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 5629 */ 5630 .features[FEAT_VMX_MISC] = 5631 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5632 MSR_VMX_MISC_VMWRITE_VMEXIT, 5633 /* missing: MSR_VMX_EPT_UC */ 5634 .features[FEAT_VMX_EPT_VPID_CAPS] = 5635 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5636 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5637 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5638 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5639 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 5640 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5641 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5642 .features[FEAT_VMX_BASIC] = 5643 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5644 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5645 .xlevel = 0x80000008, 5646 .model_id = "Zhaoxin YongFeng Processor", 5647 .versions = (X86CPUVersionDefinition[]) { 5648 { .version = 1 }, 5649 { 5650 .version = 2, 5651 .note = "with the correct model number", 5652 .props = (PropValue[]) { 5653 { "model", "0x5b" }, 5654 { /* end of list */ } 5655 } 5656 }, 5657 { /* end of list */ } 5658 } 5659 }, 5660 }; 5661 5662 /* 5663 * We resolve CPU model aliases using -v1 when using "-machine 5664 * none", but this is just for compatibility while libvirt isn't 5665 * adapted to resolve CPU model versions before creating VMs. 5666 * See "Runnability guarantee of CPU models" at 5667 * docs/about/deprecated.rst. 5668 */ 5669 X86CPUVersion default_cpu_version = 1; 5670 5671 void x86_cpu_set_default_version(X86CPUVersion version) 5672 { 5673 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5674 assert(version != CPU_VERSION_AUTO); 5675 default_cpu_version = version; 5676 } 5677 5678 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5679 { 5680 int v = 0; 5681 const X86CPUVersionDefinition *vdef = 5682 x86_cpu_def_get_versions(model->cpudef); 5683 while (vdef->version) { 5684 v = vdef->version; 5685 vdef++; 5686 } 5687 return v; 5688 } 5689 5690 /* Return the actual version being used for a specific CPU model */ 5691 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5692 { 5693 X86CPUVersion v = model->version; 5694 if (v == CPU_VERSION_AUTO) { 5695 v = default_cpu_version; 5696 } 5697 if (v == CPU_VERSION_LATEST) { 5698 return x86_cpu_model_last_version(model); 5699 } 5700 return v; 5701 } 5702 5703 static const Property max_x86_cpu_properties[] = { 5704 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5705 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5706 }; 5707 5708 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5709 { 5710 Object *obj = OBJECT(dev); 5711 5712 if (!object_property_get_int(obj, "family", &error_abort)) { 5713 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5714 object_property_set_int(obj, "family", 15, &error_abort); 5715 object_property_set_int(obj, "model", 107, &error_abort); 5716 object_property_set_int(obj, "stepping", 1, &error_abort); 5717 } else { 5718 object_property_set_int(obj, "family", 6, &error_abort); 5719 object_property_set_int(obj, "model", 6, &error_abort); 5720 object_property_set_int(obj, "stepping", 3, &error_abort); 5721 } 5722 } 5723 5724 x86_cpu_realizefn(dev, errp); 5725 } 5726 5727 static void max_x86_cpu_class_init(ObjectClass *oc, const void *data) 5728 { 5729 DeviceClass *dc = DEVICE_CLASS(oc); 5730 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5731 5732 xcc->ordering = 9; 5733 5734 xcc->model_description = 5735 "Enables all features supported by the accelerator in the current host"; 5736 5737 device_class_set_props(dc, max_x86_cpu_properties); 5738 dc->realize = max_x86_cpu_realize; 5739 } 5740 5741 static void max_x86_cpu_initfn(Object *obj) 5742 { 5743 X86CPU *cpu = X86_CPU(obj); 5744 5745 /* We can't fill the features array here because we don't know yet if 5746 * "migratable" is true or false. 5747 */ 5748 cpu->max_features = true; 5749 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5750 5751 /* 5752 * these defaults are used for TCG and all other accelerators 5753 * besides KVM and HVF, which overwrite these values 5754 */ 5755 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5756 &error_abort); 5757 object_property_set_str(OBJECT(cpu), "model-id", 5758 "QEMU TCG CPU version " QEMU_HW_VERSION, 5759 &error_abort); 5760 } 5761 5762 static const TypeInfo max_x86_cpu_type_info = { 5763 .name = X86_CPU_TYPE_NAME("max"), 5764 .parent = TYPE_X86_CPU, 5765 .instance_init = max_x86_cpu_initfn, 5766 .class_init = max_x86_cpu_class_init, 5767 }; 5768 5769 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5770 { 5771 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5772 5773 switch (f->type) { 5774 case CPUID_FEATURE_WORD: 5775 { 5776 const char *reg = get_register_name_32(f->cpuid.reg); 5777 assert(reg); 5778 return g_strdup_printf("CPUID.%02XH:%s", 5779 f->cpuid.eax, reg); 5780 } 5781 case MSR_FEATURE_WORD: 5782 return g_strdup_printf("MSR(%02XH)", 5783 f->msr.index); 5784 } 5785 5786 return NULL; 5787 } 5788 5789 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5790 { 5791 FeatureWord w; 5792 5793 for (w = 0; w < FEATURE_WORDS; w++) { 5794 if (cpu->filtered_features[w]) { 5795 return true; 5796 } 5797 } 5798 5799 return false; 5800 } 5801 5802 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5803 const char *verbose_prefix) 5804 { 5805 CPUX86State *env = &cpu->env; 5806 FeatureWordInfo *f = &feature_word_info[w]; 5807 int i; 5808 5809 if (!cpu->force_features) { 5810 env->features[w] &= ~mask; 5811 } 5812 cpu->filtered_features[w] |= mask; 5813 5814 if (!verbose_prefix) { 5815 return; 5816 } 5817 5818 for (i = 0; i < 64; ++i) { 5819 if ((1ULL << i) & mask) { 5820 g_autofree char *feat_word_str = feature_word_description(f, i); 5821 warn_report("%s: %s%s%s [bit %d]", 5822 verbose_prefix, 5823 feat_word_str, 5824 f->feat_names[i] ? "." : "", 5825 f->feat_names[i] ? f->feat_names[i] : "", i); 5826 } 5827 } 5828 } 5829 5830 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5831 const char *name, void *opaque, 5832 Error **errp) 5833 { 5834 X86CPU *cpu = X86_CPU(obj); 5835 CPUX86State *env = &cpu->env; 5836 uint64_t value; 5837 5838 value = (env->cpuid_version >> 8) & 0xf; 5839 if (value == 0xf) { 5840 value += (env->cpuid_version >> 20) & 0xff; 5841 } 5842 visit_type_uint64(v, name, &value, errp); 5843 } 5844 5845 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5846 const char *name, void *opaque, 5847 Error **errp) 5848 { 5849 X86CPU *cpu = X86_CPU(obj); 5850 CPUX86State *env = &cpu->env; 5851 const uint64_t max = 0xff + 0xf; 5852 uint64_t value; 5853 5854 if (!visit_type_uint64(v, name, &value, errp)) { 5855 return; 5856 } 5857 if (value > max) { 5858 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5859 name ? name : "null", max); 5860 return; 5861 } 5862 5863 env->cpuid_version &= ~0xff00f00; 5864 if (value > 0x0f) { 5865 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5866 } else { 5867 env->cpuid_version |= value << 8; 5868 } 5869 } 5870 5871 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5872 const char *name, void *opaque, 5873 Error **errp) 5874 { 5875 X86CPU *cpu = X86_CPU(obj); 5876 CPUX86State *env = &cpu->env; 5877 uint64_t value; 5878 5879 value = (env->cpuid_version >> 4) & 0xf; 5880 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5881 visit_type_uint64(v, name, &value, errp); 5882 } 5883 5884 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5885 const char *name, void *opaque, 5886 Error **errp) 5887 { 5888 X86CPU *cpu = X86_CPU(obj); 5889 CPUX86State *env = &cpu->env; 5890 const uint64_t max = 0xff; 5891 uint64_t value; 5892 5893 if (!visit_type_uint64(v, name, &value, errp)) { 5894 return; 5895 } 5896 if (value > max) { 5897 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5898 name ? name : "null", max); 5899 return; 5900 } 5901 5902 env->cpuid_version &= ~0xf00f0; 5903 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5904 } 5905 5906 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5907 const char *name, void *opaque, 5908 Error **errp) 5909 { 5910 X86CPU *cpu = X86_CPU(obj); 5911 CPUX86State *env = &cpu->env; 5912 uint64_t value; 5913 5914 value = env->cpuid_version & 0xf; 5915 visit_type_uint64(v, name, &value, errp); 5916 } 5917 5918 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5919 const char *name, void *opaque, 5920 Error **errp) 5921 { 5922 X86CPU *cpu = X86_CPU(obj); 5923 CPUX86State *env = &cpu->env; 5924 const uint64_t max = 0xf; 5925 uint64_t value; 5926 5927 if (!visit_type_uint64(v, name, &value, errp)) { 5928 return; 5929 } 5930 if (value > max) { 5931 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5932 name ? name : "null", max); 5933 return; 5934 } 5935 5936 env->cpuid_version &= ~0xf; 5937 env->cpuid_version |= value & 0xf; 5938 } 5939 5940 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5941 { 5942 X86CPU *cpu = X86_CPU(obj); 5943 CPUX86State *env = &cpu->env; 5944 char *value; 5945 5946 value = g_malloc(CPUID_VENDOR_SZ + 1); 5947 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5948 env->cpuid_vendor3); 5949 return value; 5950 } 5951 5952 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5953 Error **errp) 5954 { 5955 X86CPU *cpu = X86_CPU(obj); 5956 CPUX86State *env = &cpu->env; 5957 int i; 5958 5959 if (strlen(value) != CPUID_VENDOR_SZ) { 5960 error_setg(errp, "value of property 'vendor' must consist of" 5961 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5962 return; 5963 } 5964 5965 env->cpuid_vendor1 = 0; 5966 env->cpuid_vendor2 = 0; 5967 env->cpuid_vendor3 = 0; 5968 for (i = 0; i < 4; i++) { 5969 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5970 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5971 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5972 } 5973 } 5974 5975 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5976 { 5977 X86CPU *cpu = X86_CPU(obj); 5978 CPUX86State *env = &cpu->env; 5979 char *value; 5980 int i; 5981 5982 value = g_malloc(48 + 1); 5983 for (i = 0; i < 48; i++) { 5984 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5985 } 5986 value[48] = '\0'; 5987 return value; 5988 } 5989 5990 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5991 Error **errp) 5992 { 5993 X86CPU *cpu = X86_CPU(obj); 5994 CPUX86State *env = &cpu->env; 5995 int c, len, i; 5996 5997 if (model_id == NULL) { 5998 model_id = ""; 5999 } 6000 len = strlen(model_id); 6001 memset(env->cpuid_model, 0, 48); 6002 for (i = 0; i < 48; i++) { 6003 if (i >= len) { 6004 c = '\0'; 6005 } else { 6006 c = (uint8_t)model_id[i]; 6007 } 6008 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 6009 } 6010 } 6011 6012 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 6013 void *opaque, Error **errp) 6014 { 6015 X86CPU *cpu = X86_CPU(obj); 6016 int64_t value; 6017 6018 value = cpu->env.tsc_khz * 1000; 6019 visit_type_int(v, name, &value, errp); 6020 } 6021 6022 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 6023 void *opaque, Error **errp) 6024 { 6025 X86CPU *cpu = X86_CPU(obj); 6026 const int64_t max = INT64_MAX; 6027 int64_t value; 6028 6029 if (!visit_type_int(v, name, &value, errp)) { 6030 return; 6031 } 6032 if (value < 0 || value > max) { 6033 error_setg(errp, "parameter '%s' can be at most %" PRId64, 6034 name ? name : "null", max); 6035 return; 6036 } 6037 6038 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 6039 } 6040 6041 /* Generic getter for "feature-words" and "filtered-features" properties */ 6042 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 6043 const char *name, void *opaque, 6044 Error **errp) 6045 { 6046 uint64_t *array = (uint64_t *)opaque; 6047 FeatureWord w; 6048 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 6049 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 6050 X86CPUFeatureWordInfoList *list = NULL; 6051 6052 for (w = 0; w < FEATURE_WORDS; w++) { 6053 FeatureWordInfo *wi = &feature_word_info[w]; 6054 /* 6055 * We didn't have MSR features when "feature-words" was 6056 * introduced. Therefore skipped other type entries. 6057 */ 6058 if (wi->type != CPUID_FEATURE_WORD) { 6059 continue; 6060 } 6061 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 6062 qwi->cpuid_input_eax = wi->cpuid.eax; 6063 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 6064 qwi->cpuid_input_ecx = wi->cpuid.ecx; 6065 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 6066 qwi->features = array[w]; 6067 6068 /* List will be in reverse order, but order shouldn't matter */ 6069 list_entries[w].next = list; 6070 list_entries[w].value = &word_infos[w]; 6071 list = &list_entries[w]; 6072 } 6073 6074 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 6075 } 6076 6077 /* Convert all '_' in a feature string option name to '-', to make feature 6078 * name conform to QOM property naming rule, which uses '-' instead of '_'. 6079 */ 6080 static inline void feat2prop(char *s) 6081 { 6082 while ((s = strchr(s, '_'))) { 6083 *s = '-'; 6084 } 6085 } 6086 6087 /* Return the feature property name for a feature flag bit */ 6088 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 6089 { 6090 const char *name; 6091 /* XSAVE components are automatically enabled by other features, 6092 * so return the original feature name instead 6093 */ 6094 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 6095 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 6096 6097 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 6098 x86_ext_save_areas[comp].bits) { 6099 w = x86_ext_save_areas[comp].feature; 6100 bitnr = ctz32(x86_ext_save_areas[comp].bits); 6101 } 6102 } 6103 6104 assert(bitnr < 64); 6105 assert(w < FEATURE_WORDS); 6106 name = feature_word_info[w].feat_names[bitnr]; 6107 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 6108 return name; 6109 } 6110 6111 /* Compatibility hack to maintain legacy +-feat semantic, 6112 * where +-feat overwrites any feature set by 6113 * feat=on|feat even if the later is parsed after +-feat 6114 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 6115 */ 6116 static GList *plus_features, *minus_features; 6117 6118 static gint compare_string(gconstpointer a, gconstpointer b) 6119 { 6120 return g_strcmp0(a, b); 6121 } 6122 6123 /* Parse "+feature,-feature,feature=foo" CPU feature string 6124 */ 6125 static void x86_cpu_parse_featurestr(const char *typename, char *features, 6126 Error **errp) 6127 { 6128 char *featurestr; /* Single 'key=value" string being parsed */ 6129 static bool cpu_globals_initialized; 6130 bool ambiguous = false; 6131 6132 if (cpu_globals_initialized) { 6133 return; 6134 } 6135 cpu_globals_initialized = true; 6136 6137 if (!features) { 6138 return; 6139 } 6140 6141 for (featurestr = strtok(features, ","); 6142 featurestr; 6143 featurestr = strtok(NULL, ",")) { 6144 const char *name; 6145 const char *val = NULL; 6146 char *eq = NULL; 6147 char num[32]; 6148 GlobalProperty *prop; 6149 6150 /* Compatibility syntax: */ 6151 if (featurestr[0] == '+') { 6152 plus_features = g_list_append(plus_features, 6153 g_strdup(featurestr + 1)); 6154 continue; 6155 } else if (featurestr[0] == '-') { 6156 minus_features = g_list_append(minus_features, 6157 g_strdup(featurestr + 1)); 6158 continue; 6159 } 6160 6161 eq = strchr(featurestr, '='); 6162 if (eq) { 6163 *eq++ = 0; 6164 val = eq; 6165 } else { 6166 val = "on"; 6167 } 6168 6169 feat2prop(featurestr); 6170 name = featurestr; 6171 6172 if (g_list_find_custom(plus_features, name, compare_string)) { 6173 warn_report("Ambiguous CPU model string. " 6174 "Don't mix both \"+%s\" and \"%s=%s\"", 6175 name, name, val); 6176 ambiguous = true; 6177 } 6178 if (g_list_find_custom(minus_features, name, compare_string)) { 6179 warn_report("Ambiguous CPU model string. " 6180 "Don't mix both \"-%s\" and \"%s=%s\"", 6181 name, name, val); 6182 ambiguous = true; 6183 } 6184 6185 /* Special case: */ 6186 if (!strcmp(name, "tsc-freq")) { 6187 int ret; 6188 uint64_t tsc_freq; 6189 6190 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 6191 if (ret < 0 || tsc_freq > INT64_MAX) { 6192 error_setg(errp, "bad numerical value %s", val); 6193 return; 6194 } 6195 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 6196 val = num; 6197 name = "tsc-frequency"; 6198 } 6199 6200 prop = g_new0(typeof(*prop), 1); 6201 prop->driver = typename; 6202 prop->property = g_strdup(name); 6203 prop->value = g_strdup(val); 6204 qdev_prop_register_global(prop); 6205 } 6206 6207 if (ambiguous) { 6208 warn_report("Compatibility of ambiguous CPU model " 6209 "strings won't be kept on future QEMU versions"); 6210 } 6211 } 6212 6213 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 6214 6215 /* Build a list with the name of all features on a feature word array */ 6216 static void x86_cpu_list_feature_names(FeatureWordArray features, 6217 strList **list) 6218 { 6219 strList **tail = list; 6220 FeatureWord w; 6221 6222 for (w = 0; w < FEATURE_WORDS; w++) { 6223 uint64_t filtered = features[w]; 6224 int i; 6225 for (i = 0; i < 64; i++) { 6226 if (filtered & (1ULL << i)) { 6227 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 6228 } 6229 } 6230 } 6231 } 6232 6233 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 6234 const char *name, void *opaque, 6235 Error **errp) 6236 { 6237 X86CPU *xc = X86_CPU(obj); 6238 strList *result = NULL; 6239 6240 x86_cpu_list_feature_names(xc->filtered_features, &result); 6241 visit_type_strList(v, "unavailable-features", &result, errp); 6242 } 6243 6244 /* Print all cpuid feature names in featureset 6245 */ 6246 static void listflags(GList *features) 6247 { 6248 size_t len = 0; 6249 GList *tmp; 6250 6251 for (tmp = features; tmp; tmp = tmp->next) { 6252 const char *name = tmp->data; 6253 if ((len + strlen(name) + 1) >= 75) { 6254 qemu_printf("\n"); 6255 len = 0; 6256 } 6257 qemu_printf("%s%s", len == 0 ? " " : " ", name); 6258 len += strlen(name) + 1; 6259 } 6260 qemu_printf("\n"); 6261 } 6262 6263 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 6264 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d) 6265 { 6266 ObjectClass *class_a = (ObjectClass *)a; 6267 ObjectClass *class_b = (ObjectClass *)b; 6268 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 6269 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 6270 int ret; 6271 6272 if (cc_a->ordering != cc_b->ordering) { 6273 ret = cc_a->ordering - cc_b->ordering; 6274 } else { 6275 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 6276 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 6277 ret = strcmp(name_a, name_b); 6278 } 6279 return ret; 6280 } 6281 6282 static GSList *get_sorted_cpu_model_list(void) 6283 { 6284 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 6285 list = g_slist_sort_with_data(list, x86_cpu_list_compare, NULL); 6286 return list; 6287 } 6288 6289 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 6290 { 6291 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 6292 char *r = object_property_get_str(obj, "model-id", &error_abort); 6293 object_unref(obj); 6294 return r; 6295 } 6296 6297 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 6298 { 6299 X86CPUVersion version; 6300 6301 if (!cc->model || !cc->model->is_alias) { 6302 return NULL; 6303 } 6304 version = x86_cpu_model_resolve_version(cc->model); 6305 if (version <= 0) { 6306 return NULL; 6307 } 6308 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 6309 } 6310 6311 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 6312 { 6313 ObjectClass *oc = data; 6314 X86CPUClass *cc = X86_CPU_CLASS(oc); 6315 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6316 g_autofree char *desc = g_strdup(cc->model_description); 6317 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6318 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6319 6320 if (!desc && alias_of) { 6321 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6322 desc = g_strdup("(alias configured by machine type)"); 6323 } else { 6324 desc = g_strdup_printf("(alias of %s)", alias_of); 6325 } 6326 } 6327 if (!desc && cc->model && cc->model->note) { 6328 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6329 } 6330 if (!desc) { 6331 desc = g_strdup(model_id); 6332 } 6333 6334 if (cc->model && cc->model->cpudef->deprecation_note) { 6335 g_autofree char *olddesc = desc; 6336 desc = g_strdup_printf("%s (deprecated)", olddesc); 6337 } 6338 6339 qemu_printf(" %-20s %s\n", name, desc); 6340 } 6341 6342 static gint strcmp_wrap(gconstpointer a, gconstpointer b, gpointer d) 6343 { 6344 return strcmp(a, b); 6345 } 6346 6347 /* list available CPU models and flags */ 6348 static void x86_cpu_list(void) 6349 { 6350 int i, j; 6351 GSList *list; 6352 GList *names = NULL; 6353 6354 qemu_printf("Available CPUs:\n"); 6355 list = get_sorted_cpu_model_list(); 6356 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6357 g_slist_free(list); 6358 6359 names = NULL; 6360 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6361 FeatureWordInfo *fw = &feature_word_info[i]; 6362 for (j = 0; j < 64; j++) { 6363 if (fw->feat_names[j]) { 6364 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6365 } 6366 } 6367 } 6368 6369 names = g_list_sort_with_data(names, strcmp_wrap, NULL); 6370 6371 qemu_printf("\nRecognized CPUID flags:\n"); 6372 listflags(names); 6373 qemu_printf("\n"); 6374 g_list_free(names); 6375 } 6376 6377 #ifndef CONFIG_USER_ONLY 6378 6379 /* Check for missing features that may prevent the CPU class from 6380 * running using the current machine and accelerator. 6381 */ 6382 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6383 strList **list) 6384 { 6385 strList **tail = list; 6386 X86CPU *xc; 6387 Error *err = NULL; 6388 6389 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6390 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6391 return; 6392 } 6393 6394 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6395 6396 x86_cpu_expand_features(xc, &err); 6397 if (err) { 6398 /* Errors at x86_cpu_expand_features should never happen, 6399 * but in case it does, just report the model as not 6400 * runnable at all using the "type" property. 6401 */ 6402 QAPI_LIST_APPEND(tail, g_strdup("type")); 6403 error_free(err); 6404 } 6405 6406 x86_cpu_filter_features(xc, false); 6407 6408 x86_cpu_list_feature_names(xc->filtered_features, tail); 6409 6410 object_unref(OBJECT(xc)); 6411 } 6412 6413 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6414 { 6415 ObjectClass *oc = data; 6416 X86CPUClass *cc = X86_CPU_CLASS(oc); 6417 CpuDefinitionInfoList **cpu_list = user_data; 6418 CpuDefinitionInfo *info; 6419 6420 info = g_malloc0(sizeof(*info)); 6421 info->name = x86_cpu_class_get_model_name(cc); 6422 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6423 info->has_unavailable_features = true; 6424 info->q_typename = g_strdup(object_class_get_name(oc)); 6425 info->migration_safe = cc->migration_safe; 6426 info->has_migration_safe = true; 6427 info->q_static = cc->static_model; 6428 if (cc->model && cc->model->cpudef->deprecation_note) { 6429 info->deprecated = true; 6430 } else { 6431 info->deprecated = false; 6432 } 6433 /* 6434 * Old machine types won't report aliases, so that alias translation 6435 * doesn't break compatibility with previous QEMU versions. 6436 */ 6437 if (default_cpu_version != CPU_VERSION_LEGACY) { 6438 info->alias_of = x86_cpu_class_get_alias_of(cc); 6439 } 6440 6441 QAPI_LIST_PREPEND(*cpu_list, info); 6442 } 6443 6444 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6445 { 6446 CpuDefinitionInfoList *cpu_list = NULL; 6447 GSList *list = get_sorted_cpu_model_list(); 6448 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6449 g_slist_free(list); 6450 return cpu_list; 6451 } 6452 6453 #endif /* !CONFIG_USER_ONLY */ 6454 6455 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6456 { 6457 FeatureWordInfo *wi = &feature_word_info[w]; 6458 uint64_t r = 0; 6459 uint64_t unavail = 0; 6460 6461 if (kvm_enabled()) { 6462 switch (wi->type) { 6463 case CPUID_FEATURE_WORD: 6464 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6465 wi->cpuid.ecx, 6466 wi->cpuid.reg); 6467 break; 6468 case MSR_FEATURE_WORD: 6469 r = kvm_arch_get_supported_msr_feature(kvm_state, 6470 wi->msr.index); 6471 break; 6472 } 6473 } else if (hvf_enabled()) { 6474 if (wi->type != CPUID_FEATURE_WORD) { 6475 return 0; 6476 } 6477 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6478 wi->cpuid.ecx, 6479 wi->cpuid.reg); 6480 } else if (tcg_enabled()) { 6481 r = wi->tcg_features; 6482 } else { 6483 return ~0; 6484 } 6485 6486 switch (w) { 6487 #ifndef TARGET_X86_64 6488 case FEAT_8000_0001_EDX: 6489 /* 6490 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6491 * way for userspace to get out of its 32-bit jail, we can leave 6492 * the LM bit set. 6493 */ 6494 unavail = tcg_enabled() 6495 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6496 : CPUID_EXT2_LM; 6497 break; 6498 #endif 6499 6500 case FEAT_8000_0007_EBX: 6501 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6502 /* Disable AMD machine check architecture for Intel CPU. */ 6503 unavail = ~0; 6504 } 6505 break; 6506 6507 case FEAT_7_0_EBX: 6508 #ifndef CONFIG_USER_ONLY 6509 if (!check_sgx_support()) { 6510 unavail = CPUID_7_0_EBX_SGX; 6511 } 6512 #endif 6513 break; 6514 case FEAT_7_0_ECX: 6515 #ifndef CONFIG_USER_ONLY 6516 if (!check_sgx_support()) { 6517 unavail = CPUID_7_0_ECX_SGX_LC; 6518 } 6519 #endif 6520 break; 6521 6522 default: 6523 break; 6524 } 6525 6526 r &= ~unavail; 6527 if (cpu && cpu->migratable) { 6528 r &= x86_cpu_get_migratable_flags(cpu, w); 6529 } 6530 return r; 6531 } 6532 6533 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6534 uint32_t *eax, uint32_t *ebx, 6535 uint32_t *ecx, uint32_t *edx) 6536 { 6537 if (kvm_enabled()) { 6538 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6539 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6540 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6541 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6542 } else if (hvf_enabled()) { 6543 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6544 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6545 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6546 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6547 } else { 6548 *eax = 0; 6549 *ebx = 0; 6550 *ecx = 0; 6551 *edx = 0; 6552 } 6553 } 6554 6555 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6556 uint32_t *eax, uint32_t *ebx, 6557 uint32_t *ecx, uint32_t *edx) 6558 { 6559 uint32_t level, unused; 6560 6561 /* Only return valid host leaves. */ 6562 switch (func) { 6563 case 2: 6564 case 4: 6565 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6566 break; 6567 case 0x80000005: 6568 case 0x80000006: 6569 case 0x8000001d: 6570 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6571 break; 6572 default: 6573 return; 6574 } 6575 6576 if (func > level) { 6577 *eax = 0; 6578 *ebx = 0; 6579 *ecx = 0; 6580 *edx = 0; 6581 } else { 6582 host_cpuid(func, index, eax, ebx, ecx, edx); 6583 } 6584 } 6585 6586 /* 6587 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6588 */ 6589 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6590 { 6591 PropValue *pv; 6592 for (pv = props; pv->prop; pv++) { 6593 if (!pv->value) { 6594 continue; 6595 } 6596 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6597 &error_abort); 6598 } 6599 } 6600 6601 /* 6602 * Apply properties for the CPU model version specified in model. 6603 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6604 */ 6605 6606 static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) 6607 { 6608 const X86CPUVersionDefinition *vdef; 6609 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6610 6611 if (version == CPU_VERSION_LEGACY) { 6612 return; 6613 } 6614 6615 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6616 PropValue *p; 6617 6618 for (p = vdef->props; p && p->prop; p++) { 6619 object_property_parse(OBJECT(cpu), p->prop, p->value, 6620 &error_abort); 6621 } 6622 6623 if (vdef->version == version) { 6624 break; 6625 } 6626 } 6627 6628 /* 6629 * If we reached the end of the list, version number was invalid 6630 */ 6631 assert(vdef->version == version); 6632 } 6633 6634 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6635 const X86CPUModel *model) 6636 { 6637 const X86CPUVersionDefinition *vdef; 6638 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6639 const CPUCaches *cache_info = model->cpudef->cache_info; 6640 6641 if (version == CPU_VERSION_LEGACY) { 6642 return cache_info; 6643 } 6644 6645 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6646 if (vdef->cache_info) { 6647 cache_info = vdef->cache_info; 6648 } 6649 6650 if (vdef->version == version) { 6651 break; 6652 } 6653 } 6654 6655 assert(vdef->version == version); 6656 return cache_info; 6657 } 6658 6659 /* 6660 * Load data from X86CPUDefinition into a X86CPU object. 6661 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6662 */ 6663 static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) 6664 { 6665 const X86CPUDefinition *def = model->cpudef; 6666 CPUX86State *env = &cpu->env; 6667 FeatureWord w; 6668 6669 /*NOTE: any property set by this function should be returned by 6670 * x86_cpu_static_props(), so static expansion of 6671 * query-cpu-model-expansion is always complete. 6672 */ 6673 6674 /* CPU models only set _minimum_ values for level/xlevel: */ 6675 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6676 &error_abort); 6677 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6678 &error_abort); 6679 6680 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6681 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6682 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6683 &error_abort); 6684 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6685 &error_abort); 6686 for (w = 0; w < FEATURE_WORDS; w++) { 6687 env->features[w] = def->features[w]; 6688 } 6689 6690 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6691 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6692 6693 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6694 6695 /* sysenter isn't supported in compatibility mode on AMD, 6696 * syscall isn't supported in compatibility mode on Intel. 6697 * Normally we advertise the actual CPU vendor, but you can 6698 * override this using the 'vendor' property if you want to use 6699 * KVM's sysenter/syscall emulation in compatibility mode and 6700 * when doing cross vendor migration 6701 */ 6702 6703 /* 6704 * vendor property is set here but then overloaded with the 6705 * host cpu vendor for KVM and HVF. 6706 */ 6707 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6708 6709 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 6710 &error_abort); 6711 6712 x86_cpu_apply_version_props(cpu, model); 6713 6714 /* 6715 * Properties in versioned CPU model are not user specified features. 6716 * We can simply clear env->user_features here since it will be filled later 6717 * in x86_cpu_expand_features() based on plus_features and minus_features. 6718 */ 6719 memset(&env->user_features, 0, sizeof(env->user_features)); 6720 } 6721 6722 static const gchar *x86_gdb_arch_name(CPUState *cs) 6723 { 6724 #ifdef TARGET_X86_64 6725 return "i386:x86-64"; 6726 #else 6727 return "i386"; 6728 #endif 6729 } 6730 6731 static void x86_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 6732 { 6733 const X86CPUModel *model = data; 6734 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6735 CPUClass *cc = CPU_CLASS(oc); 6736 6737 xcc->model = model; 6738 xcc->migration_safe = true; 6739 cc->deprecation_note = model->cpudef->deprecation_note; 6740 } 6741 6742 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6743 { 6744 g_autofree char *typename = x86_cpu_type_name(name); 6745 TypeInfo ti = { 6746 .name = typename, 6747 .parent = TYPE_X86_CPU, 6748 .class_init = x86_cpu_cpudef_class_init, 6749 .class_data = model, 6750 }; 6751 6752 type_register_static(&ti); 6753 } 6754 6755 6756 /* 6757 * register builtin_x86_defs; 6758 * "max", "base" and subclasses ("host") are not registered here. 6759 * See x86_cpu_register_types for all model registrations. 6760 */ 6761 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6762 { 6763 X86CPUModel *m; 6764 const X86CPUVersionDefinition *vdef; 6765 6766 /* AMD aliases are handled at runtime based on CPUID vendor, so 6767 * they shouldn't be set on the CPU model table. 6768 */ 6769 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6770 /* catch mistakes instead of silently truncating model_id when too long */ 6771 assert(def->model_id && strlen(def->model_id) <= 48); 6772 6773 /* Unversioned model: */ 6774 m = g_new0(X86CPUModel, 1); 6775 m->cpudef = def; 6776 m->version = CPU_VERSION_AUTO; 6777 m->is_alias = true; 6778 x86_register_cpu_model_type(def->name, m); 6779 6780 /* Versioned models: */ 6781 6782 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6783 g_autofree char *name = 6784 x86_cpu_versioned_model_name(def, vdef->version); 6785 6786 m = g_new0(X86CPUModel, 1); 6787 m->cpudef = def; 6788 m->version = vdef->version; 6789 m->note = vdef->note; 6790 x86_register_cpu_model_type(name, m); 6791 6792 if (vdef->alias) { 6793 X86CPUModel *am = g_new0(X86CPUModel, 1); 6794 am->cpudef = def; 6795 am->version = vdef->version; 6796 am->is_alias = true; 6797 x86_register_cpu_model_type(vdef->alias, am); 6798 } 6799 } 6800 6801 } 6802 6803 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6804 { 6805 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6806 return 57; /* 57 bits virtual */ 6807 } else { 6808 return 48; /* 48 bits virtual */ 6809 } 6810 } 6811 6812 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6813 uint32_t *eax, uint32_t *ebx, 6814 uint32_t *ecx, uint32_t *edx) 6815 { 6816 X86CPU *cpu = env_archcpu(env); 6817 CPUState *cs = env_cpu(env); 6818 uint32_t limit; 6819 uint32_t signature[3]; 6820 X86CPUTopoInfo *topo_info = &env->topo_info; 6821 uint32_t threads_per_pkg; 6822 6823 threads_per_pkg = x86_threads_per_pkg(topo_info); 6824 6825 /* Calculate & apply limits for different index ranges */ 6826 if (index >= 0xC0000000) { 6827 limit = env->cpuid_xlevel2; 6828 } else if (index >= 0x80000000) { 6829 limit = env->cpuid_xlevel; 6830 } else if (index >= 0x40000000) { 6831 limit = 0x40000001; 6832 } else { 6833 limit = env->cpuid_level; 6834 } 6835 6836 if (index > limit) { 6837 /* Intel documentation states that invalid EAX input will 6838 * return the same information as EAX=cpuid_level 6839 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6840 */ 6841 index = env->cpuid_level; 6842 } 6843 6844 switch(index) { 6845 case 0: 6846 *eax = env->cpuid_level; 6847 *ebx = env->cpuid_vendor1; 6848 *edx = env->cpuid_vendor2; 6849 *ecx = env->cpuid_vendor3; 6850 break; 6851 case 1: 6852 *eax = env->cpuid_version; 6853 *ebx = (cpu->apic_id << 24) | 6854 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6855 *ecx = env->features[FEAT_1_ECX]; 6856 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6857 *ecx |= CPUID_EXT_OSXSAVE; 6858 } 6859 *edx = env->features[FEAT_1_EDX]; 6860 if (threads_per_pkg > 1) { 6861 *ebx |= threads_per_pkg << 16; 6862 } 6863 if (!cpu->enable_pmu) { 6864 *ecx &= ~CPUID_EXT_PDCM; 6865 } 6866 break; 6867 case 2: 6868 /* cache info: needed for Pentium Pro compatibility */ 6869 if (cpu->cache_info_passthrough) { 6870 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6871 break; 6872 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6873 *eax = *ebx = *ecx = *edx = 0; 6874 break; 6875 } 6876 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6877 *ebx = 0; 6878 if (!cpu->enable_l3_cache) { 6879 *ecx = 0; 6880 } else { 6881 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6882 } 6883 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6884 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6885 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6886 break; 6887 case 4: 6888 /* cache info: needed for Core compatibility */ 6889 if (cpu->cache_info_passthrough) { 6890 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6891 /* 6892 * QEMU has its own number of cores/logical cpus, 6893 * set 24..14, 31..26 bit to configured values 6894 */ 6895 if (*eax & 31) { 6896 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6897 6898 *eax &= ~0xFC000000; 6899 *eax |= max_core_ids_in_package(topo_info) << 26; 6900 if (host_vcpus_per_cache > threads_per_pkg) { 6901 *eax &= ~0x3FFC000; 6902 6903 /* Share the cache at package level. */ 6904 *eax |= max_thread_ids_for_cache(topo_info, 6905 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 6906 } 6907 } 6908 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6909 *eax = *ebx = *ecx = *edx = 0; 6910 } else { 6911 *eax = 0; 6912 6913 switch (count) { 6914 case 0: /* L1 dcache info */ 6915 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6916 topo_info, 6917 eax, ebx, ecx, edx); 6918 if (!cpu->l1_cache_per_core) { 6919 *eax &= ~MAKE_64BIT_MASK(14, 12); 6920 } 6921 break; 6922 case 1: /* L1 icache info */ 6923 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6924 topo_info, 6925 eax, ebx, ecx, edx); 6926 if (!cpu->l1_cache_per_core) { 6927 *eax &= ~MAKE_64BIT_MASK(14, 12); 6928 } 6929 break; 6930 case 2: /* L2 cache info */ 6931 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6932 topo_info, 6933 eax, ebx, ecx, edx); 6934 break; 6935 case 3: /* L3 cache info */ 6936 if (cpu->enable_l3_cache) { 6937 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6938 topo_info, 6939 eax, ebx, ecx, edx); 6940 break; 6941 } 6942 /* fall through */ 6943 default: /* end of info */ 6944 *eax = *ebx = *ecx = *edx = 0; 6945 break; 6946 } 6947 } 6948 break; 6949 case 5: 6950 /* MONITOR/MWAIT Leaf */ 6951 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6952 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6953 *ecx = cpu->mwait.ecx; /* flags */ 6954 *edx = cpu->mwait.edx; /* mwait substates */ 6955 break; 6956 case 6: 6957 /* Thermal and Power Leaf */ 6958 *eax = env->features[FEAT_6_EAX]; 6959 *ebx = 0; 6960 *ecx = 0; 6961 *edx = 0; 6962 break; 6963 case 7: 6964 /* Structured Extended Feature Flags Enumeration Leaf */ 6965 if (count == 0) { 6966 /* Maximum ECX value for sub-leaves */ 6967 *eax = env->cpuid_level_func7; 6968 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6969 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6970 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6971 *ecx |= CPUID_7_0_ECX_OSPKE; 6972 } 6973 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6974 } else if (count == 1) { 6975 *eax = env->features[FEAT_7_1_EAX]; 6976 *edx = env->features[FEAT_7_1_EDX]; 6977 *ebx = 0; 6978 *ecx = 0; 6979 } else if (count == 2) { 6980 *edx = env->features[FEAT_7_2_EDX]; 6981 *eax = 0; 6982 *ebx = 0; 6983 *ecx = 0; 6984 } else { 6985 *eax = 0; 6986 *ebx = 0; 6987 *ecx = 0; 6988 *edx = 0; 6989 } 6990 break; 6991 case 9: 6992 /* Direct Cache Access Information Leaf */ 6993 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6994 *ebx = 0; 6995 *ecx = 0; 6996 *edx = 0; 6997 break; 6998 case 0xA: 6999 /* Architectural Performance Monitoring Leaf */ 7000 if (cpu->enable_pmu) { 7001 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 7002 } else { 7003 *eax = 0; 7004 *ebx = 0; 7005 *ecx = 0; 7006 *edx = 0; 7007 } 7008 break; 7009 case 0xB: 7010 /* Extended Topology Enumeration Leaf */ 7011 if (!cpu->enable_cpuid_0xb) { 7012 *eax = *ebx = *ecx = *edx = 0; 7013 break; 7014 } 7015 7016 *ecx = count & 0xff; 7017 *edx = cpu->apic_id; 7018 7019 switch (count) { 7020 case 0: 7021 *eax = apicid_core_offset(topo_info); 7022 *ebx = topo_info->threads_per_core; 7023 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 7024 break; 7025 case 1: 7026 *eax = apicid_pkg_offset(topo_info); 7027 *ebx = threads_per_pkg; 7028 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 7029 break; 7030 default: 7031 *eax = 0; 7032 *ebx = 0; 7033 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 7034 } 7035 7036 assert(!(*eax & ~0x1f)); 7037 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 7038 break; 7039 case 0x1C: 7040 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7041 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 7042 *edx = 0; 7043 } 7044 break; 7045 case 0x1F: 7046 /* V2 Extended Topology Enumeration Leaf */ 7047 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 7048 *eax = *ebx = *ecx = *edx = 0; 7049 break; 7050 } 7051 7052 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 7053 break; 7054 case 0xD: { 7055 /* Processor Extended State */ 7056 *eax = 0; 7057 *ebx = 0; 7058 *ecx = 0; 7059 *edx = 0; 7060 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7061 break; 7062 } 7063 7064 if (count == 0) { 7065 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 7066 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 7067 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 7068 /* 7069 * The initial value of xcr0 and ebx == 0, On host without kvm 7070 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 7071 * even through guest update xcr0, this will crash some legacy guest 7072 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 7073 */ 7074 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 7075 } else if (count == 1) { 7076 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 7077 x86_cpu_xsave_xss_components(cpu); 7078 7079 *eax = env->features[FEAT_XSAVE]; 7080 *ebx = xsave_area_size(xstate, true); 7081 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 7082 *edx = env->features[FEAT_XSAVE_XSS_HI]; 7083 if (kvm_enabled() && cpu->enable_pmu && 7084 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 7085 (*eax & CPUID_XSAVE_XSAVES)) { 7086 *ecx |= XSTATE_ARCH_LBR_MASK; 7087 } else { 7088 *ecx &= ~XSTATE_ARCH_LBR_MASK; 7089 } 7090 } else if (count == 0xf && cpu->enable_pmu 7091 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7092 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 7093 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 7094 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 7095 7096 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 7097 *eax = esa->size; 7098 *ebx = esa->offset; 7099 *ecx = esa->ecx & 7100 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 7101 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 7102 *eax = esa->size; 7103 *ebx = 0; 7104 *ecx = 1; 7105 } 7106 } 7107 break; 7108 } 7109 case 0x12: 7110 #ifndef CONFIG_USER_ONLY 7111 if (!kvm_enabled() || 7112 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 7113 *eax = *ebx = *ecx = *edx = 0; 7114 break; 7115 } 7116 7117 /* 7118 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 7119 * the EPC properties, e.g. confidentiality and integrity, from the 7120 * host's first EPC section, i.e. assume there is one EPC section or 7121 * that all EPC sections have the same security properties. 7122 */ 7123 if (count > 1) { 7124 uint64_t epc_addr, epc_size; 7125 7126 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 7127 *eax = *ebx = *ecx = *edx = 0; 7128 break; 7129 } 7130 host_cpuid(index, 2, eax, ebx, ecx, edx); 7131 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 7132 *ebx = (uint32_t)(epc_addr >> 32); 7133 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 7134 *edx = (uint32_t)(epc_size >> 32); 7135 break; 7136 } 7137 7138 /* 7139 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 7140 * and KVM, i.e. QEMU cannot emulate features to override what KVM 7141 * supports. Features can be further restricted by userspace, but not 7142 * made more permissive. 7143 */ 7144 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 7145 7146 if (count == 0) { 7147 *eax &= env->features[FEAT_SGX_12_0_EAX]; 7148 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 7149 } else { 7150 *eax &= env->features[FEAT_SGX_12_1_EAX]; 7151 *ebx &= 0; /* ebx reserve */ 7152 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 7153 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 7154 7155 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 7156 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 7157 7158 /* Access to PROVISIONKEY requires additional credentials. */ 7159 if ((*eax & (1U << 4)) && 7160 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 7161 *eax &= ~(1U << 4); 7162 } 7163 } 7164 #endif 7165 break; 7166 case 0x14: { 7167 /* Intel Processor Trace Enumeration */ 7168 *eax = 0; 7169 *ebx = 0; 7170 *ecx = 0; 7171 *edx = 0; 7172 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 7173 !kvm_enabled()) { 7174 break; 7175 } 7176 7177 /* 7178 * If these are changed, they should stay in sync with 7179 * x86_cpu_filter_features(). 7180 */ 7181 if (count == 0) { 7182 *eax = INTEL_PT_MAX_SUBLEAF; 7183 *ebx = INTEL_PT_MINIMAL_EBX; 7184 *ecx = INTEL_PT_MINIMAL_ECX; 7185 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 7186 *ecx |= CPUID_14_0_ECX_LIP; 7187 } 7188 } else if (count == 1) { 7189 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 7190 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 7191 } 7192 break; 7193 } 7194 case 0x1D: { 7195 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 7196 *eax = 0; 7197 *ebx = 0; 7198 *ecx = 0; 7199 *edx = 0; 7200 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7201 break; 7202 } 7203 7204 if (count == 0) { 7205 /* Highest numbered palette subleaf */ 7206 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 7207 } else if (count == 1) { 7208 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 7209 (INTEL_AMX_BYTES_PER_TILE << 16); 7210 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 7211 *ecx = INTEL_AMX_TILE_MAX_ROWS; 7212 } 7213 break; 7214 } 7215 case 0x1E: { 7216 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 7217 *eax = 0; 7218 *ebx = 0; 7219 *ecx = 0; 7220 *edx = 0; 7221 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7222 break; 7223 } 7224 7225 if (count == 0) { 7226 /* Highest numbered palette subleaf */ 7227 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 7228 } 7229 break; 7230 } 7231 case 0x24: { 7232 *eax = 0; 7233 *ebx = 0; 7234 *ecx = 0; 7235 *edx = 0; 7236 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 7237 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 7238 } 7239 break; 7240 } 7241 case 0x40000000: 7242 /* 7243 * CPUID code in kvm_arch_init_vcpu() ignores stuff 7244 * set here, but we restrict to TCG none the less. 7245 */ 7246 if (tcg_enabled() && cpu->expose_tcg) { 7247 memcpy(signature, "TCGTCGTCGTCG", 12); 7248 *eax = 0x40000001; 7249 *ebx = signature[0]; 7250 *ecx = signature[1]; 7251 *edx = signature[2]; 7252 } else { 7253 *eax = 0; 7254 *ebx = 0; 7255 *ecx = 0; 7256 *edx = 0; 7257 } 7258 break; 7259 case 0x40000001: 7260 *eax = 0; 7261 *ebx = 0; 7262 *ecx = 0; 7263 *edx = 0; 7264 break; 7265 case 0x80000000: 7266 *eax = env->cpuid_xlevel; 7267 *ebx = env->cpuid_vendor1; 7268 *edx = env->cpuid_vendor2; 7269 *ecx = env->cpuid_vendor3; 7270 break; 7271 case 0x80000001: 7272 *eax = env->cpuid_version; 7273 *ebx = 0; 7274 *ecx = env->features[FEAT_8000_0001_ECX]; 7275 *edx = env->features[FEAT_8000_0001_EDX]; 7276 7277 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 7278 !(env->hflags & HF_LMA_MASK)) { 7279 *edx &= ~CPUID_EXT2_SYSCALL; 7280 } 7281 break; 7282 case 0x80000002: 7283 case 0x80000003: 7284 case 0x80000004: 7285 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 7286 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 7287 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 7288 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 7289 break; 7290 case 0x80000005: 7291 /* cache info (L1 cache) */ 7292 if (cpu->cache_info_passthrough) { 7293 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7294 break; 7295 } 7296 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 7297 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 7298 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 7299 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7300 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7301 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7302 break; 7303 case 0x80000006: 7304 /* cache info (L2 cache) */ 7305 if (cpu->cache_info_passthrough) { 7306 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7307 break; 7308 } 7309 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7310 (L2_DTLB_2M_ENTRIES << 16) | 7311 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7312 (L2_ITLB_2M_ENTRIES); 7313 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7314 (L2_DTLB_4K_ENTRIES << 16) | 7315 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7316 (L2_ITLB_4K_ENTRIES); 7317 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7318 cpu->enable_l3_cache ? 7319 env->cache_info_amd.l3_cache : NULL, 7320 ecx, edx); 7321 break; 7322 case 0x80000007: 7323 *eax = 0; 7324 *ebx = env->features[FEAT_8000_0007_EBX]; 7325 *ecx = 0; 7326 *edx = env->features[FEAT_8000_0007_EDX]; 7327 break; 7328 case 0x80000008: 7329 /* virtual & phys address size in low 2 bytes. */ 7330 *eax = cpu->phys_bits; 7331 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7332 /* 64 bit processor */ 7333 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7334 *eax |= (cpu->guest_phys_bits << 16); 7335 } 7336 *ebx = env->features[FEAT_8000_0008_EBX]; 7337 if (threads_per_pkg > 1) { 7338 /* 7339 * Bits 15:12 is "The number of bits in the initial 7340 * Core::X86::Apic::ApicId[ApicId] value that indicate 7341 * thread ID within a package". 7342 * Bits 7:0 is "The number of threads in the package is NC+1" 7343 */ 7344 *ecx = (apicid_pkg_offset(topo_info) << 12) | 7345 (threads_per_pkg - 1); 7346 } else { 7347 *ecx = 0; 7348 } 7349 *edx = 0; 7350 break; 7351 case 0x8000000A: 7352 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7353 *eax = 0x00000001; /* SVM Revision */ 7354 *ebx = 0x00000010; /* nr of ASIDs */ 7355 *ecx = 0; 7356 *edx = env->features[FEAT_SVM]; /* optional features */ 7357 } else { 7358 *eax = 0; 7359 *ebx = 0; 7360 *ecx = 0; 7361 *edx = 0; 7362 } 7363 break; 7364 case 0x8000001D: 7365 *eax = 0; 7366 if (cpu->cache_info_passthrough) { 7367 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7368 break; 7369 } 7370 switch (count) { 7371 case 0: /* L1 dcache info */ 7372 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7373 topo_info, eax, ebx, ecx, edx); 7374 break; 7375 case 1: /* L1 icache info */ 7376 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7377 topo_info, eax, ebx, ecx, edx); 7378 break; 7379 case 2: /* L2 cache info */ 7380 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7381 topo_info, eax, ebx, ecx, edx); 7382 break; 7383 case 3: /* L3 cache info */ 7384 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7385 topo_info, eax, ebx, ecx, edx); 7386 break; 7387 default: /* end of info */ 7388 *eax = *ebx = *ecx = *edx = 0; 7389 break; 7390 } 7391 if (cpu->amd_topoext_features_only) { 7392 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7393 } 7394 break; 7395 case 0x8000001E: 7396 if (cpu->core_id <= 255) { 7397 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 7398 } else { 7399 *eax = 0; 7400 *ebx = 0; 7401 *ecx = 0; 7402 *edx = 0; 7403 } 7404 break; 7405 case 0x80000022: 7406 *eax = *ebx = *ecx = *edx = 0; 7407 /* AMD Extended Performance Monitoring and Debug */ 7408 if (kvm_enabled() && cpu->enable_pmu && 7409 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7410 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7411 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7412 R_EBX) & 0xf; 7413 } 7414 break; 7415 case 0xC0000000: 7416 *eax = env->cpuid_xlevel2; 7417 *ebx = 0; 7418 *ecx = 0; 7419 *edx = 0; 7420 break; 7421 case 0xC0000001: 7422 /* Support for VIA CPU's CPUID instruction */ 7423 *eax = env->cpuid_version; 7424 *ebx = 0; 7425 *ecx = 0; 7426 *edx = env->features[FEAT_C000_0001_EDX]; 7427 break; 7428 case 0xC0000002: 7429 case 0xC0000003: 7430 case 0xC0000004: 7431 /* Reserved for the future, and now filled with zero */ 7432 *eax = 0; 7433 *ebx = 0; 7434 *ecx = 0; 7435 *edx = 0; 7436 break; 7437 case 0x8000001F: 7438 *eax = *ebx = *ecx = *edx = 0; 7439 if (sev_enabled()) { 7440 *eax = 0x2; 7441 *eax |= sev_es_enabled() ? 0x8 : 0; 7442 *eax |= sev_snp_enabled() ? 0x10 : 0; 7443 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7444 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7445 } 7446 break; 7447 case 0x80000021: 7448 *eax = *ebx = *ecx = *edx = 0; 7449 *eax = env->features[FEAT_8000_0021_EAX]; 7450 *ebx = env->features[FEAT_8000_0021_EBX]; 7451 break; 7452 default: 7453 /* reserved values: zero */ 7454 *eax = 0; 7455 *ebx = 0; 7456 *ecx = 0; 7457 *edx = 0; 7458 break; 7459 } 7460 } 7461 7462 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7463 { 7464 #ifndef CONFIG_USER_ONLY 7465 /* Those default values are defined in Skylake HW */ 7466 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7467 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7468 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7469 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7470 #endif 7471 } 7472 7473 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7474 { 7475 if (!esa->size) { 7476 return false; 7477 } 7478 7479 if (env->features[esa->feature] & esa->bits) { 7480 return true; 7481 } 7482 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7483 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7484 return true; 7485 } 7486 7487 return false; 7488 } 7489 7490 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7491 { 7492 CPUState *cs = CPU(obj); 7493 X86CPU *cpu = X86_CPU(cs); 7494 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7495 CPUX86State *env = &cpu->env; 7496 target_ulong cr4; 7497 uint64_t xcr0; 7498 int i; 7499 7500 if (xcc->parent_phases.hold) { 7501 xcc->parent_phases.hold(obj, type); 7502 } 7503 7504 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7505 7506 if (tcg_enabled()) { 7507 cpu_init_fp_statuses(env); 7508 } 7509 7510 env->old_exception = -1; 7511 7512 /* init to reset state */ 7513 env->int_ctl = 0; 7514 env->hflags2 |= HF2_GIF_MASK; 7515 env->hflags2 |= HF2_VGIF_MASK; 7516 env->hflags &= ~HF_GUEST_MASK; 7517 7518 cpu_x86_update_cr0(env, 0x60000010); 7519 env->a20_mask = ~0x0; 7520 env->smbase = 0x30000; 7521 env->msr_smi_count = 0; 7522 7523 env->idt.limit = 0xffff; 7524 env->gdt.limit = 0xffff; 7525 env->ldt.limit = 0xffff; 7526 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7527 env->tr.limit = 0xffff; 7528 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7529 7530 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7531 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7532 DESC_R_MASK | DESC_A_MASK); 7533 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7534 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7535 DESC_A_MASK); 7536 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7537 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7538 DESC_A_MASK); 7539 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7540 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7541 DESC_A_MASK); 7542 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7543 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7544 DESC_A_MASK); 7545 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7546 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7547 DESC_A_MASK); 7548 7549 env->eip = 0xfff0; 7550 env->regs[R_EDX] = env->cpuid_version; 7551 7552 env->eflags = 0x2; 7553 7554 /* FPU init */ 7555 for (i = 0; i < 8; i++) { 7556 env->fptags[i] = 1; 7557 } 7558 cpu_set_fpuc(env, 0x37f); 7559 7560 env->mxcsr = 0x1f80; 7561 /* All units are in INIT state. */ 7562 env->xstate_bv = 0; 7563 7564 env->pat = 0x0007040600070406ULL; 7565 7566 if (kvm_enabled()) { 7567 /* 7568 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7569 * a new CPU, use 1 instead to force a reset. 7570 */ 7571 if (env->tsc != 0) { 7572 env->tsc = 1; 7573 } 7574 } else { 7575 env->tsc = 0; 7576 } 7577 7578 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7579 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7580 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7581 } 7582 7583 memset(env->dr, 0, sizeof(env->dr)); 7584 env->dr[6] = DR6_FIXED_1; 7585 env->dr[7] = DR7_FIXED_1; 7586 cpu_breakpoint_remove_all(cs, BP_CPU); 7587 cpu_watchpoint_remove_all(cs, BP_CPU); 7588 7589 cr4 = 0; 7590 xcr0 = XSTATE_FP_MASK; 7591 7592 #ifdef CONFIG_USER_ONLY 7593 /* Enable all the features for user-mode. */ 7594 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7595 xcr0 |= XSTATE_SSE_MASK; 7596 } 7597 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7598 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7599 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7600 continue; 7601 } 7602 if (cpuid_has_xsave_feature(env, esa)) { 7603 xcr0 |= 1ull << i; 7604 } 7605 } 7606 7607 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7608 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7609 } 7610 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7611 cr4 |= CR4_FSGSBASE_MASK; 7612 } 7613 #endif 7614 7615 env->xcr0 = xcr0; 7616 cpu_x86_update_cr4(env, cr4); 7617 7618 /* 7619 * SDM 11.11.5 requires: 7620 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7621 * - IA32_MTRR_PHYSMASKn.V = 0 7622 * All other bits are undefined. For simplification, zero it all. 7623 */ 7624 env->mtrr_deftype = 0; 7625 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7626 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7627 7628 env->interrupt_injected = -1; 7629 env->exception_nr = -1; 7630 env->exception_pending = 0; 7631 env->exception_injected = 0; 7632 env->exception_has_payload = false; 7633 env->exception_payload = 0; 7634 env->nmi_injected = false; 7635 env->triple_fault_pending = false; 7636 #if !defined(CONFIG_USER_ONLY) 7637 /* We hard-wire the BSP to the first CPU. */ 7638 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7639 7640 cs->halted = !cpu_is_bsp(cpu); 7641 7642 if (kvm_enabled()) { 7643 kvm_arch_reset_vcpu(cpu); 7644 } 7645 7646 x86_cpu_set_sgxlepubkeyhash(env); 7647 7648 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7649 7650 #endif 7651 } 7652 7653 void x86_cpu_after_reset(X86CPU *cpu) 7654 { 7655 #ifndef CONFIG_USER_ONLY 7656 if (kvm_enabled()) { 7657 kvm_arch_after_reset_vcpu(cpu); 7658 } 7659 7660 if (cpu->apic_state) { 7661 device_cold_reset(cpu->apic_state); 7662 } 7663 #endif 7664 } 7665 7666 static void mce_init(X86CPU *cpu) 7667 { 7668 CPUX86State *cenv = &cpu->env; 7669 unsigned int bank; 7670 7671 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7672 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7673 (CPUID_MCE | CPUID_MCA)) { 7674 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7675 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7676 cenv->mcg_ctl = ~(uint64_t)0; 7677 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7678 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7679 } 7680 } 7681 } 7682 7683 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7684 { 7685 if (*min < value) { 7686 *min = value; 7687 } 7688 } 7689 7690 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7691 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7692 { 7693 CPUX86State *env = &cpu->env; 7694 FeatureWordInfo *fi = &feature_word_info[w]; 7695 uint32_t eax = fi->cpuid.eax; 7696 uint32_t region = eax & 0xF0000000; 7697 7698 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7699 if (!env->features[w]) { 7700 return; 7701 } 7702 7703 switch (region) { 7704 case 0x00000000: 7705 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7706 break; 7707 case 0x80000000: 7708 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7709 break; 7710 case 0xC0000000: 7711 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7712 break; 7713 } 7714 7715 if (eax == 7) { 7716 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7717 fi->cpuid.ecx); 7718 } 7719 } 7720 7721 /* Calculate XSAVE components based on the configured CPU feature flags */ 7722 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7723 { 7724 CPUX86State *env = &cpu->env; 7725 int i; 7726 uint64_t mask; 7727 static bool request_perm; 7728 7729 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7730 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7731 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7732 env->features[FEAT_XSAVE_XSS_LO] = 0; 7733 env->features[FEAT_XSAVE_XSS_HI] = 0; 7734 return; 7735 } 7736 7737 mask = 0; 7738 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7739 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7740 if (cpuid_has_xsave_feature(env, esa)) { 7741 mask |= (1ULL << i); 7742 } 7743 } 7744 7745 /* Only request permission for first vcpu */ 7746 if (kvm_enabled() && !request_perm) { 7747 kvm_request_xsave_components(cpu, mask); 7748 request_perm = true; 7749 } 7750 7751 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7752 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7753 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7754 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7755 } 7756 7757 /***** Steps involved on loading and filtering CPUID data 7758 * 7759 * When initializing and realizing a CPU object, the steps 7760 * involved in setting up CPUID data are: 7761 * 7762 * 1) Loading CPU model definition (X86CPUDefinition). This is 7763 * implemented by x86_cpu_load_model() and should be completely 7764 * transparent, as it is done automatically by instance_init. 7765 * No code should need to look at X86CPUDefinition structs 7766 * outside instance_init. 7767 * 7768 * 2) CPU expansion. This is done by realize before CPUID 7769 * filtering, and will make sure host/accelerator data is 7770 * loaded for CPU models that depend on host capabilities 7771 * (e.g. "host"). Done by x86_cpu_expand_features(). 7772 * 7773 * 3) CPUID filtering. This initializes extra data related to 7774 * CPUID, and checks if the host supports all capabilities 7775 * required by the CPU. Runnability of a CPU model is 7776 * determined at this step. Done by x86_cpu_filter_features(). 7777 * 7778 * Some operations don't require all steps to be performed. 7779 * More precisely: 7780 * 7781 * - CPU instance creation (instance_init) will run only CPU 7782 * model loading. CPU expansion can't run at instance_init-time 7783 * because host/accelerator data may be not available yet. 7784 * - CPU realization will perform both CPU model expansion and CPUID 7785 * filtering, and return an error in case one of them fails. 7786 * - query-cpu-definitions needs to run all 3 steps. It needs 7787 * to run CPUID filtering, as the 'unavailable-features' 7788 * field is set based on the filtering results. 7789 * - The query-cpu-model-expansion QMP command only needs to run 7790 * CPU model loading and CPU expansion. It should not filter 7791 * any CPUID data based on host capabilities. 7792 */ 7793 7794 /* Expand CPU configuration data, based on configured features 7795 * and host/accelerator capabilities when appropriate. 7796 */ 7797 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7798 { 7799 CPUX86State *env = &cpu->env; 7800 FeatureWord w; 7801 int i; 7802 GList *l; 7803 7804 for (l = plus_features; l; l = l->next) { 7805 const char *prop = l->data; 7806 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7807 return; 7808 } 7809 } 7810 7811 for (l = minus_features; l; l = l->next) { 7812 const char *prop = l->data; 7813 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7814 return; 7815 } 7816 } 7817 7818 /*TODO: Now cpu->max_features doesn't overwrite features 7819 * set using QOM properties, and we can convert 7820 * plus_features & minus_features to global properties 7821 * inside x86_cpu_parse_featurestr() too. 7822 */ 7823 if (cpu->max_features) { 7824 for (w = 0; w < FEATURE_WORDS; w++) { 7825 /* Override only features that weren't set explicitly 7826 * by the user. 7827 */ 7828 env->features[w] |= 7829 x86_cpu_get_supported_feature_word(cpu, w) & 7830 ~env->user_features[w] & 7831 ~feature_word_info[w].no_autoenable_flags; 7832 } 7833 7834 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 7835 uint32_t eax, ebx, ecx, edx; 7836 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 7837 env->avx10_version = ebx & 0xff; 7838 } 7839 } 7840 7841 if (x86_threads_per_pkg(&env->topo_info) > 1) { 7842 env->features[FEAT_1_EDX] |= CPUID_HT; 7843 7844 /* 7845 * The Linux kernel checks for the CMPLegacy bit and 7846 * discards multiple thread information if it is set. 7847 * So don't set it here for Intel (and other processors 7848 * following Intel's behavior) to make Linux guests happy. 7849 */ 7850 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 7851 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 7852 } 7853 } 7854 7855 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7856 FeatureDep *d = &feature_dependencies[i]; 7857 if (!(env->features[d->from.index] & d->from.mask)) { 7858 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7859 7860 /* Not an error unless the dependent feature was added explicitly. */ 7861 mark_unavailable_features(cpu, d->to.index, 7862 unavailable_features & env->user_features[d->to.index], 7863 "This feature depends on other features that were not requested"); 7864 7865 env->features[d->to.index] &= ~unavailable_features; 7866 } 7867 } 7868 7869 if (!kvm_enabled() || !cpu->expose_kvm) { 7870 env->features[FEAT_KVM] = 0; 7871 } 7872 7873 x86_cpu_enable_xsave_components(cpu); 7874 7875 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7876 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7877 if (cpu->full_cpuid_auto_level) { 7878 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7879 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7880 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7881 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7882 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7883 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7884 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7885 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7886 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7887 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7888 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7889 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7890 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7891 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7892 7893 /* Intel Processor Trace requires CPUID[0x14] */ 7894 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7895 if (cpu->intel_pt_auto_level) { 7896 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7897 } else if (cpu->env.cpuid_min_level < 0x14) { 7898 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7899 CPUID_7_0_EBX_INTEL_PT, 7900 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7901 } 7902 } 7903 7904 /* 7905 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7906 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7907 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7908 * cpu->vendor_cpuid_only has been unset for compatibility with older 7909 * machine types. 7910 */ 7911 if (x86_has_extended_topo(env->avail_cpu_topo) && 7912 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7913 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7914 } 7915 7916 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 7917 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7918 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 7919 } 7920 7921 /* SVM requires CPUID[0x8000000A] */ 7922 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7923 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7924 } 7925 7926 /* SEV requires CPUID[0x8000001F] */ 7927 if (sev_enabled()) { 7928 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7929 } 7930 7931 if (env->features[FEAT_8000_0021_EAX]) { 7932 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7933 } 7934 7935 /* SGX requires CPUID[0x12] for EPC enumeration */ 7936 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7937 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7938 } 7939 } 7940 7941 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7942 if (env->cpuid_level_func7 == UINT32_MAX) { 7943 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7944 } 7945 if (env->cpuid_level == UINT32_MAX) { 7946 env->cpuid_level = env->cpuid_min_level; 7947 } 7948 if (env->cpuid_xlevel == UINT32_MAX) { 7949 env->cpuid_xlevel = env->cpuid_min_xlevel; 7950 } 7951 if (env->cpuid_xlevel2 == UINT32_MAX) { 7952 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7953 } 7954 7955 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7956 return; 7957 } 7958 } 7959 7960 /* 7961 * Finishes initialization of CPUID data, filters CPU feature 7962 * words based on host availability of each feature. 7963 * 7964 * Returns: true if any flag is not supported by the host, false otherwise. 7965 */ 7966 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7967 { 7968 CPUX86State *env = &cpu->env; 7969 FeatureWord w; 7970 const char *prefix = NULL; 7971 bool have_filtered_features; 7972 7973 uint32_t eax_0, ebx_0, ecx_0, edx_0; 7974 uint32_t eax_1, ebx_1, ecx_1, edx_1; 7975 7976 if (verbose) { 7977 prefix = accel_uses_host_cpuid() 7978 ? "host doesn't support requested feature" 7979 : "TCG doesn't support requested feature"; 7980 } 7981 7982 for (w = 0; w < FEATURE_WORDS; w++) { 7983 uint64_t host_feat = 7984 x86_cpu_get_supported_feature_word(NULL, w); 7985 uint64_t requested_features = env->features[w]; 7986 uint64_t unavailable_features = requested_features & ~host_feat; 7987 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7988 } 7989 7990 /* 7991 * Check that KVM actually allows the processor tracing features that 7992 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7993 */ 7994 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7995 kvm_enabled()) { 7996 x86_cpu_get_supported_cpuid(0x14, 0, 7997 &eax_0, &ebx_0, &ecx_0, &edx_0); 7998 x86_cpu_get_supported_cpuid(0x14, 1, 7999 &eax_1, &ebx_1, &ecx_1, &edx_1); 8000 8001 if (!eax_0 || 8002 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 8003 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 8004 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 8005 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 8006 INTEL_PT_ADDR_RANGES_NUM) || 8007 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 8008 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 8009 ((ecx_0 & CPUID_14_0_ECX_LIP) != 8010 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 8011 /* 8012 * Processor Trace capabilities aren't configurable, so if the 8013 * host can't emulate the capabilities we report on 8014 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 8015 */ 8016 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 8017 } 8018 } 8019 8020 have_filtered_features = x86_cpu_have_filtered_features(cpu); 8021 8022 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 8023 x86_cpu_get_supported_cpuid(0x24, 0, 8024 &eax_0, &ebx_0, &ecx_0, &edx_0); 8025 uint8_t version = ebx_0 & 0xff; 8026 8027 if (version < env->avx10_version) { 8028 if (prefix) { 8029 warn_report("%s: avx10.%d. Adjust to avx10.%d", 8030 prefix, env->avx10_version, version); 8031 } 8032 env->avx10_version = version; 8033 have_filtered_features = true; 8034 } 8035 } else if (env->avx10_version) { 8036 if (prefix) { 8037 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 8038 } 8039 have_filtered_features = true; 8040 } 8041 8042 return have_filtered_features; 8043 } 8044 8045 static void x86_cpu_hyperv_realize(X86CPU *cpu) 8046 { 8047 size_t len; 8048 8049 /* Hyper-V vendor id */ 8050 if (!cpu->hyperv_vendor) { 8051 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 8052 &error_abort); 8053 } 8054 len = strlen(cpu->hyperv_vendor); 8055 if (len > 12) { 8056 warn_report("hv-vendor-id truncated to 12 characters"); 8057 len = 12; 8058 } 8059 memset(cpu->hyperv_vendor_id, 0, 12); 8060 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 8061 8062 /* 'Hv#1' interface identification*/ 8063 cpu->hyperv_interface_id[0] = 0x31237648; 8064 cpu->hyperv_interface_id[1] = 0; 8065 cpu->hyperv_interface_id[2] = 0; 8066 cpu->hyperv_interface_id[3] = 0; 8067 8068 /* Hypervisor implementation limits */ 8069 cpu->hyperv_limits[0] = 64; 8070 cpu->hyperv_limits[1] = 0; 8071 cpu->hyperv_limits[2] = 0; 8072 } 8073 8074 #ifndef CONFIG_USER_ONLY 8075 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 8076 Error **errp) 8077 { 8078 CPUX86State *env = &cpu->env; 8079 CpuTopologyLevel level; 8080 8081 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 8082 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8083 env->cache_info_cpuid4.l1d_cache->share_level = level; 8084 env->cache_info_amd.l1d_cache->share_level = level; 8085 } else { 8086 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8087 env->cache_info_cpuid4.l1d_cache->share_level); 8088 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8089 env->cache_info_amd.l1d_cache->share_level); 8090 } 8091 8092 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 8093 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8094 env->cache_info_cpuid4.l1i_cache->share_level = level; 8095 env->cache_info_amd.l1i_cache->share_level = level; 8096 } else { 8097 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8098 env->cache_info_cpuid4.l1i_cache->share_level); 8099 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8100 env->cache_info_amd.l1i_cache->share_level); 8101 } 8102 8103 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 8104 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8105 env->cache_info_cpuid4.l2_cache->share_level = level; 8106 env->cache_info_amd.l2_cache->share_level = level; 8107 } else { 8108 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8109 env->cache_info_cpuid4.l2_cache->share_level); 8110 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8111 env->cache_info_amd.l2_cache->share_level); 8112 } 8113 8114 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 8115 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8116 env->cache_info_cpuid4.l3_cache->share_level = level; 8117 env->cache_info_amd.l3_cache->share_level = level; 8118 } else { 8119 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8120 env->cache_info_cpuid4.l3_cache->share_level); 8121 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8122 env->cache_info_amd.l3_cache->share_level); 8123 } 8124 8125 if (!machine_check_smp_cache(ms, errp)) { 8126 return false; 8127 } 8128 return true; 8129 } 8130 #endif 8131 8132 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 8133 { 8134 CPUState *cs = CPU(dev); 8135 X86CPU *cpu = X86_CPU(dev); 8136 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8137 CPUX86State *env = &cpu->env; 8138 Error *local_err = NULL; 8139 unsigned requested_lbr_fmt; 8140 8141 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 8142 /* Use pc-relative instructions in system-mode */ 8143 tcg_cflags_set(cs, CF_PCREL); 8144 #endif 8145 8146 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 8147 error_setg(errp, "apic-id property was not initialized properly"); 8148 return; 8149 } 8150 8151 /* 8152 * Process Hyper-V enlightenments. 8153 * Note: this currently has to happen before the expansion of CPU features. 8154 */ 8155 x86_cpu_hyperv_realize(cpu); 8156 8157 x86_cpu_expand_features(cpu, &local_err); 8158 if (local_err) { 8159 goto out; 8160 } 8161 8162 /* 8163 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 8164 * with user-provided setting. 8165 */ 8166 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 8167 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 8168 error_setg(errp, "invalid lbr-fmt"); 8169 return; 8170 } 8171 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 8172 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 8173 } 8174 8175 /* 8176 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 8177 * 3)vPMU LBR format matches that of host setting. 8178 */ 8179 requested_lbr_fmt = 8180 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 8181 if (requested_lbr_fmt && kvm_enabled()) { 8182 uint64_t host_perf_cap = 8183 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 8184 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 8185 8186 if (!cpu->enable_pmu) { 8187 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 8188 return; 8189 } 8190 if (requested_lbr_fmt != host_lbr_fmt) { 8191 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 8192 "the host value (0x%x).", 8193 requested_lbr_fmt, host_lbr_fmt); 8194 return; 8195 } 8196 } 8197 8198 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 8199 if (cpu->enforce_cpuid) { 8200 error_setg(&local_err, 8201 accel_uses_host_cpuid() ? 8202 "Host doesn't support requested features" : 8203 "TCG doesn't support requested features"); 8204 goto out; 8205 } 8206 } 8207 8208 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 8209 * CPUID[1].EDX. 8210 */ 8211 if (IS_AMD_CPU(env)) { 8212 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 8213 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 8214 & CPUID_EXT2_AMD_ALIASES); 8215 } 8216 8217 x86_cpu_set_sgxlepubkeyhash(env); 8218 8219 /* 8220 * note: the call to the framework needs to happen after feature expansion, 8221 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 8222 * These may be set by the accel-specific code, 8223 * and the results are subsequently checked / assumed in this function. 8224 */ 8225 cpu_exec_realizefn(cs, &local_err); 8226 if (local_err != NULL) { 8227 error_propagate(errp, local_err); 8228 return; 8229 } 8230 8231 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 8232 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8233 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 8234 goto out; 8235 } 8236 8237 if (cpu->guest_phys_bits == -1) { 8238 /* 8239 * If it was not set by the user, or by the accelerator via 8240 * cpu_exec_realizefn, clear. 8241 */ 8242 cpu->guest_phys_bits = 0; 8243 } 8244 8245 if (cpu->ucode_rev == 0) { 8246 /* 8247 * The default is the same as KVM's. Note that this check 8248 * needs to happen after the evenual setting of ucode_rev in 8249 * accel-specific code in cpu_exec_realizefn. 8250 */ 8251 if (IS_AMD_CPU(env)) { 8252 cpu->ucode_rev = 0x01000065; 8253 } else { 8254 cpu->ucode_rev = 0x100000000ULL; 8255 } 8256 } 8257 8258 /* 8259 * mwait extended info: needed for Core compatibility 8260 * We always wake on interrupt even if host does not have the capability. 8261 * 8262 * requires the accel-specific code in cpu_exec_realizefn to 8263 * have already acquired the CPUID data into cpu->mwait. 8264 */ 8265 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 8266 8267 /* 8268 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 8269 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8270 * based on inputs (sockets,cores,threads), it is still better to give 8271 * users a warning. 8272 */ 8273 if (IS_AMD_CPU(env) && 8274 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8275 env->topo_info.threads_per_core > 1) { 8276 warn_report_once("This family of AMD CPU doesn't support " 8277 "hyperthreading(%d). Please configure -smp " 8278 "options properly or try enabling topoext " 8279 "feature.", env->topo_info.threads_per_core); 8280 } 8281 8282 /* For 64bit systems think about the number of physical bits to present. 8283 * ideally this should be the same as the host; anything other than matching 8284 * the host can cause incorrect guest behaviour. 8285 * QEMU used to pick the magic value of 40 bits that corresponds to 8286 * consumer AMD devices but nothing else. 8287 * 8288 * Note that this code assumes features expansion has already been done 8289 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 8290 * phys_bits adjustments to match the host have been already done in 8291 * accel-specific code in cpu_exec_realizefn. 8292 */ 8293 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8294 if (cpu->phys_bits && 8295 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 8296 cpu->phys_bits < 32)) { 8297 error_setg(errp, "phys-bits should be between 32 and %u " 8298 " (but is %u)", 8299 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 8300 return; 8301 } 8302 /* 8303 * 0 means it was not explicitly set by the user (or by machine 8304 * compat_props or by the host code in host-cpu.c). 8305 * In this case, the default is the value used by TCG (40). 8306 */ 8307 if (cpu->phys_bits == 0) { 8308 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 8309 } 8310 if (cpu->guest_phys_bits && 8311 (cpu->guest_phys_bits > cpu->phys_bits || 8312 cpu->guest_phys_bits < 32)) { 8313 error_setg(errp, "guest-phys-bits should be between 32 and %u " 8314 " (but is %u)", 8315 cpu->phys_bits, cpu->guest_phys_bits); 8316 return; 8317 } 8318 } else { 8319 /* For 32 bit systems don't use the user set value, but keep 8320 * phys_bits consistent with what we tell the guest. 8321 */ 8322 if (cpu->phys_bits != 0) { 8323 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 8324 return; 8325 } 8326 if (cpu->guest_phys_bits != 0) { 8327 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 8328 return; 8329 } 8330 8331 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 8332 cpu->phys_bits = 36; 8333 } else { 8334 cpu->phys_bits = 32; 8335 } 8336 } 8337 8338 /* Cache information initialization */ 8339 if (!cpu->legacy_cache) { 8340 const CPUCaches *cache_info = 8341 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 8342 8343 if (!xcc->model || !cache_info) { 8344 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8345 error_setg(errp, 8346 "CPU model '%s' doesn't support legacy-cache=off", name); 8347 return; 8348 } 8349 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 8350 *cache_info; 8351 } else { 8352 /* Build legacy cache information */ 8353 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 8354 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 8355 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 8356 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 8357 8358 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 8359 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 8360 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 8361 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 8362 8363 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 8364 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 8365 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 8366 env->cache_info_amd.l3_cache = &legacy_l3_cache; 8367 } 8368 8369 #ifndef CONFIG_USER_ONLY 8370 MachineState *ms = MACHINE(qdev_get_machine()); 8371 MachineClass *mc = MACHINE_GET_CLASS(ms); 8372 8373 if (mc->smp_props.has_caches) { 8374 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 8375 return; 8376 } 8377 } 8378 8379 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 8380 8381 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 8382 x86_cpu_apic_create(cpu, &local_err); 8383 if (local_err != NULL) { 8384 goto out; 8385 } 8386 } 8387 #endif 8388 8389 mce_init(cpu); 8390 8391 x86_cpu_gdb_init(cs); 8392 qemu_init_vcpu(cs); 8393 8394 #ifndef CONFIG_USER_ONLY 8395 x86_cpu_apic_realize(cpu, &local_err); 8396 if (local_err != NULL) { 8397 goto out; 8398 } 8399 #endif /* !CONFIG_USER_ONLY */ 8400 cpu_reset(cs); 8401 8402 xcc->parent_realize(dev, &local_err); 8403 8404 out: 8405 if (local_err != NULL) { 8406 error_propagate(errp, local_err); 8407 return; 8408 } 8409 } 8410 8411 static void x86_cpu_unrealizefn(DeviceState *dev) 8412 { 8413 X86CPU *cpu = X86_CPU(dev); 8414 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8415 8416 #ifndef CONFIG_USER_ONLY 8417 cpu_remove_sync(CPU(dev)); 8418 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8419 #endif 8420 8421 if (cpu->apic_state) { 8422 object_unparent(OBJECT(cpu->apic_state)); 8423 cpu->apic_state = NULL; 8424 } 8425 8426 xcc->parent_unrealize(dev); 8427 } 8428 8429 typedef struct BitProperty { 8430 FeatureWord w; 8431 uint64_t mask; 8432 } BitProperty; 8433 8434 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8435 void *opaque, Error **errp) 8436 { 8437 X86CPU *cpu = X86_CPU(obj); 8438 BitProperty *fp = opaque; 8439 uint64_t f = cpu->env.features[fp->w]; 8440 bool value = (f & fp->mask) == fp->mask; 8441 visit_type_bool(v, name, &value, errp); 8442 } 8443 8444 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8445 void *opaque, Error **errp) 8446 { 8447 DeviceState *dev = DEVICE(obj); 8448 X86CPU *cpu = X86_CPU(obj); 8449 BitProperty *fp = opaque; 8450 bool value; 8451 8452 if (dev->realized) { 8453 qdev_prop_set_after_realize(dev, name, errp); 8454 return; 8455 } 8456 8457 if (!visit_type_bool(v, name, &value, errp)) { 8458 return; 8459 } 8460 8461 if (value) { 8462 cpu->env.features[fp->w] |= fp->mask; 8463 } else { 8464 cpu->env.features[fp->w] &= ~fp->mask; 8465 } 8466 cpu->env.user_features[fp->w] |= fp->mask; 8467 } 8468 8469 /* Register a boolean property to get/set a single bit in a uint32_t field. 8470 * 8471 * The same property name can be registered multiple times to make it affect 8472 * multiple bits in the same FeatureWord. In that case, the getter will return 8473 * true only if all bits are set. 8474 */ 8475 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8476 const char *prop_name, 8477 FeatureWord w, 8478 int bitnr) 8479 { 8480 ObjectClass *oc = OBJECT_CLASS(xcc); 8481 BitProperty *fp; 8482 ObjectProperty *op; 8483 uint64_t mask = (1ULL << bitnr); 8484 8485 op = object_class_property_find(oc, prop_name); 8486 if (op) { 8487 fp = op->opaque; 8488 assert(fp->w == w); 8489 fp->mask |= mask; 8490 } else { 8491 fp = g_new0(BitProperty, 1); 8492 fp->w = w; 8493 fp->mask = mask; 8494 object_class_property_add(oc, prop_name, "bool", 8495 x86_cpu_get_bit_prop, 8496 x86_cpu_set_bit_prop, 8497 NULL, fp); 8498 } 8499 } 8500 8501 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8502 FeatureWord w, 8503 int bitnr) 8504 { 8505 FeatureWordInfo *fi = &feature_word_info[w]; 8506 const char *name = fi->feat_names[bitnr]; 8507 8508 if (!name) { 8509 return; 8510 } 8511 8512 /* Property names should use "-" instead of "_". 8513 * Old names containing underscores are registered as aliases 8514 * using object_property_add_alias() 8515 */ 8516 assert(!strchr(name, '_')); 8517 /* aliases don't use "|" delimiters anymore, they are registered 8518 * manually using object_property_add_alias() */ 8519 assert(!strchr(name, '|')); 8520 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8521 } 8522 8523 static void x86_cpu_post_initfn(Object *obj) 8524 { 8525 static bool first = true; 8526 uint64_t supported_xcr0; 8527 int i; 8528 8529 if (first) { 8530 first = false; 8531 8532 supported_xcr0 = 8533 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 8534 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 8535 8536 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 8537 ExtSaveArea *esa = &x86_ext_save_areas[i]; 8538 8539 if (!(supported_xcr0 & (1 << i))) { 8540 esa->size = 0; 8541 } 8542 } 8543 } 8544 8545 accel_cpu_instance_init(CPU(obj)); 8546 } 8547 8548 static void x86_cpu_init_default_topo(X86CPU *cpu) 8549 { 8550 CPUX86State *env = &cpu->env; 8551 8552 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 8553 8554 /* thread, core and socket levels are set by default. */ 8555 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 8556 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 8557 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 8558 } 8559 8560 static void x86_cpu_initfn(Object *obj) 8561 { 8562 X86CPU *cpu = X86_CPU(obj); 8563 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8564 CPUX86State *env = &cpu->env; 8565 8566 x86_cpu_init_default_topo(cpu); 8567 8568 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8569 x86_cpu_get_feature_words, 8570 NULL, NULL, (void *)env->features); 8571 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8572 x86_cpu_get_feature_words, 8573 NULL, NULL, (void *)cpu->filtered_features); 8574 8575 object_property_add_alias(obj, "sse3", obj, "pni"); 8576 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8577 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8578 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8579 object_property_add_alias(obj, "xd", obj, "nx"); 8580 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8581 object_property_add_alias(obj, "i64", obj, "lm"); 8582 8583 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8584 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8585 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8586 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8587 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8588 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8589 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8590 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8591 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8592 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8593 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8594 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8595 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8596 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8597 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8598 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8599 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8600 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8601 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8602 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8603 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8604 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8605 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8606 8607 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8608 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8609 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8610 8611 if (xcc->model) { 8612 x86_cpu_load_model(cpu, xcc->model); 8613 } 8614 } 8615 8616 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8617 { 8618 X86CPU *cpu = X86_CPU(cs); 8619 8620 return cpu->apic_id; 8621 } 8622 8623 #if !defined(CONFIG_USER_ONLY) 8624 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8625 { 8626 X86CPU *cpu = X86_CPU(cs); 8627 8628 return cpu->env.cr[0] & CR0_PG_MASK; 8629 } 8630 #endif /* !CONFIG_USER_ONLY */ 8631 8632 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8633 { 8634 X86CPU *cpu = X86_CPU(cs); 8635 8636 cpu->env.eip = value; 8637 } 8638 8639 static vaddr x86_cpu_get_pc(CPUState *cs) 8640 { 8641 X86CPU *cpu = X86_CPU(cs); 8642 8643 /* Match cpu_get_tb_cpu_state. */ 8644 return cpu->env.eip + cpu->env.segs[R_CS].base; 8645 } 8646 8647 #if !defined(CONFIG_USER_ONLY) 8648 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8649 { 8650 X86CPU *cpu = X86_CPU(cs); 8651 CPUX86State *env = &cpu->env; 8652 8653 if (interrupt_request & CPU_INTERRUPT_POLL) { 8654 return CPU_INTERRUPT_POLL; 8655 } 8656 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8657 return CPU_INTERRUPT_SIPI; 8658 } 8659 8660 if (env->hflags2 & HF2_GIF_MASK) { 8661 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8662 !(env->hflags & HF_SMM_MASK)) { 8663 return CPU_INTERRUPT_SMI; 8664 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8665 !(env->hflags2 & HF2_NMI_MASK)) { 8666 return CPU_INTERRUPT_NMI; 8667 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8668 return CPU_INTERRUPT_MCE; 8669 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8670 (((env->hflags2 & HF2_VINTR_MASK) && 8671 (env->hflags2 & HF2_HIF_MASK)) || 8672 (!(env->hflags2 & HF2_VINTR_MASK) && 8673 (env->eflags & IF_MASK && 8674 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8675 return CPU_INTERRUPT_HARD; 8676 } else if (env->hflags2 & HF2_VGIF_MASK) { 8677 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8678 (env->eflags & IF_MASK) && 8679 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8680 return CPU_INTERRUPT_VIRQ; 8681 } 8682 } 8683 } 8684 8685 return 0; 8686 } 8687 8688 static bool x86_cpu_has_work(CPUState *cs) 8689 { 8690 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8691 } 8692 #endif /* !CONFIG_USER_ONLY */ 8693 8694 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8695 { 8696 X86CPU *cpu = X86_CPU(cs); 8697 CPUX86State *env = &cpu->env; 8698 8699 info->endian = BFD_ENDIAN_LITTLE; 8700 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8701 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8702 : bfd_mach_i386_i8086); 8703 8704 info->cap_arch = CS_ARCH_X86; 8705 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8706 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8707 : CS_MODE_16); 8708 info->cap_insn_unit = 1; 8709 info->cap_insn_split = 8; 8710 } 8711 8712 void x86_update_hflags(CPUX86State *env) 8713 { 8714 uint32_t hflags; 8715 #define HFLAG_COPY_MASK \ 8716 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8717 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8718 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8719 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8720 8721 hflags = env->hflags & HFLAG_COPY_MASK; 8722 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8723 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8724 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8725 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8726 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8727 8728 if (env->cr[4] & CR4_OSFXSR_MASK) { 8729 hflags |= HF_OSFXSR_MASK; 8730 } 8731 8732 if (env->efer & MSR_EFER_LMA) { 8733 hflags |= HF_LMA_MASK; 8734 } 8735 8736 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8737 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8738 } else { 8739 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8740 (DESC_B_SHIFT - HF_CS32_SHIFT); 8741 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8742 (DESC_B_SHIFT - HF_SS32_SHIFT); 8743 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8744 !(hflags & HF_CS32_MASK)) { 8745 hflags |= HF_ADDSEG_MASK; 8746 } else { 8747 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8748 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8749 } 8750 } 8751 env->hflags = hflags; 8752 } 8753 8754 static const Property x86_cpu_properties[] = { 8755 #ifdef CONFIG_USER_ONLY 8756 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8757 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8758 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8759 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8760 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8761 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8762 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8763 #else 8764 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8765 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8766 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8767 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8768 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8769 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8770 #endif 8771 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8772 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8773 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8774 8775 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8776 HYPERV_SPINLOCK_NEVER_NOTIFY), 8777 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8778 HYPERV_FEAT_RELAXED, 0), 8779 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8780 HYPERV_FEAT_VAPIC, 0), 8781 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8782 HYPERV_FEAT_TIME, 0), 8783 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8784 HYPERV_FEAT_CRASH, 0), 8785 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8786 HYPERV_FEAT_RESET, 0), 8787 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8788 HYPERV_FEAT_VPINDEX, 0), 8789 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8790 HYPERV_FEAT_RUNTIME, 0), 8791 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8792 HYPERV_FEAT_SYNIC, 0), 8793 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8794 HYPERV_FEAT_STIMER, 0), 8795 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8796 HYPERV_FEAT_FREQUENCIES, 0), 8797 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8798 HYPERV_FEAT_REENLIGHTENMENT, 0), 8799 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8800 HYPERV_FEAT_TLBFLUSH, 0), 8801 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8802 HYPERV_FEAT_EVMCS, 0), 8803 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8804 HYPERV_FEAT_IPI, 0), 8805 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8806 HYPERV_FEAT_STIMER_DIRECT, 0), 8807 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8808 HYPERV_FEAT_AVIC, 0), 8809 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8810 HYPERV_FEAT_MSR_BITMAP, 0), 8811 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8812 HYPERV_FEAT_XMM_INPUT, 0), 8813 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8814 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8815 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8816 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8817 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8818 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8819 #ifdef CONFIG_SYNDBG 8820 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8821 HYPERV_FEAT_SYNDBG, 0), 8822 #endif 8823 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8824 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8825 8826 /* WS2008R2 identify by default */ 8827 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8828 0x3839), 8829 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8830 0x000A), 8831 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8832 0x0000), 8833 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8834 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8835 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8836 8837 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8838 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8839 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8840 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8841 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8842 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8843 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8844 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8845 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8846 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8847 UINT32_MAX), 8848 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8849 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8850 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8851 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8852 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8853 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8854 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 8855 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8856 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8857 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8858 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8859 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8860 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8861 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8862 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8863 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8864 false), 8865 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8866 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8867 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8868 true), 8869 /* 8870 * lecacy_cache defaults to true unless the CPU model provides its 8871 * own cache information (see x86_cpu_load_def()). 8872 */ 8873 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8874 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8875 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8876 8877 /* 8878 * From "Requirements for Implementing the Microsoft 8879 * Hypervisor Interface": 8880 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8881 * 8882 * "Starting with Windows Server 2012 and Windows 8, if 8883 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8884 * the hypervisor imposes no specific limit to the number of VPs. 8885 * In this case, Windows Server 2012 guest VMs may use more than 8886 * 64 VPs, up to the maximum supported number of processors applicable 8887 * to the specific Windows version being used." 8888 */ 8889 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8890 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8891 false), 8892 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8893 true), 8894 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8895 }; 8896 8897 #ifndef CONFIG_USER_ONLY 8898 #include "hw/core/sysemu-cpu-ops.h" 8899 8900 static const struct SysemuCPUOps i386_sysemu_ops = { 8901 .has_work = x86_cpu_has_work, 8902 .get_memory_mapping = x86_cpu_get_memory_mapping, 8903 .get_paging_enabled = x86_cpu_get_paging_enabled, 8904 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8905 .asidx_from_attrs = x86_asidx_from_attrs, 8906 .get_crash_info = x86_cpu_get_crash_info, 8907 .write_elf32_note = x86_cpu_write_elf32_note, 8908 .write_elf64_note = x86_cpu_write_elf64_note, 8909 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8910 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8911 .legacy_vmsd = &vmstate_x86_cpu, 8912 }; 8913 #endif 8914 8915 static void x86_cpu_common_class_init(ObjectClass *oc, const void *data) 8916 { 8917 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8918 CPUClass *cc = CPU_CLASS(oc); 8919 DeviceClass *dc = DEVICE_CLASS(oc); 8920 ResettableClass *rc = RESETTABLE_CLASS(oc); 8921 FeatureWord w; 8922 8923 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8924 &xcc->parent_realize); 8925 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8926 &xcc->parent_unrealize); 8927 device_class_set_props(dc, x86_cpu_properties); 8928 8929 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8930 &xcc->parent_phases); 8931 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8932 8933 cc->class_by_name = x86_cpu_class_by_name; 8934 cc->list_cpus = x86_cpu_list; 8935 cc->parse_features = x86_cpu_parse_featurestr; 8936 cc->dump_state = x86_cpu_dump_state; 8937 cc->set_pc = x86_cpu_set_pc; 8938 cc->get_pc = x86_cpu_get_pc; 8939 cc->gdb_read_register = x86_cpu_gdb_read_register; 8940 cc->gdb_write_register = x86_cpu_gdb_write_register; 8941 cc->get_arch_id = x86_cpu_get_arch_id; 8942 8943 #ifndef CONFIG_USER_ONLY 8944 cc->sysemu_ops = &i386_sysemu_ops; 8945 #endif /* !CONFIG_USER_ONLY */ 8946 #ifdef CONFIG_TCG 8947 cc->tcg_ops = &x86_tcg_ops; 8948 #endif /* CONFIG_TCG */ 8949 8950 cc->gdb_arch_name = x86_gdb_arch_name; 8951 #ifdef TARGET_X86_64 8952 cc->gdb_core_xml_file = "i386-64bit.xml"; 8953 #else 8954 cc->gdb_core_xml_file = "i386-32bit.xml"; 8955 #endif 8956 cc->disas_set_info = x86_disas_set_info; 8957 8958 dc->user_creatable = true; 8959 8960 object_class_property_add(oc, "family", "int", 8961 x86_cpuid_version_get_family, 8962 x86_cpuid_version_set_family, NULL, NULL); 8963 object_class_property_add(oc, "model", "int", 8964 x86_cpuid_version_get_model, 8965 x86_cpuid_version_set_model, NULL, NULL); 8966 object_class_property_add(oc, "stepping", "int", 8967 x86_cpuid_version_get_stepping, 8968 x86_cpuid_version_set_stepping, NULL, NULL); 8969 object_class_property_add_str(oc, "vendor", 8970 x86_cpuid_get_vendor, 8971 x86_cpuid_set_vendor); 8972 object_class_property_add_str(oc, "model-id", 8973 x86_cpuid_get_model_id, 8974 x86_cpuid_set_model_id); 8975 object_class_property_add(oc, "tsc-frequency", "int", 8976 x86_cpuid_get_tsc_freq, 8977 x86_cpuid_set_tsc_freq, NULL, NULL); 8978 /* 8979 * The "unavailable-features" property has the same semantics as 8980 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8981 * QMP command: they list the features that would have prevented the 8982 * CPU from running if the "enforce" flag was set. 8983 */ 8984 object_class_property_add(oc, "unavailable-features", "strList", 8985 x86_cpu_get_unavailable_features, 8986 NULL, NULL, NULL); 8987 8988 #if !defined(CONFIG_USER_ONLY) 8989 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8990 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8991 #endif 8992 8993 for (w = 0; w < FEATURE_WORDS; w++) { 8994 int bitnr; 8995 for (bitnr = 0; bitnr < 64; bitnr++) { 8996 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8997 } 8998 } 8999 } 9000 9001 static const TypeInfo x86_cpu_type_info = { 9002 .name = TYPE_X86_CPU, 9003 .parent = TYPE_CPU, 9004 .instance_size = sizeof(X86CPU), 9005 .instance_align = __alignof(X86CPU), 9006 .instance_init = x86_cpu_initfn, 9007 .instance_post_init = x86_cpu_post_initfn, 9008 9009 .abstract = true, 9010 .class_size = sizeof(X86CPUClass), 9011 .class_init = x86_cpu_common_class_init, 9012 }; 9013 9014 /* "base" CPU model, used by query-cpu-model-expansion */ 9015 static void x86_cpu_base_class_init(ObjectClass *oc, const void *data) 9016 { 9017 X86CPUClass *xcc = X86_CPU_CLASS(oc); 9018 9019 xcc->static_model = true; 9020 xcc->migration_safe = true; 9021 xcc->model_description = "base CPU model type with no features enabled"; 9022 xcc->ordering = 8; 9023 } 9024 9025 static const TypeInfo x86_base_cpu_type_info = { 9026 .name = X86_CPU_TYPE_NAME("base"), 9027 .parent = TYPE_X86_CPU, 9028 .class_init = x86_cpu_base_class_init, 9029 }; 9030 9031 static void x86_cpu_register_types(void) 9032 { 9033 int i; 9034 9035 type_register_static(&x86_cpu_type_info); 9036 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 9037 x86_register_cpudef_types(&builtin_x86_defs[i]); 9038 } 9039 type_register_static(&max_x86_cpu_type_info); 9040 type_register_static(&x86_base_cpu_type_info); 9041 } 9042 9043 type_init(x86_cpu_register_types) 9044