1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #include "exec/watchpoint.h" 39 #ifndef CONFIG_USER_ONLY 40 #include "confidential-guest.h" 41 #include "system/reset.h" 42 #include "qapi/qapi-commands-machine.h" 43 #include "system/address-spaces.h" 44 #include "hw/boards.h" 45 #include "hw/i386/sgx-epc.h" 46 #endif 47 #include "tcg/tcg-cpu.h" 48 49 #include "disas/capstone.h" 50 #include "cpu-internal.h" 51 52 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 53 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 54 uint32_t *eax, uint32_t *ebx, 55 uint32_t *ecx, uint32_t *edx); 56 57 /* Helpers for building CPUID[2] descriptors: */ 58 59 struct CPUID2CacheDescriptorInfo { 60 enum CacheType type; 61 int level; 62 int size; 63 int line_size; 64 int associativity; 65 }; 66 67 /* 68 * Known CPUID 2 cache descriptors. 69 * From Intel SDM Volume 2A, CPUID instruction 70 */ 71 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 72 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 73 .associativity = 4, .line_size = 32, }, 74 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 75 .associativity = 4, .line_size = 32, }, 76 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 77 .associativity = 4, .line_size = 64, }, 78 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 79 .associativity = 2, .line_size = 32, }, 80 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 81 .associativity = 4, .line_size = 32, }, 82 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 83 .associativity = 4, .line_size = 64, }, 84 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 85 .associativity = 6, .line_size = 64, }, 86 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 87 .associativity = 2, .line_size = 64, }, 88 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 89 .associativity = 8, .line_size = 64, }, 90 /* lines per sector is not supported cpuid2_cache_descriptor(), 91 * so descriptors 0x22, 0x23 are not included 92 */ 93 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 94 .associativity = 16, .line_size = 64, }, 95 /* lines per sector is not supported cpuid2_cache_descriptor(), 96 * so descriptors 0x25, 0x20 are not included 97 */ 98 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 99 .associativity = 8, .line_size = 64, }, 100 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 101 .associativity = 8, .line_size = 64, }, 102 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 107 .associativity = 4, .line_size = 32, }, 108 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 109 .associativity = 4, .line_size = 32, }, 110 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 111 .associativity = 4, .line_size = 32, }, 112 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 113 .associativity = 4, .line_size = 64, }, 114 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 115 .associativity = 8, .line_size = 64, }, 116 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 119 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 120 .associativity = 12, .line_size = 64, }, 121 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 122 .associativity = 16, .line_size = 64, }, 123 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 124 .associativity = 12, .line_size = 64, }, 125 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 126 .associativity = 16, .line_size = 64, }, 127 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 128 .associativity = 24, .line_size = 64, }, 129 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 130 .associativity = 8, .line_size = 64, }, 131 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 132 .associativity = 4, .line_size = 64, }, 133 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 134 .associativity = 4, .line_size = 64, }, 135 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 136 .associativity = 4, .line_size = 64, }, 137 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 138 .associativity = 4, .line_size = 64, }, 139 /* lines per sector is not supported cpuid2_cache_descriptor(), 140 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 141 */ 142 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 143 .associativity = 8, .line_size = 64, }, 144 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 2, .line_size = 64, }, 146 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 147 .associativity = 8, .line_size = 64, }, 148 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 8, .line_size = 32, }, 152 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 8, .line_size = 32, }, 154 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 155 .associativity = 8, .line_size = 32, }, 156 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 157 .associativity = 4, .line_size = 64, }, 158 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 159 .associativity = 8, .line_size = 64, }, 160 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 161 .associativity = 4, .line_size = 64, }, 162 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 163 .associativity = 4, .line_size = 64, }, 164 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 165 .associativity = 4, .line_size = 64, }, 166 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 167 .associativity = 8, .line_size = 64, }, 168 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 169 .associativity = 8, .line_size = 64, }, 170 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 171 .associativity = 8, .line_size = 64, }, 172 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 173 .associativity = 12, .line_size = 64, }, 174 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 175 .associativity = 12, .line_size = 64, }, 176 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 177 .associativity = 12, .line_size = 64, }, 178 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 179 .associativity = 16, .line_size = 64, }, 180 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 181 .associativity = 16, .line_size = 64, }, 182 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 183 .associativity = 16, .line_size = 64, }, 184 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 185 .associativity = 24, .line_size = 64, }, 186 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 187 .associativity = 24, .line_size = 64, }, 188 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 189 .associativity = 24, .line_size = 64, }, 190 }; 191 192 /* 193 * "CPUID leaf 2 does not report cache descriptor information, 194 * use CPUID leaf 4 to query cache parameters" 195 */ 196 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 197 198 /* 199 * Return a CPUID 2 cache descriptor for a given cache. 200 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 201 */ 202 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 203 { 204 int i; 205 206 assert(cache->size > 0); 207 assert(cache->level > 0); 208 assert(cache->line_size > 0); 209 assert(cache->associativity > 0); 210 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 211 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 212 if (d->level == cache->level && d->type == cache->type && 213 d->size == cache->size && d->line_size == cache->line_size && 214 d->associativity == cache->associativity) { 215 return i; 216 } 217 } 218 219 return CACHE_DESCRIPTOR_UNAVAILABLE; 220 } 221 222 /* CPUID Leaf 4 constants: */ 223 224 /* EAX: */ 225 #define CACHE_TYPE_D 1 226 #define CACHE_TYPE_I 2 227 #define CACHE_TYPE_UNIFIED 3 228 229 #define CACHE_LEVEL(l) (l << 5) 230 231 #define CACHE_SELF_INIT_LEVEL (1 << 8) 232 233 /* EDX: */ 234 #define CACHE_NO_INVD_SHARING (1 << 0) 235 #define CACHE_INCLUSIVE (1 << 1) 236 #define CACHE_COMPLEX_IDX (1 << 2) 237 238 /* Encode CacheType for CPUID[4].EAX */ 239 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 240 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 241 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 242 0 /* Invalid value */) 243 244 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 245 enum CpuTopologyLevel share_level) 246 { 247 uint32_t num_ids = 0; 248 249 switch (share_level) { 250 case CPU_TOPOLOGY_LEVEL_CORE: 251 num_ids = 1 << apicid_core_offset(topo_info); 252 break; 253 case CPU_TOPOLOGY_LEVEL_MODULE: 254 num_ids = 1 << apicid_module_offset(topo_info); 255 break; 256 case CPU_TOPOLOGY_LEVEL_DIE: 257 num_ids = 1 << apicid_die_offset(topo_info); 258 break; 259 case CPU_TOPOLOGY_LEVEL_SOCKET: 260 num_ids = 1 << apicid_pkg_offset(topo_info); 261 break; 262 default: 263 /* 264 * Currently there is no use case for THREAD, so use 265 * assert directly to facilitate debugging. 266 */ 267 g_assert_not_reached(); 268 } 269 270 return num_ids - 1; 271 } 272 273 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 274 { 275 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 276 apicid_core_offset(topo_info)); 277 return num_cores - 1; 278 } 279 280 /* Encode cache info for CPUID[4] */ 281 static void encode_cache_cpuid4(CPUCacheInfo *cache, 282 X86CPUTopoInfo *topo_info, 283 uint32_t *eax, uint32_t *ebx, 284 uint32_t *ecx, uint32_t *edx) 285 { 286 assert(cache->size == cache->line_size * cache->associativity * 287 cache->partitions * cache->sets); 288 289 *eax = CACHE_TYPE(cache->type) | 290 CACHE_LEVEL(cache->level) | 291 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 292 (max_core_ids_in_package(topo_info) << 26) | 293 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 294 295 assert(cache->line_size > 0); 296 assert(cache->partitions > 0); 297 assert(cache->associativity > 0); 298 /* We don't implement fully-associative caches */ 299 assert(cache->associativity < cache->sets); 300 *ebx = (cache->line_size - 1) | 301 ((cache->partitions - 1) << 12) | 302 ((cache->associativity - 1) << 22); 303 304 assert(cache->sets > 0); 305 *ecx = cache->sets - 1; 306 307 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 308 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 309 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 310 } 311 312 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 313 enum CpuTopologyLevel topo_level) 314 { 315 switch (topo_level) { 316 case CPU_TOPOLOGY_LEVEL_THREAD: 317 return 1; 318 case CPU_TOPOLOGY_LEVEL_CORE: 319 return topo_info->threads_per_core; 320 case CPU_TOPOLOGY_LEVEL_MODULE: 321 return x86_threads_per_module(topo_info); 322 case CPU_TOPOLOGY_LEVEL_DIE: 323 return x86_threads_per_die(topo_info); 324 case CPU_TOPOLOGY_LEVEL_SOCKET: 325 return x86_threads_per_pkg(topo_info); 326 default: 327 g_assert_not_reached(); 328 } 329 return 0; 330 } 331 332 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 333 enum CpuTopologyLevel topo_level) 334 { 335 switch (topo_level) { 336 case CPU_TOPOLOGY_LEVEL_THREAD: 337 return 0; 338 case CPU_TOPOLOGY_LEVEL_CORE: 339 return apicid_core_offset(topo_info); 340 case CPU_TOPOLOGY_LEVEL_MODULE: 341 return apicid_module_offset(topo_info); 342 case CPU_TOPOLOGY_LEVEL_DIE: 343 return apicid_die_offset(topo_info); 344 case CPU_TOPOLOGY_LEVEL_SOCKET: 345 return apicid_pkg_offset(topo_info); 346 default: 347 g_assert_not_reached(); 348 } 349 return 0; 350 } 351 352 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 353 { 354 switch (topo_level) { 355 case CPU_TOPOLOGY_LEVEL_INVALID: 356 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 357 case CPU_TOPOLOGY_LEVEL_THREAD: 358 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 359 case CPU_TOPOLOGY_LEVEL_CORE: 360 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 361 case CPU_TOPOLOGY_LEVEL_MODULE: 362 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 363 case CPU_TOPOLOGY_LEVEL_DIE: 364 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 365 default: 366 /* Other types are not supported in QEMU. */ 367 g_assert_not_reached(); 368 } 369 return 0; 370 } 371 372 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 373 X86CPUTopoInfo *topo_info, 374 uint32_t *eax, uint32_t *ebx, 375 uint32_t *ecx, uint32_t *edx) 376 { 377 X86CPU *cpu = env_archcpu(env); 378 unsigned long level, base_level, next_level; 379 uint32_t num_threads_next_level, offset_next_level; 380 381 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 382 383 /* 384 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 385 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 386 */ 387 level = CPU_TOPOLOGY_LEVEL_THREAD; 388 base_level = level; 389 for (int i = 0; i <= count; i++) { 390 level = find_next_bit(env->avail_cpu_topo, 391 CPU_TOPOLOGY_LEVEL_SOCKET, 392 base_level); 393 394 /* 395 * CPUID[0x1f] doesn't explicitly encode the package level, 396 * and it just encodes the invalid level (all fields are 0) 397 * into the last subleaf of 0x1f. 398 */ 399 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 400 level = CPU_TOPOLOGY_LEVEL_INVALID; 401 break; 402 } 403 /* Search the next level. */ 404 base_level = level + 1; 405 } 406 407 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 408 num_threads_next_level = 0; 409 offset_next_level = 0; 410 } else { 411 next_level = find_next_bit(env->avail_cpu_topo, 412 CPU_TOPOLOGY_LEVEL_SOCKET, 413 level + 1); 414 num_threads_next_level = num_threads_by_topo_level(topo_info, 415 next_level); 416 offset_next_level = apicid_offset_by_topo_level(topo_info, 417 next_level); 418 } 419 420 *eax = offset_next_level; 421 /* The count (bits 15-00) doesn't need to be reliable. */ 422 *ebx = num_threads_next_level & 0xffff; 423 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 424 *edx = cpu->apic_id; 425 426 assert(!(*eax & ~0x1f)); 427 } 428 429 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 430 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 431 { 432 assert(cache->size % 1024 == 0); 433 assert(cache->lines_per_tag > 0); 434 assert(cache->associativity > 0); 435 assert(cache->line_size > 0); 436 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 437 (cache->lines_per_tag << 8) | (cache->line_size); 438 } 439 440 #define ASSOC_FULL 0xFF 441 442 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 443 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 444 a == 2 ? 0x2 : \ 445 a == 4 ? 0x4 : \ 446 a == 8 ? 0x6 : \ 447 a == 16 ? 0x8 : \ 448 a == 32 ? 0xA : \ 449 a == 48 ? 0xB : \ 450 a == 64 ? 0xC : \ 451 a == 96 ? 0xD : \ 452 a == 128 ? 0xE : \ 453 a == ASSOC_FULL ? 0xF : \ 454 0 /* invalid value */) 455 456 /* 457 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 458 * @l3 can be NULL. 459 */ 460 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 461 CPUCacheInfo *l3, 462 uint32_t *ecx, uint32_t *edx) 463 { 464 assert(l2->size % 1024 == 0); 465 assert(l2->associativity > 0); 466 assert(l2->lines_per_tag > 0); 467 assert(l2->line_size > 0); 468 *ecx = ((l2->size / 1024) << 16) | 469 (AMD_ENC_ASSOC(l2->associativity) << 12) | 470 (l2->lines_per_tag << 8) | (l2->line_size); 471 472 if (l3) { 473 assert(l3->size % (512 * 1024) == 0); 474 assert(l3->associativity > 0); 475 assert(l3->lines_per_tag > 0); 476 assert(l3->line_size > 0); 477 *edx = ((l3->size / (512 * 1024)) << 18) | 478 (AMD_ENC_ASSOC(l3->associativity) << 12) | 479 (l3->lines_per_tag << 8) | (l3->line_size); 480 } else { 481 *edx = 0; 482 } 483 } 484 485 /* Encode cache info for CPUID[8000001D] */ 486 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 487 X86CPUTopoInfo *topo_info, 488 uint32_t *eax, uint32_t *ebx, 489 uint32_t *ecx, uint32_t *edx) 490 { 491 assert(cache->size == cache->line_size * cache->associativity * 492 cache->partitions * cache->sets); 493 494 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 495 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 496 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 497 498 assert(cache->line_size > 0); 499 assert(cache->partitions > 0); 500 assert(cache->associativity > 0); 501 /* We don't implement fully-associative caches */ 502 assert(cache->associativity < cache->sets); 503 *ebx = (cache->line_size - 1) | 504 ((cache->partitions - 1) << 12) | 505 ((cache->associativity - 1) << 22); 506 507 assert(cache->sets > 0); 508 *ecx = cache->sets - 1; 509 510 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 511 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 512 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 513 } 514 515 /* Encode cache info for CPUID[8000001E] */ 516 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 517 uint32_t *eax, uint32_t *ebx, 518 uint32_t *ecx, uint32_t *edx) 519 { 520 X86CPUTopoIDs topo_ids; 521 522 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 523 524 *eax = cpu->apic_id; 525 526 /* 527 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 528 * Read-only. Reset: 0000_XXXXh. 529 * See Core::X86::Cpuid::ExtApicId. 530 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 531 * Bits Description 532 * 31:16 Reserved. 533 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 534 * The number of threads per core is ThreadsPerCore+1. 535 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 536 * 537 * NOTE: CoreId is already part of apic_id. Just use it. We can 538 * use all the 8 bits to represent the core_id here. 539 */ 540 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 541 542 /* 543 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 544 * Read-only. Reset: 0000_0XXXh. 545 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 546 * Bits Description 547 * 31:11 Reserved. 548 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 549 * ValidValues: 550 * Value Description 551 * 0h 1 node per processor. 552 * 7h-1h Reserved. 553 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 554 * 555 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 556 * But users can create more nodes than the actual hardware can 557 * support. To genaralize we can use all the upper 8 bits for nodes. 558 * NodeId is combination of node and socket_id which is already decoded 559 * in apic_id. Just use it by shifting. 560 */ 561 if (cpu->legacy_multi_node) { 562 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 563 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 564 } else { 565 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 566 } 567 568 *edx = 0; 569 } 570 571 /* 572 * Definitions of the hardcoded cache entries we expose: 573 * These are legacy cache values. If there is a need to change any 574 * of these values please use builtin_x86_defs 575 */ 576 577 /* L1 data cache: */ 578 static CPUCacheInfo legacy_l1d_cache = { 579 .type = DATA_CACHE, 580 .level = 1, 581 .size = 32 * KiB, 582 .self_init = 1, 583 .line_size = 64, 584 .associativity = 8, 585 .sets = 64, 586 .partitions = 1, 587 .no_invd_sharing = true, 588 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 589 }; 590 591 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 592 static CPUCacheInfo legacy_l1d_cache_amd = { 593 .type = DATA_CACHE, 594 .level = 1, 595 .size = 64 * KiB, 596 .self_init = 1, 597 .line_size = 64, 598 .associativity = 2, 599 .sets = 512, 600 .partitions = 1, 601 .lines_per_tag = 1, 602 .no_invd_sharing = true, 603 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 604 }; 605 606 /* L1 instruction cache: */ 607 static CPUCacheInfo legacy_l1i_cache = { 608 .type = INSTRUCTION_CACHE, 609 .level = 1, 610 .size = 32 * KiB, 611 .self_init = 1, 612 .line_size = 64, 613 .associativity = 8, 614 .sets = 64, 615 .partitions = 1, 616 .no_invd_sharing = true, 617 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 618 }; 619 620 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 621 static CPUCacheInfo legacy_l1i_cache_amd = { 622 .type = INSTRUCTION_CACHE, 623 .level = 1, 624 .size = 64 * KiB, 625 .self_init = 1, 626 .line_size = 64, 627 .associativity = 2, 628 .sets = 512, 629 .partitions = 1, 630 .lines_per_tag = 1, 631 .no_invd_sharing = true, 632 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 633 }; 634 635 /* Level 2 unified cache: */ 636 static CPUCacheInfo legacy_l2_cache = { 637 .type = UNIFIED_CACHE, 638 .level = 2, 639 .size = 4 * MiB, 640 .self_init = 1, 641 .line_size = 64, 642 .associativity = 16, 643 .sets = 4096, 644 .partitions = 1, 645 .no_invd_sharing = true, 646 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 647 }; 648 649 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 650 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 651 .type = UNIFIED_CACHE, 652 .level = 2, 653 .size = 2 * MiB, 654 .line_size = 64, 655 .associativity = 8, 656 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 657 }; 658 659 660 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 661 static CPUCacheInfo legacy_l2_cache_amd = { 662 .type = UNIFIED_CACHE, 663 .level = 2, 664 .size = 512 * KiB, 665 .line_size = 64, 666 .lines_per_tag = 1, 667 .associativity = 16, 668 .sets = 512, 669 .partitions = 1, 670 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 671 }; 672 673 /* Level 3 unified cache: */ 674 static CPUCacheInfo legacy_l3_cache = { 675 .type = UNIFIED_CACHE, 676 .level = 3, 677 .size = 16 * MiB, 678 .line_size = 64, 679 .associativity = 16, 680 .sets = 16384, 681 .partitions = 1, 682 .lines_per_tag = 1, 683 .self_init = true, 684 .inclusive = true, 685 .complex_indexing = true, 686 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 687 }; 688 689 /* TLB definitions: */ 690 691 #define L1_DTLB_2M_ASSOC 1 692 #define L1_DTLB_2M_ENTRIES 255 693 #define L1_DTLB_4K_ASSOC 1 694 #define L1_DTLB_4K_ENTRIES 255 695 696 #define L1_ITLB_2M_ASSOC 1 697 #define L1_ITLB_2M_ENTRIES 255 698 #define L1_ITLB_4K_ASSOC 1 699 #define L1_ITLB_4K_ENTRIES 255 700 701 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 702 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 703 #define L2_DTLB_4K_ASSOC 4 704 #define L2_DTLB_4K_ENTRIES 512 705 706 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 707 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 708 #define L2_ITLB_4K_ASSOC 4 709 #define L2_ITLB_4K_ENTRIES 512 710 711 /* CPUID Leaf 0x14 constants: */ 712 #define INTEL_PT_MAX_SUBLEAF 0x1 713 /* 714 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 715 * MSR can be accessed; 716 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 717 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 718 * of Intel PT MSRs across warm reset; 719 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 720 */ 721 #define INTEL_PT_MINIMAL_EBX 0xf 722 /* 723 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 724 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 725 * accessed; 726 * bit[01]: ToPA tables can hold any number of output entries, up to the 727 * maximum allowed by the MaskOrTableOffset field of 728 * IA32_RTIT_OUTPUT_MASK_PTRS; 729 * bit[02]: Support Single-Range Output scheme; 730 */ 731 #define INTEL_PT_MINIMAL_ECX 0x7 732 /* generated packets which contain IP payloads have LIP values */ 733 #define INTEL_PT_IP_LIP (1 << 31) 734 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 735 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 736 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 737 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 738 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 739 740 /* CPUID Leaf 0x1D constants: */ 741 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 742 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 743 #define INTEL_AMX_BYTES_PER_TILE 0x400 744 #define INTEL_AMX_BYTES_PER_ROW 0x40 745 #define INTEL_AMX_TILE_MAX_NAMES 0x8 746 #define INTEL_AMX_TILE_MAX_ROWS 0x10 747 748 /* CPUID Leaf 0x1E constants: */ 749 #define INTEL_AMX_TMUL_MAX_K 0x10 750 #define INTEL_AMX_TMUL_MAX_N 0x40 751 752 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 753 uint32_t vendor2, uint32_t vendor3) 754 { 755 int i; 756 for (i = 0; i < 4; i++) { 757 dst[i] = vendor1 >> (8 * i); 758 dst[i + 4] = vendor2 >> (8 * i); 759 dst[i + 8] = vendor3 >> (8 * i); 760 } 761 dst[CPUID_VENDOR_SZ] = '\0'; 762 } 763 764 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 765 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 766 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 767 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 768 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 769 CPUID_PSE36 | CPUID_FXSR) 770 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 771 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 772 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 773 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 774 CPUID_PAE | CPUID_SEP | CPUID_APIC) 775 776 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 777 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 778 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 779 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 780 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE | \ 781 CPUID_HT) 782 /* partly implemented: 783 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 784 /* missing: 785 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_TM, CPUID_PBE */ 786 787 /* 788 * Kernel-only features that can be shown to usermode programs even if 789 * they aren't actually supported by TCG, because qemu-user only runs 790 * in CPL=3; remove them if they are ever implemented for system emulation. 791 */ 792 #if defined CONFIG_USER_ONLY 793 #define CPUID_EXT_KERNEL_FEATURES \ 794 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 795 #else 796 #define CPUID_EXT_KERNEL_FEATURES 0 797 #endif 798 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 799 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 800 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 801 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 802 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 803 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 804 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 805 /* missing: 806 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 807 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 808 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 809 CPUID_EXT_TSC_DEADLINE_TIMER 810 */ 811 812 #ifdef TARGET_X86_64 813 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 814 #else 815 #define TCG_EXT2_X86_64_FEATURES 0 816 #endif 817 818 /* 819 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 820 * in usermode or by 32-bit programs. Those are added to supported 821 * TCG features unconditionally in user-mode emulation mode. This may 822 * indeed seem strange or incorrect, but it works because code running 823 * under usermode emulation cannot access them. 824 * 825 * Even for long mode, qemu-i386 is not running "a userspace program on a 826 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 827 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 828 * but again the difference is only visible in kernel mode. 829 */ 830 #if defined CONFIG_LINUX_USER 831 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 832 #elif defined CONFIG_USER_ONLY 833 /* FIXME: Long mode not yet supported for i386 bsd-user */ 834 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 835 #else 836 #define CPUID_EXT2_KERNEL_FEATURES 0 837 #endif 838 839 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 840 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 841 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 842 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 843 CPUID_EXT2_KERNEL_FEATURES) 844 845 #if defined CONFIG_USER_ONLY 846 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 847 #else 848 #define CPUID_EXT3_KERNEL_FEATURES 0 849 #endif 850 851 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 852 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 853 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES | \ 854 CPUID_EXT3_CMP_LEG) 855 856 #define TCG_EXT4_FEATURES 0 857 858 #if defined CONFIG_USER_ONLY 859 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 860 #else 861 #define CPUID_SVM_KERNEL_FEATURES 0 862 #endif 863 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 864 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 865 866 #define TCG_KVM_FEATURES 0 867 868 #if defined CONFIG_USER_ONLY 869 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 870 #else 871 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 872 #endif 873 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 874 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 875 CPUID_7_0_EBX_CLFLUSHOPT | \ 876 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 877 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 878 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 879 /* missing: 880 CPUID_7_0_EBX_HLE 881 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 882 883 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 884 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 885 #else 886 #define TCG_7_0_ECX_RDPID 0 887 #endif 888 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 889 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 890 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 891 TCG_7_0_ECX_RDPID) 892 893 #if defined CONFIG_USER_ONLY 894 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 895 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 896 #else 897 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 898 #endif 899 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 900 901 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 902 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 903 #define TCG_7_1_EDX_FEATURES 0 904 #define TCG_7_2_EDX_FEATURES 0 905 #define TCG_APM_FEATURES 0 906 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 907 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 908 /* missing: 909 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 910 #define TCG_14_0_ECX_FEATURES 0 911 #define TCG_SGX_12_0_EAX_FEATURES 0 912 #define TCG_SGX_12_0_EBX_FEATURES 0 913 #define TCG_SGX_12_1_EAX_FEATURES 0 914 #define TCG_24_0_EBX_FEATURES 0 915 916 #if defined CONFIG_USER_ONLY 917 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 918 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 919 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 920 CPUID_8000_0008_EBX_AMD_PSFD) 921 #else 922 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 923 #endif 924 925 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 926 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 927 928 #if defined CONFIG_USER_ONLY 929 #define CPUID_8000_0021_EAX_KERNEL_FEATURES CPUID_8000_0021_EAX_AUTO_IBRS 930 #else 931 #define CPUID_8000_0021_EAX_KERNEL_FEATURES 0 932 #endif 933 934 #define TCG_8000_0021_EAX_FEATURES ( \ 935 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | \ 936 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | \ 937 CPUID_8000_0021_EAX_KERNEL_FEATURES) 938 939 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 940 [FEAT_1_EDX] = { 941 .type = CPUID_FEATURE_WORD, 942 .feat_names = { 943 "fpu", "vme", "de", "pse", 944 "tsc", "msr", "pae", "mce", 945 "cx8", "apic", NULL, "sep", 946 "mtrr", "pge", "mca", "cmov", 947 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 948 NULL, "ds" /* Intel dts */, "acpi", "mmx", 949 "fxsr", "sse", "sse2", "ss", 950 "ht" /* Intel htt */, "tm", "ia64", "pbe", 951 }, 952 .cpuid = {.eax = 1, .reg = R_EDX, }, 953 .tcg_features = TCG_FEATURES, 954 .no_autoenable_flags = CPUID_HT, 955 }, 956 [FEAT_1_ECX] = { 957 .type = CPUID_FEATURE_WORD, 958 .feat_names = { 959 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 960 "ds-cpl", "vmx", "smx", "est", 961 "tm2", "ssse3", "cid", NULL, 962 "fma", "cx16", "xtpr", "pdcm", 963 NULL, "pcid", "dca", "sse4.1", 964 "sse4.2", "x2apic", "movbe", "popcnt", 965 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 966 "avx", "f16c", "rdrand", "hypervisor", 967 }, 968 .cpuid = { .eax = 1, .reg = R_ECX, }, 969 .tcg_features = TCG_EXT_FEATURES, 970 }, 971 /* Feature names that are already defined on feature_name[] but 972 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 973 * names on feat_names below. They are copied automatically 974 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 975 */ 976 [FEAT_8000_0001_EDX] = { 977 .type = CPUID_FEATURE_WORD, 978 .feat_names = { 979 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 980 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 981 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 982 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 983 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 984 "nx", NULL, "mmxext", NULL /* mmx */, 985 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 986 NULL, "lm", "3dnowext", "3dnow", 987 }, 988 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 989 .tcg_features = TCG_EXT2_FEATURES, 990 }, 991 [FEAT_8000_0001_ECX] = { 992 .type = CPUID_FEATURE_WORD, 993 .feat_names = { 994 "lahf-lm", "cmp-legacy", "svm", "extapic", 995 "cr8legacy", "abm", "sse4a", "misalignsse", 996 "3dnowprefetch", "osvw", "ibs", "xop", 997 "skinit", "wdt", NULL, "lwp", 998 "fma4", "tce", NULL, "nodeid-msr", 999 NULL, "tbm", "topoext", "perfctr-core", 1000 "perfctr-nb", NULL, NULL, NULL, 1001 NULL, NULL, NULL, NULL, 1002 }, 1003 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 1004 .tcg_features = TCG_EXT3_FEATURES, 1005 /* 1006 * TOPOEXT is always allowed but can't be enabled blindly by 1007 * "-cpu host", as it requires consistent cache topology info 1008 * to be provided so it doesn't confuse guests. 1009 */ 1010 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 1011 }, 1012 [FEAT_C000_0001_EDX] = { 1013 .type = CPUID_FEATURE_WORD, 1014 .feat_names = { 1015 NULL, NULL, "xstore", "xstore-en", 1016 NULL, NULL, "xcrypt", "xcrypt-en", 1017 "ace2", "ace2-en", "phe", "phe-en", 1018 "pmm", "pmm-en", NULL, NULL, 1019 NULL, NULL, NULL, NULL, 1020 NULL, NULL, NULL, NULL, 1021 NULL, NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 }, 1024 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1025 .tcg_features = TCG_EXT4_FEATURES, 1026 }, 1027 [FEAT_KVM] = { 1028 .type = CPUID_FEATURE_WORD, 1029 .feat_names = { 1030 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1031 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1032 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1033 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1034 NULL, NULL, NULL, NULL, 1035 NULL, NULL, NULL, NULL, 1036 "kvmclock-stable-bit", NULL, NULL, NULL, 1037 NULL, NULL, NULL, NULL, 1038 }, 1039 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1040 .tcg_features = TCG_KVM_FEATURES, 1041 }, 1042 [FEAT_KVM_HINTS] = { 1043 .type = CPUID_FEATURE_WORD, 1044 .feat_names = { 1045 "kvm-hint-dedicated", NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 NULL, NULL, NULL, NULL, 1051 NULL, NULL, NULL, NULL, 1052 NULL, NULL, NULL, NULL, 1053 }, 1054 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1055 .tcg_features = TCG_KVM_FEATURES, 1056 /* 1057 * KVM hints aren't auto-enabled by -cpu host, they need to be 1058 * explicitly enabled in the command-line. 1059 */ 1060 .no_autoenable_flags = ~0U, 1061 }, 1062 [FEAT_SVM] = { 1063 .type = CPUID_FEATURE_WORD, 1064 .feat_names = { 1065 "npt", "lbrv", "svm-lock", "nrip-save", 1066 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1067 NULL, NULL, "pause-filter", NULL, 1068 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1069 "vgif", NULL, NULL, NULL, 1070 NULL, NULL, NULL, NULL, 1071 NULL, "vnmi", NULL, NULL, 1072 "svme-addr-chk", NULL, NULL, NULL, 1073 }, 1074 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1075 .tcg_features = TCG_SVM_FEATURES, 1076 }, 1077 [FEAT_7_0_EBX] = { 1078 .type = CPUID_FEATURE_WORD, 1079 .feat_names = { 1080 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1081 "hle", "avx2", "fdp-excptn-only", "smep", 1082 "bmi2", "erms", "invpcid", "rtm", 1083 NULL, "zero-fcs-fds", "mpx", NULL, 1084 "avx512f", "avx512dq", "rdseed", "adx", 1085 "smap", "avx512ifma", "pcommit", "clflushopt", 1086 "clwb", "intel-pt", "avx512pf", "avx512er", 1087 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1088 }, 1089 .cpuid = { 1090 .eax = 7, 1091 .needs_ecx = true, .ecx = 0, 1092 .reg = R_EBX, 1093 }, 1094 .tcg_features = TCG_7_0_EBX_FEATURES, 1095 }, 1096 [FEAT_7_0_ECX] = { 1097 .type = CPUID_FEATURE_WORD, 1098 .feat_names = { 1099 NULL, "avx512vbmi", "umip", "pku", 1100 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1101 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1102 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1103 "la57", NULL, NULL, NULL, 1104 NULL, NULL, "rdpid", NULL, 1105 "bus-lock-detect", "cldemote", NULL, "movdiri", 1106 "movdir64b", NULL, "sgxlc", "pks", 1107 }, 1108 .cpuid = { 1109 .eax = 7, 1110 .needs_ecx = true, .ecx = 0, 1111 .reg = R_ECX, 1112 }, 1113 .tcg_features = TCG_7_0_ECX_FEATURES, 1114 }, 1115 [FEAT_7_0_EDX] = { 1116 .type = CPUID_FEATURE_WORD, 1117 .feat_names = { 1118 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1119 "fsrm", NULL, NULL, NULL, 1120 "avx512-vp2intersect", NULL, "md-clear", NULL, 1121 NULL, NULL, "serialize", NULL, 1122 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1123 NULL, NULL, "amx-bf16", "avx512-fp16", 1124 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1125 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1126 }, 1127 .cpuid = { 1128 .eax = 7, 1129 .needs_ecx = true, .ecx = 0, 1130 .reg = R_EDX, 1131 }, 1132 .tcg_features = TCG_7_0_EDX_FEATURES, 1133 }, 1134 [FEAT_7_1_EAX] = { 1135 .type = CPUID_FEATURE_WORD, 1136 .feat_names = { 1137 "sha512", "sm3", "sm4", NULL, 1138 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1139 NULL, NULL, "fzrm", "fsrs", 1140 "fsrc", NULL, NULL, NULL, 1141 NULL, "fred", "lkgs", "wrmsrns", 1142 NULL, "amx-fp16", NULL, "avx-ifma", 1143 NULL, NULL, "lam", NULL, 1144 NULL, NULL, NULL, NULL, 1145 }, 1146 .cpuid = { 1147 .eax = 7, 1148 .needs_ecx = true, .ecx = 1, 1149 .reg = R_EAX, 1150 }, 1151 .tcg_features = TCG_7_1_EAX_FEATURES, 1152 }, 1153 [FEAT_7_1_EDX] = { 1154 .type = CPUID_FEATURE_WORD, 1155 .feat_names = { 1156 NULL, NULL, NULL, NULL, 1157 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1158 "amx-complex", NULL, "avx-vnni-int16", NULL, 1159 NULL, NULL, "prefetchiti", NULL, 1160 NULL, NULL, NULL, "avx10", 1161 NULL, NULL, NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 NULL, NULL, NULL, NULL, 1164 }, 1165 .cpuid = { 1166 .eax = 7, 1167 .needs_ecx = true, .ecx = 1, 1168 .reg = R_EDX, 1169 }, 1170 .tcg_features = TCG_7_1_EDX_FEATURES, 1171 }, 1172 [FEAT_7_2_EDX] = { 1173 .type = CPUID_FEATURE_WORD, 1174 .feat_names = { 1175 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1176 "bhi-ctrl", "mcdt-no", NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 NULL, NULL, NULL, NULL, 1180 NULL, NULL, NULL, NULL, 1181 NULL, NULL, NULL, NULL, 1182 NULL, NULL, NULL, NULL, 1183 }, 1184 .cpuid = { 1185 .eax = 7, 1186 .needs_ecx = true, .ecx = 2, 1187 .reg = R_EDX, 1188 }, 1189 .tcg_features = TCG_7_2_EDX_FEATURES, 1190 }, 1191 [FEAT_24_0_EBX] = { 1192 .type = CPUID_FEATURE_WORD, 1193 .feat_names = { 1194 [16] = "avx10-128", 1195 [17] = "avx10-256", 1196 [18] = "avx10-512", 1197 }, 1198 .cpuid = { 1199 .eax = 0x24, 1200 .needs_ecx = true, .ecx = 0, 1201 .reg = R_EBX, 1202 }, 1203 .tcg_features = TCG_24_0_EBX_FEATURES, 1204 }, 1205 [FEAT_8000_0007_EDX] = { 1206 .type = CPUID_FEATURE_WORD, 1207 .feat_names = { 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 "invtsc", NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 NULL, NULL, NULL, NULL, 1216 }, 1217 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1218 .tcg_features = TCG_APM_FEATURES, 1219 .unmigratable_flags = CPUID_APM_INVTSC, 1220 }, 1221 [FEAT_8000_0007_EBX] = { 1222 .type = CPUID_FEATURE_WORD, 1223 .feat_names = { 1224 "overflow-recov", "succor", NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 NULL, NULL, NULL, NULL, 1227 NULL, NULL, NULL, NULL, 1228 NULL, NULL, NULL, NULL, 1229 NULL, NULL, NULL, NULL, 1230 NULL, NULL, NULL, NULL, 1231 NULL, NULL, NULL, NULL, 1232 }, 1233 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1234 .tcg_features = 0, 1235 .unmigratable_flags = 0, 1236 }, 1237 [FEAT_8000_0008_EBX] = { 1238 .type = CPUID_FEATURE_WORD, 1239 .feat_names = { 1240 "clzero", NULL, "xsaveerptr", NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, "wbnoinvd", NULL, NULL, 1243 "ibpb", NULL, "ibrs", "amd-stibp", 1244 NULL, "stibp-always-on", NULL, NULL, 1245 NULL, NULL, NULL, NULL, 1246 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1247 "amd-psfd", NULL, NULL, NULL, 1248 }, 1249 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1250 .tcg_features = TCG_8000_0008_EBX, 1251 .unmigratable_flags = 0, 1252 }, 1253 [FEAT_8000_0021_EAX] = { 1254 .type = CPUID_FEATURE_WORD, 1255 .feat_names = { 1256 "no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializing", NULL, 1257 NULL, NULL, "null-sel-clr-base", NULL, 1258 "auto-ibrs", NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 NULL, NULL, NULL, NULL, 1261 "prefetchi", NULL, NULL, NULL, 1262 "eraps", NULL, NULL, "sbpb", 1263 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1264 }, 1265 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1266 .tcg_features = TCG_8000_0021_EAX_FEATURES, 1267 .unmigratable_flags = 0, 1268 }, 1269 [FEAT_8000_0021_EBX] = { 1270 .type = CPUID_FEATURE_WORD, 1271 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1272 .tcg_features = 0, 1273 .unmigratable_flags = 0, 1274 }, 1275 [FEAT_8000_0022_EAX] = { 1276 .type = CPUID_FEATURE_WORD, 1277 .feat_names = { 1278 "perfmon-v2", NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 }, 1287 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1288 .tcg_features = 0, 1289 .unmigratable_flags = 0, 1290 }, 1291 [FEAT_XSAVE] = { 1292 .type = CPUID_FEATURE_WORD, 1293 .feat_names = { 1294 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1295 "xfd", NULL, NULL, NULL, 1296 NULL, NULL, NULL, NULL, 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 NULL, NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 NULL, NULL, NULL, NULL, 1302 }, 1303 .cpuid = { 1304 .eax = 0xd, 1305 .needs_ecx = true, .ecx = 1, 1306 .reg = R_EAX, 1307 }, 1308 .tcg_features = TCG_XSAVE_FEATURES, 1309 }, 1310 [FEAT_XSAVE_XSS_LO] = { 1311 .type = CPUID_FEATURE_WORD, 1312 .feat_names = { 1313 NULL, NULL, NULL, NULL, 1314 NULL, NULL, NULL, NULL, 1315 NULL, NULL, NULL, NULL, 1316 NULL, NULL, NULL, NULL, 1317 NULL, NULL, NULL, NULL, 1318 NULL, NULL, NULL, NULL, 1319 NULL, NULL, NULL, NULL, 1320 NULL, NULL, NULL, NULL, 1321 }, 1322 .cpuid = { 1323 .eax = 0xD, 1324 .needs_ecx = true, 1325 .ecx = 1, 1326 .reg = R_ECX, 1327 }, 1328 }, 1329 [FEAT_XSAVE_XSS_HI] = { 1330 .type = CPUID_FEATURE_WORD, 1331 .cpuid = { 1332 .eax = 0xD, 1333 .needs_ecx = true, 1334 .ecx = 1, 1335 .reg = R_EDX 1336 }, 1337 }, 1338 [FEAT_6_EAX] = { 1339 .type = CPUID_FEATURE_WORD, 1340 .feat_names = { 1341 NULL, NULL, "arat", NULL, 1342 NULL, NULL, NULL, NULL, 1343 NULL, NULL, NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 NULL, NULL, NULL, NULL, 1349 }, 1350 .cpuid = { .eax = 6, .reg = R_EAX, }, 1351 .tcg_features = TCG_6_EAX_FEATURES, 1352 }, 1353 [FEAT_XSAVE_XCR0_LO] = { 1354 .type = CPUID_FEATURE_WORD, 1355 .cpuid = { 1356 .eax = 0xD, 1357 .needs_ecx = true, .ecx = 0, 1358 .reg = R_EAX, 1359 }, 1360 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1361 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1362 XSTATE_PKRU_MASK, 1363 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1364 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1365 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1366 XSTATE_PKRU_MASK, 1367 }, 1368 [FEAT_XSAVE_XCR0_HI] = { 1369 .type = CPUID_FEATURE_WORD, 1370 .cpuid = { 1371 .eax = 0xD, 1372 .needs_ecx = true, .ecx = 0, 1373 .reg = R_EDX, 1374 }, 1375 .tcg_features = 0U, 1376 }, 1377 /*Below are MSR exposed features*/ 1378 [FEAT_ARCH_CAPABILITIES] = { 1379 .type = MSR_FEATURE_WORD, 1380 .feat_names = { 1381 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1382 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1383 "taa-no", NULL, NULL, NULL, 1384 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1385 NULL, "fb-clear", NULL, NULL, 1386 "bhi-no", NULL, NULL, NULL, 1387 "pbrsb-no", NULL, "gds-no", "rfds-no", 1388 "rfds-clear", NULL, NULL, NULL, 1389 NULL, NULL, NULL, NULL, 1390 NULL, NULL, NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 NULL, NULL, NULL, NULL, 1395 NULL, NULL, NULL, NULL, 1396 NULL, NULL, "its-no", NULL, 1397 }, 1398 .msr = { 1399 .index = MSR_IA32_ARCH_CAPABILITIES, 1400 }, 1401 /* 1402 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1403 * cannot be read from user mode. Therefore, it has no impact 1404 > on any user-mode operation, and warnings about unsupported 1405 * features do not matter. 1406 */ 1407 .tcg_features = ~0U, 1408 }, 1409 [FEAT_CORE_CAPABILITY] = { 1410 .type = MSR_FEATURE_WORD, 1411 .feat_names = { 1412 NULL, NULL, NULL, NULL, 1413 NULL, "split-lock-detect", NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 NULL, NULL, NULL, NULL, 1417 NULL, NULL, NULL, NULL, 1418 NULL, NULL, NULL, NULL, 1419 NULL, NULL, NULL, NULL, 1420 }, 1421 .msr = { 1422 .index = MSR_IA32_CORE_CAPABILITY, 1423 }, 1424 }, 1425 [FEAT_PERF_CAPABILITIES] = { 1426 .type = MSR_FEATURE_WORD, 1427 .feat_names = { 1428 NULL, NULL, NULL, NULL, 1429 NULL, NULL, NULL, NULL, 1430 NULL, NULL, NULL, NULL, 1431 NULL, "full-width-write", NULL, NULL, 1432 NULL, NULL, NULL, NULL, 1433 NULL, NULL, NULL, NULL, 1434 NULL, NULL, NULL, NULL, 1435 NULL, NULL, NULL, NULL, 1436 }, 1437 .msr = { 1438 .index = MSR_IA32_PERF_CAPABILITIES, 1439 }, 1440 }, 1441 1442 [FEAT_VMX_PROCBASED_CTLS] = { 1443 .type = MSR_FEATURE_WORD, 1444 .feat_names = { 1445 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1446 NULL, NULL, NULL, "vmx-hlt-exit", 1447 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1448 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1449 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1450 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1451 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1452 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1453 }, 1454 .msr = { 1455 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1456 } 1457 }, 1458 1459 [FEAT_VMX_SECONDARY_CTLS] = { 1460 .type = MSR_FEATURE_WORD, 1461 .feat_names = { 1462 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1463 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1464 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1465 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1466 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1467 "vmx-xsaves", NULL, NULL, NULL, 1468 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1469 NULL, NULL, NULL, NULL, 1470 }, 1471 .msr = { 1472 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1473 } 1474 }, 1475 1476 [FEAT_VMX_PINBASED_CTLS] = { 1477 .type = MSR_FEATURE_WORD, 1478 .feat_names = { 1479 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1480 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1481 NULL, NULL, NULL, NULL, 1482 NULL, NULL, NULL, NULL, 1483 NULL, NULL, NULL, NULL, 1484 NULL, NULL, NULL, NULL, 1485 NULL, NULL, NULL, NULL, 1486 NULL, NULL, NULL, NULL, 1487 }, 1488 .msr = { 1489 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1490 } 1491 }, 1492 1493 [FEAT_VMX_EXIT_CTLS] = { 1494 .type = MSR_FEATURE_WORD, 1495 /* 1496 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1497 * the LM CPUID bit. 1498 */ 1499 .feat_names = { 1500 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1501 NULL, NULL, NULL, NULL, 1502 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1503 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1504 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1505 "vmx-exit-save-efer", "vmx-exit-load-efer", 1506 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1507 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1508 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1509 }, 1510 .msr = { 1511 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1512 } 1513 }, 1514 1515 [FEAT_VMX_ENTRY_CTLS] = { 1516 .type = MSR_FEATURE_WORD, 1517 .feat_names = { 1518 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1519 NULL, NULL, NULL, NULL, 1520 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1521 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1522 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1523 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1524 NULL, NULL, NULL, NULL, 1525 NULL, NULL, NULL, NULL, 1526 }, 1527 .msr = { 1528 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1529 } 1530 }, 1531 1532 [FEAT_VMX_MISC] = { 1533 .type = MSR_FEATURE_WORD, 1534 .feat_names = { 1535 NULL, NULL, NULL, NULL, 1536 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1537 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, NULL, NULL, 1540 NULL, NULL, NULL, NULL, 1541 NULL, NULL, NULL, NULL, 1542 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1543 }, 1544 .msr = { 1545 .index = MSR_IA32_VMX_MISC, 1546 } 1547 }, 1548 1549 [FEAT_VMX_EPT_VPID_CAPS] = { 1550 .type = MSR_FEATURE_WORD, 1551 .feat_names = { 1552 "vmx-ept-execonly", NULL, NULL, NULL, 1553 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1554 NULL, NULL, NULL, NULL, 1555 NULL, NULL, NULL, NULL, 1556 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1557 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1558 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1559 NULL, NULL, NULL, NULL, 1560 "vmx-invvpid", NULL, NULL, NULL, 1561 NULL, NULL, NULL, NULL, 1562 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1563 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1564 NULL, NULL, NULL, NULL, 1565 NULL, NULL, NULL, NULL, 1566 NULL, NULL, NULL, NULL, 1567 NULL, NULL, NULL, NULL, 1568 NULL, NULL, NULL, NULL, 1569 }, 1570 .msr = { 1571 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1572 } 1573 }, 1574 1575 [FEAT_VMX_BASIC] = { 1576 .type = MSR_FEATURE_WORD, 1577 .feat_names = { 1578 [54] = "vmx-ins-outs", 1579 [55] = "vmx-true-ctls", 1580 [56] = "vmx-any-errcode", 1581 [58] = "vmx-nested-exception", 1582 }, 1583 .msr = { 1584 .index = MSR_IA32_VMX_BASIC, 1585 }, 1586 /* Just to be safe - we don't support setting the MSEG version field. */ 1587 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1588 }, 1589 1590 [FEAT_VMX_VMFUNC] = { 1591 .type = MSR_FEATURE_WORD, 1592 .feat_names = { 1593 [0] = "vmx-eptp-switching", 1594 }, 1595 .msr = { 1596 .index = MSR_IA32_VMX_VMFUNC, 1597 } 1598 }, 1599 1600 [FEAT_14_0_ECX] = { 1601 .type = CPUID_FEATURE_WORD, 1602 .feat_names = { 1603 NULL, NULL, NULL, NULL, 1604 NULL, NULL, NULL, NULL, 1605 NULL, NULL, NULL, NULL, 1606 NULL, NULL, NULL, NULL, 1607 NULL, NULL, NULL, NULL, 1608 NULL, NULL, NULL, NULL, 1609 NULL, NULL, NULL, NULL, 1610 NULL, NULL, NULL, "intel-pt-lip", 1611 }, 1612 .cpuid = { 1613 .eax = 0x14, 1614 .needs_ecx = true, .ecx = 0, 1615 .reg = R_ECX, 1616 }, 1617 .tcg_features = TCG_14_0_ECX_FEATURES, 1618 }, 1619 1620 [FEAT_SGX_12_0_EAX] = { 1621 .type = CPUID_FEATURE_WORD, 1622 .feat_names = { 1623 "sgx1", "sgx2", NULL, NULL, 1624 NULL, NULL, NULL, NULL, 1625 NULL, NULL, NULL, "sgx-edeccssa", 1626 NULL, NULL, NULL, NULL, 1627 NULL, NULL, NULL, NULL, 1628 NULL, NULL, NULL, NULL, 1629 NULL, NULL, NULL, NULL, 1630 NULL, NULL, NULL, NULL, 1631 }, 1632 .cpuid = { 1633 .eax = 0x12, 1634 .needs_ecx = true, .ecx = 0, 1635 .reg = R_EAX, 1636 }, 1637 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1638 }, 1639 1640 [FEAT_SGX_12_0_EBX] = { 1641 .type = CPUID_FEATURE_WORD, 1642 .feat_names = { 1643 "sgx-exinfo" , NULL, NULL, NULL, 1644 NULL, NULL, NULL, NULL, 1645 NULL, NULL, NULL, NULL, 1646 NULL, NULL, NULL, NULL, 1647 NULL, NULL, NULL, NULL, 1648 NULL, NULL, NULL, NULL, 1649 NULL, NULL, NULL, NULL, 1650 NULL, NULL, NULL, NULL, 1651 }, 1652 .cpuid = { 1653 .eax = 0x12, 1654 .needs_ecx = true, .ecx = 0, 1655 .reg = R_EBX, 1656 }, 1657 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1658 }, 1659 1660 [FEAT_SGX_12_1_EAX] = { 1661 .type = CPUID_FEATURE_WORD, 1662 .feat_names = { 1663 NULL, "sgx-debug", "sgx-mode64", NULL, 1664 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1665 NULL, NULL, "sgx-aex-notify", NULL, 1666 NULL, NULL, NULL, NULL, 1667 NULL, NULL, NULL, NULL, 1668 NULL, NULL, NULL, NULL, 1669 NULL, NULL, NULL, NULL, 1670 NULL, NULL, NULL, NULL, 1671 }, 1672 .cpuid = { 1673 .eax = 0x12, 1674 .needs_ecx = true, .ecx = 1, 1675 .reg = R_EAX, 1676 }, 1677 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1678 }, 1679 }; 1680 1681 bool is_feature_word_cpuid(uint32_t feature, uint32_t index, int reg) 1682 { 1683 FeatureWordInfo *wi; 1684 FeatureWord w; 1685 1686 for (w = 0; w < FEATURE_WORDS; w++) { 1687 wi = &feature_word_info[w]; 1688 if (wi->type == CPUID_FEATURE_WORD && wi->cpuid.eax == feature && 1689 (!wi->cpuid.needs_ecx || wi->cpuid.ecx == index) && 1690 wi->cpuid.reg == reg) { 1691 return true; 1692 } 1693 } 1694 return false; 1695 } 1696 1697 static FeatureDep feature_dependencies[] = { 1698 { 1699 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1700 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1701 }, 1702 { 1703 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1704 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1705 }, 1706 { 1707 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1708 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1709 }, 1710 { 1711 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1712 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1713 }, 1714 { 1715 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1716 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1717 }, 1718 { 1719 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1720 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1721 }, 1722 { 1723 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1724 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1725 }, 1726 { 1727 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1728 .to = { FEAT_VMX_MISC, ~0ull }, 1729 }, 1730 { 1731 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1732 .to = { FEAT_VMX_BASIC, ~0ull }, 1733 }, 1734 { 1735 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1736 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1737 }, 1738 { 1739 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1740 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1741 }, 1742 { 1743 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1744 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1745 }, 1746 { 1747 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1748 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1749 }, 1750 { 1751 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1752 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1753 }, 1754 { 1755 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1756 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1757 }, 1758 { 1759 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1760 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1761 }, 1762 { 1763 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1764 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1765 }, 1766 { 1767 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1768 .to = { FEAT_14_0_ECX, ~0ull }, 1769 }, 1770 { 1771 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1772 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1773 }, 1774 { 1775 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1776 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1777 }, 1778 { 1779 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1780 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1781 }, 1782 { 1783 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1784 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1785 }, 1786 { 1787 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1788 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1789 }, 1790 { 1791 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1792 .to = { FEAT_SVM, ~0ull }, 1793 }, 1794 { 1795 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1796 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1797 }, 1798 { 1799 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1800 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1801 }, 1802 { 1803 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1804 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1805 }, 1806 { 1807 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1808 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1809 }, 1810 { 1811 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1812 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1813 }, 1814 { 1815 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1816 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1817 }, 1818 { 1819 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1820 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1821 }, 1822 { 1823 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1824 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1825 }, 1826 { 1827 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1828 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1829 }, 1830 { 1831 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1832 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1833 }, 1834 { 1835 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1836 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1837 }, 1838 { 1839 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1840 .to = { FEAT_24_0_EBX, ~0ull }, 1841 }, 1842 }; 1843 1844 typedef struct X86RegisterInfo32 { 1845 /* Name of register */ 1846 const char *name; 1847 /* QAPI enum value register */ 1848 X86CPURegister32 qapi_enum; 1849 } X86RegisterInfo32; 1850 1851 #define REGISTER(reg) \ 1852 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1853 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1854 REGISTER(EAX), 1855 REGISTER(ECX), 1856 REGISTER(EDX), 1857 REGISTER(EBX), 1858 REGISTER(ESP), 1859 REGISTER(EBP), 1860 REGISTER(ESI), 1861 REGISTER(EDI), 1862 }; 1863 #undef REGISTER 1864 1865 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1866 [XSTATE_FP_BIT] = { 1867 /* x87 FP state component is always enabled if XSAVE is supported */ 1868 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1869 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1870 }, 1871 [XSTATE_SSE_BIT] = { 1872 /* SSE state component is always enabled if XSAVE is supported */ 1873 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1874 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1875 }, 1876 [XSTATE_YMM_BIT] = 1877 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1878 .size = sizeof(XSaveAVX) }, 1879 [XSTATE_BNDREGS_BIT] = 1880 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1881 .size = sizeof(XSaveBNDREG) }, 1882 [XSTATE_BNDCSR_BIT] = 1883 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1884 .size = sizeof(XSaveBNDCSR) }, 1885 [XSTATE_OPMASK_BIT] = 1886 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1887 .size = sizeof(XSaveOpmask) }, 1888 [XSTATE_ZMM_Hi256_BIT] = 1889 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1890 .size = sizeof(XSaveZMM_Hi256) }, 1891 [XSTATE_Hi16_ZMM_BIT] = 1892 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1893 .size = sizeof(XSaveHi16_ZMM) }, 1894 [XSTATE_PKRU_BIT] = 1895 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1896 .size = sizeof(XSavePKRU) }, 1897 [XSTATE_ARCH_LBR_BIT] = { 1898 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1899 .offset = 0 /*supervisor mode component, offset = 0 */, 1900 .size = sizeof(XSavesArchLBR) }, 1901 [XSTATE_XTILE_CFG_BIT] = { 1902 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1903 .size = sizeof(XSaveXTILECFG), 1904 }, 1905 [XSTATE_XTILE_DATA_BIT] = { 1906 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1907 .size = sizeof(XSaveXTILEDATA) 1908 }, 1909 }; 1910 1911 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1912 { 1913 uint64_t ret = x86_ext_save_areas[0].size; 1914 const ExtSaveArea *esa; 1915 uint32_t offset = 0; 1916 int i; 1917 1918 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1919 esa = &x86_ext_save_areas[i]; 1920 if ((mask >> i) & 1) { 1921 offset = compacted ? ret : esa->offset; 1922 ret = MAX(ret, offset + esa->size); 1923 } 1924 } 1925 return ret; 1926 } 1927 1928 static inline bool accel_uses_host_cpuid(void) 1929 { 1930 return kvm_enabled() || hvf_enabled(); 1931 } 1932 1933 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1934 { 1935 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1936 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1937 } 1938 1939 /* Return name of 32-bit register, from a R_* constant */ 1940 static const char *get_register_name_32(unsigned int reg) 1941 { 1942 if (reg >= CPU_NB_REGS32) { 1943 return NULL; 1944 } 1945 return x86_reg_info_32[reg].name; 1946 } 1947 1948 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1949 { 1950 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1951 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1952 } 1953 1954 /* 1955 * Returns the set of feature flags that are supported and migratable by 1956 * QEMU, for a given FeatureWord. 1957 */ 1958 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1959 { 1960 FeatureWordInfo *wi = &feature_word_info[w]; 1961 CPUX86State *env = &cpu->env; 1962 uint64_t r = 0; 1963 int i; 1964 1965 for (i = 0; i < 64; i++) { 1966 uint64_t f = 1ULL << i; 1967 1968 /* If the feature name is known, it is implicitly considered migratable, 1969 * unless it is explicitly set in unmigratable_flags */ 1970 if ((wi->migratable_flags & f) || 1971 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1972 r |= f; 1973 } 1974 } 1975 1976 /* when tsc-khz is set explicitly, invtsc is migratable */ 1977 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1978 r |= CPUID_APM_INVTSC; 1979 } 1980 1981 return r; 1982 } 1983 1984 void host_cpuid(uint32_t function, uint32_t count, 1985 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1986 { 1987 uint32_t vec[4]; 1988 1989 #ifdef __x86_64__ 1990 asm volatile("cpuid" 1991 : "=a"(vec[0]), "=b"(vec[1]), 1992 "=c"(vec[2]), "=d"(vec[3]) 1993 : "0"(function), "c"(count) : "cc"); 1994 #elif defined(__i386__) 1995 asm volatile("pusha \n\t" 1996 "cpuid \n\t" 1997 "mov %%eax, 0(%2) \n\t" 1998 "mov %%ebx, 4(%2) \n\t" 1999 "mov %%ecx, 8(%2) \n\t" 2000 "mov %%edx, 12(%2) \n\t" 2001 "popa" 2002 : : "a"(function), "c"(count), "S"(vec) 2003 : "memory", "cc"); 2004 #else 2005 abort(); 2006 #endif 2007 2008 if (eax) 2009 *eax = vec[0]; 2010 if (ebx) 2011 *ebx = vec[1]; 2012 if (ecx) 2013 *ecx = vec[2]; 2014 if (edx) 2015 *edx = vec[3]; 2016 } 2017 2018 /* CPU class name definitions: */ 2019 2020 /* Return type name for a given CPU model name 2021 * Caller is responsible for freeing the returned string. 2022 */ 2023 static char *x86_cpu_type_name(const char *model_name) 2024 { 2025 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 2026 } 2027 2028 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2029 { 2030 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2031 return object_class_by_name(typename); 2032 } 2033 2034 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2035 { 2036 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2037 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2038 return cpu_model_from_type(class_name); 2039 } 2040 2041 typedef struct X86CPUVersionDefinition { 2042 X86CPUVersion version; 2043 const char *alias; 2044 const char *note; 2045 PropValue *props; 2046 const CPUCaches *const cache_info; 2047 } X86CPUVersionDefinition; 2048 2049 /* Base definition for a CPU model */ 2050 typedef struct X86CPUDefinition { 2051 const char *name; 2052 uint32_t level; 2053 uint32_t xlevel; 2054 /* vendor is zero-terminated, 12 character ASCII string */ 2055 char vendor[CPUID_VENDOR_SZ + 1]; 2056 int family; 2057 int model; 2058 int stepping; 2059 uint8_t avx10_version; 2060 FeatureWordArray features; 2061 const char *model_id; 2062 const CPUCaches *const cache_info; 2063 /* 2064 * Definitions for alternative versions of CPU model. 2065 * List is terminated by item with version == 0. 2066 * If NULL, version 1 will be registered automatically. 2067 */ 2068 const X86CPUVersionDefinition *versions; 2069 const char *deprecation_note; 2070 } X86CPUDefinition; 2071 2072 /* Reference to a specific CPU model version */ 2073 struct X86CPUModel { 2074 /* Base CPU definition */ 2075 const X86CPUDefinition *cpudef; 2076 /* CPU model version */ 2077 X86CPUVersion version; 2078 const char *note; 2079 /* 2080 * If true, this is an alias CPU model. 2081 * This matters only for "-cpu help" and query-cpu-definitions 2082 */ 2083 bool is_alias; 2084 }; 2085 2086 /* Get full model name for CPU version */ 2087 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2088 X86CPUVersion version) 2089 { 2090 assert(version > 0); 2091 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2092 } 2093 2094 static const X86CPUVersionDefinition * 2095 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2096 { 2097 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2098 static const X86CPUVersionDefinition default_version_list[] = { 2099 { 1 }, 2100 { /* end of list */ } 2101 }; 2102 2103 return def->versions ?: default_version_list; 2104 } 2105 2106 static const CPUCaches epyc_cache_info = { 2107 .l1d_cache = &(CPUCacheInfo) { 2108 .type = DATA_CACHE, 2109 .level = 1, 2110 .size = 32 * KiB, 2111 .line_size = 64, 2112 .associativity = 8, 2113 .partitions = 1, 2114 .sets = 64, 2115 .lines_per_tag = 1, 2116 .self_init = 1, 2117 .no_invd_sharing = true, 2118 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2119 }, 2120 .l1i_cache = &(CPUCacheInfo) { 2121 .type = INSTRUCTION_CACHE, 2122 .level = 1, 2123 .size = 64 * KiB, 2124 .line_size = 64, 2125 .associativity = 4, 2126 .partitions = 1, 2127 .sets = 256, 2128 .lines_per_tag = 1, 2129 .self_init = 1, 2130 .no_invd_sharing = true, 2131 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2132 }, 2133 .l2_cache = &(CPUCacheInfo) { 2134 .type = UNIFIED_CACHE, 2135 .level = 2, 2136 .size = 512 * KiB, 2137 .line_size = 64, 2138 .associativity = 8, 2139 .partitions = 1, 2140 .sets = 1024, 2141 .lines_per_tag = 1, 2142 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2143 }, 2144 .l3_cache = &(CPUCacheInfo) { 2145 .type = UNIFIED_CACHE, 2146 .level = 3, 2147 .size = 8 * MiB, 2148 .line_size = 64, 2149 .associativity = 16, 2150 .partitions = 1, 2151 .sets = 8192, 2152 .lines_per_tag = 1, 2153 .self_init = true, 2154 .inclusive = true, 2155 .complex_indexing = true, 2156 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2157 }, 2158 }; 2159 2160 static CPUCaches epyc_v4_cache_info = { 2161 .l1d_cache = &(CPUCacheInfo) { 2162 .type = DATA_CACHE, 2163 .level = 1, 2164 .size = 32 * KiB, 2165 .line_size = 64, 2166 .associativity = 8, 2167 .partitions = 1, 2168 .sets = 64, 2169 .lines_per_tag = 1, 2170 .self_init = 1, 2171 .no_invd_sharing = true, 2172 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2173 }, 2174 .l1i_cache = &(CPUCacheInfo) { 2175 .type = INSTRUCTION_CACHE, 2176 .level = 1, 2177 .size = 64 * KiB, 2178 .line_size = 64, 2179 .associativity = 4, 2180 .partitions = 1, 2181 .sets = 256, 2182 .lines_per_tag = 1, 2183 .self_init = 1, 2184 .no_invd_sharing = true, 2185 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2186 }, 2187 .l2_cache = &(CPUCacheInfo) { 2188 .type = UNIFIED_CACHE, 2189 .level = 2, 2190 .size = 512 * KiB, 2191 .line_size = 64, 2192 .associativity = 8, 2193 .partitions = 1, 2194 .sets = 1024, 2195 .lines_per_tag = 1, 2196 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2197 }, 2198 .l3_cache = &(CPUCacheInfo) { 2199 .type = UNIFIED_CACHE, 2200 .level = 3, 2201 .size = 8 * MiB, 2202 .line_size = 64, 2203 .associativity = 16, 2204 .partitions = 1, 2205 .sets = 8192, 2206 .lines_per_tag = 1, 2207 .self_init = true, 2208 .inclusive = true, 2209 .complex_indexing = false, 2210 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2211 }, 2212 }; 2213 2214 static CPUCaches epyc_v5_cache_info = { 2215 .l1d_cache = &(CPUCacheInfo) { 2216 .type = DATA_CACHE, 2217 .level = 1, 2218 .size = 32 * KiB, 2219 .line_size = 64, 2220 .associativity = 8, 2221 .partitions = 1, 2222 .sets = 64, 2223 .lines_per_tag = 1, 2224 .self_init = true, 2225 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2226 }, 2227 .l1i_cache = &(CPUCacheInfo) { 2228 .type = INSTRUCTION_CACHE, 2229 .level = 1, 2230 .size = 64 * KiB, 2231 .line_size = 64, 2232 .associativity = 4, 2233 .partitions = 1, 2234 .sets = 256, 2235 .lines_per_tag = 1, 2236 .self_init = true, 2237 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2238 }, 2239 .l2_cache = &(CPUCacheInfo) { 2240 .type = UNIFIED_CACHE, 2241 .level = 2, 2242 .size = 512 * KiB, 2243 .line_size = 64, 2244 .associativity = 8, 2245 .partitions = 1, 2246 .sets = 1024, 2247 .lines_per_tag = 1, 2248 .self_init = true, 2249 .inclusive = true, 2250 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2251 }, 2252 .l3_cache = &(CPUCacheInfo) { 2253 .type = UNIFIED_CACHE, 2254 .level = 3, 2255 .size = 8 * MiB, 2256 .line_size = 64, 2257 .associativity = 16, 2258 .partitions = 1, 2259 .sets = 8192, 2260 .lines_per_tag = 1, 2261 .self_init = true, 2262 .no_invd_sharing = true, 2263 .complex_indexing = false, 2264 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2265 }, 2266 }; 2267 2268 static const CPUCaches epyc_rome_cache_info = { 2269 .l1d_cache = &(CPUCacheInfo) { 2270 .type = DATA_CACHE, 2271 .level = 1, 2272 .size = 32 * KiB, 2273 .line_size = 64, 2274 .associativity = 8, 2275 .partitions = 1, 2276 .sets = 64, 2277 .lines_per_tag = 1, 2278 .self_init = 1, 2279 .no_invd_sharing = true, 2280 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2281 }, 2282 .l1i_cache = &(CPUCacheInfo) { 2283 .type = INSTRUCTION_CACHE, 2284 .level = 1, 2285 .size = 32 * KiB, 2286 .line_size = 64, 2287 .associativity = 8, 2288 .partitions = 1, 2289 .sets = 64, 2290 .lines_per_tag = 1, 2291 .self_init = 1, 2292 .no_invd_sharing = true, 2293 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2294 }, 2295 .l2_cache = &(CPUCacheInfo) { 2296 .type = UNIFIED_CACHE, 2297 .level = 2, 2298 .size = 512 * KiB, 2299 .line_size = 64, 2300 .associativity = 8, 2301 .partitions = 1, 2302 .sets = 1024, 2303 .lines_per_tag = 1, 2304 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2305 }, 2306 .l3_cache = &(CPUCacheInfo) { 2307 .type = UNIFIED_CACHE, 2308 .level = 3, 2309 .size = 16 * MiB, 2310 .line_size = 64, 2311 .associativity = 16, 2312 .partitions = 1, 2313 .sets = 16384, 2314 .lines_per_tag = 1, 2315 .self_init = true, 2316 .inclusive = true, 2317 .complex_indexing = true, 2318 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2319 }, 2320 }; 2321 2322 static const CPUCaches epyc_rome_v3_cache_info = { 2323 .l1d_cache = &(CPUCacheInfo) { 2324 .type = DATA_CACHE, 2325 .level = 1, 2326 .size = 32 * KiB, 2327 .line_size = 64, 2328 .associativity = 8, 2329 .partitions = 1, 2330 .sets = 64, 2331 .lines_per_tag = 1, 2332 .self_init = 1, 2333 .no_invd_sharing = true, 2334 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2335 }, 2336 .l1i_cache = &(CPUCacheInfo) { 2337 .type = INSTRUCTION_CACHE, 2338 .level = 1, 2339 .size = 32 * KiB, 2340 .line_size = 64, 2341 .associativity = 8, 2342 .partitions = 1, 2343 .sets = 64, 2344 .lines_per_tag = 1, 2345 .self_init = 1, 2346 .no_invd_sharing = true, 2347 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2348 }, 2349 .l2_cache = &(CPUCacheInfo) { 2350 .type = UNIFIED_CACHE, 2351 .level = 2, 2352 .size = 512 * KiB, 2353 .line_size = 64, 2354 .associativity = 8, 2355 .partitions = 1, 2356 .sets = 1024, 2357 .lines_per_tag = 1, 2358 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2359 }, 2360 .l3_cache = &(CPUCacheInfo) { 2361 .type = UNIFIED_CACHE, 2362 .level = 3, 2363 .size = 16 * MiB, 2364 .line_size = 64, 2365 .associativity = 16, 2366 .partitions = 1, 2367 .sets = 16384, 2368 .lines_per_tag = 1, 2369 .self_init = true, 2370 .inclusive = true, 2371 .complex_indexing = false, 2372 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2373 }, 2374 }; 2375 2376 static const CPUCaches epyc_rome_v5_cache_info = { 2377 .l1d_cache = &(CPUCacheInfo) { 2378 .type = DATA_CACHE, 2379 .level = 1, 2380 .size = 32 * KiB, 2381 .line_size = 64, 2382 .associativity = 8, 2383 .partitions = 1, 2384 .sets = 64, 2385 .lines_per_tag = 1, 2386 .self_init = true, 2387 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2388 }, 2389 .l1i_cache = &(CPUCacheInfo) { 2390 .type = INSTRUCTION_CACHE, 2391 .level = 1, 2392 .size = 32 * KiB, 2393 .line_size = 64, 2394 .associativity = 8, 2395 .partitions = 1, 2396 .sets = 64, 2397 .lines_per_tag = 1, 2398 .self_init = true, 2399 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2400 }, 2401 .l2_cache = &(CPUCacheInfo) { 2402 .type = UNIFIED_CACHE, 2403 .level = 2, 2404 .size = 512 * KiB, 2405 .line_size = 64, 2406 .associativity = 8, 2407 .partitions = 1, 2408 .sets = 1024, 2409 .lines_per_tag = 1, 2410 .self_init = true, 2411 .inclusive = true, 2412 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2413 }, 2414 .l3_cache = &(CPUCacheInfo) { 2415 .type = UNIFIED_CACHE, 2416 .level = 3, 2417 .size = 16 * MiB, 2418 .line_size = 64, 2419 .associativity = 16, 2420 .partitions = 1, 2421 .sets = 16384, 2422 .lines_per_tag = 1, 2423 .self_init = true, 2424 .no_invd_sharing = true, 2425 .complex_indexing = false, 2426 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2427 }, 2428 }; 2429 2430 static const CPUCaches epyc_milan_cache_info = { 2431 .l1d_cache = &(CPUCacheInfo) { 2432 .type = DATA_CACHE, 2433 .level = 1, 2434 .size = 32 * KiB, 2435 .line_size = 64, 2436 .associativity = 8, 2437 .partitions = 1, 2438 .sets = 64, 2439 .lines_per_tag = 1, 2440 .self_init = 1, 2441 .no_invd_sharing = true, 2442 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2443 }, 2444 .l1i_cache = &(CPUCacheInfo) { 2445 .type = INSTRUCTION_CACHE, 2446 .level = 1, 2447 .size = 32 * KiB, 2448 .line_size = 64, 2449 .associativity = 8, 2450 .partitions = 1, 2451 .sets = 64, 2452 .lines_per_tag = 1, 2453 .self_init = 1, 2454 .no_invd_sharing = true, 2455 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2456 }, 2457 .l2_cache = &(CPUCacheInfo) { 2458 .type = UNIFIED_CACHE, 2459 .level = 2, 2460 .size = 512 * KiB, 2461 .line_size = 64, 2462 .associativity = 8, 2463 .partitions = 1, 2464 .sets = 1024, 2465 .lines_per_tag = 1, 2466 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2467 }, 2468 .l3_cache = &(CPUCacheInfo) { 2469 .type = UNIFIED_CACHE, 2470 .level = 3, 2471 .size = 32 * MiB, 2472 .line_size = 64, 2473 .associativity = 16, 2474 .partitions = 1, 2475 .sets = 32768, 2476 .lines_per_tag = 1, 2477 .self_init = true, 2478 .inclusive = true, 2479 .complex_indexing = true, 2480 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2481 }, 2482 }; 2483 2484 static const CPUCaches epyc_milan_v2_cache_info = { 2485 .l1d_cache = &(CPUCacheInfo) { 2486 .type = DATA_CACHE, 2487 .level = 1, 2488 .size = 32 * KiB, 2489 .line_size = 64, 2490 .associativity = 8, 2491 .partitions = 1, 2492 .sets = 64, 2493 .lines_per_tag = 1, 2494 .self_init = 1, 2495 .no_invd_sharing = true, 2496 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2497 }, 2498 .l1i_cache = &(CPUCacheInfo) { 2499 .type = INSTRUCTION_CACHE, 2500 .level = 1, 2501 .size = 32 * KiB, 2502 .line_size = 64, 2503 .associativity = 8, 2504 .partitions = 1, 2505 .sets = 64, 2506 .lines_per_tag = 1, 2507 .self_init = 1, 2508 .no_invd_sharing = true, 2509 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2510 }, 2511 .l2_cache = &(CPUCacheInfo) { 2512 .type = UNIFIED_CACHE, 2513 .level = 2, 2514 .size = 512 * KiB, 2515 .line_size = 64, 2516 .associativity = 8, 2517 .partitions = 1, 2518 .sets = 1024, 2519 .lines_per_tag = 1, 2520 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2521 }, 2522 .l3_cache = &(CPUCacheInfo) { 2523 .type = UNIFIED_CACHE, 2524 .level = 3, 2525 .size = 32 * MiB, 2526 .line_size = 64, 2527 .associativity = 16, 2528 .partitions = 1, 2529 .sets = 32768, 2530 .lines_per_tag = 1, 2531 .self_init = true, 2532 .inclusive = true, 2533 .complex_indexing = false, 2534 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2535 }, 2536 }; 2537 2538 static const CPUCaches epyc_milan_v3_cache_info = { 2539 .l1d_cache = &(CPUCacheInfo) { 2540 .type = DATA_CACHE, 2541 .level = 1, 2542 .size = 32 * KiB, 2543 .line_size = 64, 2544 .associativity = 8, 2545 .partitions = 1, 2546 .sets = 64, 2547 .lines_per_tag = 1, 2548 .self_init = true, 2549 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2550 }, 2551 .l1i_cache = &(CPUCacheInfo) { 2552 .type = INSTRUCTION_CACHE, 2553 .level = 1, 2554 .size = 32 * KiB, 2555 .line_size = 64, 2556 .associativity = 8, 2557 .partitions = 1, 2558 .sets = 64, 2559 .lines_per_tag = 1, 2560 .self_init = true, 2561 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2562 }, 2563 .l2_cache = &(CPUCacheInfo) { 2564 .type = UNIFIED_CACHE, 2565 .level = 2, 2566 .size = 512 * KiB, 2567 .line_size = 64, 2568 .associativity = 8, 2569 .partitions = 1, 2570 .sets = 1024, 2571 .lines_per_tag = 1, 2572 .self_init = true, 2573 .inclusive = true, 2574 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2575 }, 2576 .l3_cache = &(CPUCacheInfo) { 2577 .type = UNIFIED_CACHE, 2578 .level = 3, 2579 .size = 32 * MiB, 2580 .line_size = 64, 2581 .associativity = 16, 2582 .partitions = 1, 2583 .sets = 32768, 2584 .lines_per_tag = 1, 2585 .self_init = true, 2586 .no_invd_sharing = true, 2587 .complex_indexing = false, 2588 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2589 }, 2590 }; 2591 2592 static const CPUCaches epyc_genoa_cache_info = { 2593 .l1d_cache = &(CPUCacheInfo) { 2594 .type = DATA_CACHE, 2595 .level = 1, 2596 .size = 32 * KiB, 2597 .line_size = 64, 2598 .associativity = 8, 2599 .partitions = 1, 2600 .sets = 64, 2601 .lines_per_tag = 1, 2602 .self_init = 1, 2603 .no_invd_sharing = true, 2604 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2605 }, 2606 .l1i_cache = &(CPUCacheInfo) { 2607 .type = INSTRUCTION_CACHE, 2608 .level = 1, 2609 .size = 32 * KiB, 2610 .line_size = 64, 2611 .associativity = 8, 2612 .partitions = 1, 2613 .sets = 64, 2614 .lines_per_tag = 1, 2615 .self_init = 1, 2616 .no_invd_sharing = true, 2617 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2618 }, 2619 .l2_cache = &(CPUCacheInfo) { 2620 .type = UNIFIED_CACHE, 2621 .level = 2, 2622 .size = 1 * MiB, 2623 .line_size = 64, 2624 .associativity = 8, 2625 .partitions = 1, 2626 .sets = 2048, 2627 .lines_per_tag = 1, 2628 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2629 }, 2630 .l3_cache = &(CPUCacheInfo) { 2631 .type = UNIFIED_CACHE, 2632 .level = 3, 2633 .size = 32 * MiB, 2634 .line_size = 64, 2635 .associativity = 16, 2636 .partitions = 1, 2637 .sets = 32768, 2638 .lines_per_tag = 1, 2639 .self_init = true, 2640 .inclusive = true, 2641 .complex_indexing = false, 2642 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2643 }, 2644 }; 2645 2646 static const CPUCaches epyc_genoa_v2_cache_info = { 2647 .l1d_cache = &(CPUCacheInfo) { 2648 .type = DATA_CACHE, 2649 .level = 1, 2650 .size = 32 * KiB, 2651 .line_size = 64, 2652 .associativity = 8, 2653 .partitions = 1, 2654 .sets = 64, 2655 .lines_per_tag = 1, 2656 .self_init = true, 2657 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2658 }, 2659 .l1i_cache = &(CPUCacheInfo) { 2660 .type = INSTRUCTION_CACHE, 2661 .level = 1, 2662 .size = 32 * KiB, 2663 .line_size = 64, 2664 .associativity = 8, 2665 .partitions = 1, 2666 .sets = 64, 2667 .lines_per_tag = 1, 2668 .self_init = true, 2669 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2670 }, 2671 .l2_cache = &(CPUCacheInfo) { 2672 .type = UNIFIED_CACHE, 2673 .level = 2, 2674 .size = 1 * MiB, 2675 .line_size = 64, 2676 .associativity = 8, 2677 .partitions = 1, 2678 .sets = 2048, 2679 .lines_per_tag = 1, 2680 .self_init = true, 2681 .inclusive = true, 2682 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2683 }, 2684 .l3_cache = &(CPUCacheInfo) { 2685 .type = UNIFIED_CACHE, 2686 .level = 3, 2687 .size = 32 * MiB, 2688 .line_size = 64, 2689 .associativity = 16, 2690 .partitions = 1, 2691 .sets = 32768, 2692 .lines_per_tag = 1, 2693 .self_init = true, 2694 .no_invd_sharing = true, 2695 .complex_indexing = false, 2696 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2697 }, 2698 }; 2699 2700 static const CPUCaches epyc_turin_cache_info = { 2701 .l1d_cache = &(CPUCacheInfo) { 2702 .type = DATA_CACHE, 2703 .level = 1, 2704 .size = 48 * KiB, 2705 .line_size = 64, 2706 .associativity = 12, 2707 .partitions = 1, 2708 .sets = 64, 2709 .lines_per_tag = 1, 2710 .self_init = true, 2711 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2712 }, 2713 .l1i_cache = &(CPUCacheInfo) { 2714 .type = INSTRUCTION_CACHE, 2715 .level = 1, 2716 .size = 32 * KiB, 2717 .line_size = 64, 2718 .associativity = 8, 2719 .partitions = 1, 2720 .sets = 64, 2721 .lines_per_tag = 1, 2722 .self_init = true, 2723 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2724 }, 2725 .l2_cache = &(CPUCacheInfo) { 2726 .type = UNIFIED_CACHE, 2727 .level = 2, 2728 .size = 1 * MiB, 2729 .line_size = 64, 2730 .associativity = 16, 2731 .partitions = 1, 2732 .sets = 1024, 2733 .lines_per_tag = 1, 2734 .self_init = true, 2735 .inclusive = true, 2736 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2737 }, 2738 .l3_cache = &(CPUCacheInfo) { 2739 .type = UNIFIED_CACHE, 2740 .level = 3, 2741 .size = 32 * MiB, 2742 .line_size = 64, 2743 .associativity = 16, 2744 .partitions = 1, 2745 .sets = 32768, 2746 .lines_per_tag = 1, 2747 .self_init = true, 2748 .no_invd_sharing = true, 2749 .complex_indexing = false, 2750 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2751 }, 2752 }; 2753 2754 /* The following VMX features are not supported by KVM and are left out in the 2755 * CPU definitions: 2756 * 2757 * Dual-monitor support (all processors) 2758 * Entry to SMM 2759 * Deactivate dual-monitor treatment 2760 * Number of CR3-target values 2761 * Shutdown activity state 2762 * Wait-for-SIPI activity state 2763 * PAUSE-loop exiting (Westmere and newer) 2764 * EPT-violation #VE (Broadwell and newer) 2765 * Inject event with insn length=0 (Skylake and newer) 2766 * Conceal non-root operation from PT 2767 * Conceal VM exits from PT 2768 * Conceal VM entries from PT 2769 * Enable ENCLS exiting 2770 * Mode-based execute control (XS/XU) 2771 * TSC scaling (Skylake Server and newer) 2772 * GPA translation for PT (IceLake and newer) 2773 * User wait and pause 2774 * ENCLV exiting 2775 * Load IA32_RTIT_CTL 2776 * Clear IA32_RTIT_CTL 2777 * Advanced VM-exit information for EPT violations 2778 * Sub-page write permissions 2779 * PT in VMX operation 2780 */ 2781 2782 static const X86CPUDefinition builtin_x86_defs[] = { 2783 { 2784 .name = "qemu64", 2785 .level = 0xd, 2786 .vendor = CPUID_VENDOR_AMD, 2787 .family = 15, 2788 .model = 107, 2789 .stepping = 1, 2790 .features[FEAT_1_EDX] = 2791 PPRO_FEATURES | 2792 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2793 CPUID_PSE36, 2794 .features[FEAT_1_ECX] = 2795 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2796 .features[FEAT_8000_0001_EDX] = 2797 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2798 .features[FEAT_8000_0001_ECX] = 2799 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2800 .xlevel = 0x8000000A, 2801 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2802 }, 2803 { 2804 .name = "phenom", 2805 .level = 5, 2806 .vendor = CPUID_VENDOR_AMD, 2807 .family = 16, 2808 .model = 2, 2809 .stepping = 3, 2810 /* Missing: CPUID_HT */ 2811 .features[FEAT_1_EDX] = 2812 PPRO_FEATURES | 2813 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2814 CPUID_PSE36 | CPUID_VME, 2815 .features[FEAT_1_ECX] = 2816 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2817 CPUID_EXT_POPCNT, 2818 .features[FEAT_8000_0001_EDX] = 2819 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2820 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2821 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2822 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2823 CPUID_EXT3_CR8LEG, 2824 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2825 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2826 .features[FEAT_8000_0001_ECX] = 2827 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2828 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2829 /* Missing: CPUID_SVM_LBRV */ 2830 .features[FEAT_SVM] = 2831 CPUID_SVM_NPT, 2832 .xlevel = 0x8000001A, 2833 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2834 }, 2835 { 2836 .name = "core2duo", 2837 .level = 10, 2838 .vendor = CPUID_VENDOR_INTEL, 2839 .family = 6, 2840 .model = 15, 2841 .stepping = 11, 2842 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2843 .features[FEAT_1_EDX] = 2844 PPRO_FEATURES | 2845 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2846 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2847 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2848 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2849 .features[FEAT_1_ECX] = 2850 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2851 CPUID_EXT_CX16, 2852 .features[FEAT_8000_0001_EDX] = 2853 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2854 .features[FEAT_8000_0001_ECX] = 2855 CPUID_EXT3_LAHF_LM, 2856 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2857 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2858 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2859 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2860 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2861 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2862 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2863 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2864 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2865 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2866 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2867 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2868 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2869 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2870 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2871 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2872 .features[FEAT_VMX_SECONDARY_CTLS] = 2873 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2874 .xlevel = 0x80000008, 2875 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2876 }, 2877 { 2878 .name = "kvm64", 2879 .level = 0xd, 2880 .vendor = CPUID_VENDOR_INTEL, 2881 .family = 15, 2882 .model = 6, 2883 .stepping = 1, 2884 /* Missing: CPUID_HT */ 2885 .features[FEAT_1_EDX] = 2886 PPRO_FEATURES | CPUID_VME | 2887 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2888 CPUID_PSE36, 2889 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2890 .features[FEAT_1_ECX] = 2891 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2892 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2893 .features[FEAT_8000_0001_EDX] = 2894 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2895 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2896 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2897 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2898 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2899 .features[FEAT_8000_0001_ECX] = 2900 0, 2901 /* VMX features from Cedar Mill/Prescott */ 2902 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2903 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2904 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2905 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2906 VMX_PIN_BASED_NMI_EXITING, 2907 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2908 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2909 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2910 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2911 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2912 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2913 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2914 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2915 .xlevel = 0x80000008, 2916 .model_id = "Common KVM processor" 2917 }, 2918 { 2919 .name = "qemu32", 2920 .level = 4, 2921 .vendor = CPUID_VENDOR_INTEL, 2922 .family = 6, 2923 .model = 6, 2924 .stepping = 3, 2925 .features[FEAT_1_EDX] = 2926 PPRO_FEATURES, 2927 .features[FEAT_1_ECX] = 2928 CPUID_EXT_SSE3, 2929 .xlevel = 0x80000004, 2930 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2931 }, 2932 { 2933 .name = "kvm32", 2934 .level = 5, 2935 .vendor = CPUID_VENDOR_INTEL, 2936 .family = 15, 2937 .model = 6, 2938 .stepping = 1, 2939 .features[FEAT_1_EDX] = 2940 PPRO_FEATURES | CPUID_VME | 2941 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2942 .features[FEAT_1_ECX] = 2943 CPUID_EXT_SSE3, 2944 .features[FEAT_8000_0001_ECX] = 2945 0, 2946 /* VMX features from Yonah */ 2947 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2948 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2949 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2950 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2951 VMX_PIN_BASED_NMI_EXITING, 2952 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2953 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2954 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2955 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2956 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2957 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2958 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2959 .xlevel = 0x80000008, 2960 .model_id = "Common 32-bit KVM processor" 2961 }, 2962 { 2963 .name = "coreduo", 2964 .level = 10, 2965 .vendor = CPUID_VENDOR_INTEL, 2966 .family = 6, 2967 .model = 14, 2968 .stepping = 8, 2969 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2970 .features[FEAT_1_EDX] = 2971 PPRO_FEATURES | CPUID_VME | 2972 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2973 CPUID_SS, 2974 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2975 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2976 .features[FEAT_1_ECX] = 2977 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2978 .features[FEAT_8000_0001_EDX] = 2979 CPUID_EXT2_NX, 2980 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2981 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2982 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2983 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2984 VMX_PIN_BASED_NMI_EXITING, 2985 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2986 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2987 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2988 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2989 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2990 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2991 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2992 .xlevel = 0x80000008, 2993 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2994 }, 2995 { 2996 .name = "486", 2997 .level = 1, 2998 .vendor = CPUID_VENDOR_INTEL, 2999 .family = 4, 3000 .model = 8, 3001 .stepping = 0, 3002 .features[FEAT_1_EDX] = 3003 I486_FEATURES, 3004 .xlevel = 0, 3005 .model_id = "", 3006 }, 3007 { 3008 .name = "pentium", 3009 .level = 1, 3010 .vendor = CPUID_VENDOR_INTEL, 3011 .family = 5, 3012 .model = 4, 3013 .stepping = 3, 3014 .features[FEAT_1_EDX] = 3015 PENTIUM_FEATURES, 3016 .xlevel = 0, 3017 .model_id = "", 3018 }, 3019 { 3020 .name = "pentium2", 3021 .level = 2, 3022 .vendor = CPUID_VENDOR_INTEL, 3023 .family = 6, 3024 .model = 5, 3025 .stepping = 2, 3026 .features[FEAT_1_EDX] = 3027 PENTIUM2_FEATURES, 3028 .xlevel = 0, 3029 .model_id = "", 3030 }, 3031 { 3032 .name = "pentium3", 3033 .level = 3, 3034 .vendor = CPUID_VENDOR_INTEL, 3035 .family = 6, 3036 .model = 7, 3037 .stepping = 3, 3038 .features[FEAT_1_EDX] = 3039 PENTIUM3_FEATURES, 3040 .xlevel = 0, 3041 .model_id = "", 3042 }, 3043 { 3044 .name = "athlon", 3045 .level = 2, 3046 .vendor = CPUID_VENDOR_AMD, 3047 .family = 6, 3048 .model = 2, 3049 .stepping = 3, 3050 .features[FEAT_1_EDX] = 3051 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 3052 CPUID_MCA, 3053 .features[FEAT_8000_0001_EDX] = 3054 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 3055 .xlevel = 0x80000008, 3056 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 3057 }, 3058 { 3059 .name = "n270", 3060 .level = 10, 3061 .vendor = CPUID_VENDOR_INTEL, 3062 .family = 6, 3063 .model = 28, 3064 .stepping = 2, 3065 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3066 .features[FEAT_1_EDX] = 3067 PPRO_FEATURES | 3068 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 3069 CPUID_ACPI | CPUID_SS, 3070 /* Some CPUs got no CPUID_SEP */ 3071 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 3072 * CPUID_EXT_XTPR */ 3073 .features[FEAT_1_ECX] = 3074 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 3075 CPUID_EXT_MOVBE, 3076 .features[FEAT_8000_0001_EDX] = 3077 CPUID_EXT2_NX, 3078 .features[FEAT_8000_0001_ECX] = 3079 CPUID_EXT3_LAHF_LM, 3080 .xlevel = 0x80000008, 3081 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 3082 }, 3083 { 3084 .name = "Conroe", 3085 .level = 10, 3086 .vendor = CPUID_VENDOR_INTEL, 3087 .family = 6, 3088 .model = 15, 3089 .stepping = 3, 3090 .features[FEAT_1_EDX] = 3091 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3092 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3093 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3094 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3095 CPUID_DE | CPUID_FP87, 3096 .features[FEAT_1_ECX] = 3097 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 3098 .features[FEAT_8000_0001_EDX] = 3099 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3100 .features[FEAT_8000_0001_ECX] = 3101 CPUID_EXT3_LAHF_LM, 3102 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 3103 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3104 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3105 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3106 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3107 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 3108 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3109 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3110 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3111 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3112 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3113 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3114 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3115 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3116 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3117 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3118 .features[FEAT_VMX_SECONDARY_CTLS] = 3119 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 3120 .xlevel = 0x80000008, 3121 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 3122 }, 3123 { 3124 .name = "Penryn", 3125 .level = 10, 3126 .vendor = CPUID_VENDOR_INTEL, 3127 .family = 6, 3128 .model = 23, 3129 .stepping = 3, 3130 .features[FEAT_1_EDX] = 3131 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3132 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3133 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3134 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3135 CPUID_DE | CPUID_FP87, 3136 .features[FEAT_1_ECX] = 3137 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3138 CPUID_EXT_SSE3, 3139 .features[FEAT_8000_0001_EDX] = 3140 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3141 .features[FEAT_8000_0001_ECX] = 3142 CPUID_EXT3_LAHF_LM, 3143 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 3144 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3145 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 3146 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 3147 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 3148 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3149 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3150 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 3151 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3152 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3153 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3154 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3155 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3156 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3157 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3158 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3159 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3160 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3161 .features[FEAT_VMX_SECONDARY_CTLS] = 3162 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3163 VMX_SECONDARY_EXEC_WBINVD_EXITING, 3164 .xlevel = 0x80000008, 3165 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 3166 }, 3167 { 3168 .name = "Nehalem", 3169 .level = 11, 3170 .vendor = CPUID_VENDOR_INTEL, 3171 .family = 6, 3172 .model = 26, 3173 .stepping = 3, 3174 .features[FEAT_1_EDX] = 3175 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3176 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3177 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3178 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3179 CPUID_DE | CPUID_FP87, 3180 .features[FEAT_1_ECX] = 3181 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3182 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 3183 .features[FEAT_8000_0001_EDX] = 3184 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3185 .features[FEAT_8000_0001_ECX] = 3186 CPUID_EXT3_LAHF_LM, 3187 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3188 MSR_VMX_BASIC_TRUE_CTLS, 3189 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3190 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3191 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3192 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3193 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3194 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3195 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3196 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3197 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3198 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3199 .features[FEAT_VMX_EXIT_CTLS] = 3200 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3201 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3202 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3203 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3204 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3205 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3206 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3207 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3208 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3209 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3210 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3211 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3212 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3213 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3214 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3215 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3216 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3217 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3218 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3219 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3220 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3221 .features[FEAT_VMX_SECONDARY_CTLS] = 3222 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3223 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3224 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3225 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3226 VMX_SECONDARY_EXEC_ENABLE_VPID, 3227 .xlevel = 0x80000008, 3228 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 3229 .versions = (X86CPUVersionDefinition[]) { 3230 { .version = 1 }, 3231 { 3232 .version = 2, 3233 .alias = "Nehalem-IBRS", 3234 .props = (PropValue[]) { 3235 { "spec-ctrl", "on" }, 3236 { "model-id", 3237 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 3238 { /* end of list */ } 3239 } 3240 }, 3241 { /* end of list */ } 3242 } 3243 }, 3244 { 3245 .name = "Westmere", 3246 .level = 11, 3247 .vendor = CPUID_VENDOR_INTEL, 3248 .family = 6, 3249 .model = 44, 3250 .stepping = 1, 3251 .features[FEAT_1_EDX] = 3252 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3253 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3254 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3255 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3256 CPUID_DE | CPUID_FP87, 3257 .features[FEAT_1_ECX] = 3258 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 3259 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3260 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3261 .features[FEAT_8000_0001_EDX] = 3262 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3263 .features[FEAT_8000_0001_ECX] = 3264 CPUID_EXT3_LAHF_LM, 3265 .features[FEAT_6_EAX] = 3266 CPUID_6_EAX_ARAT, 3267 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3268 MSR_VMX_BASIC_TRUE_CTLS, 3269 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3270 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3271 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3272 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3273 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3274 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3275 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3276 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3277 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3278 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3279 .features[FEAT_VMX_EXIT_CTLS] = 3280 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3281 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3282 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3283 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3284 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3285 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3286 MSR_VMX_MISC_STORE_LMA, 3287 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3288 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3289 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3290 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3291 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3292 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3293 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3294 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3295 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3296 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3297 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3298 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3299 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3300 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3301 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3302 .features[FEAT_VMX_SECONDARY_CTLS] = 3303 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3304 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3305 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3306 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3307 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3308 .xlevel = 0x80000008, 3309 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3310 .versions = (X86CPUVersionDefinition[]) { 3311 { .version = 1 }, 3312 { 3313 .version = 2, 3314 .alias = "Westmere-IBRS", 3315 .props = (PropValue[]) { 3316 { "spec-ctrl", "on" }, 3317 { "model-id", 3318 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3319 { /* end of list */ } 3320 } 3321 }, 3322 { /* end of list */ } 3323 } 3324 }, 3325 { 3326 .name = "SandyBridge", 3327 .level = 0xd, 3328 .vendor = CPUID_VENDOR_INTEL, 3329 .family = 6, 3330 .model = 42, 3331 .stepping = 1, 3332 .features[FEAT_1_EDX] = 3333 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3334 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3335 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3336 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3337 CPUID_DE | CPUID_FP87, 3338 .features[FEAT_1_ECX] = 3339 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3340 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3341 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3342 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3343 CPUID_EXT_SSE3, 3344 .features[FEAT_8000_0001_EDX] = 3345 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3346 CPUID_EXT2_SYSCALL, 3347 .features[FEAT_8000_0001_ECX] = 3348 CPUID_EXT3_LAHF_LM, 3349 .features[FEAT_XSAVE] = 3350 CPUID_XSAVE_XSAVEOPT, 3351 .features[FEAT_6_EAX] = 3352 CPUID_6_EAX_ARAT, 3353 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3354 MSR_VMX_BASIC_TRUE_CTLS, 3355 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3356 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3357 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3358 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3359 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3360 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3361 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3362 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3363 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3364 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3365 .features[FEAT_VMX_EXIT_CTLS] = 3366 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3367 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3368 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3369 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3370 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3371 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3372 MSR_VMX_MISC_STORE_LMA, 3373 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3374 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3375 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3376 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3377 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3378 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3379 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3380 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3381 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3382 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3383 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3384 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3385 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3386 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3387 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3388 .features[FEAT_VMX_SECONDARY_CTLS] = 3389 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3390 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3391 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3392 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3393 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3394 .xlevel = 0x80000008, 3395 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3396 .versions = (X86CPUVersionDefinition[]) { 3397 { .version = 1 }, 3398 { 3399 .version = 2, 3400 .alias = "SandyBridge-IBRS", 3401 .props = (PropValue[]) { 3402 { "spec-ctrl", "on" }, 3403 { "model-id", 3404 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3405 { /* end of list */ } 3406 } 3407 }, 3408 { /* end of list */ } 3409 } 3410 }, 3411 { 3412 .name = "IvyBridge", 3413 .level = 0xd, 3414 .vendor = CPUID_VENDOR_INTEL, 3415 .family = 6, 3416 .model = 58, 3417 .stepping = 9, 3418 .features[FEAT_1_EDX] = 3419 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3420 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3421 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3422 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3423 CPUID_DE | CPUID_FP87, 3424 .features[FEAT_1_ECX] = 3425 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3426 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3427 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3428 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3429 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3430 .features[FEAT_7_0_EBX] = 3431 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3432 CPUID_7_0_EBX_ERMS, 3433 .features[FEAT_8000_0001_EDX] = 3434 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3435 CPUID_EXT2_SYSCALL, 3436 .features[FEAT_8000_0001_ECX] = 3437 CPUID_EXT3_LAHF_LM, 3438 .features[FEAT_XSAVE] = 3439 CPUID_XSAVE_XSAVEOPT, 3440 .features[FEAT_6_EAX] = 3441 CPUID_6_EAX_ARAT, 3442 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3443 MSR_VMX_BASIC_TRUE_CTLS, 3444 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3445 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3446 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3447 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3448 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3449 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3450 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3451 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3452 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3453 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3454 .features[FEAT_VMX_EXIT_CTLS] = 3455 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3456 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3457 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3458 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3459 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3460 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3461 MSR_VMX_MISC_STORE_LMA, 3462 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3463 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3464 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3465 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3466 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3467 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3468 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3469 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3470 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3471 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3472 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3473 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3474 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3475 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3476 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3477 .features[FEAT_VMX_SECONDARY_CTLS] = 3478 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3479 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3480 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3481 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3482 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3483 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3484 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3485 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3486 .xlevel = 0x80000008, 3487 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3488 .versions = (X86CPUVersionDefinition[]) { 3489 { .version = 1 }, 3490 { 3491 .version = 2, 3492 .alias = "IvyBridge-IBRS", 3493 .props = (PropValue[]) { 3494 { "spec-ctrl", "on" }, 3495 { "model-id", 3496 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3497 { /* end of list */ } 3498 } 3499 }, 3500 { /* end of list */ } 3501 } 3502 }, 3503 { 3504 .name = "Haswell", 3505 .level = 0xd, 3506 .vendor = CPUID_VENDOR_INTEL, 3507 .family = 6, 3508 .model = 60, 3509 .stepping = 4, 3510 .features[FEAT_1_EDX] = 3511 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3512 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3513 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3514 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3515 CPUID_DE | CPUID_FP87, 3516 .features[FEAT_1_ECX] = 3517 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3518 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3519 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3520 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3521 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3522 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3523 .features[FEAT_8000_0001_EDX] = 3524 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3525 CPUID_EXT2_SYSCALL, 3526 .features[FEAT_8000_0001_ECX] = 3527 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3528 .features[FEAT_7_0_EBX] = 3529 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3530 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3531 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3532 CPUID_7_0_EBX_RTM, 3533 .features[FEAT_XSAVE] = 3534 CPUID_XSAVE_XSAVEOPT, 3535 .features[FEAT_6_EAX] = 3536 CPUID_6_EAX_ARAT, 3537 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3538 MSR_VMX_BASIC_TRUE_CTLS, 3539 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3540 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3541 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3542 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3543 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3544 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3545 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3546 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3547 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3548 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3549 .features[FEAT_VMX_EXIT_CTLS] = 3550 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3551 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3552 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3553 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3554 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3555 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3556 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3557 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3558 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3559 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3560 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3561 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3562 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3563 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3564 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3565 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3566 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3567 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3568 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3569 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3570 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3571 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3572 .features[FEAT_VMX_SECONDARY_CTLS] = 3573 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3574 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3575 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3576 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3577 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3578 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3579 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3580 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3581 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3582 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3583 .xlevel = 0x80000008, 3584 .model_id = "Intel Core Processor (Haswell)", 3585 .versions = (X86CPUVersionDefinition[]) { 3586 { .version = 1 }, 3587 { 3588 .version = 2, 3589 .alias = "Haswell-noTSX", 3590 .props = (PropValue[]) { 3591 { "hle", "off" }, 3592 { "rtm", "off" }, 3593 { "stepping", "1" }, 3594 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3595 { /* end of list */ } 3596 }, 3597 }, 3598 { 3599 .version = 3, 3600 .alias = "Haswell-IBRS", 3601 .props = (PropValue[]) { 3602 /* Restore TSX features removed by -v2 above */ 3603 { "hle", "on" }, 3604 { "rtm", "on" }, 3605 /* 3606 * Haswell and Haswell-IBRS had stepping=4 in 3607 * QEMU 4.0 and older 3608 */ 3609 { "stepping", "4" }, 3610 { "spec-ctrl", "on" }, 3611 { "model-id", 3612 "Intel Core Processor (Haswell, IBRS)" }, 3613 { /* end of list */ } 3614 } 3615 }, 3616 { 3617 .version = 4, 3618 .alias = "Haswell-noTSX-IBRS", 3619 .props = (PropValue[]) { 3620 { "hle", "off" }, 3621 { "rtm", "off" }, 3622 /* spec-ctrl was already enabled by -v3 above */ 3623 { "stepping", "1" }, 3624 { "model-id", 3625 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3626 { /* end of list */ } 3627 } 3628 }, 3629 { /* end of list */ } 3630 } 3631 }, 3632 { 3633 .name = "Broadwell", 3634 .level = 0xd, 3635 .vendor = CPUID_VENDOR_INTEL, 3636 .family = 6, 3637 .model = 61, 3638 .stepping = 2, 3639 .features[FEAT_1_EDX] = 3640 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3641 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3642 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3643 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3644 CPUID_DE | CPUID_FP87, 3645 .features[FEAT_1_ECX] = 3646 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3647 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3648 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3649 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3650 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3651 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3652 .features[FEAT_8000_0001_EDX] = 3653 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3654 CPUID_EXT2_SYSCALL, 3655 .features[FEAT_8000_0001_ECX] = 3656 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3657 .features[FEAT_7_0_EBX] = 3658 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3659 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3660 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3661 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3662 CPUID_7_0_EBX_SMAP, 3663 .features[FEAT_XSAVE] = 3664 CPUID_XSAVE_XSAVEOPT, 3665 .features[FEAT_6_EAX] = 3666 CPUID_6_EAX_ARAT, 3667 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3668 MSR_VMX_BASIC_TRUE_CTLS, 3669 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3670 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3671 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3672 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3673 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3674 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3675 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3676 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3677 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3678 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3679 .features[FEAT_VMX_EXIT_CTLS] = 3680 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3681 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3682 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3683 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3684 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3685 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3686 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3687 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3688 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3689 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3690 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3691 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3692 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3693 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3694 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3695 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3696 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3697 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3698 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3699 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3700 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3701 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3702 .features[FEAT_VMX_SECONDARY_CTLS] = 3703 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3704 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3705 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3706 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3707 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3708 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3709 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3710 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3711 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3712 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3713 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3714 .xlevel = 0x80000008, 3715 .model_id = "Intel Core Processor (Broadwell)", 3716 .versions = (X86CPUVersionDefinition[]) { 3717 { .version = 1 }, 3718 { 3719 .version = 2, 3720 .alias = "Broadwell-noTSX", 3721 .props = (PropValue[]) { 3722 { "hle", "off" }, 3723 { "rtm", "off" }, 3724 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3725 { /* end of list */ } 3726 }, 3727 }, 3728 { 3729 .version = 3, 3730 .alias = "Broadwell-IBRS", 3731 .props = (PropValue[]) { 3732 /* Restore TSX features removed by -v2 above */ 3733 { "hle", "on" }, 3734 { "rtm", "on" }, 3735 { "spec-ctrl", "on" }, 3736 { "model-id", 3737 "Intel Core Processor (Broadwell, IBRS)" }, 3738 { /* end of list */ } 3739 } 3740 }, 3741 { 3742 .version = 4, 3743 .alias = "Broadwell-noTSX-IBRS", 3744 .props = (PropValue[]) { 3745 { "hle", "off" }, 3746 { "rtm", "off" }, 3747 /* spec-ctrl was already enabled by -v3 above */ 3748 { "model-id", 3749 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3750 { /* end of list */ } 3751 } 3752 }, 3753 { /* end of list */ } 3754 } 3755 }, 3756 { 3757 .name = "Skylake-Client", 3758 .level = 0xd, 3759 .vendor = CPUID_VENDOR_INTEL, 3760 .family = 6, 3761 .model = 94, 3762 .stepping = 3, 3763 .features[FEAT_1_EDX] = 3764 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3765 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3766 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3767 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3768 CPUID_DE | CPUID_FP87, 3769 .features[FEAT_1_ECX] = 3770 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3771 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3772 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3773 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3774 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3775 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3776 .features[FEAT_8000_0001_EDX] = 3777 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3778 CPUID_EXT2_SYSCALL, 3779 .features[FEAT_8000_0001_ECX] = 3780 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3781 .features[FEAT_7_0_EBX] = 3782 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3783 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3784 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3785 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3786 CPUID_7_0_EBX_SMAP, 3787 /* XSAVES is added in version 4 */ 3788 .features[FEAT_XSAVE] = 3789 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3790 CPUID_XSAVE_XGETBV1, 3791 .features[FEAT_6_EAX] = 3792 CPUID_6_EAX_ARAT, 3793 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3794 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3795 MSR_VMX_BASIC_TRUE_CTLS, 3796 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3797 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3798 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3799 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3800 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3801 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3802 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3803 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3804 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3805 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3806 .features[FEAT_VMX_EXIT_CTLS] = 3807 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3808 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3809 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3810 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3811 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3812 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3813 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3814 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3815 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3816 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3817 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3818 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3819 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3820 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3821 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3822 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3823 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3824 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3825 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3826 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3827 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3828 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3829 .features[FEAT_VMX_SECONDARY_CTLS] = 3830 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3831 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3832 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3833 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3834 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3835 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3836 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3837 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3838 .xlevel = 0x80000008, 3839 .model_id = "Intel Core Processor (Skylake)", 3840 .versions = (X86CPUVersionDefinition[]) { 3841 { .version = 1 }, 3842 { 3843 .version = 2, 3844 .alias = "Skylake-Client-IBRS", 3845 .props = (PropValue[]) { 3846 { "spec-ctrl", "on" }, 3847 { "model-id", 3848 "Intel Core Processor (Skylake, IBRS)" }, 3849 { /* end of list */ } 3850 } 3851 }, 3852 { 3853 .version = 3, 3854 .alias = "Skylake-Client-noTSX-IBRS", 3855 .props = (PropValue[]) { 3856 { "hle", "off" }, 3857 { "rtm", "off" }, 3858 { "model-id", 3859 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3860 { /* end of list */ } 3861 } 3862 }, 3863 { 3864 .version = 4, 3865 .note = "IBRS, XSAVES, no TSX", 3866 .props = (PropValue[]) { 3867 { "xsaves", "on" }, 3868 { "vmx-xsaves", "on" }, 3869 { /* end of list */ } 3870 } 3871 }, 3872 { /* end of list */ } 3873 } 3874 }, 3875 { 3876 .name = "Skylake-Server", 3877 .level = 0xd, 3878 .vendor = CPUID_VENDOR_INTEL, 3879 .family = 6, 3880 .model = 85, 3881 .stepping = 4, 3882 .features[FEAT_1_EDX] = 3883 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3884 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3885 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3886 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3887 CPUID_DE | CPUID_FP87, 3888 .features[FEAT_1_ECX] = 3889 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3890 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3891 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3892 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3893 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3894 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3895 .features[FEAT_8000_0001_EDX] = 3896 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3897 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3898 .features[FEAT_8000_0001_ECX] = 3899 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3900 .features[FEAT_7_0_EBX] = 3901 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3902 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3903 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3904 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3905 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3906 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3907 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3908 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3909 .features[FEAT_7_0_ECX] = 3910 CPUID_7_0_ECX_PKU, 3911 /* XSAVES is added in version 5 */ 3912 .features[FEAT_XSAVE] = 3913 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3914 CPUID_XSAVE_XGETBV1, 3915 .features[FEAT_6_EAX] = 3916 CPUID_6_EAX_ARAT, 3917 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3918 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3919 MSR_VMX_BASIC_TRUE_CTLS, 3920 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3921 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3922 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3923 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3924 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3925 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3926 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3927 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3928 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3929 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3930 .features[FEAT_VMX_EXIT_CTLS] = 3931 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3932 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3933 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3934 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3935 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3936 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3937 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3938 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3939 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3940 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3941 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3942 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3943 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3944 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3945 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3946 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3947 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3948 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3949 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3950 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3951 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3952 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3953 .features[FEAT_VMX_SECONDARY_CTLS] = 3954 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3955 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3956 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3957 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3958 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3959 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3960 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3961 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3962 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3963 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3964 .xlevel = 0x80000008, 3965 .model_id = "Intel Xeon Processor (Skylake)", 3966 .versions = (X86CPUVersionDefinition[]) { 3967 { .version = 1 }, 3968 { 3969 .version = 2, 3970 .alias = "Skylake-Server-IBRS", 3971 .props = (PropValue[]) { 3972 /* clflushopt was not added to Skylake-Server-IBRS */ 3973 /* TODO: add -v3 including clflushopt */ 3974 { "clflushopt", "off" }, 3975 { "spec-ctrl", "on" }, 3976 { "model-id", 3977 "Intel Xeon Processor (Skylake, IBRS)" }, 3978 { /* end of list */ } 3979 } 3980 }, 3981 { 3982 .version = 3, 3983 .alias = "Skylake-Server-noTSX-IBRS", 3984 .props = (PropValue[]) { 3985 { "hle", "off" }, 3986 { "rtm", "off" }, 3987 { "model-id", 3988 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3989 { /* end of list */ } 3990 } 3991 }, 3992 { 3993 .version = 4, 3994 .note = "IBRS, EPT switching, no TSX", 3995 .props = (PropValue[]) { 3996 { "vmx-eptp-switching", "on" }, 3997 { /* end of list */ } 3998 } 3999 }, 4000 { 4001 .version = 5, 4002 .note = "IBRS, XSAVES, EPT switching, no TSX", 4003 .props = (PropValue[]) { 4004 { "xsaves", "on" }, 4005 { "vmx-xsaves", "on" }, 4006 { /* end of list */ } 4007 } 4008 }, 4009 { /* end of list */ } 4010 } 4011 }, 4012 { 4013 .name = "Cascadelake-Server", 4014 .level = 0xd, 4015 .vendor = CPUID_VENDOR_INTEL, 4016 .family = 6, 4017 .model = 85, 4018 .stepping = 6, 4019 .features[FEAT_1_EDX] = 4020 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4021 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4022 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4023 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4024 CPUID_DE | CPUID_FP87, 4025 .features[FEAT_1_ECX] = 4026 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4027 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4028 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4029 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4030 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4031 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4032 .features[FEAT_8000_0001_EDX] = 4033 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4034 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4035 .features[FEAT_8000_0001_ECX] = 4036 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4037 .features[FEAT_7_0_EBX] = 4038 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4039 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4040 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4041 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4042 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4043 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4044 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4045 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4046 .features[FEAT_7_0_ECX] = 4047 CPUID_7_0_ECX_PKU | 4048 CPUID_7_0_ECX_AVX512VNNI, 4049 .features[FEAT_7_0_EDX] = 4050 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4051 /* XSAVES is added in version 5 */ 4052 .features[FEAT_XSAVE] = 4053 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4054 CPUID_XSAVE_XGETBV1, 4055 .features[FEAT_6_EAX] = 4056 CPUID_6_EAX_ARAT, 4057 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4058 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4059 MSR_VMX_BASIC_TRUE_CTLS, 4060 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4061 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4062 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4063 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4064 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4065 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4066 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4067 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4068 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4069 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4070 .features[FEAT_VMX_EXIT_CTLS] = 4071 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4072 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4073 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4074 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4075 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4076 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4077 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4078 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4079 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4080 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4081 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4082 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4083 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4084 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4085 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4086 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4087 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4088 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4089 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4090 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4091 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4092 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4093 .features[FEAT_VMX_SECONDARY_CTLS] = 4094 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4095 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4096 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4097 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4098 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4099 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4100 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4101 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4102 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4103 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4104 .xlevel = 0x80000008, 4105 .model_id = "Intel Xeon Processor (Cascadelake)", 4106 .versions = (X86CPUVersionDefinition[]) { 4107 { .version = 1 }, 4108 { .version = 2, 4109 .note = "ARCH_CAPABILITIES", 4110 .props = (PropValue[]) { 4111 { "arch-capabilities", "on" }, 4112 { "rdctl-no", "on" }, 4113 { "ibrs-all", "on" }, 4114 { "skip-l1dfl-vmentry", "on" }, 4115 { "mds-no", "on" }, 4116 { /* end of list */ } 4117 }, 4118 }, 4119 { .version = 3, 4120 .alias = "Cascadelake-Server-noTSX", 4121 .note = "ARCH_CAPABILITIES, no TSX", 4122 .props = (PropValue[]) { 4123 { "hle", "off" }, 4124 { "rtm", "off" }, 4125 { /* end of list */ } 4126 }, 4127 }, 4128 { .version = 4, 4129 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 4130 .props = (PropValue[]) { 4131 { "vmx-eptp-switching", "on" }, 4132 { /* end of list */ } 4133 }, 4134 }, 4135 { .version = 5, 4136 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 4137 .props = (PropValue[]) { 4138 { "xsaves", "on" }, 4139 { "vmx-xsaves", "on" }, 4140 { /* end of list */ } 4141 }, 4142 }, 4143 { /* end of list */ } 4144 } 4145 }, 4146 { 4147 .name = "Cooperlake", 4148 .level = 0xd, 4149 .vendor = CPUID_VENDOR_INTEL, 4150 .family = 6, 4151 .model = 85, 4152 .stepping = 10, 4153 .features[FEAT_1_EDX] = 4154 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4155 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4156 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4157 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4158 CPUID_DE | CPUID_FP87, 4159 .features[FEAT_1_ECX] = 4160 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4161 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4162 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4163 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4164 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4165 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4166 .features[FEAT_8000_0001_EDX] = 4167 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4168 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4169 .features[FEAT_8000_0001_ECX] = 4170 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4171 .features[FEAT_7_0_EBX] = 4172 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4173 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4174 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4175 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4176 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4177 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4178 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4179 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4180 .features[FEAT_7_0_ECX] = 4181 CPUID_7_0_ECX_PKU | 4182 CPUID_7_0_ECX_AVX512VNNI, 4183 .features[FEAT_7_0_EDX] = 4184 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 4185 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 4186 .features[FEAT_ARCH_CAPABILITIES] = 4187 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4188 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4189 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4190 .features[FEAT_7_1_EAX] = 4191 CPUID_7_1_EAX_AVX512_BF16, 4192 /* XSAVES is added in version 2 */ 4193 .features[FEAT_XSAVE] = 4194 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4195 CPUID_XSAVE_XGETBV1, 4196 .features[FEAT_6_EAX] = 4197 CPUID_6_EAX_ARAT, 4198 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4199 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4200 MSR_VMX_BASIC_TRUE_CTLS, 4201 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4202 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4203 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4204 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4205 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4206 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4207 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4208 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4209 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4210 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4211 .features[FEAT_VMX_EXIT_CTLS] = 4212 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4213 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4214 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4215 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4216 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4217 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4218 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4219 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4220 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4221 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4222 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4223 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4224 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4225 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4226 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4227 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4228 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4229 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4230 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4231 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4232 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4233 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4234 .features[FEAT_VMX_SECONDARY_CTLS] = 4235 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4236 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4237 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4238 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4239 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4240 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4241 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4242 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4243 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4244 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4245 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4246 .xlevel = 0x80000008, 4247 .model_id = "Intel Xeon Processor (Cooperlake)", 4248 .versions = (X86CPUVersionDefinition[]) { 4249 { .version = 1 }, 4250 { .version = 2, 4251 .note = "XSAVES", 4252 .props = (PropValue[]) { 4253 { "xsaves", "on" }, 4254 { "vmx-xsaves", "on" }, 4255 { /* end of list */ } 4256 }, 4257 }, 4258 { /* end of list */ } 4259 } 4260 }, 4261 { 4262 .name = "Icelake-Server", 4263 .level = 0xd, 4264 .vendor = CPUID_VENDOR_INTEL, 4265 .family = 6, 4266 .model = 134, 4267 .stepping = 0, 4268 .features[FEAT_1_EDX] = 4269 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4270 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4271 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4272 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4273 CPUID_DE | CPUID_FP87, 4274 .features[FEAT_1_ECX] = 4275 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4276 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4277 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4278 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4279 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4280 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4281 .features[FEAT_8000_0001_EDX] = 4282 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4283 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4284 .features[FEAT_8000_0001_ECX] = 4285 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4286 .features[FEAT_8000_0008_EBX] = 4287 CPUID_8000_0008_EBX_WBNOINVD, 4288 .features[FEAT_7_0_EBX] = 4289 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4290 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4291 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4292 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4293 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4294 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4295 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4296 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4297 .features[FEAT_7_0_ECX] = 4298 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4299 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4300 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4301 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4302 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4303 .features[FEAT_7_0_EDX] = 4304 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4305 /* XSAVES is added in version 5 */ 4306 .features[FEAT_XSAVE] = 4307 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4308 CPUID_XSAVE_XGETBV1, 4309 .features[FEAT_6_EAX] = 4310 CPUID_6_EAX_ARAT, 4311 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4312 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4313 MSR_VMX_BASIC_TRUE_CTLS, 4314 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4315 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4316 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4317 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4318 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4319 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4320 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4321 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4322 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4323 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4324 .features[FEAT_VMX_EXIT_CTLS] = 4325 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4326 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4327 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4328 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4329 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4330 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4331 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4332 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4333 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4334 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4335 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4336 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4337 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4338 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4339 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4340 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4341 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4342 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4343 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4344 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4345 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4346 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4347 .features[FEAT_VMX_SECONDARY_CTLS] = 4348 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4349 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4350 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4351 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4352 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4353 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4354 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4355 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4356 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4357 .xlevel = 0x80000008, 4358 .model_id = "Intel Xeon Processor (Icelake)", 4359 .versions = (X86CPUVersionDefinition[]) { 4360 { .version = 1 }, 4361 { 4362 .version = 2, 4363 .note = "no TSX", 4364 .alias = "Icelake-Server-noTSX", 4365 .props = (PropValue[]) { 4366 { "hle", "off" }, 4367 { "rtm", "off" }, 4368 { /* end of list */ } 4369 }, 4370 }, 4371 { 4372 .version = 3, 4373 .props = (PropValue[]) { 4374 { "arch-capabilities", "on" }, 4375 { "rdctl-no", "on" }, 4376 { "ibrs-all", "on" }, 4377 { "skip-l1dfl-vmentry", "on" }, 4378 { "mds-no", "on" }, 4379 { "pschange-mc-no", "on" }, 4380 { "taa-no", "on" }, 4381 { /* end of list */ } 4382 }, 4383 }, 4384 { 4385 .version = 4, 4386 .props = (PropValue[]) { 4387 { "sha-ni", "on" }, 4388 { "avx512ifma", "on" }, 4389 { "rdpid", "on" }, 4390 { "fsrm", "on" }, 4391 { "vmx-rdseed-exit", "on" }, 4392 { "vmx-pml", "on" }, 4393 { "vmx-eptp-switching", "on" }, 4394 { "model", "106" }, 4395 { /* end of list */ } 4396 }, 4397 }, 4398 { 4399 .version = 5, 4400 .note = "XSAVES", 4401 .props = (PropValue[]) { 4402 { "xsaves", "on" }, 4403 { "vmx-xsaves", "on" }, 4404 { /* end of list */ } 4405 }, 4406 }, 4407 { 4408 .version = 6, 4409 .note = "5-level EPT", 4410 .props = (PropValue[]) { 4411 { "vmx-page-walk-5", "on" }, 4412 { /* end of list */ } 4413 }, 4414 }, 4415 { 4416 .version = 7, 4417 .note = "TSX, taa-no", 4418 .props = (PropValue[]) { 4419 /* Restore TSX features removed by -v2 above */ 4420 { "hle", "on" }, 4421 { "rtm", "on" }, 4422 { /* end of list */ } 4423 }, 4424 }, 4425 { /* end of list */ } 4426 } 4427 }, 4428 { 4429 .name = "SapphireRapids", 4430 .level = 0x20, 4431 .vendor = CPUID_VENDOR_INTEL, 4432 .family = 6, 4433 .model = 143, 4434 .stepping = 4, 4435 /* 4436 * please keep the ascending order so that we can have a clear view of 4437 * bit position of each feature. 4438 */ 4439 .features[FEAT_1_EDX] = 4440 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4441 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4442 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4443 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4444 CPUID_SSE | CPUID_SSE2, 4445 .features[FEAT_1_ECX] = 4446 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4447 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4448 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4449 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4450 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4451 .features[FEAT_8000_0001_EDX] = 4452 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4453 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4454 .features[FEAT_8000_0001_ECX] = 4455 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4456 .features[FEAT_8000_0008_EBX] = 4457 CPUID_8000_0008_EBX_WBNOINVD, 4458 .features[FEAT_7_0_EBX] = 4459 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4460 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4461 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4462 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4463 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4464 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4465 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4466 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4467 .features[FEAT_7_0_ECX] = 4468 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4469 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4470 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4471 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4472 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4473 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4474 .features[FEAT_7_0_EDX] = 4475 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4476 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4477 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4478 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4479 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4480 .features[FEAT_ARCH_CAPABILITIES] = 4481 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4482 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4483 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4484 .features[FEAT_XSAVE] = 4485 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4486 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4487 .features[FEAT_6_EAX] = 4488 CPUID_6_EAX_ARAT, 4489 .features[FEAT_7_1_EAX] = 4490 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4491 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4492 .features[FEAT_VMX_BASIC] = 4493 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4494 .features[FEAT_VMX_ENTRY_CTLS] = 4495 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4496 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4497 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4498 .features[FEAT_VMX_EPT_VPID_CAPS] = 4499 MSR_VMX_EPT_EXECONLY | 4500 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4501 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4502 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4503 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4504 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4505 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4506 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4507 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4508 .features[FEAT_VMX_EXIT_CTLS] = 4509 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4510 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4511 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4512 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4513 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4514 .features[FEAT_VMX_MISC] = 4515 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4516 MSR_VMX_MISC_VMWRITE_VMEXIT, 4517 .features[FEAT_VMX_PINBASED_CTLS] = 4518 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4519 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4520 VMX_PIN_BASED_POSTED_INTR, 4521 .features[FEAT_VMX_PROCBASED_CTLS] = 4522 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4523 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4524 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4525 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4526 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4527 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4528 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4529 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4530 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4531 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4532 VMX_CPU_BASED_PAUSE_EXITING | 4533 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4534 .features[FEAT_VMX_SECONDARY_CTLS] = 4535 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4536 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4537 VMX_SECONDARY_EXEC_RDTSCP | 4538 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4539 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4540 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4541 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4542 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4543 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4544 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4545 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4546 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4547 VMX_SECONDARY_EXEC_XSAVES, 4548 .features[FEAT_VMX_VMFUNC] = 4549 MSR_VMX_VMFUNC_EPT_SWITCHING, 4550 .xlevel = 0x80000008, 4551 .model_id = "Intel Xeon Processor (SapphireRapids)", 4552 .versions = (X86CPUVersionDefinition[]) { 4553 { .version = 1 }, 4554 { 4555 .version = 2, 4556 .props = (PropValue[]) { 4557 { "sbdr-ssdp-no", "on" }, 4558 { "fbsdp-no", "on" }, 4559 { "psdp-no", "on" }, 4560 { /* end of list */ } 4561 } 4562 }, 4563 { 4564 .version = 3, 4565 .props = (PropValue[]) { 4566 { "ss", "on" }, 4567 { "tsc-adjust", "on" }, 4568 { "cldemote", "on" }, 4569 { "movdiri", "on" }, 4570 { "movdir64b", "on" }, 4571 { /* end of list */ } 4572 } 4573 }, 4574 { /* end of list */ } 4575 } 4576 }, 4577 { 4578 .name = "GraniteRapids", 4579 .level = 0x20, 4580 .vendor = CPUID_VENDOR_INTEL, 4581 .family = 6, 4582 .model = 173, 4583 .stepping = 0, 4584 /* 4585 * please keep the ascending order so that we can have a clear view of 4586 * bit position of each feature. 4587 */ 4588 .features[FEAT_1_EDX] = 4589 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4590 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4591 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4592 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4593 CPUID_SSE | CPUID_SSE2, 4594 .features[FEAT_1_ECX] = 4595 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4596 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4597 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4598 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4599 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4600 .features[FEAT_8000_0001_EDX] = 4601 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4602 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4603 .features[FEAT_8000_0001_ECX] = 4604 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4605 .features[FEAT_8000_0008_EBX] = 4606 CPUID_8000_0008_EBX_WBNOINVD, 4607 .features[FEAT_7_0_EBX] = 4608 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4609 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4610 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4611 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4612 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4613 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4614 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4615 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4616 .features[FEAT_7_0_ECX] = 4617 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4618 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4619 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4620 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4621 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4622 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4623 .features[FEAT_7_0_EDX] = 4624 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4625 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4626 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4627 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4628 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4629 .features[FEAT_ARCH_CAPABILITIES] = 4630 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4631 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4632 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4633 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4634 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4635 .features[FEAT_XSAVE] = 4636 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4637 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4638 .features[FEAT_6_EAX] = 4639 CPUID_6_EAX_ARAT, 4640 .features[FEAT_7_1_EAX] = 4641 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4642 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4643 CPUID_7_1_EAX_AMX_FP16, 4644 .features[FEAT_7_1_EDX] = 4645 CPUID_7_1_EDX_PREFETCHITI, 4646 .features[FEAT_7_2_EDX] = 4647 CPUID_7_2_EDX_MCDT_NO, 4648 .features[FEAT_VMX_BASIC] = 4649 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4650 .features[FEAT_VMX_ENTRY_CTLS] = 4651 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4652 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4653 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4654 .features[FEAT_VMX_EPT_VPID_CAPS] = 4655 MSR_VMX_EPT_EXECONLY | 4656 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4657 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4658 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4659 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4660 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4661 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4662 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4663 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4664 .features[FEAT_VMX_EXIT_CTLS] = 4665 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4666 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4667 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4668 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4669 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4670 .features[FEAT_VMX_MISC] = 4671 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4672 MSR_VMX_MISC_VMWRITE_VMEXIT, 4673 .features[FEAT_VMX_PINBASED_CTLS] = 4674 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4675 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4676 VMX_PIN_BASED_POSTED_INTR, 4677 .features[FEAT_VMX_PROCBASED_CTLS] = 4678 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4679 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4680 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4681 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4682 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4683 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4684 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4685 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4686 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4687 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4688 VMX_CPU_BASED_PAUSE_EXITING | 4689 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4690 .features[FEAT_VMX_SECONDARY_CTLS] = 4691 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4692 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4693 VMX_SECONDARY_EXEC_RDTSCP | 4694 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4695 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4696 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4697 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4698 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4699 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4700 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4701 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4702 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4703 VMX_SECONDARY_EXEC_XSAVES, 4704 .features[FEAT_VMX_VMFUNC] = 4705 MSR_VMX_VMFUNC_EPT_SWITCHING, 4706 .xlevel = 0x80000008, 4707 .model_id = "Intel Xeon Processor (GraniteRapids)", 4708 .versions = (X86CPUVersionDefinition[]) { 4709 { .version = 1 }, 4710 { 4711 .version = 2, 4712 .props = (PropValue[]) { 4713 { "ss", "on" }, 4714 { "tsc-adjust", "on" }, 4715 { "cldemote", "on" }, 4716 { "movdiri", "on" }, 4717 { "movdir64b", "on" }, 4718 { "avx10", "on" }, 4719 { "avx10-128", "on" }, 4720 { "avx10-256", "on" }, 4721 { "avx10-512", "on" }, 4722 { "avx10-version", "1" }, 4723 { "stepping", "1" }, 4724 { /* end of list */ } 4725 } 4726 }, 4727 { /* end of list */ }, 4728 }, 4729 }, 4730 { 4731 .name = "SierraForest", 4732 .level = 0x23, 4733 .vendor = CPUID_VENDOR_INTEL, 4734 .family = 6, 4735 .model = 175, 4736 .stepping = 0, 4737 /* 4738 * please keep the ascending order so that we can have a clear view of 4739 * bit position of each feature. 4740 */ 4741 .features[FEAT_1_EDX] = 4742 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4743 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4744 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4745 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4746 CPUID_SSE | CPUID_SSE2, 4747 .features[FEAT_1_ECX] = 4748 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4749 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4750 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4751 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4752 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4753 .features[FEAT_8000_0001_EDX] = 4754 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4755 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4756 .features[FEAT_8000_0001_ECX] = 4757 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4758 .features[FEAT_8000_0008_EBX] = 4759 CPUID_8000_0008_EBX_WBNOINVD, 4760 .features[FEAT_7_0_EBX] = 4761 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4762 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4763 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4764 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4765 CPUID_7_0_EBX_SHA_NI, 4766 .features[FEAT_7_0_ECX] = 4767 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4768 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4769 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4770 .features[FEAT_7_0_EDX] = 4771 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4772 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4773 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4774 .features[FEAT_ARCH_CAPABILITIES] = 4775 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4776 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4777 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4778 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4779 MSR_ARCH_CAP_PBRSB_NO, 4780 .features[FEAT_XSAVE] = 4781 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4782 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4783 .features[FEAT_6_EAX] = 4784 CPUID_6_EAX_ARAT, 4785 .features[FEAT_7_1_EAX] = 4786 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4787 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4788 .features[FEAT_7_1_EDX] = 4789 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4790 .features[FEAT_7_2_EDX] = 4791 CPUID_7_2_EDX_MCDT_NO, 4792 .features[FEAT_VMX_BASIC] = 4793 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4794 .features[FEAT_VMX_ENTRY_CTLS] = 4795 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4796 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4797 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4798 .features[FEAT_VMX_EPT_VPID_CAPS] = 4799 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4800 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4801 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4802 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4803 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4804 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4805 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4806 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4807 .features[FEAT_VMX_EXIT_CTLS] = 4808 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4809 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4810 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4811 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4812 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4813 .features[FEAT_VMX_MISC] = 4814 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4815 MSR_VMX_MISC_VMWRITE_VMEXIT, 4816 .features[FEAT_VMX_PINBASED_CTLS] = 4817 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4818 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4819 VMX_PIN_BASED_POSTED_INTR, 4820 .features[FEAT_VMX_PROCBASED_CTLS] = 4821 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4822 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4823 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4824 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4825 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4826 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4827 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4828 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4829 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4830 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4831 VMX_CPU_BASED_PAUSE_EXITING | 4832 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4833 .features[FEAT_VMX_SECONDARY_CTLS] = 4834 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4835 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4836 VMX_SECONDARY_EXEC_RDTSCP | 4837 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4838 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4839 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4840 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4841 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4842 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4843 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4844 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4845 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4846 VMX_SECONDARY_EXEC_XSAVES, 4847 .features[FEAT_VMX_VMFUNC] = 4848 MSR_VMX_VMFUNC_EPT_SWITCHING, 4849 .xlevel = 0x80000008, 4850 .model_id = "Intel Xeon Processor (SierraForest)", 4851 .versions = (X86CPUVersionDefinition[]) { 4852 { .version = 1 }, 4853 { 4854 .version = 2, 4855 .props = (PropValue[]) { 4856 { "ss", "on" }, 4857 { "tsc-adjust", "on" }, 4858 { "cldemote", "on" }, 4859 { "movdiri", "on" }, 4860 { "movdir64b", "on" }, 4861 { "gds-no", "on" }, 4862 { "rfds-no", "on" }, 4863 { "lam", "on" }, 4864 { "intel-psfd", "on"}, 4865 { "ipred-ctrl", "on"}, 4866 { "rrsba-ctrl", "on"}, 4867 { "bhi-ctrl", "on"}, 4868 { "stepping", "3" }, 4869 { /* end of list */ } 4870 } 4871 }, 4872 { /* end of list */ }, 4873 }, 4874 }, 4875 { 4876 .name = "ClearwaterForest", 4877 .level = 0x23, 4878 .xlevel = 0x80000008, 4879 .vendor = CPUID_VENDOR_INTEL, 4880 .family = 6, 4881 .model = 221, 4882 .stepping = 0, 4883 /* 4884 * please keep the ascending order so that we can have a clear view of 4885 * bit position of each feature. 4886 */ 4887 .features[FEAT_1_EDX] = 4888 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4889 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4890 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4891 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4892 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 4893 .features[FEAT_1_ECX] = 4894 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4895 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4896 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4897 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4898 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4899 .features[FEAT_8000_0001_EDX] = 4900 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4901 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4902 .features[FEAT_8000_0001_ECX] = 4903 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4904 .features[FEAT_8000_0008_EBX] = 4905 CPUID_8000_0008_EBX_WBNOINVD, 4906 .features[FEAT_7_0_EBX] = 4907 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 4908 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4909 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4910 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4911 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4912 CPUID_7_0_EBX_SHA_NI, 4913 .features[FEAT_7_0_ECX] = 4914 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4915 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4916 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 4917 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 4918 CPUID_7_0_ECX_MOVDIR64B, 4919 .features[FEAT_7_0_EDX] = 4920 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4921 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4922 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4923 .features[FEAT_ARCH_CAPABILITIES] = 4924 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4925 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4926 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4927 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4928 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 4929 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 4930 .features[FEAT_XSAVE] = 4931 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4932 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4933 .features[FEAT_6_EAX] = 4934 CPUID_6_EAX_ARAT, 4935 .features[FEAT_7_1_EAX] = 4936 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 4937 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4938 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 4939 CPUID_7_1_EAX_LAM, 4940 .features[FEAT_7_1_EDX] = 4941 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 4942 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 4943 .features[FEAT_7_2_EDX] = 4944 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 4945 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 4946 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 4947 .features[FEAT_VMX_BASIC] = 4948 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4949 .features[FEAT_VMX_ENTRY_CTLS] = 4950 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4951 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4952 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4953 .features[FEAT_VMX_EPT_VPID_CAPS] = 4954 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4955 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4956 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4957 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4958 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4959 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4960 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4961 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4962 .features[FEAT_VMX_EXIT_CTLS] = 4963 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4964 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4965 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4966 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4967 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4968 .features[FEAT_VMX_MISC] = 4969 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4970 MSR_VMX_MISC_VMWRITE_VMEXIT, 4971 .features[FEAT_VMX_PINBASED_CTLS] = 4972 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4973 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4974 VMX_PIN_BASED_POSTED_INTR, 4975 .features[FEAT_VMX_PROCBASED_CTLS] = 4976 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4977 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4978 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4979 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4980 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4981 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4982 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4983 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4984 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4985 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4986 VMX_CPU_BASED_PAUSE_EXITING | 4987 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4988 .features[FEAT_VMX_SECONDARY_CTLS] = 4989 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4990 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4991 VMX_SECONDARY_EXEC_RDTSCP | 4992 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4993 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4994 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4995 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4996 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4997 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4998 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4999 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5000 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 5001 VMX_SECONDARY_EXEC_XSAVES, 5002 .features[FEAT_VMX_VMFUNC] = 5003 MSR_VMX_VMFUNC_EPT_SWITCHING, 5004 .model_id = "Intel Xeon Processor (ClearwaterForest)", 5005 .versions = (X86CPUVersionDefinition[]) { 5006 { .version = 1 }, 5007 { /* end of list */ }, 5008 }, 5009 }, 5010 { 5011 .name = "Denverton", 5012 .level = 21, 5013 .vendor = CPUID_VENDOR_INTEL, 5014 .family = 6, 5015 .model = 95, 5016 .stepping = 1, 5017 .features[FEAT_1_EDX] = 5018 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 5019 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 5020 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5021 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 5022 CPUID_SSE | CPUID_SSE2, 5023 .features[FEAT_1_ECX] = 5024 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 5025 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 5026 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5027 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 5028 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 5029 .features[FEAT_8000_0001_EDX] = 5030 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 5031 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 5032 .features[FEAT_8000_0001_ECX] = 5033 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5034 .features[FEAT_7_0_EBX] = 5035 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 5036 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 5037 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 5038 .features[FEAT_7_0_EDX] = 5039 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 5040 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5041 /* XSAVES is added in version 3 */ 5042 .features[FEAT_XSAVE] = 5043 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 5044 .features[FEAT_6_EAX] = 5045 CPUID_6_EAX_ARAT, 5046 .features[FEAT_ARCH_CAPABILITIES] = 5047 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 5048 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 5049 MSR_VMX_BASIC_TRUE_CTLS, 5050 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 5051 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 5052 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 5053 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 5054 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 5055 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 5056 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5057 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5058 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5059 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 5060 .features[FEAT_VMX_EXIT_CTLS] = 5061 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5062 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5063 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 5064 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5065 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5066 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 5067 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 5068 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 5069 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 5070 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 5071 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5072 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5073 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5074 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5075 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5076 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 5077 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5078 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5079 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 5080 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5081 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5082 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5083 .features[FEAT_VMX_SECONDARY_CTLS] = 5084 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5085 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 5086 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 5087 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5088 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5089 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5090 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5091 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5092 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5093 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 5094 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5095 .xlevel = 0x80000008, 5096 .model_id = "Intel Atom Processor (Denverton)", 5097 .versions = (X86CPUVersionDefinition[]) { 5098 { .version = 1 }, 5099 { 5100 .version = 2, 5101 .note = "no MPX, no MONITOR", 5102 .props = (PropValue[]) { 5103 { "monitor", "off" }, 5104 { "mpx", "off" }, 5105 { /* end of list */ }, 5106 }, 5107 }, 5108 { 5109 .version = 3, 5110 .note = "XSAVES, no MPX, no MONITOR", 5111 .props = (PropValue[]) { 5112 { "xsaves", "on" }, 5113 { "vmx-xsaves", "on" }, 5114 { /* end of list */ }, 5115 }, 5116 }, 5117 { /* end of list */ }, 5118 }, 5119 }, 5120 { 5121 .name = "Snowridge", 5122 .level = 27, 5123 .vendor = CPUID_VENDOR_INTEL, 5124 .family = 6, 5125 .model = 134, 5126 .stepping = 1, 5127 .features[FEAT_1_EDX] = 5128 /* missing: CPUID_PN CPUID_IA64 */ 5129 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 5130 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 5131 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 5132 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 5133 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5134 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 5135 CPUID_MMX | 5136 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 5137 .features[FEAT_1_ECX] = 5138 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 5139 CPUID_EXT_SSSE3 | 5140 CPUID_EXT_CX16 | 5141 CPUID_EXT_SSE41 | 5142 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5143 CPUID_EXT_POPCNT | 5144 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 5145 CPUID_EXT_RDRAND, 5146 .features[FEAT_8000_0001_EDX] = 5147 CPUID_EXT2_SYSCALL | 5148 CPUID_EXT2_NX | 5149 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5150 CPUID_EXT2_LM, 5151 .features[FEAT_8000_0001_ECX] = 5152 CPUID_EXT3_LAHF_LM | 5153 CPUID_EXT3_3DNOWPREFETCH, 5154 .features[FEAT_7_0_EBX] = 5155 CPUID_7_0_EBX_FSGSBASE | 5156 CPUID_7_0_EBX_SMEP | 5157 CPUID_7_0_EBX_ERMS | 5158 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 5159 CPUID_7_0_EBX_RDSEED | 5160 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5161 CPUID_7_0_EBX_CLWB | 5162 CPUID_7_0_EBX_SHA_NI, 5163 .features[FEAT_7_0_ECX] = 5164 CPUID_7_0_ECX_UMIP | 5165 /* missing bit 5 */ 5166 CPUID_7_0_ECX_GFNI | 5167 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 5168 CPUID_7_0_ECX_MOVDIR64B, 5169 .features[FEAT_7_0_EDX] = 5170 CPUID_7_0_EDX_SPEC_CTRL | 5171 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 5172 CPUID_7_0_EDX_CORE_CAPABILITY, 5173 .features[FEAT_CORE_CAPABILITY] = 5174 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 5175 /* XSAVES is added in version 3 */ 5176 .features[FEAT_XSAVE] = 5177 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5178 CPUID_XSAVE_XGETBV1, 5179 .features[FEAT_6_EAX] = 5180 CPUID_6_EAX_ARAT, 5181 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 5182 MSR_VMX_BASIC_TRUE_CTLS, 5183 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 5184 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 5185 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 5186 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 5187 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 5188 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 5189 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5190 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5191 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5192 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 5193 .features[FEAT_VMX_EXIT_CTLS] = 5194 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5195 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5196 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 5197 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5198 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5199 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 5200 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 5201 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 5202 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 5203 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 5204 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5205 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5206 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5207 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5208 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5209 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 5210 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5211 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5212 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 5213 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5214 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5215 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5216 .features[FEAT_VMX_SECONDARY_CTLS] = 5217 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5218 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 5219 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 5220 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5221 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5222 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5223 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5224 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5225 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5226 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 5227 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5228 .xlevel = 0x80000008, 5229 .model_id = "Intel Atom Processor (SnowRidge)", 5230 .versions = (X86CPUVersionDefinition[]) { 5231 { .version = 1 }, 5232 { 5233 .version = 2, 5234 .props = (PropValue[]) { 5235 { "mpx", "off" }, 5236 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 5237 { /* end of list */ }, 5238 }, 5239 }, 5240 { 5241 .version = 3, 5242 .note = "XSAVES, no MPX", 5243 .props = (PropValue[]) { 5244 { "xsaves", "on" }, 5245 { "vmx-xsaves", "on" }, 5246 { /* end of list */ }, 5247 }, 5248 }, 5249 { 5250 .version = 4, 5251 .note = "no split lock detect, no core-capability", 5252 .props = (PropValue[]) { 5253 { "split-lock-detect", "off" }, 5254 { "core-capability", "off" }, 5255 { /* end of list */ }, 5256 }, 5257 }, 5258 { /* end of list */ }, 5259 }, 5260 }, 5261 { 5262 .name = "KnightsMill", 5263 .level = 0xd, 5264 .vendor = CPUID_VENDOR_INTEL, 5265 .family = 6, 5266 .model = 133, 5267 .stepping = 0, 5268 .features[FEAT_1_EDX] = 5269 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 5270 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5271 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5272 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5273 CPUID_PSE | CPUID_DE | CPUID_FP87, 5274 .features[FEAT_1_ECX] = 5275 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5276 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 5277 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 5278 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5279 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 5280 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5281 .features[FEAT_8000_0001_EDX] = 5282 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5283 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5284 .features[FEAT_8000_0001_ECX] = 5285 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5286 .features[FEAT_7_0_EBX] = 5287 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5288 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5289 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 5290 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 5291 CPUID_7_0_EBX_AVX512ER, 5292 .features[FEAT_7_0_ECX] = 5293 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 5294 .features[FEAT_7_0_EDX] = 5295 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 5296 .features[FEAT_XSAVE] = 5297 CPUID_XSAVE_XSAVEOPT, 5298 .features[FEAT_6_EAX] = 5299 CPUID_6_EAX_ARAT, 5300 .xlevel = 0x80000008, 5301 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5302 }, 5303 { 5304 .name = "Opteron_G1", 5305 .level = 5, 5306 .vendor = CPUID_VENDOR_AMD, 5307 .family = 15, 5308 .model = 6, 5309 .stepping = 1, 5310 .features[FEAT_1_EDX] = 5311 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5312 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5313 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5314 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5315 CPUID_DE | CPUID_FP87, 5316 .features[FEAT_1_ECX] = 5317 CPUID_EXT_SSE3, 5318 .features[FEAT_8000_0001_EDX] = 5319 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5320 .xlevel = 0x80000008, 5321 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5322 }, 5323 { 5324 .name = "Opteron_G2", 5325 .level = 5, 5326 .vendor = CPUID_VENDOR_AMD, 5327 .family = 15, 5328 .model = 6, 5329 .stepping = 1, 5330 .features[FEAT_1_EDX] = 5331 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5332 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5333 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5334 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5335 CPUID_DE | CPUID_FP87, 5336 .features[FEAT_1_ECX] = 5337 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5338 .features[FEAT_8000_0001_EDX] = 5339 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5340 .features[FEAT_8000_0001_ECX] = 5341 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5342 .xlevel = 0x80000008, 5343 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5344 }, 5345 { 5346 .name = "Opteron_G3", 5347 .level = 5, 5348 .vendor = CPUID_VENDOR_AMD, 5349 .family = 16, 5350 .model = 2, 5351 .stepping = 3, 5352 .features[FEAT_1_EDX] = 5353 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5354 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5355 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5356 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5357 CPUID_DE | CPUID_FP87, 5358 .features[FEAT_1_ECX] = 5359 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5360 CPUID_EXT_SSE3, 5361 .features[FEAT_8000_0001_EDX] = 5362 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5363 CPUID_EXT2_RDTSCP, 5364 .features[FEAT_8000_0001_ECX] = 5365 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5366 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5367 .xlevel = 0x80000008, 5368 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5369 }, 5370 { 5371 .name = "Opteron_G4", 5372 .level = 0xd, 5373 .vendor = CPUID_VENDOR_AMD, 5374 .family = 21, 5375 .model = 1, 5376 .stepping = 2, 5377 .features[FEAT_1_EDX] = 5378 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5379 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5380 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5381 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5382 CPUID_DE | CPUID_FP87, 5383 .features[FEAT_1_ECX] = 5384 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5385 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5386 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5387 CPUID_EXT_SSE3, 5388 .features[FEAT_8000_0001_EDX] = 5389 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5390 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5391 .features[FEAT_8000_0001_ECX] = 5392 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5393 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5394 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5395 CPUID_EXT3_LAHF_LM, 5396 .features[FEAT_SVM] = 5397 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5398 /* no xsaveopt! */ 5399 .xlevel = 0x8000001A, 5400 .model_id = "AMD Opteron 62xx class CPU", 5401 }, 5402 { 5403 .name = "Opteron_G5", 5404 .level = 0xd, 5405 .vendor = CPUID_VENDOR_AMD, 5406 .family = 21, 5407 .model = 2, 5408 .stepping = 0, 5409 .features[FEAT_1_EDX] = 5410 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5411 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5412 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5413 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5414 CPUID_DE | CPUID_FP87, 5415 .features[FEAT_1_ECX] = 5416 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5417 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5418 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5419 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5420 .features[FEAT_8000_0001_EDX] = 5421 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5422 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5423 .features[FEAT_8000_0001_ECX] = 5424 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5425 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5426 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5427 CPUID_EXT3_LAHF_LM, 5428 .features[FEAT_SVM] = 5429 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5430 /* no xsaveopt! */ 5431 .xlevel = 0x8000001A, 5432 .model_id = "AMD Opteron 63xx class CPU", 5433 }, 5434 { 5435 .name = "EPYC", 5436 .level = 0xd, 5437 .vendor = CPUID_VENDOR_AMD, 5438 .family = 23, 5439 .model = 1, 5440 .stepping = 2, 5441 .features[FEAT_1_EDX] = 5442 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5443 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5444 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5445 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5446 CPUID_VME | CPUID_FP87, 5447 .features[FEAT_1_ECX] = 5448 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5449 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5450 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5451 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5452 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5453 .features[FEAT_8000_0001_EDX] = 5454 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5455 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5456 CPUID_EXT2_SYSCALL, 5457 .features[FEAT_8000_0001_ECX] = 5458 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5459 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5460 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5461 CPUID_EXT3_TOPOEXT, 5462 .features[FEAT_7_0_EBX] = 5463 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5464 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5465 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5466 CPUID_7_0_EBX_SHA_NI, 5467 .features[FEAT_XSAVE] = 5468 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5469 CPUID_XSAVE_XGETBV1, 5470 .features[FEAT_6_EAX] = 5471 CPUID_6_EAX_ARAT, 5472 .features[FEAT_SVM] = 5473 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5474 .xlevel = 0x8000001E, 5475 .model_id = "AMD EPYC Processor", 5476 .cache_info = &epyc_cache_info, 5477 .versions = (X86CPUVersionDefinition[]) { 5478 { .version = 1 }, 5479 { 5480 .version = 2, 5481 .alias = "EPYC-IBPB", 5482 .props = (PropValue[]) { 5483 { "ibpb", "on" }, 5484 { "model-id", 5485 "AMD EPYC Processor (with IBPB)" }, 5486 { /* end of list */ } 5487 } 5488 }, 5489 { 5490 .version = 3, 5491 .props = (PropValue[]) { 5492 { "ibpb", "on" }, 5493 { "perfctr-core", "on" }, 5494 { "clzero", "on" }, 5495 { "xsaveerptr", "on" }, 5496 { "xsaves", "on" }, 5497 { "model-id", 5498 "AMD EPYC Processor" }, 5499 { /* end of list */ } 5500 } 5501 }, 5502 { 5503 .version = 4, 5504 .props = (PropValue[]) { 5505 { "model-id", 5506 "AMD EPYC-v4 Processor" }, 5507 { /* end of list */ } 5508 }, 5509 .cache_info = &epyc_v4_cache_info 5510 }, 5511 { 5512 .version = 5, 5513 .props = (PropValue[]) { 5514 { "overflow-recov", "on" }, 5515 { "succor", "on" }, 5516 { "lbrv", "on" }, 5517 { "tsc-scale", "on" }, 5518 { "vmcb-clean", "on" }, 5519 { "flushbyasid", "on" }, 5520 { "pause-filter", "on" }, 5521 { "pfthreshold", "on" }, 5522 { "v-vmsave-vmload", "on" }, 5523 { "vgif", "on" }, 5524 { "model-id", 5525 "AMD EPYC-v5 Processor" }, 5526 { /* end of list */ } 5527 }, 5528 .cache_info = &epyc_v5_cache_info 5529 }, 5530 { /* end of list */ } 5531 } 5532 }, 5533 { 5534 .name = "Dhyana", 5535 .level = 0xd, 5536 .vendor = CPUID_VENDOR_HYGON, 5537 .family = 24, 5538 .model = 0, 5539 .stepping = 1, 5540 .features[FEAT_1_EDX] = 5541 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5542 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5543 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5544 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5545 CPUID_VME | CPUID_FP87, 5546 .features[FEAT_1_ECX] = 5547 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5548 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5549 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5550 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5551 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5552 .features[FEAT_8000_0001_EDX] = 5553 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5554 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5555 CPUID_EXT2_SYSCALL, 5556 .features[FEAT_8000_0001_ECX] = 5557 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5558 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5559 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5560 CPUID_EXT3_TOPOEXT, 5561 .features[FEAT_8000_0008_EBX] = 5562 CPUID_8000_0008_EBX_IBPB, 5563 .features[FEAT_7_0_EBX] = 5564 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5565 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5566 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5567 /* XSAVES is added in version 2 */ 5568 .features[FEAT_XSAVE] = 5569 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5570 CPUID_XSAVE_XGETBV1, 5571 .features[FEAT_6_EAX] = 5572 CPUID_6_EAX_ARAT, 5573 .features[FEAT_SVM] = 5574 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5575 .xlevel = 0x8000001E, 5576 .model_id = "Hygon Dhyana Processor", 5577 .cache_info = &epyc_cache_info, 5578 .versions = (X86CPUVersionDefinition[]) { 5579 { .version = 1 }, 5580 { .version = 2, 5581 .note = "XSAVES", 5582 .props = (PropValue[]) { 5583 { "xsaves", "on" }, 5584 { /* end of list */ } 5585 }, 5586 }, 5587 { /* end of list */ } 5588 } 5589 }, 5590 { 5591 .name = "EPYC-Rome", 5592 .level = 0xd, 5593 .vendor = CPUID_VENDOR_AMD, 5594 .family = 23, 5595 .model = 49, 5596 .stepping = 0, 5597 .features[FEAT_1_EDX] = 5598 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5599 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5600 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5601 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5602 CPUID_VME | CPUID_FP87, 5603 .features[FEAT_1_ECX] = 5604 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5605 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5606 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5607 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5608 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5609 .features[FEAT_8000_0001_EDX] = 5610 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5611 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5612 CPUID_EXT2_SYSCALL, 5613 .features[FEAT_8000_0001_ECX] = 5614 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5615 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5616 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5617 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5618 .features[FEAT_8000_0008_EBX] = 5619 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5620 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5621 CPUID_8000_0008_EBX_STIBP, 5622 .features[FEAT_7_0_EBX] = 5623 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5624 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5625 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5626 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5627 .features[FEAT_7_0_ECX] = 5628 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5629 .features[FEAT_XSAVE] = 5630 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5631 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5632 .features[FEAT_6_EAX] = 5633 CPUID_6_EAX_ARAT, 5634 .features[FEAT_SVM] = 5635 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5636 .xlevel = 0x8000001E, 5637 .model_id = "AMD EPYC-Rome Processor", 5638 .cache_info = &epyc_rome_cache_info, 5639 .versions = (X86CPUVersionDefinition[]) { 5640 { .version = 1 }, 5641 { 5642 .version = 2, 5643 .props = (PropValue[]) { 5644 { "ibrs", "on" }, 5645 { "amd-ssbd", "on" }, 5646 { /* end of list */ } 5647 } 5648 }, 5649 { 5650 .version = 3, 5651 .props = (PropValue[]) { 5652 { "model-id", 5653 "AMD EPYC-Rome-v3 Processor" }, 5654 { /* end of list */ } 5655 }, 5656 .cache_info = &epyc_rome_v3_cache_info 5657 }, 5658 { 5659 .version = 4, 5660 .props = (PropValue[]) { 5661 /* Erratum 1386 */ 5662 { "model-id", 5663 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5664 { "xsaves", "off" }, 5665 { /* end of list */ } 5666 }, 5667 }, 5668 { 5669 .version = 5, 5670 .props = (PropValue[]) { 5671 { "overflow-recov", "on" }, 5672 { "succor", "on" }, 5673 { "lbrv", "on" }, 5674 { "tsc-scale", "on" }, 5675 { "vmcb-clean", "on" }, 5676 { "flushbyasid", "on" }, 5677 { "pause-filter", "on" }, 5678 { "pfthreshold", "on" }, 5679 { "v-vmsave-vmload", "on" }, 5680 { "vgif", "on" }, 5681 { "model-id", 5682 "AMD EPYC-Rome-v5 Processor" }, 5683 { /* end of list */ } 5684 }, 5685 .cache_info = &epyc_rome_v5_cache_info 5686 }, 5687 { /* end of list */ } 5688 } 5689 }, 5690 { 5691 .name = "EPYC-Milan", 5692 .level = 0xd, 5693 .vendor = CPUID_VENDOR_AMD, 5694 .family = 25, 5695 .model = 1, 5696 .stepping = 1, 5697 .features[FEAT_1_EDX] = 5698 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5699 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5700 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5701 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5702 CPUID_VME | CPUID_FP87, 5703 .features[FEAT_1_ECX] = 5704 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5705 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5706 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5707 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5708 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5709 CPUID_EXT_PCID, 5710 .features[FEAT_8000_0001_EDX] = 5711 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5712 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5713 CPUID_EXT2_SYSCALL, 5714 .features[FEAT_8000_0001_ECX] = 5715 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5716 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5717 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5718 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5719 .features[FEAT_8000_0008_EBX] = 5720 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5721 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5722 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5723 CPUID_8000_0008_EBX_AMD_SSBD, 5724 .features[FEAT_7_0_EBX] = 5725 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5726 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5727 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5728 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5729 CPUID_7_0_EBX_INVPCID, 5730 .features[FEAT_7_0_ECX] = 5731 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5732 .features[FEAT_7_0_EDX] = 5733 CPUID_7_0_EDX_FSRM, 5734 .features[FEAT_XSAVE] = 5735 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5736 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5737 .features[FEAT_6_EAX] = 5738 CPUID_6_EAX_ARAT, 5739 .features[FEAT_SVM] = 5740 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5741 .xlevel = 0x8000001E, 5742 .model_id = "AMD EPYC-Milan Processor", 5743 .cache_info = &epyc_milan_cache_info, 5744 .versions = (X86CPUVersionDefinition[]) { 5745 { .version = 1 }, 5746 { 5747 .version = 2, 5748 .props = (PropValue[]) { 5749 { "model-id", 5750 "AMD EPYC-Milan-v2 Processor" }, 5751 { "vaes", "on" }, 5752 { "vpclmulqdq", "on" }, 5753 { "stibp-always-on", "on" }, 5754 { "amd-psfd", "on" }, 5755 { "no-nested-data-bp", "on" }, 5756 { "lfence-always-serializing", "on" }, 5757 { "null-sel-clr-base", "on" }, 5758 { /* end of list */ } 5759 }, 5760 .cache_info = &epyc_milan_v2_cache_info 5761 }, 5762 { 5763 .version = 3, 5764 .props = (PropValue[]) { 5765 { "overflow-recov", "on" }, 5766 { "succor", "on" }, 5767 { "lbrv", "on" }, 5768 { "tsc-scale", "on" }, 5769 { "vmcb-clean", "on" }, 5770 { "flushbyasid", "on" }, 5771 { "pause-filter", "on" }, 5772 { "pfthreshold", "on" }, 5773 { "v-vmsave-vmload", "on" }, 5774 { "vgif", "on" }, 5775 { "model-id", 5776 "AMD EPYC-Milan-v3 Processor" }, 5777 { /* end of list */ } 5778 }, 5779 .cache_info = &epyc_milan_v3_cache_info 5780 }, 5781 { /* end of list */ } 5782 } 5783 }, 5784 { 5785 .name = "EPYC-Genoa", 5786 .level = 0xd, 5787 .vendor = CPUID_VENDOR_AMD, 5788 .family = 25, 5789 .model = 17, 5790 .stepping = 0, 5791 .features[FEAT_1_EDX] = 5792 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5793 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5794 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5795 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5796 CPUID_VME | CPUID_FP87, 5797 .features[FEAT_1_ECX] = 5798 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5799 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5800 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5801 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5802 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5803 CPUID_EXT_SSE3, 5804 .features[FEAT_8000_0001_EDX] = 5805 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5806 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5807 CPUID_EXT2_SYSCALL, 5808 .features[FEAT_8000_0001_ECX] = 5809 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5810 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5811 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5812 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5813 .features[FEAT_8000_0008_EBX] = 5814 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5815 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5816 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5817 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5818 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5819 .features[FEAT_8000_0021_EAX] = 5820 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5821 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5822 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5823 CPUID_8000_0021_EAX_AUTO_IBRS, 5824 .features[FEAT_7_0_EBX] = 5825 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5826 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5827 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5828 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5829 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5830 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5831 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5832 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5833 .features[FEAT_7_0_ECX] = 5834 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5835 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5836 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5837 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5838 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5839 CPUID_7_0_ECX_RDPID, 5840 .features[FEAT_7_0_EDX] = 5841 CPUID_7_0_EDX_FSRM, 5842 .features[FEAT_7_1_EAX] = 5843 CPUID_7_1_EAX_AVX512_BF16, 5844 .features[FEAT_XSAVE] = 5845 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5846 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5847 .features[FEAT_6_EAX] = 5848 CPUID_6_EAX_ARAT, 5849 .features[FEAT_SVM] = 5850 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5851 CPUID_SVM_SVME_ADDR_CHK, 5852 .xlevel = 0x80000022, 5853 .model_id = "AMD EPYC-Genoa Processor", 5854 .cache_info = &epyc_genoa_cache_info, 5855 .versions = (X86CPUVersionDefinition[]) { 5856 { .version = 1 }, 5857 { 5858 .version = 2, 5859 .props = (PropValue[]) { 5860 { "overflow-recov", "on" }, 5861 { "succor", "on" }, 5862 { "lbrv", "on" }, 5863 { "tsc-scale", "on" }, 5864 { "vmcb-clean", "on" }, 5865 { "flushbyasid", "on" }, 5866 { "pause-filter", "on" }, 5867 { "pfthreshold", "on" }, 5868 { "v-vmsave-vmload", "on" }, 5869 { "vgif", "on" }, 5870 { "fs-gs-base-ns", "on" }, 5871 { "perfmon-v2", "on" }, 5872 { "model-id", 5873 "AMD EPYC-Genoa-v2 Processor" }, 5874 { /* end of list */ } 5875 }, 5876 .cache_info = &epyc_genoa_v2_cache_info 5877 }, 5878 { /* end of list */ } 5879 } 5880 }, 5881 { 5882 .name = "YongFeng", 5883 .level = 0x1F, 5884 .vendor = CPUID_VENDOR_ZHAOXIN1, 5885 .family = 7, 5886 .model = 11, 5887 .stepping = 3, 5888 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 5889 .features[FEAT_1_EDX] = 5890 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5891 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5892 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5893 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5894 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 5895 /* 5896 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 5897 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 5898 */ 5899 .features[FEAT_1_ECX] = 5900 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5901 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 5902 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 5903 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 5904 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5905 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5906 .features[FEAT_7_0_EBX] = 5907 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 5908 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 5909 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 5910 CPUID_7_0_EBX_FSGSBASE, 5911 /* missing: CPUID_7_0_ECX_OSPKE */ 5912 .features[FEAT_7_0_ECX] = 5913 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 5914 .features[FEAT_7_0_EDX] = 5915 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 5916 .features[FEAT_8000_0001_EDX] = 5917 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5918 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5919 .features[FEAT_8000_0001_ECX] = 5920 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 5921 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 5922 /* 5923 * TODO: When the Linux kernel introduces other existing definitions 5924 * for this leaf, remember to update the definitions here. 5925 */ 5926 .features[FEAT_C000_0001_EDX] = 5927 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 5928 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 5929 CPUID_C000_0001_EDX_ACE2 | 5930 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 5931 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 5932 .features[FEAT_XSAVE] = 5933 CPUID_XSAVE_XSAVEOPT, 5934 .features[FEAT_ARCH_CAPABILITIES] = 5935 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 5936 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 5937 MSR_ARCH_CAP_SSB_NO, 5938 .features[FEAT_VMX_PROCBASED_CTLS] = 5939 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 5940 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 5941 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 5942 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 5943 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 5944 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 5945 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 5946 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5947 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 5948 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5949 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5950 /* 5951 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 5952 * VMX_SECONDARY_EXEC_TSC_SCALING 5953 */ 5954 .features[FEAT_VMX_SECONDARY_CTLS] = 5955 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5956 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5957 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 5958 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5959 VMX_SECONDARY_EXEC_WBINVD_EXITING | 5960 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5961 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5962 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5963 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5964 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5965 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 5966 VMX_SECONDARY_EXEC_SHADOW_VMCS | 5967 VMX_SECONDARY_EXEC_ENABLE_PML, 5968 .features[FEAT_VMX_PINBASED_CTLS] = 5969 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5970 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5971 VMX_PIN_BASED_POSTED_INTR, 5972 .features[FEAT_VMX_EXIT_CTLS] = 5973 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 5974 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5975 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5976 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5977 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5978 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 5979 .features[FEAT_VMX_ENTRY_CTLS] = 5980 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5981 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5982 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5983 /* 5984 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 5985 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 5986 */ 5987 .features[FEAT_VMX_MISC] = 5988 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5989 MSR_VMX_MISC_VMWRITE_VMEXIT, 5990 /* missing: MSR_VMX_EPT_UC */ 5991 .features[FEAT_VMX_EPT_VPID_CAPS] = 5992 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5993 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5994 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5995 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5996 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 5997 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5998 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5999 .features[FEAT_VMX_BASIC] = 6000 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 6001 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 6002 .xlevel = 0x80000008, 6003 .model_id = "Zhaoxin YongFeng Processor", 6004 .versions = (X86CPUVersionDefinition[]) { 6005 { .version = 1 }, 6006 { 6007 .version = 2, 6008 .note = "with the correct model number", 6009 .props = (PropValue[]) { 6010 { "model", "0x5b" }, 6011 { /* end of list */ } 6012 } 6013 }, 6014 { /* end of list */ } 6015 } 6016 }, 6017 { 6018 .name = "EPYC-Turin", 6019 .level = 0xd, 6020 .vendor = CPUID_VENDOR_AMD, 6021 .family = 26, 6022 .model = 0, 6023 .stepping = 0, 6024 .features[FEAT_1_ECX] = 6025 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6026 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6027 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6028 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 6029 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 6030 CPUID_EXT_SSE3, 6031 .features[FEAT_1_EDX] = 6032 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6033 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6034 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6035 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6036 CPUID_VME | CPUID_FP87, 6037 .features[FEAT_6_EAX] = 6038 CPUID_6_EAX_ARAT, 6039 .features[FEAT_7_0_EBX] = 6040 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6041 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 6042 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 6043 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 6044 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 6045 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 6046 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 6047 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 6048 .features[FEAT_7_0_ECX] = 6049 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 6050 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 6051 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 6052 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 6053 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 6054 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_MOVDIRI | 6055 CPUID_7_0_ECX_MOVDIR64B, 6056 .features[FEAT_7_0_EDX] = 6057 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_AVX512_VP2INTERSECT, 6058 .features[FEAT_7_1_EAX] = 6059 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16, 6060 .features[FEAT_8000_0001_ECX] = 6061 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6062 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6063 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6064 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 6065 .features[FEAT_8000_0001_EDX] = 6066 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6067 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6068 CPUID_EXT2_SYSCALL, 6069 .features[FEAT_8000_0007_EBX] = 6070 CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR, 6071 .features[FEAT_8000_0008_EBX] = 6072 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 6073 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 6074 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 6075 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 6076 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 6077 .features[FEAT_8000_0021_EAX] = 6078 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 6079 CPUID_8000_0021_EAX_FS_GS_BASE_NS | 6080 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 6081 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 6082 CPUID_8000_0021_EAX_AUTO_IBRS | CPUID_8000_0021_EAX_PREFETCHI | 6083 CPUID_8000_0021_EAX_SBPB | CPUID_8000_0021_EAX_IBPB_BRTYPE | 6084 CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO, 6085 .features[FEAT_8000_0022_EAX] = 6086 CPUID_8000_0022_EAX_PERFMON_V2, 6087 .features[FEAT_XSAVE] = 6088 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6089 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 6090 .features[FEAT_SVM] = 6091 CPUID_SVM_NPT | CPUID_SVM_LBRV | CPUID_SVM_NRIPSAVE | 6092 CPUID_SVM_TSCSCALE | CPUID_SVM_VMCBCLEAN | CPUID_SVM_FLUSHASID | 6093 CPUID_SVM_PAUSEFILTER | CPUID_SVM_PFTHRESHOLD | 6094 CPUID_SVM_V_VMSAVE_VMLOAD | CPUID_SVM_VGIF | 6095 CPUID_SVM_VNMI | CPUID_SVM_SVME_ADDR_CHK, 6096 .xlevel = 0x80000022, 6097 .model_id = "AMD EPYC-Turin Processor", 6098 .cache_info = &epyc_turin_cache_info, 6099 }, 6100 }; 6101 6102 /* 6103 * We resolve CPU model aliases using -v1 when using "-machine 6104 * none", but this is just for compatibility while libvirt isn't 6105 * adapted to resolve CPU model versions before creating VMs. 6106 * See "Runnability guarantee of CPU models" at 6107 * docs/about/deprecated.rst. 6108 */ 6109 X86CPUVersion default_cpu_version = 1; 6110 6111 void x86_cpu_set_default_version(X86CPUVersion version) 6112 { 6113 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 6114 assert(version != CPU_VERSION_AUTO); 6115 default_cpu_version = version; 6116 } 6117 6118 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 6119 { 6120 int v = 0; 6121 const X86CPUVersionDefinition *vdef = 6122 x86_cpu_def_get_versions(model->cpudef); 6123 while (vdef->version) { 6124 v = vdef->version; 6125 vdef++; 6126 } 6127 return v; 6128 } 6129 6130 /* Return the actual version being used for a specific CPU model */ 6131 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 6132 { 6133 X86CPUVersion v = model->version; 6134 if (v == CPU_VERSION_AUTO) { 6135 v = default_cpu_version; 6136 } 6137 if (v == CPU_VERSION_LATEST) { 6138 return x86_cpu_model_last_version(model); 6139 } 6140 return v; 6141 } 6142 6143 static const Property max_x86_cpu_properties[] = { 6144 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 6145 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 6146 }; 6147 6148 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 6149 { 6150 Object *obj = OBJECT(dev); 6151 6152 if (!object_property_get_int(obj, "family", &error_abort)) { 6153 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6154 object_property_set_int(obj, "family", 15, &error_abort); 6155 object_property_set_int(obj, "model", 107, &error_abort); 6156 object_property_set_int(obj, "stepping", 1, &error_abort); 6157 } else { 6158 object_property_set_int(obj, "family", 6, &error_abort); 6159 object_property_set_int(obj, "model", 6, &error_abort); 6160 object_property_set_int(obj, "stepping", 3, &error_abort); 6161 } 6162 } 6163 6164 x86_cpu_realizefn(dev, errp); 6165 } 6166 6167 static void max_x86_cpu_class_init(ObjectClass *oc, const void *data) 6168 { 6169 DeviceClass *dc = DEVICE_CLASS(oc); 6170 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6171 6172 xcc->ordering = 9; 6173 6174 xcc->model_description = 6175 "Enables all features supported by the accelerator in the current host"; 6176 6177 device_class_set_props(dc, max_x86_cpu_properties); 6178 dc->realize = max_x86_cpu_realize; 6179 } 6180 6181 static void max_x86_cpu_initfn(Object *obj) 6182 { 6183 X86CPU *cpu = X86_CPU(obj); 6184 6185 /* We can't fill the features array here because we don't know yet if 6186 * "migratable" is true or false. 6187 */ 6188 cpu->max_features = true; 6189 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 6190 6191 /* 6192 * these defaults are used for TCG and all other accelerators 6193 * besides KVM and HVF, which overwrite these values 6194 */ 6195 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 6196 &error_abort); 6197 object_property_set_str(OBJECT(cpu), "model-id", 6198 "QEMU TCG CPU version " QEMU_HW_VERSION, 6199 &error_abort); 6200 } 6201 6202 static const TypeInfo max_x86_cpu_type_info = { 6203 .name = X86_CPU_TYPE_NAME("max"), 6204 .parent = TYPE_X86_CPU, 6205 .instance_init = max_x86_cpu_initfn, 6206 .class_init = max_x86_cpu_class_init, 6207 }; 6208 6209 static char *feature_word_description(FeatureWordInfo *f) 6210 { 6211 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 6212 6213 switch (f->type) { 6214 case CPUID_FEATURE_WORD: 6215 { 6216 const char *reg = get_register_name_32(f->cpuid.reg); 6217 assert(reg); 6218 if (!f->cpuid.needs_ecx) { 6219 return g_strdup_printf("CPUID[eax=%02Xh].%s", f->cpuid.eax, reg); 6220 } else { 6221 return g_strdup_printf("CPUID[eax=%02Xh,ecx=%02Xh].%s", 6222 f->cpuid.eax, f->cpuid.ecx, reg); 6223 } 6224 } 6225 case MSR_FEATURE_WORD: 6226 return g_strdup_printf("MSR(%02Xh)", 6227 f->msr.index); 6228 } 6229 6230 return NULL; 6231 } 6232 6233 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 6234 { 6235 FeatureWord w; 6236 6237 for (w = 0; w < FEATURE_WORDS; w++) { 6238 if (cpu->filtered_features[w]) { 6239 return true; 6240 } 6241 } 6242 6243 return false; 6244 } 6245 6246 void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 6247 const char *verbose_prefix) 6248 { 6249 CPUX86State *env = &cpu->env; 6250 FeatureWordInfo *f = &feature_word_info[w]; 6251 int i; 6252 g_autofree char *feat_word_str = feature_word_description(f); 6253 6254 if (!cpu->force_features) { 6255 env->features[w] &= ~mask; 6256 } 6257 cpu->filtered_features[w] |= mask; 6258 6259 if (!verbose_prefix) { 6260 return; 6261 } 6262 6263 for (i = 0; i < 64; ++i) { 6264 if ((1ULL << i) & mask) { 6265 warn_report("%s: %s%s%s [bit %d]", 6266 verbose_prefix, 6267 feat_word_str, 6268 f->feat_names[i] ? "." : "", 6269 f->feat_names[i] ? f->feat_names[i] : "", i); 6270 } 6271 } 6272 } 6273 6274 void mark_forced_on_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 6275 const char *verbose_prefix) 6276 { 6277 CPUX86State *env = &cpu->env; 6278 FeatureWordInfo *f = &feature_word_info[w]; 6279 int i; 6280 6281 if (!cpu->force_features) { 6282 env->features[w] |= mask; 6283 } 6284 6285 cpu->forced_on_features[w] |= mask; 6286 6287 if (!verbose_prefix) { 6288 return; 6289 } 6290 6291 for (i = 0; i < 64; ++i) { 6292 if ((1ULL << i) & mask) { 6293 g_autofree char *feat_word_str = feature_word_description(f); 6294 warn_report("%s: %s%s%s [bit %d]", 6295 verbose_prefix, 6296 feat_word_str, 6297 f->feat_names[i] ? "." : "", 6298 f->feat_names[i] ? f->feat_names[i] : "", i); 6299 } 6300 } 6301 } 6302 6303 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 6304 const char *name, void *opaque, 6305 Error **errp) 6306 { 6307 X86CPU *cpu = X86_CPU(obj); 6308 CPUX86State *env = &cpu->env; 6309 uint64_t value; 6310 6311 value = (env->cpuid_version >> 8) & 0xf; 6312 if (value == 0xf) { 6313 value += (env->cpuid_version >> 20) & 0xff; 6314 } 6315 visit_type_uint64(v, name, &value, errp); 6316 } 6317 6318 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 6319 const char *name, void *opaque, 6320 Error **errp) 6321 { 6322 X86CPU *cpu = X86_CPU(obj); 6323 CPUX86State *env = &cpu->env; 6324 const uint64_t max = 0xff + 0xf; 6325 uint64_t value; 6326 6327 if (!visit_type_uint64(v, name, &value, errp)) { 6328 return; 6329 } 6330 if (value > max) { 6331 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6332 name ? name : "null", max); 6333 return; 6334 } 6335 6336 env->cpuid_version &= ~0xff00f00; 6337 if (value > 0x0f) { 6338 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 6339 } else { 6340 env->cpuid_version |= value << 8; 6341 } 6342 } 6343 6344 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 6345 const char *name, void *opaque, 6346 Error **errp) 6347 { 6348 X86CPU *cpu = X86_CPU(obj); 6349 CPUX86State *env = &cpu->env; 6350 uint64_t value; 6351 6352 value = (env->cpuid_version >> 4) & 0xf; 6353 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 6354 visit_type_uint64(v, name, &value, errp); 6355 } 6356 6357 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 6358 const char *name, void *opaque, 6359 Error **errp) 6360 { 6361 X86CPU *cpu = X86_CPU(obj); 6362 CPUX86State *env = &cpu->env; 6363 const uint64_t max = 0xff; 6364 uint64_t value; 6365 6366 if (!visit_type_uint64(v, name, &value, errp)) { 6367 return; 6368 } 6369 if (value > max) { 6370 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6371 name ? name : "null", max); 6372 return; 6373 } 6374 6375 env->cpuid_version &= ~0xf00f0; 6376 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 6377 } 6378 6379 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 6380 const char *name, void *opaque, 6381 Error **errp) 6382 { 6383 X86CPU *cpu = X86_CPU(obj); 6384 CPUX86State *env = &cpu->env; 6385 uint64_t value; 6386 6387 value = env->cpuid_version & 0xf; 6388 visit_type_uint64(v, name, &value, errp); 6389 } 6390 6391 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 6392 const char *name, void *opaque, 6393 Error **errp) 6394 { 6395 X86CPU *cpu = X86_CPU(obj); 6396 CPUX86State *env = &cpu->env; 6397 const uint64_t max = 0xf; 6398 uint64_t value; 6399 6400 if (!visit_type_uint64(v, name, &value, errp)) { 6401 return; 6402 } 6403 if (value > max) { 6404 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6405 name ? name : "null", max); 6406 return; 6407 } 6408 6409 env->cpuid_version &= ~0xf; 6410 env->cpuid_version |= value & 0xf; 6411 } 6412 6413 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 6414 { 6415 X86CPU *cpu = X86_CPU(obj); 6416 CPUX86State *env = &cpu->env; 6417 char *value; 6418 6419 value = g_malloc(CPUID_VENDOR_SZ + 1); 6420 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 6421 env->cpuid_vendor3); 6422 return value; 6423 } 6424 6425 static void x86_cpuid_set_vendor(Object *obj, const char *value, 6426 Error **errp) 6427 { 6428 X86CPU *cpu = X86_CPU(obj); 6429 CPUX86State *env = &cpu->env; 6430 int i; 6431 6432 if (strlen(value) != CPUID_VENDOR_SZ) { 6433 error_setg(errp, "value of property 'vendor' must consist of" 6434 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 6435 return; 6436 } 6437 6438 env->cpuid_vendor1 = 0; 6439 env->cpuid_vendor2 = 0; 6440 env->cpuid_vendor3 = 0; 6441 for (i = 0; i < 4; i++) { 6442 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 6443 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 6444 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 6445 } 6446 } 6447 6448 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 6449 { 6450 X86CPU *cpu = X86_CPU(obj); 6451 CPUX86State *env = &cpu->env; 6452 char *value; 6453 int i; 6454 6455 value = g_malloc(48 + 1); 6456 for (i = 0; i < 48; i++) { 6457 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 6458 } 6459 value[48] = '\0'; 6460 return value; 6461 } 6462 6463 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 6464 Error **errp) 6465 { 6466 X86CPU *cpu = X86_CPU(obj); 6467 CPUX86State *env = &cpu->env; 6468 int c, len, i; 6469 6470 if (model_id == NULL) { 6471 model_id = ""; 6472 } 6473 len = strlen(model_id); 6474 memset(env->cpuid_model, 0, 48); 6475 for (i = 0; i < 48; i++) { 6476 if (i >= len) { 6477 c = '\0'; 6478 } else { 6479 c = (uint8_t)model_id[i]; 6480 } 6481 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 6482 } 6483 } 6484 6485 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 6486 void *opaque, Error **errp) 6487 { 6488 X86CPU *cpu = X86_CPU(obj); 6489 int64_t value; 6490 6491 value = cpu->env.tsc_khz * 1000; 6492 visit_type_int(v, name, &value, errp); 6493 } 6494 6495 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 6496 void *opaque, Error **errp) 6497 { 6498 X86CPU *cpu = X86_CPU(obj); 6499 const int64_t max = INT64_MAX; 6500 int64_t value; 6501 6502 if (!visit_type_int(v, name, &value, errp)) { 6503 return; 6504 } 6505 if (value < 0 || value > max) { 6506 error_setg(errp, "parameter '%s' can be at most %" PRId64, 6507 name ? name : "null", max); 6508 return; 6509 } 6510 6511 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 6512 } 6513 6514 /* Generic getter for "feature-words" and "filtered-features" properties */ 6515 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 6516 const char *name, void *opaque, 6517 Error **errp) 6518 { 6519 uint64_t *array = (uint64_t *)opaque; 6520 FeatureWord w; 6521 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 6522 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 6523 X86CPUFeatureWordInfoList *list = NULL; 6524 6525 for (w = 0; w < FEATURE_WORDS; w++) { 6526 FeatureWordInfo *wi = &feature_word_info[w]; 6527 /* 6528 * We didn't have MSR features when "feature-words" was 6529 * introduced. Therefore skipped other type entries. 6530 */ 6531 if (wi->type != CPUID_FEATURE_WORD) { 6532 continue; 6533 } 6534 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 6535 qwi->cpuid_input_eax = wi->cpuid.eax; 6536 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 6537 qwi->cpuid_input_ecx = wi->cpuid.ecx; 6538 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 6539 qwi->features = array[w]; 6540 6541 /* List will be in reverse order, but order shouldn't matter */ 6542 list_entries[w].next = list; 6543 list_entries[w].value = &word_infos[w]; 6544 list = &list_entries[w]; 6545 } 6546 6547 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 6548 } 6549 6550 /* Convert all '_' in a feature string option name to '-', to make feature 6551 * name conform to QOM property naming rule, which uses '-' instead of '_'. 6552 */ 6553 static inline void feat2prop(char *s) 6554 { 6555 while ((s = strchr(s, '_'))) { 6556 *s = '-'; 6557 } 6558 } 6559 6560 /* Return the feature property name for a feature flag bit */ 6561 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 6562 { 6563 const char *name; 6564 /* XSAVE components are automatically enabled by other features, 6565 * so return the original feature name instead 6566 */ 6567 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 6568 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 6569 6570 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 6571 x86_ext_save_areas[comp].bits) { 6572 w = x86_ext_save_areas[comp].feature; 6573 bitnr = ctz32(x86_ext_save_areas[comp].bits); 6574 } 6575 } 6576 6577 assert(bitnr < 64); 6578 assert(w < FEATURE_WORDS); 6579 name = feature_word_info[w].feat_names[bitnr]; 6580 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 6581 return name; 6582 } 6583 6584 /* Compatibility hack to maintain legacy +-feat semantic, 6585 * where +-feat overwrites any feature set by 6586 * feat=on|feat even if the later is parsed after +-feat 6587 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 6588 */ 6589 static GList *plus_features, *minus_features; 6590 6591 static gint compare_string(gconstpointer a, gconstpointer b) 6592 { 6593 return g_strcmp0(a, b); 6594 } 6595 6596 /* Parse "+feature,-feature,feature=foo" CPU feature string 6597 */ 6598 static void x86_cpu_parse_featurestr(const char *typename, char *features, 6599 Error **errp) 6600 { 6601 char *featurestr; /* Single 'key=value" string being parsed */ 6602 static bool cpu_globals_initialized; 6603 bool ambiguous = false; 6604 6605 if (cpu_globals_initialized) { 6606 return; 6607 } 6608 cpu_globals_initialized = true; 6609 6610 if (!features) { 6611 return; 6612 } 6613 6614 for (featurestr = strtok(features, ","); 6615 featurestr; 6616 featurestr = strtok(NULL, ",")) { 6617 const char *name; 6618 const char *val = NULL; 6619 char *eq = NULL; 6620 char num[32]; 6621 GlobalProperty *prop; 6622 6623 /* Compatibility syntax: */ 6624 if (featurestr[0] == '+') { 6625 plus_features = g_list_append(plus_features, 6626 g_strdup(featurestr + 1)); 6627 continue; 6628 } else if (featurestr[0] == '-') { 6629 minus_features = g_list_append(minus_features, 6630 g_strdup(featurestr + 1)); 6631 continue; 6632 } 6633 6634 eq = strchr(featurestr, '='); 6635 if (eq) { 6636 *eq++ = 0; 6637 val = eq; 6638 } else { 6639 val = "on"; 6640 } 6641 6642 feat2prop(featurestr); 6643 name = featurestr; 6644 6645 if (g_list_find_custom(plus_features, name, compare_string)) { 6646 warn_report("Ambiguous CPU model string. " 6647 "Don't mix both \"+%s\" and \"%s=%s\"", 6648 name, name, val); 6649 ambiguous = true; 6650 } 6651 if (g_list_find_custom(minus_features, name, compare_string)) { 6652 warn_report("Ambiguous CPU model string. " 6653 "Don't mix both \"-%s\" and \"%s=%s\"", 6654 name, name, val); 6655 ambiguous = true; 6656 } 6657 6658 /* Special case: */ 6659 if (!strcmp(name, "tsc-freq")) { 6660 int ret; 6661 uint64_t tsc_freq; 6662 6663 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 6664 if (ret < 0 || tsc_freq > INT64_MAX) { 6665 error_setg(errp, "bad numerical value %s", val); 6666 return; 6667 } 6668 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 6669 val = num; 6670 name = "tsc-frequency"; 6671 } 6672 6673 prop = g_new0(typeof(*prop), 1); 6674 prop->driver = typename; 6675 prop->property = g_strdup(name); 6676 prop->value = g_strdup(val); 6677 qdev_prop_register_global(prop); 6678 } 6679 6680 if (ambiguous) { 6681 warn_report("Compatibility of ambiguous CPU model " 6682 "strings won't be kept on future QEMU versions"); 6683 } 6684 } 6685 6686 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 6687 6688 /* Build a list with the name of all features on a feature word array */ 6689 static void x86_cpu_list_feature_names(FeatureWordArray features, 6690 strList **list) 6691 { 6692 strList **tail = list; 6693 FeatureWord w; 6694 6695 for (w = 0; w < FEATURE_WORDS; w++) { 6696 uint64_t filtered = features[w]; 6697 int i; 6698 for (i = 0; i < 64; i++) { 6699 if (filtered & (1ULL << i)) { 6700 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 6701 } 6702 } 6703 } 6704 } 6705 6706 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 6707 const char *name, void *opaque, 6708 Error **errp) 6709 { 6710 X86CPU *xc = X86_CPU(obj); 6711 strList *result = NULL; 6712 6713 x86_cpu_list_feature_names(xc->filtered_features, &result); 6714 visit_type_strList(v, "unavailable-features", &result, errp); 6715 } 6716 6717 /* Print all cpuid feature names in featureset 6718 */ 6719 static void listflags(GList *features) 6720 { 6721 size_t len = 0; 6722 GList *tmp; 6723 6724 for (tmp = features; tmp; tmp = tmp->next) { 6725 const char *name = tmp->data; 6726 if ((len + strlen(name) + 1) >= 75) { 6727 qemu_printf("\n"); 6728 len = 0; 6729 } 6730 qemu_printf("%s%s", len == 0 ? " " : " ", name); 6731 len += strlen(name) + 1; 6732 } 6733 qemu_printf("\n"); 6734 } 6735 6736 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 6737 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d) 6738 { 6739 ObjectClass *class_a = (ObjectClass *)a; 6740 ObjectClass *class_b = (ObjectClass *)b; 6741 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 6742 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 6743 int ret; 6744 6745 if (cc_a->ordering != cc_b->ordering) { 6746 ret = cc_a->ordering - cc_b->ordering; 6747 } else { 6748 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 6749 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 6750 ret = strcmp(name_a, name_b); 6751 } 6752 return ret; 6753 } 6754 6755 static GSList *get_sorted_cpu_model_list(void) 6756 { 6757 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 6758 list = g_slist_sort_with_data(list, x86_cpu_list_compare, NULL); 6759 return list; 6760 } 6761 6762 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 6763 { 6764 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 6765 char *r = object_property_get_str(obj, "model-id", &error_abort); 6766 object_unref(obj); 6767 return r; 6768 } 6769 6770 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 6771 { 6772 X86CPUVersion version; 6773 6774 if (!cc->model || !cc->model->is_alias) { 6775 return NULL; 6776 } 6777 version = x86_cpu_model_resolve_version(cc->model); 6778 if (version <= 0) { 6779 return NULL; 6780 } 6781 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 6782 } 6783 6784 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 6785 { 6786 ObjectClass *oc = data; 6787 X86CPUClass *cc = X86_CPU_CLASS(oc); 6788 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6789 g_autofree char *desc = g_strdup(cc->model_description); 6790 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6791 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6792 6793 if (!desc && alias_of) { 6794 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6795 desc = g_strdup("(alias configured by machine type)"); 6796 } else { 6797 desc = g_strdup_printf("(alias of %s)", alias_of); 6798 } 6799 } 6800 if (!desc && cc->model && cc->model->note) { 6801 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6802 } 6803 if (!desc) { 6804 desc = g_strdup(model_id); 6805 } 6806 6807 if (cc->model && cc->model->cpudef->deprecation_note) { 6808 g_autofree char *olddesc = desc; 6809 desc = g_strdup_printf("%s (deprecated)", olddesc); 6810 } 6811 6812 qemu_printf(" %-20s %s\n", name, desc); 6813 } 6814 6815 static gint strcmp_wrap(gconstpointer a, gconstpointer b, gpointer d) 6816 { 6817 return strcmp(a, b); 6818 } 6819 6820 /* list available CPU models and flags */ 6821 static void x86_cpu_list(void) 6822 { 6823 int i, j; 6824 GSList *list; 6825 GList *names = NULL; 6826 6827 qemu_printf("Available CPUs:\n"); 6828 list = get_sorted_cpu_model_list(); 6829 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6830 g_slist_free(list); 6831 6832 names = NULL; 6833 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6834 FeatureWordInfo *fw = &feature_word_info[i]; 6835 for (j = 0; j < 64; j++) { 6836 if (fw->feat_names[j]) { 6837 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6838 } 6839 } 6840 } 6841 6842 names = g_list_sort_with_data(names, strcmp_wrap, NULL); 6843 6844 qemu_printf("\nRecognized CPUID flags:\n"); 6845 listflags(names); 6846 qemu_printf("\n"); 6847 g_list_free(names); 6848 } 6849 6850 #ifndef CONFIG_USER_ONLY 6851 6852 /* Check for missing features that may prevent the CPU class from 6853 * running using the current machine and accelerator. 6854 */ 6855 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6856 strList **list) 6857 { 6858 strList **tail = list; 6859 X86CPU *xc; 6860 Error *err = NULL; 6861 6862 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6863 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6864 return; 6865 } 6866 6867 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6868 6869 x86_cpu_expand_features(xc, &err); 6870 if (err) { 6871 /* Errors at x86_cpu_expand_features should never happen, 6872 * but in case it does, just report the model as not 6873 * runnable at all using the "type" property. 6874 */ 6875 QAPI_LIST_APPEND(tail, g_strdup("type")); 6876 error_free(err); 6877 } 6878 6879 x86_cpu_filter_features(xc, false); 6880 6881 x86_cpu_list_feature_names(xc->filtered_features, tail); 6882 6883 object_unref(OBJECT(xc)); 6884 } 6885 6886 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6887 { 6888 ObjectClass *oc = data; 6889 X86CPUClass *cc = X86_CPU_CLASS(oc); 6890 CpuDefinitionInfoList **cpu_list = user_data; 6891 CpuDefinitionInfo *info; 6892 6893 info = g_malloc0(sizeof(*info)); 6894 info->name = x86_cpu_class_get_model_name(cc); 6895 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6896 info->has_unavailable_features = true; 6897 info->q_typename = g_strdup(object_class_get_name(oc)); 6898 info->migration_safe = cc->migration_safe; 6899 info->has_migration_safe = true; 6900 info->q_static = cc->static_model; 6901 if (cc->model && cc->model->cpudef->deprecation_note) { 6902 info->deprecated = true; 6903 } else { 6904 info->deprecated = false; 6905 } 6906 /* 6907 * Old machine types won't report aliases, so that alias translation 6908 * doesn't break compatibility with previous QEMU versions. 6909 */ 6910 if (default_cpu_version != CPU_VERSION_LEGACY) { 6911 info->alias_of = x86_cpu_class_get_alias_of(cc); 6912 } 6913 6914 QAPI_LIST_PREPEND(*cpu_list, info); 6915 } 6916 6917 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6918 { 6919 CpuDefinitionInfoList *cpu_list = NULL; 6920 GSList *list = get_sorted_cpu_model_list(); 6921 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6922 g_slist_free(list); 6923 return cpu_list; 6924 } 6925 6926 #endif /* !CONFIG_USER_ONLY */ 6927 6928 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6929 { 6930 FeatureWordInfo *wi = &feature_word_info[w]; 6931 uint64_t r = 0; 6932 uint64_t unavail = 0; 6933 6934 if (kvm_enabled()) { 6935 switch (wi->type) { 6936 case CPUID_FEATURE_WORD: 6937 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6938 wi->cpuid.ecx, 6939 wi->cpuid.reg); 6940 break; 6941 case MSR_FEATURE_WORD: 6942 r = kvm_arch_get_supported_msr_feature(kvm_state, 6943 wi->msr.index); 6944 break; 6945 } 6946 } else if (hvf_enabled()) { 6947 if (wi->type != CPUID_FEATURE_WORD) { 6948 return 0; 6949 } 6950 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6951 wi->cpuid.ecx, 6952 wi->cpuid.reg); 6953 } else if (tcg_enabled()) { 6954 r = wi->tcg_features; 6955 } else { 6956 return ~0; 6957 } 6958 6959 switch (w) { 6960 #ifndef TARGET_X86_64 6961 case FEAT_8000_0001_EDX: 6962 /* 6963 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6964 * way for userspace to get out of its 32-bit jail, we can leave 6965 * the LM bit set. 6966 */ 6967 unavail = tcg_enabled() 6968 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6969 : CPUID_EXT2_LM; 6970 break; 6971 #endif 6972 6973 case FEAT_8000_0007_EBX: 6974 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6975 /* Disable AMD machine check architecture for Intel CPU. */ 6976 unavail = ~0; 6977 } 6978 break; 6979 6980 case FEAT_7_0_EBX: 6981 #ifndef CONFIG_USER_ONLY 6982 if (!check_sgx_support()) { 6983 unavail = CPUID_7_0_EBX_SGX; 6984 } 6985 #endif 6986 break; 6987 case FEAT_7_0_ECX: 6988 #ifndef CONFIG_USER_ONLY 6989 if (!check_sgx_support()) { 6990 unavail = CPUID_7_0_ECX_SGX_LC; 6991 } 6992 #endif 6993 break; 6994 6995 default: 6996 break; 6997 } 6998 6999 r &= ~unavail; 7000 if (cpu && cpu->migratable) { 7001 r &= x86_cpu_get_migratable_flags(cpu, w); 7002 } 7003 return r; 7004 } 7005 7006 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 7007 uint32_t *eax, uint32_t *ebx, 7008 uint32_t *ecx, uint32_t *edx) 7009 { 7010 if (kvm_enabled()) { 7011 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 7012 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 7013 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 7014 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 7015 } else if (hvf_enabled()) { 7016 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 7017 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 7018 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 7019 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 7020 } else { 7021 *eax = 0; 7022 *ebx = 0; 7023 *ecx = 0; 7024 *edx = 0; 7025 } 7026 } 7027 7028 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 7029 uint32_t *eax, uint32_t *ebx, 7030 uint32_t *ecx, uint32_t *edx) 7031 { 7032 uint32_t level, unused; 7033 7034 /* Only return valid host leaves. */ 7035 switch (func) { 7036 case 2: 7037 case 4: 7038 host_cpuid(0, 0, &level, &unused, &unused, &unused); 7039 break; 7040 case 0x80000005: 7041 case 0x80000006: 7042 case 0x8000001d: 7043 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 7044 break; 7045 default: 7046 return; 7047 } 7048 7049 if (func > level) { 7050 *eax = 0; 7051 *ebx = 0; 7052 *ecx = 0; 7053 *edx = 0; 7054 } else { 7055 host_cpuid(func, index, eax, ebx, ecx, edx); 7056 } 7057 } 7058 7059 /* 7060 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7061 */ 7062 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 7063 { 7064 PropValue *pv; 7065 for (pv = props; pv->prop; pv++) { 7066 if (!pv->value) { 7067 continue; 7068 } 7069 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 7070 &error_abort); 7071 } 7072 } 7073 7074 /* 7075 * Apply properties for the CPU model version specified in model. 7076 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7077 */ 7078 7079 static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) 7080 { 7081 const X86CPUVersionDefinition *vdef; 7082 X86CPUVersion version = x86_cpu_model_resolve_version(model); 7083 7084 if (version == CPU_VERSION_LEGACY) { 7085 return; 7086 } 7087 7088 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 7089 PropValue *p; 7090 7091 for (p = vdef->props; p && p->prop; p++) { 7092 object_property_parse(OBJECT(cpu), p->prop, p->value, 7093 &error_abort); 7094 } 7095 7096 if (vdef->version == version) { 7097 break; 7098 } 7099 } 7100 7101 /* 7102 * If we reached the end of the list, version number was invalid 7103 */ 7104 assert(vdef->version == version); 7105 } 7106 7107 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 7108 const X86CPUModel *model) 7109 { 7110 const X86CPUVersionDefinition *vdef; 7111 X86CPUVersion version = x86_cpu_model_resolve_version(model); 7112 const CPUCaches *cache_info = model->cpudef->cache_info; 7113 7114 if (version == CPU_VERSION_LEGACY) { 7115 return cache_info; 7116 } 7117 7118 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 7119 if (vdef->cache_info) { 7120 cache_info = vdef->cache_info; 7121 } 7122 7123 if (vdef->version == version) { 7124 break; 7125 } 7126 } 7127 7128 assert(vdef->version == version); 7129 return cache_info; 7130 } 7131 7132 /* 7133 * Load data from X86CPUDefinition into a X86CPU object. 7134 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7135 */ 7136 static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) 7137 { 7138 const X86CPUDefinition *def = model->cpudef; 7139 CPUX86State *env = &cpu->env; 7140 FeatureWord w; 7141 7142 /*NOTE: any property set by this function should be returned by 7143 * x86_cpu_static_props(), so static expansion of 7144 * query-cpu-model-expansion is always complete. 7145 */ 7146 7147 /* CPU models only set _minimum_ values for level/xlevel: */ 7148 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 7149 &error_abort); 7150 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 7151 &error_abort); 7152 7153 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 7154 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 7155 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 7156 &error_abort); 7157 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 7158 &error_abort); 7159 for (w = 0; w < FEATURE_WORDS; w++) { 7160 env->features[w] = def->features[w]; 7161 } 7162 7163 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 7164 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 7165 7166 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 7167 7168 /* sysenter isn't supported in compatibility mode on AMD, 7169 * syscall isn't supported in compatibility mode on Intel. 7170 * Normally we advertise the actual CPU vendor, but you can 7171 * override this using the 'vendor' property if you want to use 7172 * KVM's sysenter/syscall emulation in compatibility mode and 7173 * when doing cross vendor migration 7174 */ 7175 7176 /* 7177 * vendor property is set here but then overloaded with the 7178 * host cpu vendor for KVM and HVF. 7179 */ 7180 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 7181 7182 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 7183 &error_abort); 7184 7185 x86_cpu_apply_version_props(cpu, model); 7186 7187 /* 7188 * Properties in versioned CPU model are not user specified features. 7189 * We can simply clear env->user_features here since it will be filled later 7190 * in x86_cpu_expand_features() based on plus_features and minus_features. 7191 */ 7192 memset(&env->user_features, 0, sizeof(env->user_features)); 7193 } 7194 7195 static const gchar *x86_gdb_arch_name(CPUState *cs) 7196 { 7197 #ifdef TARGET_X86_64 7198 return "i386:x86-64"; 7199 #else 7200 return "i386"; 7201 #endif 7202 } 7203 7204 static void x86_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 7205 { 7206 const X86CPUModel *model = data; 7207 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7208 CPUClass *cc = CPU_CLASS(oc); 7209 7210 xcc->model = model; 7211 xcc->migration_safe = true; 7212 cc->deprecation_note = model->cpudef->deprecation_note; 7213 } 7214 7215 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 7216 { 7217 g_autofree char *typename = x86_cpu_type_name(name); 7218 TypeInfo ti = { 7219 .name = typename, 7220 .parent = TYPE_X86_CPU, 7221 .class_init = x86_cpu_cpudef_class_init, 7222 .class_data = model, 7223 }; 7224 7225 type_register_static(&ti); 7226 } 7227 7228 7229 /* 7230 * register builtin_x86_defs; 7231 * "max", "base" and subclasses ("host") are not registered here. 7232 * See x86_cpu_register_types for all model registrations. 7233 */ 7234 static void x86_register_cpudef_types(const X86CPUDefinition *def) 7235 { 7236 X86CPUModel *m; 7237 const X86CPUVersionDefinition *vdef; 7238 7239 /* AMD aliases are handled at runtime based on CPUID vendor, so 7240 * they shouldn't be set on the CPU model table. 7241 */ 7242 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 7243 /* catch mistakes instead of silently truncating model_id when too long */ 7244 assert(def->model_id && strlen(def->model_id) <= 48); 7245 7246 /* Unversioned model: */ 7247 m = g_new0(X86CPUModel, 1); 7248 m->cpudef = def; 7249 m->version = CPU_VERSION_AUTO; 7250 m->is_alias = true; 7251 x86_register_cpu_model_type(def->name, m); 7252 7253 /* Versioned models: */ 7254 7255 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 7256 g_autofree char *name = 7257 x86_cpu_versioned_model_name(def, vdef->version); 7258 7259 m = g_new0(X86CPUModel, 1); 7260 m->cpudef = def; 7261 m->version = vdef->version; 7262 m->note = vdef->note; 7263 x86_register_cpu_model_type(name, m); 7264 7265 if (vdef->alias) { 7266 X86CPUModel *am = g_new0(X86CPUModel, 1); 7267 am->cpudef = def; 7268 am->version = vdef->version; 7269 am->is_alias = true; 7270 x86_register_cpu_model_type(vdef->alias, am); 7271 } 7272 } 7273 7274 } 7275 7276 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 7277 { 7278 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 7279 return 57; /* 57 bits virtual */ 7280 } else { 7281 return 48; /* 48 bits virtual */ 7282 } 7283 } 7284 7285 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 7286 uint32_t *eax, uint32_t *ebx, 7287 uint32_t *ecx, uint32_t *edx) 7288 { 7289 X86CPU *cpu = env_archcpu(env); 7290 CPUState *cs = env_cpu(env); 7291 uint32_t limit; 7292 uint32_t signature[3]; 7293 X86CPUTopoInfo *topo_info = &env->topo_info; 7294 uint32_t threads_per_pkg; 7295 7296 threads_per_pkg = x86_threads_per_pkg(topo_info); 7297 7298 /* Calculate & apply limits for different index ranges */ 7299 if (index >= 0xC0000000) { 7300 limit = env->cpuid_xlevel2; 7301 } else if (index >= 0x80000000) { 7302 limit = env->cpuid_xlevel; 7303 } else if (index >= 0x40000000) { 7304 limit = 0x40000001; 7305 } else { 7306 limit = env->cpuid_level; 7307 } 7308 7309 if (index > limit) { 7310 /* Intel documentation states that invalid EAX input will 7311 * return the same information as EAX=cpuid_level 7312 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 7313 */ 7314 index = env->cpuid_level; 7315 } 7316 7317 switch(index) { 7318 case 0: 7319 *eax = env->cpuid_level; 7320 *ebx = env->cpuid_vendor1; 7321 *edx = env->cpuid_vendor2; 7322 *ecx = env->cpuid_vendor3; 7323 break; 7324 case 1: 7325 *eax = env->cpuid_version; 7326 *ebx = (cpu->apic_id << 24) | 7327 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 7328 *ecx = env->features[FEAT_1_ECX]; 7329 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 7330 *ecx |= CPUID_EXT_OSXSAVE; 7331 } 7332 *edx = env->features[FEAT_1_EDX]; 7333 if (threads_per_pkg > 1) { 7334 *ebx |= threads_per_pkg << 16; 7335 } 7336 if (!cpu->enable_pmu) { 7337 *ecx &= ~CPUID_EXT_PDCM; 7338 } 7339 break; 7340 case 2: 7341 /* cache info: needed for Pentium Pro compatibility */ 7342 if (cpu->cache_info_passthrough) { 7343 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7344 break; 7345 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 7346 *eax = *ebx = *ecx = *edx = 0; 7347 break; 7348 } 7349 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 7350 *ebx = 0; 7351 if (!cpu->enable_l3_cache) { 7352 *ecx = 0; 7353 } else { 7354 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 7355 } 7356 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 7357 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 7358 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 7359 break; 7360 case 4: 7361 /* cache info: needed for Core compatibility */ 7362 if (cpu->cache_info_passthrough) { 7363 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7364 /* 7365 * QEMU has its own number of cores/logical cpus, 7366 * set 24..14, 31..26 bit to configured values 7367 */ 7368 if (*eax & 31) { 7369 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 7370 7371 *eax &= ~0xFC000000; 7372 *eax |= max_core_ids_in_package(topo_info) << 26; 7373 if (host_vcpus_per_cache > threads_per_pkg) { 7374 *eax &= ~0x3FFC000; 7375 7376 /* Share the cache at package level. */ 7377 *eax |= max_thread_ids_for_cache(topo_info, 7378 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 7379 } 7380 } 7381 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 7382 *eax = *ebx = *ecx = *edx = 0; 7383 } else { 7384 *eax = 0; 7385 7386 switch (count) { 7387 case 0: /* L1 dcache info */ 7388 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 7389 topo_info, 7390 eax, ebx, ecx, edx); 7391 if (!cpu->l1_cache_per_core) { 7392 *eax &= ~MAKE_64BIT_MASK(14, 12); 7393 } 7394 break; 7395 case 1: /* L1 icache info */ 7396 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 7397 topo_info, 7398 eax, ebx, ecx, edx); 7399 if (!cpu->l1_cache_per_core) { 7400 *eax &= ~MAKE_64BIT_MASK(14, 12); 7401 } 7402 break; 7403 case 2: /* L2 cache info */ 7404 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 7405 topo_info, 7406 eax, ebx, ecx, edx); 7407 break; 7408 case 3: /* L3 cache info */ 7409 if (cpu->enable_l3_cache) { 7410 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 7411 topo_info, 7412 eax, ebx, ecx, edx); 7413 break; 7414 } 7415 /* fall through */ 7416 default: /* end of info */ 7417 *eax = *ebx = *ecx = *edx = 0; 7418 break; 7419 } 7420 } 7421 break; 7422 case 5: 7423 /* MONITOR/MWAIT Leaf */ 7424 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 7425 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 7426 *ecx = cpu->mwait.ecx; /* flags */ 7427 *edx = cpu->mwait.edx; /* mwait substates */ 7428 break; 7429 case 6: 7430 /* Thermal and Power Leaf */ 7431 *eax = env->features[FEAT_6_EAX]; 7432 *ebx = 0; 7433 *ecx = 0; 7434 *edx = 0; 7435 break; 7436 case 7: 7437 /* Structured Extended Feature Flags Enumeration Leaf */ 7438 if (count == 0) { 7439 /* Maximum ECX value for sub-leaves */ 7440 *eax = env->cpuid_level_func7; 7441 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 7442 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 7443 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 7444 *ecx |= CPUID_7_0_ECX_OSPKE; 7445 } 7446 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 7447 } else if (count == 1) { 7448 *eax = env->features[FEAT_7_1_EAX]; 7449 *edx = env->features[FEAT_7_1_EDX]; 7450 *ebx = 0; 7451 *ecx = 0; 7452 } else if (count == 2) { 7453 *edx = env->features[FEAT_7_2_EDX]; 7454 *eax = 0; 7455 *ebx = 0; 7456 *ecx = 0; 7457 } else { 7458 *eax = 0; 7459 *ebx = 0; 7460 *ecx = 0; 7461 *edx = 0; 7462 } 7463 break; 7464 case 9: 7465 /* Direct Cache Access Information Leaf */ 7466 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 7467 *ebx = 0; 7468 *ecx = 0; 7469 *edx = 0; 7470 break; 7471 case 0xA: 7472 /* Architectural Performance Monitoring Leaf */ 7473 if (cpu->enable_pmu) { 7474 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 7475 } else { 7476 *eax = 0; 7477 *ebx = 0; 7478 *ecx = 0; 7479 *edx = 0; 7480 } 7481 break; 7482 case 0xB: 7483 /* Extended Topology Enumeration Leaf */ 7484 if (!cpu->enable_cpuid_0xb) { 7485 *eax = *ebx = *ecx = *edx = 0; 7486 break; 7487 } 7488 7489 *ecx = count & 0xff; 7490 *edx = cpu->apic_id; 7491 7492 switch (count) { 7493 case 0: 7494 *eax = apicid_core_offset(topo_info); 7495 *ebx = topo_info->threads_per_core; 7496 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 7497 break; 7498 case 1: 7499 *eax = apicid_pkg_offset(topo_info); 7500 *ebx = threads_per_pkg; 7501 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 7502 break; 7503 default: 7504 *eax = 0; 7505 *ebx = 0; 7506 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 7507 } 7508 7509 assert(!(*eax & ~0x1f)); 7510 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 7511 break; 7512 case 0x1C: 7513 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7514 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 7515 *edx = 0; 7516 } 7517 break; 7518 case 0x1F: 7519 /* V2 Extended Topology Enumeration Leaf */ 7520 if (!x86_has_cpuid_0x1f(cpu)) { 7521 *eax = *ebx = *ecx = *edx = 0; 7522 break; 7523 } 7524 7525 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 7526 break; 7527 case 0xD: { 7528 /* Processor Extended State */ 7529 *eax = 0; 7530 *ebx = 0; 7531 *ecx = 0; 7532 *edx = 0; 7533 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7534 break; 7535 } 7536 7537 if (count == 0) { 7538 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 7539 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 7540 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 7541 /* 7542 * The initial value of xcr0 and ebx == 0, On host without kvm 7543 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 7544 * even through guest update xcr0, this will crash some legacy guest 7545 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 7546 */ 7547 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 7548 } else if (count == 1) { 7549 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 7550 x86_cpu_xsave_xss_components(cpu); 7551 7552 *eax = env->features[FEAT_XSAVE]; 7553 *ebx = xsave_area_size(xstate, true); 7554 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 7555 *edx = env->features[FEAT_XSAVE_XSS_HI]; 7556 if (kvm_enabled() && cpu->enable_pmu && 7557 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 7558 (*eax & CPUID_XSAVE_XSAVES)) { 7559 *ecx |= XSTATE_ARCH_LBR_MASK; 7560 } else { 7561 *ecx &= ~XSTATE_ARCH_LBR_MASK; 7562 } 7563 } else if (count == 0xf && cpu->enable_pmu 7564 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7565 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 7566 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 7567 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 7568 7569 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 7570 *eax = esa->size; 7571 *ebx = esa->offset; 7572 *ecx = esa->ecx & 7573 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 7574 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 7575 *eax = esa->size; 7576 *ebx = 0; 7577 *ecx = 1; 7578 } 7579 } 7580 break; 7581 } 7582 case 0x12: 7583 #ifndef CONFIG_USER_ONLY 7584 if (!kvm_enabled() || 7585 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 7586 *eax = *ebx = *ecx = *edx = 0; 7587 break; 7588 } 7589 7590 /* 7591 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 7592 * the EPC properties, e.g. confidentiality and integrity, from the 7593 * host's first EPC section, i.e. assume there is one EPC section or 7594 * that all EPC sections have the same security properties. 7595 */ 7596 if (count > 1) { 7597 uint64_t epc_addr, epc_size; 7598 7599 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 7600 *eax = *ebx = *ecx = *edx = 0; 7601 break; 7602 } 7603 host_cpuid(index, 2, eax, ebx, ecx, edx); 7604 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 7605 *ebx = (uint32_t)(epc_addr >> 32); 7606 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 7607 *edx = (uint32_t)(epc_size >> 32); 7608 break; 7609 } 7610 7611 /* 7612 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 7613 * and KVM, i.e. QEMU cannot emulate features to override what KVM 7614 * supports. Features can be further restricted by userspace, but not 7615 * made more permissive. 7616 */ 7617 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 7618 7619 if (count == 0) { 7620 *eax &= env->features[FEAT_SGX_12_0_EAX]; 7621 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 7622 } else { 7623 *eax &= env->features[FEAT_SGX_12_1_EAX]; 7624 *ebx &= 0; /* ebx reserve */ 7625 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 7626 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 7627 7628 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 7629 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 7630 7631 /* Access to PROVISIONKEY requires additional credentials. */ 7632 if ((*eax & (1U << 4)) && 7633 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 7634 *eax &= ~(1U << 4); 7635 } 7636 } 7637 #endif 7638 break; 7639 case 0x14: { 7640 /* Intel Processor Trace Enumeration */ 7641 *eax = 0; 7642 *ebx = 0; 7643 *ecx = 0; 7644 *edx = 0; 7645 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 7646 !kvm_enabled()) { 7647 break; 7648 } 7649 7650 /* 7651 * If these are changed, they should stay in sync with 7652 * x86_cpu_filter_features(). 7653 */ 7654 if (count == 0) { 7655 *eax = INTEL_PT_MAX_SUBLEAF; 7656 *ebx = INTEL_PT_MINIMAL_EBX; 7657 *ecx = INTEL_PT_MINIMAL_ECX; 7658 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 7659 *ecx |= CPUID_14_0_ECX_LIP; 7660 } 7661 } else if (count == 1) { 7662 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 7663 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 7664 } 7665 break; 7666 } 7667 case 0x1D: { 7668 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 7669 *eax = 0; 7670 *ebx = 0; 7671 *ecx = 0; 7672 *edx = 0; 7673 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7674 break; 7675 } 7676 7677 if (count == 0) { 7678 /* Highest numbered palette subleaf */ 7679 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 7680 } else if (count == 1) { 7681 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 7682 (INTEL_AMX_BYTES_PER_TILE << 16); 7683 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 7684 *ecx = INTEL_AMX_TILE_MAX_ROWS; 7685 } 7686 break; 7687 } 7688 case 0x1E: { 7689 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 7690 *eax = 0; 7691 *ebx = 0; 7692 *ecx = 0; 7693 *edx = 0; 7694 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7695 break; 7696 } 7697 7698 if (count == 0) { 7699 /* Highest numbered palette subleaf */ 7700 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 7701 } 7702 break; 7703 } 7704 case 0x24: { 7705 *eax = 0; 7706 *ebx = 0; 7707 *ecx = 0; 7708 *edx = 0; 7709 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 7710 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 7711 } 7712 break; 7713 } 7714 case 0x40000000: 7715 /* 7716 * CPUID code in kvm_arch_init_vcpu() ignores stuff 7717 * set here, but we restrict to TCG none the less. 7718 */ 7719 if (tcg_enabled() && cpu->expose_tcg) { 7720 memcpy(signature, "TCGTCGTCGTCG", 12); 7721 *eax = 0x40000001; 7722 *ebx = signature[0]; 7723 *ecx = signature[1]; 7724 *edx = signature[2]; 7725 } else { 7726 *eax = 0; 7727 *ebx = 0; 7728 *ecx = 0; 7729 *edx = 0; 7730 } 7731 break; 7732 case 0x40000001: 7733 *eax = 0; 7734 *ebx = 0; 7735 *ecx = 0; 7736 *edx = 0; 7737 break; 7738 case 0x80000000: 7739 *eax = env->cpuid_xlevel; 7740 *ebx = env->cpuid_vendor1; 7741 *edx = env->cpuid_vendor2; 7742 *ecx = env->cpuid_vendor3; 7743 break; 7744 case 0x80000001: 7745 *eax = env->cpuid_version; 7746 *ebx = 0; 7747 *ecx = env->features[FEAT_8000_0001_ECX]; 7748 *edx = env->features[FEAT_8000_0001_EDX]; 7749 7750 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 7751 !(env->hflags & HF_LMA_MASK)) { 7752 *edx &= ~CPUID_EXT2_SYSCALL; 7753 } 7754 break; 7755 case 0x80000002: 7756 case 0x80000003: 7757 case 0x80000004: 7758 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 7759 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 7760 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 7761 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 7762 break; 7763 case 0x80000005: 7764 /* cache info (L1 cache) */ 7765 if (cpu->cache_info_passthrough) { 7766 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7767 break; 7768 } 7769 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 7770 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 7771 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 7772 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7773 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7774 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7775 break; 7776 case 0x80000006: 7777 /* cache info (L2 cache) */ 7778 if (cpu->cache_info_passthrough) { 7779 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7780 break; 7781 } 7782 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7783 (L2_DTLB_2M_ENTRIES << 16) | 7784 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7785 (L2_ITLB_2M_ENTRIES); 7786 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7787 (L2_DTLB_4K_ENTRIES << 16) | 7788 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7789 (L2_ITLB_4K_ENTRIES); 7790 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7791 cpu->enable_l3_cache ? 7792 env->cache_info_amd.l3_cache : NULL, 7793 ecx, edx); 7794 break; 7795 case 0x80000007: 7796 *eax = 0; 7797 *ebx = env->features[FEAT_8000_0007_EBX]; 7798 *ecx = 0; 7799 *edx = env->features[FEAT_8000_0007_EDX]; 7800 break; 7801 case 0x80000008: 7802 /* virtual & phys address size in low 2 bytes. */ 7803 *eax = cpu->phys_bits; 7804 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7805 /* 64 bit processor */ 7806 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7807 *eax |= (cpu->guest_phys_bits << 16); 7808 } 7809 *ebx = env->features[FEAT_8000_0008_EBX]; 7810 if (threads_per_pkg > 1) { 7811 /* 7812 * Bits 15:12 is "The number of bits in the initial 7813 * Core::X86::Apic::ApicId[ApicId] value that indicate 7814 * thread ID within a package". 7815 * Bits 7:0 is "The number of threads in the package is NC+1" 7816 */ 7817 *ecx = (apicid_pkg_offset(topo_info) << 12) | 7818 (threads_per_pkg - 1); 7819 } else { 7820 *ecx = 0; 7821 } 7822 *edx = 0; 7823 break; 7824 case 0x8000000A: 7825 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7826 *eax = 0x00000001; /* SVM Revision */ 7827 *ebx = 0x00000010; /* nr of ASIDs */ 7828 *ecx = 0; 7829 *edx = env->features[FEAT_SVM]; /* optional features */ 7830 } else { 7831 *eax = 0; 7832 *ebx = 0; 7833 *ecx = 0; 7834 *edx = 0; 7835 } 7836 break; 7837 case 0x8000001D: 7838 *eax = 0; 7839 if (cpu->cache_info_passthrough) { 7840 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7841 break; 7842 } 7843 switch (count) { 7844 case 0: /* L1 dcache info */ 7845 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7846 topo_info, eax, ebx, ecx, edx); 7847 break; 7848 case 1: /* L1 icache info */ 7849 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7850 topo_info, eax, ebx, ecx, edx); 7851 break; 7852 case 2: /* L2 cache info */ 7853 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7854 topo_info, eax, ebx, ecx, edx); 7855 break; 7856 case 3: /* L3 cache info */ 7857 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7858 topo_info, eax, ebx, ecx, edx); 7859 break; 7860 default: /* end of info */ 7861 *eax = *ebx = *ecx = *edx = 0; 7862 break; 7863 } 7864 if (cpu->amd_topoext_features_only) { 7865 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7866 } 7867 break; 7868 case 0x8000001E: 7869 if (cpu->core_id <= 255) { 7870 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 7871 } else { 7872 *eax = 0; 7873 *ebx = 0; 7874 *ecx = 0; 7875 *edx = 0; 7876 } 7877 break; 7878 case 0x80000022: 7879 *eax = *ebx = *ecx = *edx = 0; 7880 /* AMD Extended Performance Monitoring and Debug */ 7881 if (kvm_enabled() && cpu->enable_pmu && 7882 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7883 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7884 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7885 R_EBX) & 0xf; 7886 } 7887 break; 7888 case 0xC0000000: 7889 *eax = env->cpuid_xlevel2; 7890 *ebx = 0; 7891 *ecx = 0; 7892 *edx = 0; 7893 break; 7894 case 0xC0000001: 7895 /* Support for VIA CPU's CPUID instruction */ 7896 *eax = env->cpuid_version; 7897 *ebx = 0; 7898 *ecx = 0; 7899 *edx = env->features[FEAT_C000_0001_EDX]; 7900 break; 7901 case 0xC0000002: 7902 case 0xC0000003: 7903 case 0xC0000004: 7904 /* Reserved for the future, and now filled with zero */ 7905 *eax = 0; 7906 *ebx = 0; 7907 *ecx = 0; 7908 *edx = 0; 7909 break; 7910 case 0x8000001F: 7911 *eax = *ebx = *ecx = *edx = 0; 7912 if (sev_enabled()) { 7913 *eax = 0x2; 7914 *eax |= sev_es_enabled() ? 0x8 : 0; 7915 *eax |= sev_snp_enabled() ? 0x10 : 0; 7916 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7917 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7918 } 7919 break; 7920 case 0x80000021: 7921 *eax = *ebx = *ecx = *edx = 0; 7922 *eax = env->features[FEAT_8000_0021_EAX]; 7923 *ebx = env->features[FEAT_8000_0021_EBX]; 7924 break; 7925 default: 7926 /* reserved values: zero */ 7927 *eax = 0; 7928 *ebx = 0; 7929 *ecx = 0; 7930 *edx = 0; 7931 break; 7932 } 7933 } 7934 7935 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7936 { 7937 #ifndef CONFIG_USER_ONLY 7938 /* Those default values are defined in Skylake HW */ 7939 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7940 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7941 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7942 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7943 #endif 7944 } 7945 7946 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7947 { 7948 if (!esa->size) { 7949 return false; 7950 } 7951 7952 if (env->features[esa->feature] & esa->bits) { 7953 return true; 7954 } 7955 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7956 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7957 return true; 7958 } 7959 7960 return false; 7961 } 7962 7963 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7964 { 7965 CPUState *cs = CPU(obj); 7966 X86CPU *cpu = X86_CPU(cs); 7967 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7968 CPUX86State *env = &cpu->env; 7969 target_ulong cr4; 7970 uint64_t xcr0; 7971 int i; 7972 7973 if (xcc->parent_phases.hold) { 7974 xcc->parent_phases.hold(obj, type); 7975 } 7976 7977 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7978 7979 if (tcg_enabled()) { 7980 cpu_init_fp_statuses(env); 7981 } 7982 7983 env->old_exception = -1; 7984 7985 /* init to reset state */ 7986 env->int_ctl = 0; 7987 env->hflags2 |= HF2_GIF_MASK; 7988 env->hflags2 |= HF2_VGIF_MASK; 7989 env->hflags &= ~HF_GUEST_MASK; 7990 7991 cpu_x86_update_cr0(env, 0x60000010); 7992 env->a20_mask = ~0x0; 7993 env->smbase = 0x30000; 7994 env->msr_smi_count = 0; 7995 7996 env->idt.limit = 0xffff; 7997 env->gdt.limit = 0xffff; 7998 env->ldt.limit = 0xffff; 7999 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 8000 env->tr.limit = 0xffff; 8001 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 8002 8003 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 8004 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 8005 DESC_R_MASK | DESC_A_MASK); 8006 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 8007 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8008 DESC_A_MASK); 8009 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 8010 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8011 DESC_A_MASK); 8012 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 8013 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8014 DESC_A_MASK); 8015 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 8016 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8017 DESC_A_MASK); 8018 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 8019 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8020 DESC_A_MASK); 8021 8022 env->eip = 0xfff0; 8023 env->regs[R_EDX] = env->cpuid_version; 8024 8025 env->eflags = 0x2; 8026 8027 /* FPU init */ 8028 for (i = 0; i < 8; i++) { 8029 env->fptags[i] = 1; 8030 } 8031 cpu_set_fpuc(env, 0x37f); 8032 8033 env->mxcsr = 0x1f80; 8034 /* All units are in INIT state. */ 8035 env->xstate_bv = 0; 8036 8037 env->pat = 0x0007040600070406ULL; 8038 8039 if (kvm_enabled()) { 8040 /* 8041 * KVM handles TSC = 0 specially and thinks we are hot-plugging 8042 * a new CPU, use 1 instead to force a reset. 8043 */ 8044 if (env->tsc != 0) { 8045 env->tsc = 1; 8046 } 8047 } else { 8048 env->tsc = 0; 8049 } 8050 8051 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 8052 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 8053 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 8054 } 8055 8056 memset(env->dr, 0, sizeof(env->dr)); 8057 env->dr[6] = DR6_FIXED_1; 8058 env->dr[7] = DR7_FIXED_1; 8059 cpu_breakpoint_remove_all(cs, BP_CPU); 8060 cpu_watchpoint_remove_all(cs, BP_CPU); 8061 8062 cr4 = 0; 8063 xcr0 = XSTATE_FP_MASK; 8064 8065 #ifdef CONFIG_USER_ONLY 8066 /* Enable all the features for user-mode. */ 8067 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 8068 xcr0 |= XSTATE_SSE_MASK; 8069 } 8070 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 8071 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 8072 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 8073 continue; 8074 } 8075 if (cpuid_has_xsave_feature(env, esa)) { 8076 xcr0 |= 1ull << i; 8077 } 8078 } 8079 8080 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 8081 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 8082 } 8083 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 8084 cr4 |= CR4_FSGSBASE_MASK; 8085 } 8086 #endif 8087 8088 env->xcr0 = xcr0; 8089 cpu_x86_update_cr4(env, cr4); 8090 8091 /* 8092 * SDM 11.11.5 requires: 8093 * - IA32_MTRR_DEF_TYPE MSR.E = 0 8094 * - IA32_MTRR_PHYSMASKn.V = 0 8095 * All other bits are undefined. For simplification, zero it all. 8096 */ 8097 env->mtrr_deftype = 0; 8098 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 8099 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 8100 8101 env->interrupt_injected = -1; 8102 env->exception_nr = -1; 8103 env->exception_pending = 0; 8104 env->exception_injected = 0; 8105 env->exception_has_payload = false; 8106 env->exception_payload = 0; 8107 env->nmi_injected = false; 8108 env->triple_fault_pending = false; 8109 #if !defined(CONFIG_USER_ONLY) 8110 /* We hard-wire the BSP to the first CPU. */ 8111 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 8112 8113 cs->halted = !cpu_is_bsp(cpu); 8114 8115 if (kvm_enabled()) { 8116 kvm_arch_reset_vcpu(cpu); 8117 } 8118 8119 x86_cpu_set_sgxlepubkeyhash(env); 8120 8121 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 8122 8123 #endif 8124 } 8125 8126 void x86_cpu_after_reset(X86CPU *cpu) 8127 { 8128 #ifndef CONFIG_USER_ONLY 8129 if (kvm_enabled()) { 8130 kvm_arch_after_reset_vcpu(cpu); 8131 } 8132 8133 if (cpu->apic_state) { 8134 device_cold_reset(cpu->apic_state); 8135 } 8136 #endif 8137 } 8138 8139 static void mce_init(X86CPU *cpu) 8140 { 8141 CPUX86State *cenv = &cpu->env; 8142 unsigned int bank; 8143 8144 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 8145 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 8146 (CPUID_MCE | CPUID_MCA)) { 8147 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 8148 (cpu->enable_lmce ? MCG_LMCE_P : 0); 8149 cenv->mcg_ctl = ~(uint64_t)0; 8150 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 8151 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 8152 } 8153 } 8154 } 8155 8156 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 8157 { 8158 if (*min < value) { 8159 *min = value; 8160 } 8161 } 8162 8163 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 8164 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 8165 { 8166 CPUX86State *env = &cpu->env; 8167 FeatureWordInfo *fi = &feature_word_info[w]; 8168 uint32_t eax = fi->cpuid.eax; 8169 uint32_t region = eax & 0xF0000000; 8170 8171 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 8172 if (!env->features[w]) { 8173 return; 8174 } 8175 8176 switch (region) { 8177 case 0x00000000: 8178 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 8179 break; 8180 case 0x80000000: 8181 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 8182 break; 8183 case 0xC0000000: 8184 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 8185 break; 8186 } 8187 8188 if (eax == 7) { 8189 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 8190 fi->cpuid.ecx); 8191 } 8192 } 8193 8194 /* Calculate XSAVE components based on the configured CPU feature flags */ 8195 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 8196 { 8197 CPUX86State *env = &cpu->env; 8198 int i; 8199 uint64_t mask; 8200 static bool request_perm; 8201 8202 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 8203 env->features[FEAT_XSAVE_XCR0_LO] = 0; 8204 env->features[FEAT_XSAVE_XCR0_HI] = 0; 8205 env->features[FEAT_XSAVE_XSS_LO] = 0; 8206 env->features[FEAT_XSAVE_XSS_HI] = 0; 8207 return; 8208 } 8209 8210 mask = 0; 8211 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 8212 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 8213 if (cpuid_has_xsave_feature(env, esa)) { 8214 mask |= (1ULL << i); 8215 } 8216 } 8217 8218 /* Only request permission for first vcpu */ 8219 if (kvm_enabled() && !request_perm) { 8220 kvm_request_xsave_components(cpu, mask); 8221 request_perm = true; 8222 } 8223 8224 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 8225 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 8226 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 8227 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 8228 } 8229 8230 /***** Steps involved on loading and filtering CPUID data 8231 * 8232 * When initializing and realizing a CPU object, the steps 8233 * involved in setting up CPUID data are: 8234 * 8235 * 1) Loading CPU model definition (X86CPUDefinition). This is 8236 * implemented by x86_cpu_load_model() and should be completely 8237 * transparent, as it is done automatically by instance_init. 8238 * No code should need to look at X86CPUDefinition structs 8239 * outside instance_init. 8240 * 8241 * 2) CPU expansion. This is done by realize before CPUID 8242 * filtering, and will make sure host/accelerator data is 8243 * loaded for CPU models that depend on host capabilities 8244 * (e.g. "host"). Done by x86_cpu_expand_features(). 8245 * 8246 * 3) CPUID filtering. This initializes extra data related to 8247 * CPUID, and checks if the host supports all capabilities 8248 * required by the CPU. Runnability of a CPU model is 8249 * determined at this step. Done by x86_cpu_filter_features(). 8250 * 8251 * Some operations don't require all steps to be performed. 8252 * More precisely: 8253 * 8254 * - CPU instance creation (instance_init) will run only CPU 8255 * model loading. CPU expansion can't run at instance_init-time 8256 * because host/accelerator data may be not available yet. 8257 * - CPU realization will perform both CPU model expansion and CPUID 8258 * filtering, and return an error in case one of them fails. 8259 * - query-cpu-definitions needs to run all 3 steps. It needs 8260 * to run CPUID filtering, as the 'unavailable-features' 8261 * field is set based on the filtering results. 8262 * - The query-cpu-model-expansion QMP command only needs to run 8263 * CPU model loading and CPU expansion. It should not filter 8264 * any CPUID data based on host capabilities. 8265 */ 8266 8267 /* Expand CPU configuration data, based on configured features 8268 * and host/accelerator capabilities when appropriate. 8269 */ 8270 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 8271 { 8272 CPUX86State *env = &cpu->env; 8273 FeatureWord w; 8274 int i; 8275 GList *l; 8276 8277 for (l = plus_features; l; l = l->next) { 8278 const char *prop = l->data; 8279 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 8280 return; 8281 } 8282 } 8283 8284 for (l = minus_features; l; l = l->next) { 8285 const char *prop = l->data; 8286 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 8287 return; 8288 } 8289 } 8290 8291 /*TODO: Now cpu->max_features doesn't overwrite features 8292 * set using QOM properties, and we can convert 8293 * plus_features & minus_features to global properties 8294 * inside x86_cpu_parse_featurestr() too. 8295 */ 8296 if (cpu->max_features) { 8297 for (w = 0; w < FEATURE_WORDS; w++) { 8298 /* Override only features that weren't set explicitly 8299 * by the user. 8300 */ 8301 env->features[w] |= 8302 x86_cpu_get_supported_feature_word(cpu, w) & 8303 ~env->user_features[w] & 8304 ~feature_word_info[w].no_autoenable_flags; 8305 } 8306 8307 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 8308 uint32_t eax, ebx, ecx, edx; 8309 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 8310 env->avx10_version = ebx & 0xff; 8311 } 8312 } 8313 8314 if (x86_threads_per_pkg(&env->topo_info) > 1) { 8315 env->features[FEAT_1_EDX] |= CPUID_HT; 8316 8317 /* 8318 * The Linux kernel checks for the CMPLegacy bit and 8319 * discards multiple thread information if it is set. 8320 * So don't set it here for Intel (and other processors 8321 * following Intel's behavior) to make Linux guests happy. 8322 */ 8323 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 8324 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 8325 } 8326 } 8327 8328 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 8329 FeatureDep *d = &feature_dependencies[i]; 8330 if (!(env->features[d->from.index] & d->from.mask)) { 8331 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 8332 8333 /* Not an error unless the dependent feature was added explicitly. */ 8334 mark_unavailable_features(cpu, d->to.index, 8335 unavailable_features & env->user_features[d->to.index], 8336 "This feature depends on other features that were not requested"); 8337 8338 env->features[d->to.index] &= ~unavailable_features; 8339 } 8340 } 8341 8342 if (!kvm_enabled() || !cpu->expose_kvm) { 8343 env->features[FEAT_KVM] = 0; 8344 } 8345 8346 x86_cpu_enable_xsave_components(cpu); 8347 8348 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 8349 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 8350 if (cpu->full_cpuid_auto_level) { 8351 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 8352 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 8353 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 8354 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 8355 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 8356 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 8357 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 8358 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 8359 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 8360 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 8361 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 8362 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 8363 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 8364 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 8365 8366 /* Intel Processor Trace requires CPUID[0x14] */ 8367 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 8368 if (cpu->intel_pt_auto_level) { 8369 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 8370 } else if (cpu->env.cpuid_min_level < 0x14) { 8371 mark_unavailable_features(cpu, FEAT_7_0_EBX, 8372 CPUID_7_0_EBX_INTEL_PT, 8373 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 8374 } 8375 } 8376 8377 /* 8378 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 8379 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 8380 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 8381 * cpu->vendor_cpuid_only has been unset for compatibility with older 8382 * machine types. 8383 */ 8384 if (x86_has_cpuid_0x1f(cpu) && 8385 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 8386 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 8387 } 8388 8389 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 8390 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 8391 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 8392 } 8393 8394 /* SVM requires CPUID[0x8000000A] */ 8395 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 8396 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 8397 } 8398 8399 /* SEV requires CPUID[0x8000001F] */ 8400 if (sev_enabled()) { 8401 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 8402 } 8403 8404 if (env->features[FEAT_8000_0021_EAX]) { 8405 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 8406 } 8407 8408 /* SGX requires CPUID[0x12] for EPC enumeration */ 8409 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 8410 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 8411 } 8412 } 8413 8414 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 8415 if (env->cpuid_level_func7 == UINT32_MAX) { 8416 env->cpuid_level_func7 = env->cpuid_min_level_func7; 8417 } 8418 if (env->cpuid_level == UINT32_MAX) { 8419 env->cpuid_level = env->cpuid_min_level; 8420 } 8421 if (env->cpuid_xlevel == UINT32_MAX) { 8422 env->cpuid_xlevel = env->cpuid_min_xlevel; 8423 } 8424 if (env->cpuid_xlevel2 == UINT32_MAX) { 8425 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 8426 } 8427 8428 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 8429 return; 8430 } 8431 } 8432 8433 /* 8434 * Finishes initialization of CPUID data, filters CPU feature 8435 * words based on host availability of each feature. 8436 * 8437 * Returns: true if any flag is not supported by the host, false otherwise. 8438 */ 8439 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 8440 { 8441 CPUX86State *env = &cpu->env; 8442 FeatureWord w; 8443 const char *prefix = NULL; 8444 bool have_filtered_features; 8445 8446 uint32_t eax_0, ebx_0, ecx_0, edx_0; 8447 uint32_t eax_1, ebx_1, ecx_1, edx_1; 8448 8449 if (verbose) { 8450 prefix = accel_uses_host_cpuid() 8451 ? "host doesn't support requested feature" 8452 : "TCG doesn't support requested feature"; 8453 } 8454 8455 for (w = 0; w < FEATURE_WORDS; w++) { 8456 uint64_t host_feat = 8457 x86_cpu_get_supported_feature_word(NULL, w); 8458 uint64_t requested_features = env->features[w]; 8459 uint64_t unavailable_features = requested_features & ~host_feat; 8460 mark_unavailable_features(cpu, w, unavailable_features, prefix); 8461 } 8462 8463 /* 8464 * Check that KVM actually allows the processor tracing features that 8465 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 8466 */ 8467 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 8468 kvm_enabled()) { 8469 x86_cpu_get_supported_cpuid(0x14, 0, 8470 &eax_0, &ebx_0, &ecx_0, &edx_0); 8471 x86_cpu_get_supported_cpuid(0x14, 1, 8472 &eax_1, &ebx_1, &ecx_1, &edx_1); 8473 8474 if (!eax_0 || 8475 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 8476 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 8477 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 8478 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 8479 INTEL_PT_ADDR_RANGES_NUM) || 8480 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 8481 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 8482 ((ecx_0 & CPUID_14_0_ECX_LIP) != 8483 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 8484 /* 8485 * Processor Trace capabilities aren't configurable, so if the 8486 * host can't emulate the capabilities we report on 8487 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 8488 */ 8489 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 8490 } 8491 } 8492 8493 have_filtered_features = x86_cpu_have_filtered_features(cpu); 8494 8495 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 8496 x86_cpu_get_supported_cpuid(0x24, 0, 8497 &eax_0, &ebx_0, &ecx_0, &edx_0); 8498 uint8_t version = ebx_0 & 0xff; 8499 8500 if (version < env->avx10_version) { 8501 if (prefix) { 8502 warn_report("%s: avx10.%d. Adjust to avx10.%d", 8503 prefix, env->avx10_version, version); 8504 } 8505 env->avx10_version = version; 8506 have_filtered_features = true; 8507 } 8508 } else if (env->avx10_version) { 8509 if (prefix) { 8510 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 8511 } 8512 have_filtered_features = true; 8513 } 8514 8515 return have_filtered_features; 8516 } 8517 8518 static void x86_cpu_hyperv_realize(X86CPU *cpu) 8519 { 8520 size_t len; 8521 8522 /* Hyper-V vendor id */ 8523 if (!cpu->hyperv_vendor) { 8524 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 8525 &error_abort); 8526 } 8527 len = strlen(cpu->hyperv_vendor); 8528 if (len > 12) { 8529 warn_report("hv-vendor-id truncated to 12 characters"); 8530 len = 12; 8531 } 8532 memset(cpu->hyperv_vendor_id, 0, 12); 8533 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 8534 8535 /* 'Hv#1' interface identification*/ 8536 cpu->hyperv_interface_id[0] = 0x31237648; 8537 cpu->hyperv_interface_id[1] = 0; 8538 cpu->hyperv_interface_id[2] = 0; 8539 cpu->hyperv_interface_id[3] = 0; 8540 8541 /* Hypervisor implementation limits */ 8542 cpu->hyperv_limits[0] = 64; 8543 cpu->hyperv_limits[1] = 0; 8544 cpu->hyperv_limits[2] = 0; 8545 } 8546 8547 #ifndef CONFIG_USER_ONLY 8548 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 8549 Error **errp) 8550 { 8551 CPUX86State *env = &cpu->env; 8552 CpuTopologyLevel level; 8553 8554 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 8555 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8556 env->cache_info_cpuid4.l1d_cache->share_level = level; 8557 env->cache_info_amd.l1d_cache->share_level = level; 8558 } else { 8559 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8560 env->cache_info_cpuid4.l1d_cache->share_level); 8561 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8562 env->cache_info_amd.l1d_cache->share_level); 8563 } 8564 8565 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 8566 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8567 env->cache_info_cpuid4.l1i_cache->share_level = level; 8568 env->cache_info_amd.l1i_cache->share_level = level; 8569 } else { 8570 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8571 env->cache_info_cpuid4.l1i_cache->share_level); 8572 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8573 env->cache_info_amd.l1i_cache->share_level); 8574 } 8575 8576 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 8577 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8578 env->cache_info_cpuid4.l2_cache->share_level = level; 8579 env->cache_info_amd.l2_cache->share_level = level; 8580 } else { 8581 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8582 env->cache_info_cpuid4.l2_cache->share_level); 8583 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8584 env->cache_info_amd.l2_cache->share_level); 8585 } 8586 8587 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 8588 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8589 env->cache_info_cpuid4.l3_cache->share_level = level; 8590 env->cache_info_amd.l3_cache->share_level = level; 8591 } else { 8592 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8593 env->cache_info_cpuid4.l3_cache->share_level); 8594 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8595 env->cache_info_amd.l3_cache->share_level); 8596 } 8597 8598 if (!machine_check_smp_cache(ms, errp)) { 8599 return false; 8600 } 8601 return true; 8602 } 8603 #endif 8604 8605 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 8606 { 8607 CPUState *cs = CPU(dev); 8608 X86CPU *cpu = X86_CPU(dev); 8609 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8610 CPUX86State *env = &cpu->env; 8611 Error *local_err = NULL; 8612 unsigned requested_lbr_fmt; 8613 8614 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 8615 /* Use pc-relative instructions in system-mode */ 8616 tcg_cflags_set(cs, CF_PCREL); 8617 #endif 8618 8619 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 8620 error_setg(errp, "apic-id property was not initialized properly"); 8621 return; 8622 } 8623 8624 /* 8625 * Process Hyper-V enlightenments. 8626 * Note: this currently has to happen before the expansion of CPU features. 8627 */ 8628 x86_cpu_hyperv_realize(cpu); 8629 8630 x86_cpu_expand_features(cpu, &local_err); 8631 if (local_err) { 8632 goto out; 8633 } 8634 8635 /* 8636 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 8637 * with user-provided setting. 8638 */ 8639 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 8640 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 8641 error_setg(errp, "invalid lbr-fmt"); 8642 return; 8643 } 8644 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 8645 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 8646 } 8647 8648 /* 8649 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 8650 * 3)vPMU LBR format matches that of host setting. 8651 */ 8652 requested_lbr_fmt = 8653 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 8654 if (requested_lbr_fmt && kvm_enabled()) { 8655 uint64_t host_perf_cap = 8656 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 8657 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 8658 8659 if (!cpu->enable_pmu) { 8660 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 8661 return; 8662 } 8663 if (requested_lbr_fmt != host_lbr_fmt) { 8664 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 8665 "the host value (0x%x).", 8666 requested_lbr_fmt, host_lbr_fmt); 8667 return; 8668 } 8669 } 8670 8671 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 8672 if (cpu->enforce_cpuid) { 8673 error_setg(&local_err, 8674 accel_uses_host_cpuid() ? 8675 "Host doesn't support requested features" : 8676 "TCG doesn't support requested features"); 8677 goto out; 8678 } 8679 } 8680 8681 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 8682 * CPUID[1].EDX. 8683 */ 8684 if (IS_AMD_CPU(env)) { 8685 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 8686 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 8687 & CPUID_EXT2_AMD_ALIASES); 8688 } 8689 8690 x86_cpu_set_sgxlepubkeyhash(env); 8691 8692 /* 8693 * note: the call to the framework needs to happen after feature expansion, 8694 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 8695 * These may be set by the accel-specific code, 8696 * and the results are subsequently checked / assumed in this function. 8697 */ 8698 cpu_exec_realizefn(cs, &local_err); 8699 if (local_err != NULL) { 8700 error_propagate(errp, local_err); 8701 return; 8702 } 8703 8704 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 8705 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8706 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 8707 goto out; 8708 } 8709 8710 if (cpu->guest_phys_bits == -1) { 8711 /* 8712 * If it was not set by the user, or by the accelerator via 8713 * cpu_exec_realizefn, clear. 8714 */ 8715 cpu->guest_phys_bits = 0; 8716 } 8717 8718 if (cpu->ucode_rev == 0) { 8719 /* 8720 * The default is the same as KVM's. Note that this check 8721 * needs to happen after the evenual setting of ucode_rev in 8722 * accel-specific code in cpu_exec_realizefn. 8723 */ 8724 if (IS_AMD_CPU(env)) { 8725 cpu->ucode_rev = 0x01000065; 8726 } else { 8727 cpu->ucode_rev = 0x100000000ULL; 8728 } 8729 } 8730 8731 /* 8732 * mwait extended info: needed for Core compatibility 8733 * We always wake on interrupt even if host does not have the capability. 8734 * 8735 * requires the accel-specific code in cpu_exec_realizefn to 8736 * have already acquired the CPUID data into cpu->mwait. 8737 */ 8738 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 8739 8740 /* 8741 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 8742 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8743 * based on inputs (sockets,cores,threads), it is still better to give 8744 * users a warning. 8745 */ 8746 if (IS_AMD_CPU(env) && 8747 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8748 env->topo_info.threads_per_core > 1) { 8749 warn_report_once("This family of AMD CPU doesn't support " 8750 "hyperthreading(%d). Please configure -smp " 8751 "options properly or try enabling topoext " 8752 "feature.", env->topo_info.threads_per_core); 8753 } 8754 8755 /* For 64bit systems think about the number of physical bits to present. 8756 * ideally this should be the same as the host; anything other than matching 8757 * the host can cause incorrect guest behaviour. 8758 * QEMU used to pick the magic value of 40 bits that corresponds to 8759 * consumer AMD devices but nothing else. 8760 * 8761 * Note that this code assumes features expansion has already been done 8762 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 8763 * phys_bits adjustments to match the host have been already done in 8764 * accel-specific code in cpu_exec_realizefn. 8765 */ 8766 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8767 if (cpu->phys_bits && 8768 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 8769 cpu->phys_bits < 32)) { 8770 error_setg(errp, "phys-bits should be between 32 and %u " 8771 " (but is %u)", 8772 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 8773 return; 8774 } 8775 /* 8776 * 0 means it was not explicitly set by the user (or by machine 8777 * compat_props or by the host code in host-cpu.c). 8778 * In this case, the default is the value used by TCG (40). 8779 */ 8780 if (cpu->phys_bits == 0) { 8781 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 8782 } 8783 if (cpu->guest_phys_bits && 8784 (cpu->guest_phys_bits > cpu->phys_bits || 8785 cpu->guest_phys_bits < 32)) { 8786 error_setg(errp, "guest-phys-bits should be between 32 and %u " 8787 " (but is %u)", 8788 cpu->phys_bits, cpu->guest_phys_bits); 8789 return; 8790 } 8791 } else { 8792 /* For 32 bit systems don't use the user set value, but keep 8793 * phys_bits consistent with what we tell the guest. 8794 */ 8795 if (cpu->phys_bits != 0) { 8796 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 8797 return; 8798 } 8799 if (cpu->guest_phys_bits != 0) { 8800 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 8801 return; 8802 } 8803 8804 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 8805 cpu->phys_bits = 36; 8806 } else { 8807 cpu->phys_bits = 32; 8808 } 8809 } 8810 8811 /* Cache information initialization */ 8812 if (!cpu->legacy_cache) { 8813 const CPUCaches *cache_info = 8814 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 8815 8816 if (!xcc->model || !cache_info) { 8817 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8818 error_setg(errp, 8819 "CPU model '%s' doesn't support legacy-cache=off", name); 8820 return; 8821 } 8822 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 8823 *cache_info; 8824 } else { 8825 /* Build legacy cache information */ 8826 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 8827 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 8828 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 8829 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 8830 8831 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 8832 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 8833 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 8834 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 8835 8836 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 8837 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 8838 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 8839 env->cache_info_amd.l3_cache = &legacy_l3_cache; 8840 } 8841 8842 #ifndef CONFIG_USER_ONLY 8843 MachineState *ms = MACHINE(qdev_get_machine()); 8844 MachineClass *mc = MACHINE_GET_CLASS(ms); 8845 8846 if (mc->smp_props.has_caches) { 8847 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 8848 return; 8849 } 8850 } 8851 8852 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 8853 8854 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 8855 x86_cpu_apic_create(cpu, &local_err); 8856 if (local_err != NULL) { 8857 goto out; 8858 } 8859 } 8860 #endif 8861 8862 mce_init(cpu); 8863 8864 x86_cpu_gdb_init(cs); 8865 qemu_init_vcpu(cs); 8866 8867 #ifndef CONFIG_USER_ONLY 8868 x86_cpu_apic_realize(cpu, &local_err); 8869 if (local_err != NULL) { 8870 goto out; 8871 } 8872 #endif /* !CONFIG_USER_ONLY */ 8873 cpu_reset(cs); 8874 8875 xcc->parent_realize(dev, &local_err); 8876 8877 out: 8878 if (local_err != NULL) { 8879 error_propagate(errp, local_err); 8880 return; 8881 } 8882 } 8883 8884 static void x86_cpu_unrealizefn(DeviceState *dev) 8885 { 8886 X86CPU *cpu = X86_CPU(dev); 8887 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8888 8889 #ifndef CONFIG_USER_ONLY 8890 cpu_remove_sync(CPU(dev)); 8891 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8892 #endif 8893 8894 if (cpu->apic_state) { 8895 object_unparent(OBJECT(cpu->apic_state)); 8896 cpu->apic_state = NULL; 8897 } 8898 8899 xcc->parent_unrealize(dev); 8900 } 8901 8902 typedef struct BitProperty { 8903 FeatureWord w; 8904 uint64_t mask; 8905 } BitProperty; 8906 8907 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8908 void *opaque, Error **errp) 8909 { 8910 X86CPU *cpu = X86_CPU(obj); 8911 BitProperty *fp = opaque; 8912 uint64_t f = cpu->env.features[fp->w]; 8913 bool value = (f & fp->mask) == fp->mask; 8914 visit_type_bool(v, name, &value, errp); 8915 } 8916 8917 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8918 void *opaque, Error **errp) 8919 { 8920 DeviceState *dev = DEVICE(obj); 8921 X86CPU *cpu = X86_CPU(obj); 8922 BitProperty *fp = opaque; 8923 bool value; 8924 8925 if (dev->realized) { 8926 qdev_prop_set_after_realize(dev, name, errp); 8927 return; 8928 } 8929 8930 if (!visit_type_bool(v, name, &value, errp)) { 8931 return; 8932 } 8933 8934 if (value) { 8935 cpu->env.features[fp->w] |= fp->mask; 8936 } else { 8937 cpu->env.features[fp->w] &= ~fp->mask; 8938 } 8939 cpu->env.user_features[fp->w] |= fp->mask; 8940 } 8941 8942 /* Register a boolean property to get/set a single bit in a uint32_t field. 8943 * 8944 * The same property name can be registered multiple times to make it affect 8945 * multiple bits in the same FeatureWord. In that case, the getter will return 8946 * true only if all bits are set. 8947 */ 8948 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8949 const char *prop_name, 8950 FeatureWord w, 8951 int bitnr) 8952 { 8953 ObjectClass *oc = OBJECT_CLASS(xcc); 8954 BitProperty *fp; 8955 ObjectProperty *op; 8956 uint64_t mask = (1ULL << bitnr); 8957 8958 op = object_class_property_find(oc, prop_name); 8959 if (op) { 8960 fp = op->opaque; 8961 assert(fp->w == w); 8962 fp->mask |= mask; 8963 } else { 8964 fp = g_new0(BitProperty, 1); 8965 fp->w = w; 8966 fp->mask = mask; 8967 object_class_property_add(oc, prop_name, "bool", 8968 x86_cpu_get_bit_prop, 8969 x86_cpu_set_bit_prop, 8970 NULL, fp); 8971 } 8972 } 8973 8974 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8975 FeatureWord w, 8976 int bitnr) 8977 { 8978 FeatureWordInfo *fi = &feature_word_info[w]; 8979 const char *name = fi->feat_names[bitnr]; 8980 8981 if (!name) { 8982 return; 8983 } 8984 8985 /* Property names should use "-" instead of "_". 8986 * Old names containing underscores are registered as aliases 8987 * using object_property_add_alias() 8988 */ 8989 assert(!strchr(name, '_')); 8990 /* aliases don't use "|" delimiters anymore, they are registered 8991 * manually using object_property_add_alias() */ 8992 assert(!strchr(name, '|')); 8993 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8994 } 8995 8996 static void x86_cpu_post_initfn(Object *obj) 8997 { 8998 static bool first = true; 8999 uint64_t supported_xcr0; 9000 int i; 9001 9002 if (first) { 9003 first = false; 9004 9005 supported_xcr0 = 9006 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 9007 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 9008 9009 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 9010 ExtSaveArea *esa = &x86_ext_save_areas[i]; 9011 9012 if (!(supported_xcr0 & (1 << i))) { 9013 esa->size = 0; 9014 } 9015 } 9016 } 9017 9018 accel_cpu_instance_init(CPU(obj)); 9019 9020 #ifndef CONFIG_USER_ONLY 9021 if (current_machine && current_machine->cgs) { 9022 x86_confidential_guest_cpu_instance_init( 9023 X86_CONFIDENTIAL_GUEST(current_machine->cgs), (CPU(obj))); 9024 } 9025 #endif 9026 } 9027 9028 static void x86_cpu_init_default_topo(X86CPU *cpu) 9029 { 9030 CPUX86State *env = &cpu->env; 9031 9032 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 9033 9034 /* thread, core and socket levels are set by default. */ 9035 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 9036 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 9037 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 9038 } 9039 9040 static void x86_cpu_initfn(Object *obj) 9041 { 9042 X86CPU *cpu = X86_CPU(obj); 9043 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 9044 CPUX86State *env = &cpu->env; 9045 9046 x86_cpu_init_default_topo(cpu); 9047 9048 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 9049 x86_cpu_get_feature_words, 9050 NULL, NULL, (void *)env->features); 9051 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 9052 x86_cpu_get_feature_words, 9053 NULL, NULL, (void *)cpu->filtered_features); 9054 9055 object_property_add_alias(obj, "sse3", obj, "pni"); 9056 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 9057 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 9058 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 9059 object_property_add_alias(obj, "xd", obj, "nx"); 9060 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 9061 object_property_add_alias(obj, "i64", obj, "lm"); 9062 9063 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 9064 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 9065 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 9066 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 9067 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 9068 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 9069 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 9070 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 9071 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 9072 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 9073 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 9074 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 9075 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 9076 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 9077 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 9078 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 9079 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 9080 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 9081 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 9082 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 9083 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 9084 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 9085 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 9086 9087 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 9088 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 9089 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 9090 9091 if (xcc->model) { 9092 x86_cpu_load_model(cpu, xcc->model); 9093 } 9094 } 9095 9096 static int64_t x86_cpu_get_arch_id(CPUState *cs) 9097 { 9098 X86CPU *cpu = X86_CPU(cs); 9099 9100 return cpu->apic_id; 9101 } 9102 9103 #if !defined(CONFIG_USER_ONLY) 9104 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 9105 { 9106 X86CPU *cpu = X86_CPU(cs); 9107 9108 return cpu->env.cr[0] & CR0_PG_MASK; 9109 } 9110 #endif /* !CONFIG_USER_ONLY */ 9111 9112 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 9113 { 9114 X86CPU *cpu = X86_CPU(cs); 9115 9116 cpu->env.eip = value; 9117 } 9118 9119 static vaddr x86_cpu_get_pc(CPUState *cs) 9120 { 9121 X86CPU *cpu = X86_CPU(cs); 9122 9123 /* Match cpu_get_tb_cpu_state. */ 9124 return cpu->env.eip + cpu->env.segs[R_CS].base; 9125 } 9126 9127 #if !defined(CONFIG_USER_ONLY) 9128 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 9129 { 9130 X86CPU *cpu = X86_CPU(cs); 9131 CPUX86State *env = &cpu->env; 9132 9133 if (interrupt_request & CPU_INTERRUPT_POLL) { 9134 return CPU_INTERRUPT_POLL; 9135 } 9136 if (interrupt_request & CPU_INTERRUPT_SIPI) { 9137 return CPU_INTERRUPT_SIPI; 9138 } 9139 9140 if (env->hflags2 & HF2_GIF_MASK) { 9141 if ((interrupt_request & CPU_INTERRUPT_SMI) && 9142 !(env->hflags & HF_SMM_MASK)) { 9143 return CPU_INTERRUPT_SMI; 9144 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 9145 !(env->hflags2 & HF2_NMI_MASK)) { 9146 return CPU_INTERRUPT_NMI; 9147 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 9148 return CPU_INTERRUPT_MCE; 9149 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 9150 (((env->hflags2 & HF2_VINTR_MASK) && 9151 (env->hflags2 & HF2_HIF_MASK)) || 9152 (!(env->hflags2 & HF2_VINTR_MASK) && 9153 (env->eflags & IF_MASK && 9154 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 9155 return CPU_INTERRUPT_HARD; 9156 } else if (env->hflags2 & HF2_VGIF_MASK) { 9157 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 9158 (env->eflags & IF_MASK) && 9159 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 9160 return CPU_INTERRUPT_VIRQ; 9161 } 9162 } 9163 } 9164 9165 return 0; 9166 } 9167 9168 static bool x86_cpu_has_work(CPUState *cs) 9169 { 9170 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 9171 } 9172 #endif /* !CONFIG_USER_ONLY */ 9173 9174 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 9175 { 9176 X86CPU *cpu = X86_CPU(cs); 9177 CPUX86State *env = &cpu->env; 9178 9179 info->endian = BFD_ENDIAN_LITTLE; 9180 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 9181 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 9182 : bfd_mach_i386_i8086); 9183 9184 info->cap_arch = CS_ARCH_X86; 9185 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 9186 : env->hflags & HF_CS32_MASK ? CS_MODE_32 9187 : CS_MODE_16); 9188 info->cap_insn_unit = 1; 9189 info->cap_insn_split = 8; 9190 } 9191 9192 void x86_update_hflags(CPUX86State *env) 9193 { 9194 uint32_t hflags; 9195 #define HFLAG_COPY_MASK \ 9196 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 9197 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 9198 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 9199 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 9200 9201 hflags = env->hflags & HFLAG_COPY_MASK; 9202 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 9203 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 9204 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 9205 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 9206 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 9207 9208 if (env->cr[4] & CR4_OSFXSR_MASK) { 9209 hflags |= HF_OSFXSR_MASK; 9210 } 9211 9212 if (env->efer & MSR_EFER_LMA) { 9213 hflags |= HF_LMA_MASK; 9214 } 9215 9216 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 9217 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 9218 } else { 9219 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 9220 (DESC_B_SHIFT - HF_CS32_SHIFT); 9221 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 9222 (DESC_B_SHIFT - HF_SS32_SHIFT); 9223 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 9224 !(hflags & HF_CS32_MASK)) { 9225 hflags |= HF_ADDSEG_MASK; 9226 } else { 9227 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 9228 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 9229 } 9230 } 9231 env->hflags = hflags; 9232 } 9233 9234 static const Property x86_cpu_properties[] = { 9235 #ifdef CONFIG_USER_ONLY 9236 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 9237 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 9238 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 9239 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 9240 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 9241 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 9242 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 9243 #else 9244 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 9245 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 9246 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 9247 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 9248 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 9249 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 9250 #endif 9251 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 9252 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 9253 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 9254 9255 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 9256 HYPERV_SPINLOCK_NEVER_NOTIFY), 9257 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 9258 HYPERV_FEAT_RELAXED, 0), 9259 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 9260 HYPERV_FEAT_VAPIC, 0), 9261 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 9262 HYPERV_FEAT_TIME, 0), 9263 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 9264 HYPERV_FEAT_CRASH, 0), 9265 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 9266 HYPERV_FEAT_RESET, 0), 9267 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 9268 HYPERV_FEAT_VPINDEX, 0), 9269 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 9270 HYPERV_FEAT_RUNTIME, 0), 9271 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 9272 HYPERV_FEAT_SYNIC, 0), 9273 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 9274 HYPERV_FEAT_STIMER, 0), 9275 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 9276 HYPERV_FEAT_FREQUENCIES, 0), 9277 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 9278 HYPERV_FEAT_REENLIGHTENMENT, 0), 9279 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 9280 HYPERV_FEAT_TLBFLUSH, 0), 9281 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 9282 HYPERV_FEAT_EVMCS, 0), 9283 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 9284 HYPERV_FEAT_IPI, 0), 9285 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 9286 HYPERV_FEAT_STIMER_DIRECT, 0), 9287 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 9288 HYPERV_FEAT_AVIC, 0), 9289 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 9290 HYPERV_FEAT_MSR_BITMAP, 0), 9291 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 9292 HYPERV_FEAT_XMM_INPUT, 0), 9293 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 9294 HYPERV_FEAT_TLBFLUSH_EXT, 0), 9295 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 9296 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 9297 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 9298 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 9299 #ifdef CONFIG_SYNDBG 9300 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 9301 HYPERV_FEAT_SYNDBG, 0), 9302 #endif 9303 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 9304 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 9305 9306 /* WS2008R2 identify by default */ 9307 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 9308 0x3839), 9309 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 9310 0x000A), 9311 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 9312 0x0000), 9313 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 9314 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 9315 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 9316 9317 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 9318 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 9319 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 9320 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 9321 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 9322 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 9323 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 9324 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 9325 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 9326 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 9327 UINT32_MAX), 9328 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 9329 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 9330 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 9331 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 9332 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 9333 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 9334 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 9335 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 9336 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 9337 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 9338 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 9339 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 9340 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 9341 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 9342 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 9343 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 9344 false), 9345 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 9346 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 9347 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 9348 true), 9349 /* 9350 * lecacy_cache defaults to true unless the CPU model provides its 9351 * own cache information (see x86_cpu_load_def()). 9352 */ 9353 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 9354 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 9355 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 9356 9357 /* 9358 * From "Requirements for Implementing the Microsoft 9359 * Hypervisor Interface": 9360 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 9361 * 9362 * "Starting with Windows Server 2012 and Windows 8, if 9363 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 9364 * the hypervisor imposes no specific limit to the number of VPs. 9365 * In this case, Windows Server 2012 guest VMs may use more than 9366 * 64 VPs, up to the maximum supported number of processors applicable 9367 * to the specific Windows version being used." 9368 */ 9369 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 9370 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 9371 false), 9372 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 9373 true), 9374 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 9375 }; 9376 9377 #ifndef CONFIG_USER_ONLY 9378 #include "hw/core/sysemu-cpu-ops.h" 9379 9380 static const struct SysemuCPUOps i386_sysemu_ops = { 9381 .has_work = x86_cpu_has_work, 9382 .get_memory_mapping = x86_cpu_get_memory_mapping, 9383 .get_paging_enabled = x86_cpu_get_paging_enabled, 9384 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 9385 .asidx_from_attrs = x86_asidx_from_attrs, 9386 .get_crash_info = x86_cpu_get_crash_info, 9387 .write_elf32_note = x86_cpu_write_elf32_note, 9388 .write_elf64_note = x86_cpu_write_elf64_note, 9389 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 9390 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 9391 .legacy_vmsd = &vmstate_x86_cpu, 9392 }; 9393 #endif 9394 9395 static void x86_cpu_common_class_init(ObjectClass *oc, const void *data) 9396 { 9397 X86CPUClass *xcc = X86_CPU_CLASS(oc); 9398 CPUClass *cc = CPU_CLASS(oc); 9399 DeviceClass *dc = DEVICE_CLASS(oc); 9400 ResettableClass *rc = RESETTABLE_CLASS(oc); 9401 FeatureWord w; 9402 9403 device_class_set_parent_realize(dc, x86_cpu_realizefn, 9404 &xcc->parent_realize); 9405 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 9406 &xcc->parent_unrealize); 9407 device_class_set_props(dc, x86_cpu_properties); 9408 9409 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 9410 &xcc->parent_phases); 9411 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 9412 9413 cc->class_by_name = x86_cpu_class_by_name; 9414 cc->list_cpus = x86_cpu_list; 9415 cc->parse_features = x86_cpu_parse_featurestr; 9416 cc->dump_state = x86_cpu_dump_state; 9417 cc->set_pc = x86_cpu_set_pc; 9418 cc->get_pc = x86_cpu_get_pc; 9419 cc->gdb_read_register = x86_cpu_gdb_read_register; 9420 cc->gdb_write_register = x86_cpu_gdb_write_register; 9421 cc->get_arch_id = x86_cpu_get_arch_id; 9422 9423 #ifndef CONFIG_USER_ONLY 9424 cc->sysemu_ops = &i386_sysemu_ops; 9425 #endif /* !CONFIG_USER_ONLY */ 9426 #ifdef CONFIG_TCG 9427 cc->tcg_ops = &x86_tcg_ops; 9428 #endif /* CONFIG_TCG */ 9429 9430 cc->gdb_arch_name = x86_gdb_arch_name; 9431 #ifdef TARGET_X86_64 9432 cc->gdb_core_xml_file = "i386-64bit.xml"; 9433 #else 9434 cc->gdb_core_xml_file = "i386-32bit.xml"; 9435 #endif 9436 cc->disas_set_info = x86_disas_set_info; 9437 9438 dc->user_creatable = true; 9439 9440 object_class_property_add(oc, "family", "int", 9441 x86_cpuid_version_get_family, 9442 x86_cpuid_version_set_family, NULL, NULL); 9443 object_class_property_add(oc, "model", "int", 9444 x86_cpuid_version_get_model, 9445 x86_cpuid_version_set_model, NULL, NULL); 9446 object_class_property_add(oc, "stepping", "int", 9447 x86_cpuid_version_get_stepping, 9448 x86_cpuid_version_set_stepping, NULL, NULL); 9449 object_class_property_add_str(oc, "vendor", 9450 x86_cpuid_get_vendor, 9451 x86_cpuid_set_vendor); 9452 object_class_property_add_str(oc, "model-id", 9453 x86_cpuid_get_model_id, 9454 x86_cpuid_set_model_id); 9455 object_class_property_add(oc, "tsc-frequency", "int", 9456 x86_cpuid_get_tsc_freq, 9457 x86_cpuid_set_tsc_freq, NULL, NULL); 9458 /* 9459 * The "unavailable-features" property has the same semantics as 9460 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 9461 * QMP command: they list the features that would have prevented the 9462 * CPU from running if the "enforce" flag was set. 9463 */ 9464 object_class_property_add(oc, "unavailable-features", "strList", 9465 x86_cpu_get_unavailable_features, 9466 NULL, NULL, NULL); 9467 9468 #if !defined(CONFIG_USER_ONLY) 9469 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 9470 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 9471 #endif 9472 9473 for (w = 0; w < FEATURE_WORDS; w++) { 9474 int bitnr; 9475 for (bitnr = 0; bitnr < 64; bitnr++) { 9476 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 9477 } 9478 } 9479 } 9480 9481 static const TypeInfo x86_cpu_type_info = { 9482 .name = TYPE_X86_CPU, 9483 .parent = TYPE_CPU, 9484 .instance_size = sizeof(X86CPU), 9485 .instance_align = __alignof(X86CPU), 9486 .instance_init = x86_cpu_initfn, 9487 .instance_post_init = x86_cpu_post_initfn, 9488 9489 .abstract = true, 9490 .class_size = sizeof(X86CPUClass), 9491 .class_init = x86_cpu_common_class_init, 9492 }; 9493 9494 /* "base" CPU model, used by query-cpu-model-expansion */ 9495 static void x86_cpu_base_class_init(ObjectClass *oc, const void *data) 9496 { 9497 X86CPUClass *xcc = X86_CPU_CLASS(oc); 9498 9499 xcc->static_model = true; 9500 xcc->migration_safe = true; 9501 xcc->model_description = "base CPU model type with no features enabled"; 9502 xcc->ordering = 8; 9503 } 9504 9505 static const TypeInfo x86_base_cpu_type_info = { 9506 .name = X86_CPU_TYPE_NAME("base"), 9507 .parent = TYPE_X86_CPU, 9508 .class_init = x86_cpu_base_class_init, 9509 }; 9510 9511 static void x86_cpu_register_types(void) 9512 { 9513 int i; 9514 9515 type_register_static(&x86_cpu_type_info); 9516 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 9517 x86_register_cpudef_types(&builtin_x86_defs[i]); 9518 } 9519 type_register_static(&max_x86_cpu_type_info); 9520 type_register_static(&x86_base_cpu_type_info); 9521 } 9522 9523 type_init(x86_cpu_register_types) 9524