1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #include "exec/watchpoint.h" 39 #ifndef CONFIG_USER_ONLY 40 #include "confidential-guest.h" 41 #include "system/reset.h" 42 #include "qapi/qapi-commands-machine-target.h" 43 #include "system/address-spaces.h" 44 #include "hw/boards.h" 45 #include "hw/i386/sgx-epc.h" 46 #endif 47 #include "tcg/tcg-cpu.h" 48 49 #include "disas/capstone.h" 50 #include "cpu-internal.h" 51 52 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 53 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 54 uint32_t *eax, uint32_t *ebx, 55 uint32_t *ecx, uint32_t *edx); 56 57 /* Helpers for building CPUID[2] descriptors: */ 58 59 struct CPUID2CacheDescriptorInfo { 60 enum CacheType type; 61 int level; 62 int size; 63 int line_size; 64 int associativity; 65 }; 66 67 /* 68 * Known CPUID 2 cache descriptors. 69 * From Intel SDM Volume 2A, CPUID instruction 70 */ 71 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 72 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 73 .associativity = 4, .line_size = 32, }, 74 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 75 .associativity = 4, .line_size = 32, }, 76 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 77 .associativity = 4, .line_size = 64, }, 78 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 79 .associativity = 2, .line_size = 32, }, 80 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 81 .associativity = 4, .line_size = 32, }, 82 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 83 .associativity = 4, .line_size = 64, }, 84 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 85 .associativity = 6, .line_size = 64, }, 86 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 87 .associativity = 2, .line_size = 64, }, 88 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 89 .associativity = 8, .line_size = 64, }, 90 /* lines per sector is not supported cpuid2_cache_descriptor(), 91 * so descriptors 0x22, 0x23 are not included 92 */ 93 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 94 .associativity = 16, .line_size = 64, }, 95 /* lines per sector is not supported cpuid2_cache_descriptor(), 96 * so descriptors 0x25, 0x20 are not included 97 */ 98 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 99 .associativity = 8, .line_size = 64, }, 100 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 101 .associativity = 8, .line_size = 64, }, 102 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 107 .associativity = 4, .line_size = 32, }, 108 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 109 .associativity = 4, .line_size = 32, }, 110 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 111 .associativity = 4, .line_size = 32, }, 112 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 113 .associativity = 4, .line_size = 64, }, 114 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 115 .associativity = 8, .line_size = 64, }, 116 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 119 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 120 .associativity = 12, .line_size = 64, }, 121 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 122 .associativity = 16, .line_size = 64, }, 123 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 124 .associativity = 12, .line_size = 64, }, 125 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 126 .associativity = 16, .line_size = 64, }, 127 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 128 .associativity = 24, .line_size = 64, }, 129 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 130 .associativity = 8, .line_size = 64, }, 131 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 132 .associativity = 4, .line_size = 64, }, 133 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 134 .associativity = 4, .line_size = 64, }, 135 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 136 .associativity = 4, .line_size = 64, }, 137 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 138 .associativity = 4, .line_size = 64, }, 139 /* lines per sector is not supported cpuid2_cache_descriptor(), 140 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 141 */ 142 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 143 .associativity = 8, .line_size = 64, }, 144 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 2, .line_size = 64, }, 146 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 147 .associativity = 8, .line_size = 64, }, 148 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 8, .line_size = 32, }, 152 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 8, .line_size = 32, }, 154 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 155 .associativity = 8, .line_size = 32, }, 156 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 157 .associativity = 4, .line_size = 64, }, 158 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 159 .associativity = 8, .line_size = 64, }, 160 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 161 .associativity = 4, .line_size = 64, }, 162 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 163 .associativity = 4, .line_size = 64, }, 164 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 165 .associativity = 4, .line_size = 64, }, 166 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 167 .associativity = 8, .line_size = 64, }, 168 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 169 .associativity = 8, .line_size = 64, }, 170 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 171 .associativity = 8, .line_size = 64, }, 172 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 173 .associativity = 12, .line_size = 64, }, 174 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 175 .associativity = 12, .line_size = 64, }, 176 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 177 .associativity = 12, .line_size = 64, }, 178 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 179 .associativity = 16, .line_size = 64, }, 180 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 181 .associativity = 16, .line_size = 64, }, 182 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 183 .associativity = 16, .line_size = 64, }, 184 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 185 .associativity = 24, .line_size = 64, }, 186 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 187 .associativity = 24, .line_size = 64, }, 188 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 189 .associativity = 24, .line_size = 64, }, 190 }; 191 192 /* 193 * "CPUID leaf 2 does not report cache descriptor information, 194 * use CPUID leaf 4 to query cache parameters" 195 */ 196 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 197 198 /* 199 * Return a CPUID 2 cache descriptor for a given cache. 200 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 201 */ 202 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 203 { 204 int i; 205 206 assert(cache->size > 0); 207 assert(cache->level > 0); 208 assert(cache->line_size > 0); 209 assert(cache->associativity > 0); 210 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 211 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 212 if (d->level == cache->level && d->type == cache->type && 213 d->size == cache->size && d->line_size == cache->line_size && 214 d->associativity == cache->associativity) { 215 return i; 216 } 217 } 218 219 return CACHE_DESCRIPTOR_UNAVAILABLE; 220 } 221 222 /* CPUID Leaf 4 constants: */ 223 224 /* EAX: */ 225 #define CACHE_TYPE_D 1 226 #define CACHE_TYPE_I 2 227 #define CACHE_TYPE_UNIFIED 3 228 229 #define CACHE_LEVEL(l) (l << 5) 230 231 #define CACHE_SELF_INIT_LEVEL (1 << 8) 232 233 /* EDX: */ 234 #define CACHE_NO_INVD_SHARING (1 << 0) 235 #define CACHE_INCLUSIVE (1 << 1) 236 #define CACHE_COMPLEX_IDX (1 << 2) 237 238 /* Encode CacheType for CPUID[4].EAX */ 239 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 240 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 241 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 242 0 /* Invalid value */) 243 244 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 245 enum CpuTopologyLevel share_level) 246 { 247 uint32_t num_ids = 0; 248 249 switch (share_level) { 250 case CPU_TOPOLOGY_LEVEL_CORE: 251 num_ids = 1 << apicid_core_offset(topo_info); 252 break; 253 case CPU_TOPOLOGY_LEVEL_MODULE: 254 num_ids = 1 << apicid_module_offset(topo_info); 255 break; 256 case CPU_TOPOLOGY_LEVEL_DIE: 257 num_ids = 1 << apicid_die_offset(topo_info); 258 break; 259 case CPU_TOPOLOGY_LEVEL_SOCKET: 260 num_ids = 1 << apicid_pkg_offset(topo_info); 261 break; 262 default: 263 /* 264 * Currently there is no use case for THREAD, so use 265 * assert directly to facilitate debugging. 266 */ 267 g_assert_not_reached(); 268 } 269 270 return num_ids - 1; 271 } 272 273 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 274 { 275 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 276 apicid_core_offset(topo_info)); 277 return num_cores - 1; 278 } 279 280 /* Encode cache info for CPUID[4] */ 281 static void encode_cache_cpuid4(CPUCacheInfo *cache, 282 X86CPUTopoInfo *topo_info, 283 uint32_t *eax, uint32_t *ebx, 284 uint32_t *ecx, uint32_t *edx) 285 { 286 assert(cache->size == cache->line_size * cache->associativity * 287 cache->partitions * cache->sets); 288 289 *eax = CACHE_TYPE(cache->type) | 290 CACHE_LEVEL(cache->level) | 291 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 292 (max_core_ids_in_package(topo_info) << 26) | 293 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 294 295 assert(cache->line_size > 0); 296 assert(cache->partitions > 0); 297 assert(cache->associativity > 0); 298 /* We don't implement fully-associative caches */ 299 assert(cache->associativity < cache->sets); 300 *ebx = (cache->line_size - 1) | 301 ((cache->partitions - 1) << 12) | 302 ((cache->associativity - 1) << 22); 303 304 assert(cache->sets > 0); 305 *ecx = cache->sets - 1; 306 307 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 308 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 309 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 310 } 311 312 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 313 enum CpuTopologyLevel topo_level) 314 { 315 switch (topo_level) { 316 case CPU_TOPOLOGY_LEVEL_THREAD: 317 return 1; 318 case CPU_TOPOLOGY_LEVEL_CORE: 319 return topo_info->threads_per_core; 320 case CPU_TOPOLOGY_LEVEL_MODULE: 321 return x86_threads_per_module(topo_info); 322 case CPU_TOPOLOGY_LEVEL_DIE: 323 return x86_threads_per_die(topo_info); 324 case CPU_TOPOLOGY_LEVEL_SOCKET: 325 return x86_threads_per_pkg(topo_info); 326 default: 327 g_assert_not_reached(); 328 } 329 return 0; 330 } 331 332 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 333 enum CpuTopologyLevel topo_level) 334 { 335 switch (topo_level) { 336 case CPU_TOPOLOGY_LEVEL_THREAD: 337 return 0; 338 case CPU_TOPOLOGY_LEVEL_CORE: 339 return apicid_core_offset(topo_info); 340 case CPU_TOPOLOGY_LEVEL_MODULE: 341 return apicid_module_offset(topo_info); 342 case CPU_TOPOLOGY_LEVEL_DIE: 343 return apicid_die_offset(topo_info); 344 case CPU_TOPOLOGY_LEVEL_SOCKET: 345 return apicid_pkg_offset(topo_info); 346 default: 347 g_assert_not_reached(); 348 } 349 return 0; 350 } 351 352 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 353 { 354 switch (topo_level) { 355 case CPU_TOPOLOGY_LEVEL_INVALID: 356 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 357 case CPU_TOPOLOGY_LEVEL_THREAD: 358 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 359 case CPU_TOPOLOGY_LEVEL_CORE: 360 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 361 case CPU_TOPOLOGY_LEVEL_MODULE: 362 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 363 case CPU_TOPOLOGY_LEVEL_DIE: 364 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 365 default: 366 /* Other types are not supported in QEMU. */ 367 g_assert_not_reached(); 368 } 369 return 0; 370 } 371 372 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 373 X86CPUTopoInfo *topo_info, 374 uint32_t *eax, uint32_t *ebx, 375 uint32_t *ecx, uint32_t *edx) 376 { 377 X86CPU *cpu = env_archcpu(env); 378 unsigned long level, base_level, next_level; 379 uint32_t num_threads_next_level, offset_next_level; 380 381 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 382 383 /* 384 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 385 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 386 */ 387 level = CPU_TOPOLOGY_LEVEL_THREAD; 388 base_level = level; 389 for (int i = 0; i <= count; i++) { 390 level = find_next_bit(env->avail_cpu_topo, 391 CPU_TOPOLOGY_LEVEL_SOCKET, 392 base_level); 393 394 /* 395 * CPUID[0x1f] doesn't explicitly encode the package level, 396 * and it just encodes the invalid level (all fields are 0) 397 * into the last subleaf of 0x1f. 398 */ 399 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 400 level = CPU_TOPOLOGY_LEVEL_INVALID; 401 break; 402 } 403 /* Search the next level. */ 404 base_level = level + 1; 405 } 406 407 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 408 num_threads_next_level = 0; 409 offset_next_level = 0; 410 } else { 411 next_level = find_next_bit(env->avail_cpu_topo, 412 CPU_TOPOLOGY_LEVEL_SOCKET, 413 level + 1); 414 num_threads_next_level = num_threads_by_topo_level(topo_info, 415 next_level); 416 offset_next_level = apicid_offset_by_topo_level(topo_info, 417 next_level); 418 } 419 420 *eax = offset_next_level; 421 /* The count (bits 15-00) doesn't need to be reliable. */ 422 *ebx = num_threads_next_level & 0xffff; 423 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 424 *edx = cpu->apic_id; 425 426 assert(!(*eax & ~0x1f)); 427 } 428 429 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 430 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 431 { 432 assert(cache->size % 1024 == 0); 433 assert(cache->lines_per_tag > 0); 434 assert(cache->associativity > 0); 435 assert(cache->line_size > 0); 436 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 437 (cache->lines_per_tag << 8) | (cache->line_size); 438 } 439 440 #define ASSOC_FULL 0xFF 441 442 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 443 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 444 a == 2 ? 0x2 : \ 445 a == 4 ? 0x4 : \ 446 a == 8 ? 0x6 : \ 447 a == 16 ? 0x8 : \ 448 a == 32 ? 0xA : \ 449 a == 48 ? 0xB : \ 450 a == 64 ? 0xC : \ 451 a == 96 ? 0xD : \ 452 a == 128 ? 0xE : \ 453 a == ASSOC_FULL ? 0xF : \ 454 0 /* invalid value */) 455 456 /* 457 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 458 * @l3 can be NULL. 459 */ 460 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 461 CPUCacheInfo *l3, 462 uint32_t *ecx, uint32_t *edx) 463 { 464 assert(l2->size % 1024 == 0); 465 assert(l2->associativity > 0); 466 assert(l2->lines_per_tag > 0); 467 assert(l2->line_size > 0); 468 *ecx = ((l2->size / 1024) << 16) | 469 (AMD_ENC_ASSOC(l2->associativity) << 12) | 470 (l2->lines_per_tag << 8) | (l2->line_size); 471 472 if (l3) { 473 assert(l3->size % (512 * 1024) == 0); 474 assert(l3->associativity > 0); 475 assert(l3->lines_per_tag > 0); 476 assert(l3->line_size > 0); 477 *edx = ((l3->size / (512 * 1024)) << 18) | 478 (AMD_ENC_ASSOC(l3->associativity) << 12) | 479 (l3->lines_per_tag << 8) | (l3->line_size); 480 } else { 481 *edx = 0; 482 } 483 } 484 485 /* Encode cache info for CPUID[8000001D] */ 486 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 487 X86CPUTopoInfo *topo_info, 488 uint32_t *eax, uint32_t *ebx, 489 uint32_t *ecx, uint32_t *edx) 490 { 491 assert(cache->size == cache->line_size * cache->associativity * 492 cache->partitions * cache->sets); 493 494 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 495 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 496 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 497 498 assert(cache->line_size > 0); 499 assert(cache->partitions > 0); 500 assert(cache->associativity > 0); 501 /* We don't implement fully-associative caches */ 502 assert(cache->associativity < cache->sets); 503 *ebx = (cache->line_size - 1) | 504 ((cache->partitions - 1) << 12) | 505 ((cache->associativity - 1) << 22); 506 507 assert(cache->sets > 0); 508 *ecx = cache->sets - 1; 509 510 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 511 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 512 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 513 } 514 515 /* Encode cache info for CPUID[8000001E] */ 516 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 517 uint32_t *eax, uint32_t *ebx, 518 uint32_t *ecx, uint32_t *edx) 519 { 520 X86CPUTopoIDs topo_ids; 521 522 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 523 524 *eax = cpu->apic_id; 525 526 /* 527 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 528 * Read-only. Reset: 0000_XXXXh. 529 * See Core::X86::Cpuid::ExtApicId. 530 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 531 * Bits Description 532 * 31:16 Reserved. 533 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 534 * The number of threads per core is ThreadsPerCore+1. 535 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 536 * 537 * NOTE: CoreId is already part of apic_id. Just use it. We can 538 * use all the 8 bits to represent the core_id here. 539 */ 540 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 541 542 /* 543 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 544 * Read-only. Reset: 0000_0XXXh. 545 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 546 * Bits Description 547 * 31:11 Reserved. 548 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 549 * ValidValues: 550 * Value Description 551 * 0h 1 node per processor. 552 * 7h-1h Reserved. 553 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 554 * 555 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 556 * But users can create more nodes than the actual hardware can 557 * support. To genaralize we can use all the upper 8 bits for nodes. 558 * NodeId is combination of node and socket_id which is already decoded 559 * in apic_id. Just use it by shifting. 560 */ 561 if (cpu->legacy_multi_node) { 562 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 563 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 564 } else { 565 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 566 } 567 568 *edx = 0; 569 } 570 571 /* 572 * Definitions of the hardcoded cache entries we expose: 573 * These are legacy cache values. If there is a need to change any 574 * of these values please use builtin_x86_defs 575 */ 576 577 /* L1 data cache: */ 578 static CPUCacheInfo legacy_l1d_cache = { 579 .type = DATA_CACHE, 580 .level = 1, 581 .size = 32 * KiB, 582 .self_init = 1, 583 .line_size = 64, 584 .associativity = 8, 585 .sets = 64, 586 .partitions = 1, 587 .no_invd_sharing = true, 588 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 589 }; 590 591 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 592 static CPUCacheInfo legacy_l1d_cache_amd = { 593 .type = DATA_CACHE, 594 .level = 1, 595 .size = 64 * KiB, 596 .self_init = 1, 597 .line_size = 64, 598 .associativity = 2, 599 .sets = 512, 600 .partitions = 1, 601 .lines_per_tag = 1, 602 .no_invd_sharing = true, 603 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 604 }; 605 606 /* L1 instruction cache: */ 607 static CPUCacheInfo legacy_l1i_cache = { 608 .type = INSTRUCTION_CACHE, 609 .level = 1, 610 .size = 32 * KiB, 611 .self_init = 1, 612 .line_size = 64, 613 .associativity = 8, 614 .sets = 64, 615 .partitions = 1, 616 .no_invd_sharing = true, 617 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 618 }; 619 620 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 621 static CPUCacheInfo legacy_l1i_cache_amd = { 622 .type = INSTRUCTION_CACHE, 623 .level = 1, 624 .size = 64 * KiB, 625 .self_init = 1, 626 .line_size = 64, 627 .associativity = 2, 628 .sets = 512, 629 .partitions = 1, 630 .lines_per_tag = 1, 631 .no_invd_sharing = true, 632 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 633 }; 634 635 /* Level 2 unified cache: */ 636 static CPUCacheInfo legacy_l2_cache = { 637 .type = UNIFIED_CACHE, 638 .level = 2, 639 .size = 4 * MiB, 640 .self_init = 1, 641 .line_size = 64, 642 .associativity = 16, 643 .sets = 4096, 644 .partitions = 1, 645 .no_invd_sharing = true, 646 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 647 }; 648 649 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 650 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 651 .type = UNIFIED_CACHE, 652 .level = 2, 653 .size = 2 * MiB, 654 .line_size = 64, 655 .associativity = 8, 656 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 657 }; 658 659 660 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 661 static CPUCacheInfo legacy_l2_cache_amd = { 662 .type = UNIFIED_CACHE, 663 .level = 2, 664 .size = 512 * KiB, 665 .line_size = 64, 666 .lines_per_tag = 1, 667 .associativity = 16, 668 .sets = 512, 669 .partitions = 1, 670 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 671 }; 672 673 /* Level 3 unified cache: */ 674 static CPUCacheInfo legacy_l3_cache = { 675 .type = UNIFIED_CACHE, 676 .level = 3, 677 .size = 16 * MiB, 678 .line_size = 64, 679 .associativity = 16, 680 .sets = 16384, 681 .partitions = 1, 682 .lines_per_tag = 1, 683 .self_init = true, 684 .inclusive = true, 685 .complex_indexing = true, 686 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 687 }; 688 689 /* TLB definitions: */ 690 691 #define L1_DTLB_2M_ASSOC 1 692 #define L1_DTLB_2M_ENTRIES 255 693 #define L1_DTLB_4K_ASSOC 1 694 #define L1_DTLB_4K_ENTRIES 255 695 696 #define L1_ITLB_2M_ASSOC 1 697 #define L1_ITLB_2M_ENTRIES 255 698 #define L1_ITLB_4K_ASSOC 1 699 #define L1_ITLB_4K_ENTRIES 255 700 701 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 702 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 703 #define L2_DTLB_4K_ASSOC 4 704 #define L2_DTLB_4K_ENTRIES 512 705 706 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 707 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 708 #define L2_ITLB_4K_ASSOC 4 709 #define L2_ITLB_4K_ENTRIES 512 710 711 /* CPUID Leaf 0x14 constants: */ 712 #define INTEL_PT_MAX_SUBLEAF 0x1 713 /* 714 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 715 * MSR can be accessed; 716 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 717 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 718 * of Intel PT MSRs across warm reset; 719 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 720 */ 721 #define INTEL_PT_MINIMAL_EBX 0xf 722 /* 723 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 724 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 725 * accessed; 726 * bit[01]: ToPA tables can hold any number of output entries, up to the 727 * maximum allowed by the MaskOrTableOffset field of 728 * IA32_RTIT_OUTPUT_MASK_PTRS; 729 * bit[02]: Support Single-Range Output scheme; 730 */ 731 #define INTEL_PT_MINIMAL_ECX 0x7 732 /* generated packets which contain IP payloads have LIP values */ 733 #define INTEL_PT_IP_LIP (1 << 31) 734 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 735 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 736 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 737 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 738 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 739 740 /* CPUID Leaf 0x1D constants: */ 741 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 742 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 743 #define INTEL_AMX_BYTES_PER_TILE 0x400 744 #define INTEL_AMX_BYTES_PER_ROW 0x40 745 #define INTEL_AMX_TILE_MAX_NAMES 0x8 746 #define INTEL_AMX_TILE_MAX_ROWS 0x10 747 748 /* CPUID Leaf 0x1E constants: */ 749 #define INTEL_AMX_TMUL_MAX_K 0x10 750 #define INTEL_AMX_TMUL_MAX_N 0x40 751 752 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 753 uint32_t vendor2, uint32_t vendor3) 754 { 755 int i; 756 for (i = 0; i < 4; i++) { 757 dst[i] = vendor1 >> (8 * i); 758 dst[i + 4] = vendor2 >> (8 * i); 759 dst[i + 8] = vendor3 >> (8 * i); 760 } 761 dst[CPUID_VENDOR_SZ] = '\0'; 762 } 763 764 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 765 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 766 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 767 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 768 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 769 CPUID_PSE36 | CPUID_FXSR) 770 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 771 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 772 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 773 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 774 CPUID_PAE | CPUID_SEP | CPUID_APIC) 775 776 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 777 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 778 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 779 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 780 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE | \ 781 CPUID_HT) 782 /* partly implemented: 783 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 784 /* missing: 785 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_TM, CPUID_PBE */ 786 787 /* 788 * Kernel-only features that can be shown to usermode programs even if 789 * they aren't actually supported by TCG, because qemu-user only runs 790 * in CPL=3; remove them if they are ever implemented for system emulation. 791 */ 792 #if defined CONFIG_USER_ONLY 793 #define CPUID_EXT_KERNEL_FEATURES \ 794 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 795 #else 796 #define CPUID_EXT_KERNEL_FEATURES 0 797 #endif 798 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 799 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 800 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 801 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 802 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 803 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 804 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 805 /* missing: 806 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 807 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 808 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 809 CPUID_EXT_TSC_DEADLINE_TIMER 810 */ 811 812 #ifdef TARGET_X86_64 813 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 814 #else 815 #define TCG_EXT2_X86_64_FEATURES 0 816 #endif 817 818 /* 819 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 820 * in usermode or by 32-bit programs. Those are added to supported 821 * TCG features unconditionally in user-mode emulation mode. This may 822 * indeed seem strange or incorrect, but it works because code running 823 * under usermode emulation cannot access them. 824 * 825 * Even for long mode, qemu-i386 is not running "a userspace program on a 826 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 827 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 828 * but again the difference is only visible in kernel mode. 829 */ 830 #if defined CONFIG_LINUX_USER 831 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 832 #elif defined CONFIG_USER_ONLY 833 /* FIXME: Long mode not yet supported for i386 bsd-user */ 834 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 835 #else 836 #define CPUID_EXT2_KERNEL_FEATURES 0 837 #endif 838 839 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 840 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 841 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 842 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 843 CPUID_EXT2_KERNEL_FEATURES) 844 845 #if defined CONFIG_USER_ONLY 846 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 847 #else 848 #define CPUID_EXT3_KERNEL_FEATURES 0 849 #endif 850 851 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 852 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 853 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES | \ 854 CPUID_EXT3_CMP_LEG) 855 856 #define TCG_EXT4_FEATURES 0 857 858 #if defined CONFIG_USER_ONLY 859 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 860 #else 861 #define CPUID_SVM_KERNEL_FEATURES 0 862 #endif 863 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 864 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 865 866 #define TCG_KVM_FEATURES 0 867 868 #if defined CONFIG_USER_ONLY 869 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 870 #else 871 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 872 #endif 873 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 874 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 875 CPUID_7_0_EBX_CLFLUSHOPT | \ 876 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 877 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 878 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 879 /* missing: 880 CPUID_7_0_EBX_HLE 881 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 882 883 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 884 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 885 #else 886 #define TCG_7_0_ECX_RDPID 0 887 #endif 888 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 889 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 890 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 891 TCG_7_0_ECX_RDPID) 892 893 #if defined CONFIG_USER_ONLY 894 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 895 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 896 #else 897 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 898 #endif 899 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 900 901 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 902 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 903 #define TCG_7_1_EDX_FEATURES 0 904 #define TCG_7_2_EDX_FEATURES 0 905 #define TCG_APM_FEATURES 0 906 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 907 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 908 /* missing: 909 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 910 #define TCG_14_0_ECX_FEATURES 0 911 #define TCG_SGX_12_0_EAX_FEATURES 0 912 #define TCG_SGX_12_0_EBX_FEATURES 0 913 #define TCG_SGX_12_1_EAX_FEATURES 0 914 #define TCG_24_0_EBX_FEATURES 0 915 916 #if defined CONFIG_USER_ONLY 917 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 918 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 919 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 920 CPUID_8000_0008_EBX_AMD_PSFD) 921 #else 922 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 923 #endif 924 925 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 926 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 927 928 #if defined CONFIG_USER_ONLY 929 #define CPUID_8000_0021_EAX_KERNEL_FEATURES CPUID_8000_0021_EAX_AUTO_IBRS 930 #else 931 #define CPUID_8000_0021_EAX_KERNEL_FEATURES 0 932 #endif 933 934 #define TCG_8000_0021_EAX_FEATURES ( \ 935 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | \ 936 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | \ 937 CPUID_8000_0021_EAX_KERNEL_FEATURES) 938 939 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 940 [FEAT_1_EDX] = { 941 .type = CPUID_FEATURE_WORD, 942 .feat_names = { 943 "fpu", "vme", "de", "pse", 944 "tsc", "msr", "pae", "mce", 945 "cx8", "apic", NULL, "sep", 946 "mtrr", "pge", "mca", "cmov", 947 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 948 NULL, "ds" /* Intel dts */, "acpi", "mmx", 949 "fxsr", "sse", "sse2", "ss", 950 "ht" /* Intel htt */, "tm", "ia64", "pbe", 951 }, 952 .cpuid = {.eax = 1, .reg = R_EDX, }, 953 .tcg_features = TCG_FEATURES, 954 .no_autoenable_flags = CPUID_HT, 955 }, 956 [FEAT_1_ECX] = { 957 .type = CPUID_FEATURE_WORD, 958 .feat_names = { 959 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 960 "ds-cpl", "vmx", "smx", "est", 961 "tm2", "ssse3", "cid", NULL, 962 "fma", "cx16", "xtpr", "pdcm", 963 NULL, "pcid", "dca", "sse4.1", 964 "sse4.2", "x2apic", "movbe", "popcnt", 965 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 966 "avx", "f16c", "rdrand", "hypervisor", 967 }, 968 .cpuid = { .eax = 1, .reg = R_ECX, }, 969 .tcg_features = TCG_EXT_FEATURES, 970 }, 971 /* Feature names that are already defined on feature_name[] but 972 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 973 * names on feat_names below. They are copied automatically 974 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 975 */ 976 [FEAT_8000_0001_EDX] = { 977 .type = CPUID_FEATURE_WORD, 978 .feat_names = { 979 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 980 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 981 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 982 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 983 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 984 "nx", NULL, "mmxext", NULL /* mmx */, 985 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 986 NULL, "lm", "3dnowext", "3dnow", 987 }, 988 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 989 .tcg_features = TCG_EXT2_FEATURES, 990 }, 991 [FEAT_8000_0001_ECX] = { 992 .type = CPUID_FEATURE_WORD, 993 .feat_names = { 994 "lahf-lm", "cmp-legacy", "svm", "extapic", 995 "cr8legacy", "abm", "sse4a", "misalignsse", 996 "3dnowprefetch", "osvw", "ibs", "xop", 997 "skinit", "wdt", NULL, "lwp", 998 "fma4", "tce", NULL, "nodeid-msr", 999 NULL, "tbm", "topoext", "perfctr-core", 1000 "perfctr-nb", NULL, NULL, NULL, 1001 NULL, NULL, NULL, NULL, 1002 }, 1003 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 1004 .tcg_features = TCG_EXT3_FEATURES, 1005 /* 1006 * TOPOEXT is always allowed but can't be enabled blindly by 1007 * "-cpu host", as it requires consistent cache topology info 1008 * to be provided so it doesn't confuse guests. 1009 */ 1010 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 1011 }, 1012 [FEAT_C000_0001_EDX] = { 1013 .type = CPUID_FEATURE_WORD, 1014 .feat_names = { 1015 NULL, NULL, "xstore", "xstore-en", 1016 NULL, NULL, "xcrypt", "xcrypt-en", 1017 "ace2", "ace2-en", "phe", "phe-en", 1018 "pmm", "pmm-en", NULL, NULL, 1019 NULL, NULL, NULL, NULL, 1020 NULL, NULL, NULL, NULL, 1021 NULL, NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 }, 1024 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1025 .tcg_features = TCG_EXT4_FEATURES, 1026 }, 1027 [FEAT_KVM] = { 1028 .type = CPUID_FEATURE_WORD, 1029 .feat_names = { 1030 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1031 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1032 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1033 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1034 NULL, NULL, NULL, NULL, 1035 NULL, NULL, NULL, NULL, 1036 "kvmclock-stable-bit", NULL, NULL, NULL, 1037 NULL, NULL, NULL, NULL, 1038 }, 1039 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1040 .tcg_features = TCG_KVM_FEATURES, 1041 }, 1042 [FEAT_KVM_HINTS] = { 1043 .type = CPUID_FEATURE_WORD, 1044 .feat_names = { 1045 "kvm-hint-dedicated", NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 NULL, NULL, NULL, NULL, 1051 NULL, NULL, NULL, NULL, 1052 NULL, NULL, NULL, NULL, 1053 }, 1054 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1055 .tcg_features = TCG_KVM_FEATURES, 1056 /* 1057 * KVM hints aren't auto-enabled by -cpu host, they need to be 1058 * explicitly enabled in the command-line. 1059 */ 1060 .no_autoenable_flags = ~0U, 1061 }, 1062 [FEAT_SVM] = { 1063 .type = CPUID_FEATURE_WORD, 1064 .feat_names = { 1065 "npt", "lbrv", "svm-lock", "nrip-save", 1066 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1067 NULL, NULL, "pause-filter", NULL, 1068 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1069 "vgif", NULL, NULL, NULL, 1070 NULL, NULL, NULL, NULL, 1071 NULL, "vnmi", NULL, NULL, 1072 "svme-addr-chk", NULL, NULL, NULL, 1073 }, 1074 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1075 .tcg_features = TCG_SVM_FEATURES, 1076 }, 1077 [FEAT_7_0_EBX] = { 1078 .type = CPUID_FEATURE_WORD, 1079 .feat_names = { 1080 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1081 "hle", "avx2", "fdp-excptn-only", "smep", 1082 "bmi2", "erms", "invpcid", "rtm", 1083 NULL, "zero-fcs-fds", "mpx", NULL, 1084 "avx512f", "avx512dq", "rdseed", "adx", 1085 "smap", "avx512ifma", "pcommit", "clflushopt", 1086 "clwb", "intel-pt", "avx512pf", "avx512er", 1087 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1088 }, 1089 .cpuid = { 1090 .eax = 7, 1091 .needs_ecx = true, .ecx = 0, 1092 .reg = R_EBX, 1093 }, 1094 .tcg_features = TCG_7_0_EBX_FEATURES, 1095 }, 1096 [FEAT_7_0_ECX] = { 1097 .type = CPUID_FEATURE_WORD, 1098 .feat_names = { 1099 NULL, "avx512vbmi", "umip", "pku", 1100 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1101 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1102 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1103 "la57", NULL, NULL, NULL, 1104 NULL, NULL, "rdpid", NULL, 1105 "bus-lock-detect", "cldemote", NULL, "movdiri", 1106 "movdir64b", NULL, "sgxlc", "pks", 1107 }, 1108 .cpuid = { 1109 .eax = 7, 1110 .needs_ecx = true, .ecx = 0, 1111 .reg = R_ECX, 1112 }, 1113 .tcg_features = TCG_7_0_ECX_FEATURES, 1114 }, 1115 [FEAT_7_0_EDX] = { 1116 .type = CPUID_FEATURE_WORD, 1117 .feat_names = { 1118 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1119 "fsrm", NULL, NULL, NULL, 1120 "avx512-vp2intersect", NULL, "md-clear", NULL, 1121 NULL, NULL, "serialize", NULL, 1122 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1123 NULL, NULL, "amx-bf16", "avx512-fp16", 1124 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1125 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1126 }, 1127 .cpuid = { 1128 .eax = 7, 1129 .needs_ecx = true, .ecx = 0, 1130 .reg = R_EDX, 1131 }, 1132 .tcg_features = TCG_7_0_EDX_FEATURES, 1133 }, 1134 [FEAT_7_1_EAX] = { 1135 .type = CPUID_FEATURE_WORD, 1136 .feat_names = { 1137 "sha512", "sm3", "sm4", NULL, 1138 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1139 NULL, NULL, "fzrm", "fsrs", 1140 "fsrc", NULL, NULL, NULL, 1141 NULL, "fred", "lkgs", "wrmsrns", 1142 NULL, "amx-fp16", NULL, "avx-ifma", 1143 NULL, NULL, "lam", NULL, 1144 NULL, NULL, NULL, NULL, 1145 }, 1146 .cpuid = { 1147 .eax = 7, 1148 .needs_ecx = true, .ecx = 1, 1149 .reg = R_EAX, 1150 }, 1151 .tcg_features = TCG_7_1_EAX_FEATURES, 1152 }, 1153 [FEAT_7_1_EDX] = { 1154 .type = CPUID_FEATURE_WORD, 1155 .feat_names = { 1156 NULL, NULL, NULL, NULL, 1157 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1158 "amx-complex", NULL, "avx-vnni-int16", NULL, 1159 NULL, NULL, "prefetchiti", NULL, 1160 NULL, NULL, NULL, "avx10", 1161 NULL, NULL, NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 NULL, NULL, NULL, NULL, 1164 }, 1165 .cpuid = { 1166 .eax = 7, 1167 .needs_ecx = true, .ecx = 1, 1168 .reg = R_EDX, 1169 }, 1170 .tcg_features = TCG_7_1_EDX_FEATURES, 1171 }, 1172 [FEAT_7_2_EDX] = { 1173 .type = CPUID_FEATURE_WORD, 1174 .feat_names = { 1175 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1176 "bhi-ctrl", "mcdt-no", NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 NULL, NULL, NULL, NULL, 1180 NULL, NULL, NULL, NULL, 1181 NULL, NULL, NULL, NULL, 1182 NULL, NULL, NULL, NULL, 1183 }, 1184 .cpuid = { 1185 .eax = 7, 1186 .needs_ecx = true, .ecx = 2, 1187 .reg = R_EDX, 1188 }, 1189 .tcg_features = TCG_7_2_EDX_FEATURES, 1190 }, 1191 [FEAT_24_0_EBX] = { 1192 .type = CPUID_FEATURE_WORD, 1193 .feat_names = { 1194 [16] = "avx10-128", 1195 [17] = "avx10-256", 1196 [18] = "avx10-512", 1197 }, 1198 .cpuid = { 1199 .eax = 0x24, 1200 .needs_ecx = true, .ecx = 0, 1201 .reg = R_EBX, 1202 }, 1203 .tcg_features = TCG_24_0_EBX_FEATURES, 1204 }, 1205 [FEAT_8000_0007_EDX] = { 1206 .type = CPUID_FEATURE_WORD, 1207 .feat_names = { 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 "invtsc", NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 NULL, NULL, NULL, NULL, 1216 }, 1217 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1218 .tcg_features = TCG_APM_FEATURES, 1219 .unmigratable_flags = CPUID_APM_INVTSC, 1220 }, 1221 [FEAT_8000_0007_EBX] = { 1222 .type = CPUID_FEATURE_WORD, 1223 .feat_names = { 1224 "overflow-recov", "succor", NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 NULL, NULL, NULL, NULL, 1227 NULL, NULL, NULL, NULL, 1228 NULL, NULL, NULL, NULL, 1229 NULL, NULL, NULL, NULL, 1230 NULL, NULL, NULL, NULL, 1231 NULL, NULL, NULL, NULL, 1232 }, 1233 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1234 .tcg_features = 0, 1235 .unmigratable_flags = 0, 1236 }, 1237 [FEAT_8000_0008_EBX] = { 1238 .type = CPUID_FEATURE_WORD, 1239 .feat_names = { 1240 "clzero", NULL, "xsaveerptr", NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, "wbnoinvd", NULL, NULL, 1243 "ibpb", NULL, "ibrs", "amd-stibp", 1244 NULL, "stibp-always-on", NULL, NULL, 1245 NULL, NULL, NULL, NULL, 1246 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1247 "amd-psfd", NULL, NULL, NULL, 1248 }, 1249 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1250 .tcg_features = TCG_8000_0008_EBX, 1251 .unmigratable_flags = 0, 1252 }, 1253 [FEAT_8000_0021_EAX] = { 1254 .type = CPUID_FEATURE_WORD, 1255 .feat_names = { 1256 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1257 NULL, NULL, "null-sel-clr-base", NULL, 1258 "auto-ibrs", NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 NULL, NULL, NULL, NULL, 1261 NULL, NULL, NULL, NULL, 1262 "eraps", NULL, NULL, "sbpb", 1263 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1264 }, 1265 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1266 .tcg_features = TCG_8000_0021_EAX_FEATURES, 1267 .unmigratable_flags = 0, 1268 }, 1269 [FEAT_8000_0021_EBX] = { 1270 .type = CPUID_FEATURE_WORD, 1271 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1272 .tcg_features = 0, 1273 .unmigratable_flags = 0, 1274 }, 1275 [FEAT_8000_0022_EAX] = { 1276 .type = CPUID_FEATURE_WORD, 1277 .feat_names = { 1278 "perfmon-v2", NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 }, 1287 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1288 .tcg_features = 0, 1289 .unmigratable_flags = 0, 1290 }, 1291 [FEAT_XSAVE] = { 1292 .type = CPUID_FEATURE_WORD, 1293 .feat_names = { 1294 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1295 "xfd", NULL, NULL, NULL, 1296 NULL, NULL, NULL, NULL, 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 NULL, NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 NULL, NULL, NULL, NULL, 1302 }, 1303 .cpuid = { 1304 .eax = 0xd, 1305 .needs_ecx = true, .ecx = 1, 1306 .reg = R_EAX, 1307 }, 1308 .tcg_features = TCG_XSAVE_FEATURES, 1309 }, 1310 [FEAT_XSAVE_XSS_LO] = { 1311 .type = CPUID_FEATURE_WORD, 1312 .feat_names = { 1313 NULL, NULL, NULL, NULL, 1314 NULL, NULL, NULL, NULL, 1315 NULL, NULL, NULL, NULL, 1316 NULL, NULL, NULL, NULL, 1317 NULL, NULL, NULL, NULL, 1318 NULL, NULL, NULL, NULL, 1319 NULL, NULL, NULL, NULL, 1320 NULL, NULL, NULL, NULL, 1321 }, 1322 .cpuid = { 1323 .eax = 0xD, 1324 .needs_ecx = true, 1325 .ecx = 1, 1326 .reg = R_ECX, 1327 }, 1328 }, 1329 [FEAT_XSAVE_XSS_HI] = { 1330 .type = CPUID_FEATURE_WORD, 1331 .cpuid = { 1332 .eax = 0xD, 1333 .needs_ecx = true, 1334 .ecx = 1, 1335 .reg = R_EDX 1336 }, 1337 }, 1338 [FEAT_6_EAX] = { 1339 .type = CPUID_FEATURE_WORD, 1340 .feat_names = { 1341 NULL, NULL, "arat", NULL, 1342 NULL, NULL, NULL, NULL, 1343 NULL, NULL, NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 NULL, NULL, NULL, NULL, 1349 }, 1350 .cpuid = { .eax = 6, .reg = R_EAX, }, 1351 .tcg_features = TCG_6_EAX_FEATURES, 1352 }, 1353 [FEAT_XSAVE_XCR0_LO] = { 1354 .type = CPUID_FEATURE_WORD, 1355 .cpuid = { 1356 .eax = 0xD, 1357 .needs_ecx = true, .ecx = 0, 1358 .reg = R_EAX, 1359 }, 1360 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1361 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1362 XSTATE_PKRU_MASK, 1363 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1364 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1365 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1366 XSTATE_PKRU_MASK, 1367 }, 1368 [FEAT_XSAVE_XCR0_HI] = { 1369 .type = CPUID_FEATURE_WORD, 1370 .cpuid = { 1371 .eax = 0xD, 1372 .needs_ecx = true, .ecx = 0, 1373 .reg = R_EDX, 1374 }, 1375 .tcg_features = 0U, 1376 }, 1377 /*Below are MSR exposed features*/ 1378 [FEAT_ARCH_CAPABILITIES] = { 1379 .type = MSR_FEATURE_WORD, 1380 .feat_names = { 1381 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1382 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1383 "taa-no", NULL, NULL, NULL, 1384 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1385 NULL, "fb-clear", NULL, NULL, 1386 "bhi-no", NULL, NULL, NULL, 1387 "pbrsb-no", NULL, "gds-no", "rfds-no", 1388 "rfds-clear", NULL, NULL, NULL, 1389 NULL, NULL, NULL, NULL, 1390 NULL, NULL, NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 NULL, NULL, NULL, NULL, 1395 NULL, NULL, NULL, NULL, 1396 NULL, NULL, "its-no", NULL, 1397 }, 1398 .msr = { 1399 .index = MSR_IA32_ARCH_CAPABILITIES, 1400 }, 1401 /* 1402 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1403 * cannot be read from user mode. Therefore, it has no impact 1404 > on any user-mode operation, and warnings about unsupported 1405 * features do not matter. 1406 */ 1407 .tcg_features = ~0U, 1408 }, 1409 [FEAT_CORE_CAPABILITY] = { 1410 .type = MSR_FEATURE_WORD, 1411 .feat_names = { 1412 NULL, NULL, NULL, NULL, 1413 NULL, "split-lock-detect", NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 NULL, NULL, NULL, NULL, 1417 NULL, NULL, NULL, NULL, 1418 NULL, NULL, NULL, NULL, 1419 NULL, NULL, NULL, NULL, 1420 }, 1421 .msr = { 1422 .index = MSR_IA32_CORE_CAPABILITY, 1423 }, 1424 }, 1425 [FEAT_PERF_CAPABILITIES] = { 1426 .type = MSR_FEATURE_WORD, 1427 .feat_names = { 1428 NULL, NULL, NULL, NULL, 1429 NULL, NULL, NULL, NULL, 1430 NULL, NULL, NULL, NULL, 1431 NULL, "full-width-write", NULL, NULL, 1432 NULL, NULL, NULL, NULL, 1433 NULL, NULL, NULL, NULL, 1434 NULL, NULL, NULL, NULL, 1435 NULL, NULL, NULL, NULL, 1436 }, 1437 .msr = { 1438 .index = MSR_IA32_PERF_CAPABILITIES, 1439 }, 1440 }, 1441 1442 [FEAT_VMX_PROCBASED_CTLS] = { 1443 .type = MSR_FEATURE_WORD, 1444 .feat_names = { 1445 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1446 NULL, NULL, NULL, "vmx-hlt-exit", 1447 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1448 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1449 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1450 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1451 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1452 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1453 }, 1454 .msr = { 1455 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1456 } 1457 }, 1458 1459 [FEAT_VMX_SECONDARY_CTLS] = { 1460 .type = MSR_FEATURE_WORD, 1461 .feat_names = { 1462 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1463 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1464 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1465 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1466 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1467 "vmx-xsaves", NULL, NULL, NULL, 1468 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1469 NULL, NULL, NULL, NULL, 1470 }, 1471 .msr = { 1472 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1473 } 1474 }, 1475 1476 [FEAT_VMX_PINBASED_CTLS] = { 1477 .type = MSR_FEATURE_WORD, 1478 .feat_names = { 1479 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1480 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1481 NULL, NULL, NULL, NULL, 1482 NULL, NULL, NULL, NULL, 1483 NULL, NULL, NULL, NULL, 1484 NULL, NULL, NULL, NULL, 1485 NULL, NULL, NULL, NULL, 1486 NULL, NULL, NULL, NULL, 1487 }, 1488 .msr = { 1489 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1490 } 1491 }, 1492 1493 [FEAT_VMX_EXIT_CTLS] = { 1494 .type = MSR_FEATURE_WORD, 1495 /* 1496 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1497 * the LM CPUID bit. 1498 */ 1499 .feat_names = { 1500 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1501 NULL, NULL, NULL, NULL, 1502 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1503 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1504 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1505 "vmx-exit-save-efer", "vmx-exit-load-efer", 1506 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1507 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1508 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1509 }, 1510 .msr = { 1511 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1512 } 1513 }, 1514 1515 [FEAT_VMX_ENTRY_CTLS] = { 1516 .type = MSR_FEATURE_WORD, 1517 .feat_names = { 1518 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1519 NULL, NULL, NULL, NULL, 1520 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1521 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1522 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1523 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1524 NULL, NULL, NULL, NULL, 1525 NULL, NULL, NULL, NULL, 1526 }, 1527 .msr = { 1528 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1529 } 1530 }, 1531 1532 [FEAT_VMX_MISC] = { 1533 .type = MSR_FEATURE_WORD, 1534 .feat_names = { 1535 NULL, NULL, NULL, NULL, 1536 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1537 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, NULL, NULL, 1540 NULL, NULL, NULL, NULL, 1541 NULL, NULL, NULL, NULL, 1542 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1543 }, 1544 .msr = { 1545 .index = MSR_IA32_VMX_MISC, 1546 } 1547 }, 1548 1549 [FEAT_VMX_EPT_VPID_CAPS] = { 1550 .type = MSR_FEATURE_WORD, 1551 .feat_names = { 1552 "vmx-ept-execonly", NULL, NULL, NULL, 1553 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1554 NULL, NULL, NULL, NULL, 1555 NULL, NULL, NULL, NULL, 1556 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1557 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1558 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1559 NULL, NULL, NULL, NULL, 1560 "vmx-invvpid", NULL, NULL, NULL, 1561 NULL, NULL, NULL, NULL, 1562 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1563 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1564 NULL, NULL, NULL, NULL, 1565 NULL, NULL, NULL, NULL, 1566 NULL, NULL, NULL, NULL, 1567 NULL, NULL, NULL, NULL, 1568 NULL, NULL, NULL, NULL, 1569 }, 1570 .msr = { 1571 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1572 } 1573 }, 1574 1575 [FEAT_VMX_BASIC] = { 1576 .type = MSR_FEATURE_WORD, 1577 .feat_names = { 1578 [54] = "vmx-ins-outs", 1579 [55] = "vmx-true-ctls", 1580 [56] = "vmx-any-errcode", 1581 [58] = "vmx-nested-exception", 1582 }, 1583 .msr = { 1584 .index = MSR_IA32_VMX_BASIC, 1585 }, 1586 /* Just to be safe - we don't support setting the MSEG version field. */ 1587 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1588 }, 1589 1590 [FEAT_VMX_VMFUNC] = { 1591 .type = MSR_FEATURE_WORD, 1592 .feat_names = { 1593 [0] = "vmx-eptp-switching", 1594 }, 1595 .msr = { 1596 .index = MSR_IA32_VMX_VMFUNC, 1597 } 1598 }, 1599 1600 [FEAT_14_0_ECX] = { 1601 .type = CPUID_FEATURE_WORD, 1602 .feat_names = { 1603 NULL, NULL, NULL, NULL, 1604 NULL, NULL, NULL, NULL, 1605 NULL, NULL, NULL, NULL, 1606 NULL, NULL, NULL, NULL, 1607 NULL, NULL, NULL, NULL, 1608 NULL, NULL, NULL, NULL, 1609 NULL, NULL, NULL, NULL, 1610 NULL, NULL, NULL, "intel-pt-lip", 1611 }, 1612 .cpuid = { 1613 .eax = 0x14, 1614 .needs_ecx = true, .ecx = 0, 1615 .reg = R_ECX, 1616 }, 1617 .tcg_features = TCG_14_0_ECX_FEATURES, 1618 }, 1619 1620 [FEAT_SGX_12_0_EAX] = { 1621 .type = CPUID_FEATURE_WORD, 1622 .feat_names = { 1623 "sgx1", "sgx2", NULL, NULL, 1624 NULL, NULL, NULL, NULL, 1625 NULL, NULL, NULL, "sgx-edeccssa", 1626 NULL, NULL, NULL, NULL, 1627 NULL, NULL, NULL, NULL, 1628 NULL, NULL, NULL, NULL, 1629 NULL, NULL, NULL, NULL, 1630 NULL, NULL, NULL, NULL, 1631 }, 1632 .cpuid = { 1633 .eax = 0x12, 1634 .needs_ecx = true, .ecx = 0, 1635 .reg = R_EAX, 1636 }, 1637 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1638 }, 1639 1640 [FEAT_SGX_12_0_EBX] = { 1641 .type = CPUID_FEATURE_WORD, 1642 .feat_names = { 1643 "sgx-exinfo" , NULL, NULL, NULL, 1644 NULL, NULL, NULL, NULL, 1645 NULL, NULL, NULL, NULL, 1646 NULL, NULL, NULL, NULL, 1647 NULL, NULL, NULL, NULL, 1648 NULL, NULL, NULL, NULL, 1649 NULL, NULL, NULL, NULL, 1650 NULL, NULL, NULL, NULL, 1651 }, 1652 .cpuid = { 1653 .eax = 0x12, 1654 .needs_ecx = true, .ecx = 0, 1655 .reg = R_EBX, 1656 }, 1657 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1658 }, 1659 1660 [FEAT_SGX_12_1_EAX] = { 1661 .type = CPUID_FEATURE_WORD, 1662 .feat_names = { 1663 NULL, "sgx-debug", "sgx-mode64", NULL, 1664 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1665 NULL, NULL, "sgx-aex-notify", NULL, 1666 NULL, NULL, NULL, NULL, 1667 NULL, NULL, NULL, NULL, 1668 NULL, NULL, NULL, NULL, 1669 NULL, NULL, NULL, NULL, 1670 NULL, NULL, NULL, NULL, 1671 }, 1672 .cpuid = { 1673 .eax = 0x12, 1674 .needs_ecx = true, .ecx = 1, 1675 .reg = R_EAX, 1676 }, 1677 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1678 }, 1679 }; 1680 1681 bool is_feature_word_cpuid(uint32_t feature, uint32_t index, int reg) 1682 { 1683 FeatureWordInfo *wi; 1684 FeatureWord w; 1685 1686 for (w = 0; w < FEATURE_WORDS; w++) { 1687 wi = &feature_word_info[w]; 1688 if (wi->type == CPUID_FEATURE_WORD && wi->cpuid.eax == feature && 1689 (!wi->cpuid.needs_ecx || wi->cpuid.ecx == index) && 1690 wi->cpuid.reg == reg) { 1691 return true; 1692 } 1693 } 1694 return false; 1695 } 1696 1697 static FeatureDep feature_dependencies[] = { 1698 { 1699 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1700 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1701 }, 1702 { 1703 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1704 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1705 }, 1706 { 1707 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1708 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1709 }, 1710 { 1711 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1712 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1713 }, 1714 { 1715 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1716 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1717 }, 1718 { 1719 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1720 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1721 }, 1722 { 1723 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1724 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1725 }, 1726 { 1727 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1728 .to = { FEAT_VMX_MISC, ~0ull }, 1729 }, 1730 { 1731 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1732 .to = { FEAT_VMX_BASIC, ~0ull }, 1733 }, 1734 { 1735 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1736 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1737 }, 1738 { 1739 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1740 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1741 }, 1742 { 1743 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1744 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1745 }, 1746 { 1747 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1748 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1749 }, 1750 { 1751 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1752 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1753 }, 1754 { 1755 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1756 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1757 }, 1758 { 1759 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1760 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1761 }, 1762 { 1763 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1764 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1765 }, 1766 { 1767 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1768 .to = { FEAT_14_0_ECX, ~0ull }, 1769 }, 1770 { 1771 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1772 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1773 }, 1774 { 1775 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1776 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1777 }, 1778 { 1779 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1780 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1781 }, 1782 { 1783 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1784 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1785 }, 1786 { 1787 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1788 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1789 }, 1790 { 1791 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1792 .to = { FEAT_SVM, ~0ull }, 1793 }, 1794 { 1795 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1796 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1797 }, 1798 { 1799 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1800 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1801 }, 1802 { 1803 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1804 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1805 }, 1806 { 1807 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1808 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1809 }, 1810 { 1811 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1812 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1813 }, 1814 { 1815 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1816 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1817 }, 1818 { 1819 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1820 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1821 }, 1822 { 1823 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1824 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1825 }, 1826 { 1827 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1828 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1829 }, 1830 { 1831 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1832 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1833 }, 1834 { 1835 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1836 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1837 }, 1838 { 1839 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1840 .to = { FEAT_24_0_EBX, ~0ull }, 1841 }, 1842 }; 1843 1844 typedef struct X86RegisterInfo32 { 1845 /* Name of register */ 1846 const char *name; 1847 /* QAPI enum value register */ 1848 X86CPURegister32 qapi_enum; 1849 } X86RegisterInfo32; 1850 1851 #define REGISTER(reg) \ 1852 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1853 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1854 REGISTER(EAX), 1855 REGISTER(ECX), 1856 REGISTER(EDX), 1857 REGISTER(EBX), 1858 REGISTER(ESP), 1859 REGISTER(EBP), 1860 REGISTER(ESI), 1861 REGISTER(EDI), 1862 }; 1863 #undef REGISTER 1864 1865 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1866 [XSTATE_FP_BIT] = { 1867 /* x87 FP state component is always enabled if XSAVE is supported */ 1868 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1869 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1870 }, 1871 [XSTATE_SSE_BIT] = { 1872 /* SSE state component is always enabled if XSAVE is supported */ 1873 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1874 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1875 }, 1876 [XSTATE_YMM_BIT] = 1877 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1878 .size = sizeof(XSaveAVX) }, 1879 [XSTATE_BNDREGS_BIT] = 1880 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1881 .size = sizeof(XSaveBNDREG) }, 1882 [XSTATE_BNDCSR_BIT] = 1883 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1884 .size = sizeof(XSaveBNDCSR) }, 1885 [XSTATE_OPMASK_BIT] = 1886 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1887 .size = sizeof(XSaveOpmask) }, 1888 [XSTATE_ZMM_Hi256_BIT] = 1889 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1890 .size = sizeof(XSaveZMM_Hi256) }, 1891 [XSTATE_Hi16_ZMM_BIT] = 1892 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1893 .size = sizeof(XSaveHi16_ZMM) }, 1894 [XSTATE_PKRU_BIT] = 1895 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1896 .size = sizeof(XSavePKRU) }, 1897 [XSTATE_ARCH_LBR_BIT] = { 1898 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1899 .offset = 0 /*supervisor mode component, offset = 0 */, 1900 .size = sizeof(XSavesArchLBR) }, 1901 [XSTATE_XTILE_CFG_BIT] = { 1902 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1903 .size = sizeof(XSaveXTILECFG), 1904 }, 1905 [XSTATE_XTILE_DATA_BIT] = { 1906 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1907 .size = sizeof(XSaveXTILEDATA) 1908 }, 1909 }; 1910 1911 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1912 { 1913 uint64_t ret = x86_ext_save_areas[0].size; 1914 const ExtSaveArea *esa; 1915 uint32_t offset = 0; 1916 int i; 1917 1918 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1919 esa = &x86_ext_save_areas[i]; 1920 if ((mask >> i) & 1) { 1921 offset = compacted ? ret : esa->offset; 1922 ret = MAX(ret, offset + esa->size); 1923 } 1924 } 1925 return ret; 1926 } 1927 1928 static inline bool accel_uses_host_cpuid(void) 1929 { 1930 return kvm_enabled() || hvf_enabled(); 1931 } 1932 1933 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1934 { 1935 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1936 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1937 } 1938 1939 /* Return name of 32-bit register, from a R_* constant */ 1940 static const char *get_register_name_32(unsigned int reg) 1941 { 1942 if (reg >= CPU_NB_REGS32) { 1943 return NULL; 1944 } 1945 return x86_reg_info_32[reg].name; 1946 } 1947 1948 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1949 { 1950 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1951 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1952 } 1953 1954 /* 1955 * Returns the set of feature flags that are supported and migratable by 1956 * QEMU, for a given FeatureWord. 1957 */ 1958 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1959 { 1960 FeatureWordInfo *wi = &feature_word_info[w]; 1961 CPUX86State *env = &cpu->env; 1962 uint64_t r = 0; 1963 int i; 1964 1965 for (i = 0; i < 64; i++) { 1966 uint64_t f = 1ULL << i; 1967 1968 /* If the feature name is known, it is implicitly considered migratable, 1969 * unless it is explicitly set in unmigratable_flags */ 1970 if ((wi->migratable_flags & f) || 1971 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1972 r |= f; 1973 } 1974 } 1975 1976 /* when tsc-khz is set explicitly, invtsc is migratable */ 1977 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1978 r |= CPUID_APM_INVTSC; 1979 } 1980 1981 return r; 1982 } 1983 1984 void host_cpuid(uint32_t function, uint32_t count, 1985 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1986 { 1987 uint32_t vec[4]; 1988 1989 #ifdef __x86_64__ 1990 asm volatile("cpuid" 1991 : "=a"(vec[0]), "=b"(vec[1]), 1992 "=c"(vec[2]), "=d"(vec[3]) 1993 : "0"(function), "c"(count) : "cc"); 1994 #elif defined(__i386__) 1995 asm volatile("pusha \n\t" 1996 "cpuid \n\t" 1997 "mov %%eax, 0(%2) \n\t" 1998 "mov %%ebx, 4(%2) \n\t" 1999 "mov %%ecx, 8(%2) \n\t" 2000 "mov %%edx, 12(%2) \n\t" 2001 "popa" 2002 : : "a"(function), "c"(count), "S"(vec) 2003 : "memory", "cc"); 2004 #else 2005 abort(); 2006 #endif 2007 2008 if (eax) 2009 *eax = vec[0]; 2010 if (ebx) 2011 *ebx = vec[1]; 2012 if (ecx) 2013 *ecx = vec[2]; 2014 if (edx) 2015 *edx = vec[3]; 2016 } 2017 2018 /* CPU class name definitions: */ 2019 2020 /* Return type name for a given CPU model name 2021 * Caller is responsible for freeing the returned string. 2022 */ 2023 static char *x86_cpu_type_name(const char *model_name) 2024 { 2025 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 2026 } 2027 2028 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2029 { 2030 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2031 return object_class_by_name(typename); 2032 } 2033 2034 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2035 { 2036 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2037 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2038 return cpu_model_from_type(class_name); 2039 } 2040 2041 typedef struct X86CPUVersionDefinition { 2042 X86CPUVersion version; 2043 const char *alias; 2044 const char *note; 2045 PropValue *props; 2046 const CPUCaches *const cache_info; 2047 } X86CPUVersionDefinition; 2048 2049 /* Base definition for a CPU model */ 2050 typedef struct X86CPUDefinition { 2051 const char *name; 2052 uint32_t level; 2053 uint32_t xlevel; 2054 /* vendor is zero-terminated, 12 character ASCII string */ 2055 char vendor[CPUID_VENDOR_SZ + 1]; 2056 int family; 2057 int model; 2058 int stepping; 2059 uint8_t avx10_version; 2060 FeatureWordArray features; 2061 const char *model_id; 2062 const CPUCaches *const cache_info; 2063 /* 2064 * Definitions for alternative versions of CPU model. 2065 * List is terminated by item with version == 0. 2066 * If NULL, version 1 will be registered automatically. 2067 */ 2068 const X86CPUVersionDefinition *versions; 2069 const char *deprecation_note; 2070 } X86CPUDefinition; 2071 2072 /* Reference to a specific CPU model version */ 2073 struct X86CPUModel { 2074 /* Base CPU definition */ 2075 const X86CPUDefinition *cpudef; 2076 /* CPU model version */ 2077 X86CPUVersion version; 2078 const char *note; 2079 /* 2080 * If true, this is an alias CPU model. 2081 * This matters only for "-cpu help" and query-cpu-definitions 2082 */ 2083 bool is_alias; 2084 }; 2085 2086 /* Get full model name for CPU version */ 2087 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2088 X86CPUVersion version) 2089 { 2090 assert(version > 0); 2091 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2092 } 2093 2094 static const X86CPUVersionDefinition * 2095 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2096 { 2097 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2098 static const X86CPUVersionDefinition default_version_list[] = { 2099 { 1 }, 2100 { /* end of list */ } 2101 }; 2102 2103 return def->versions ?: default_version_list; 2104 } 2105 2106 static const CPUCaches epyc_cache_info = { 2107 .l1d_cache = &(CPUCacheInfo) { 2108 .type = DATA_CACHE, 2109 .level = 1, 2110 .size = 32 * KiB, 2111 .line_size = 64, 2112 .associativity = 8, 2113 .partitions = 1, 2114 .sets = 64, 2115 .lines_per_tag = 1, 2116 .self_init = 1, 2117 .no_invd_sharing = true, 2118 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2119 }, 2120 .l1i_cache = &(CPUCacheInfo) { 2121 .type = INSTRUCTION_CACHE, 2122 .level = 1, 2123 .size = 64 * KiB, 2124 .line_size = 64, 2125 .associativity = 4, 2126 .partitions = 1, 2127 .sets = 256, 2128 .lines_per_tag = 1, 2129 .self_init = 1, 2130 .no_invd_sharing = true, 2131 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2132 }, 2133 .l2_cache = &(CPUCacheInfo) { 2134 .type = UNIFIED_CACHE, 2135 .level = 2, 2136 .size = 512 * KiB, 2137 .line_size = 64, 2138 .associativity = 8, 2139 .partitions = 1, 2140 .sets = 1024, 2141 .lines_per_tag = 1, 2142 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2143 }, 2144 .l3_cache = &(CPUCacheInfo) { 2145 .type = UNIFIED_CACHE, 2146 .level = 3, 2147 .size = 8 * MiB, 2148 .line_size = 64, 2149 .associativity = 16, 2150 .partitions = 1, 2151 .sets = 8192, 2152 .lines_per_tag = 1, 2153 .self_init = true, 2154 .inclusive = true, 2155 .complex_indexing = true, 2156 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2157 }, 2158 }; 2159 2160 static CPUCaches epyc_v4_cache_info = { 2161 .l1d_cache = &(CPUCacheInfo) { 2162 .type = DATA_CACHE, 2163 .level = 1, 2164 .size = 32 * KiB, 2165 .line_size = 64, 2166 .associativity = 8, 2167 .partitions = 1, 2168 .sets = 64, 2169 .lines_per_tag = 1, 2170 .self_init = 1, 2171 .no_invd_sharing = true, 2172 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2173 }, 2174 .l1i_cache = &(CPUCacheInfo) { 2175 .type = INSTRUCTION_CACHE, 2176 .level = 1, 2177 .size = 64 * KiB, 2178 .line_size = 64, 2179 .associativity = 4, 2180 .partitions = 1, 2181 .sets = 256, 2182 .lines_per_tag = 1, 2183 .self_init = 1, 2184 .no_invd_sharing = true, 2185 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2186 }, 2187 .l2_cache = &(CPUCacheInfo) { 2188 .type = UNIFIED_CACHE, 2189 .level = 2, 2190 .size = 512 * KiB, 2191 .line_size = 64, 2192 .associativity = 8, 2193 .partitions = 1, 2194 .sets = 1024, 2195 .lines_per_tag = 1, 2196 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2197 }, 2198 .l3_cache = &(CPUCacheInfo) { 2199 .type = UNIFIED_CACHE, 2200 .level = 3, 2201 .size = 8 * MiB, 2202 .line_size = 64, 2203 .associativity = 16, 2204 .partitions = 1, 2205 .sets = 8192, 2206 .lines_per_tag = 1, 2207 .self_init = true, 2208 .inclusive = true, 2209 .complex_indexing = false, 2210 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2211 }, 2212 }; 2213 2214 static const CPUCaches epyc_rome_cache_info = { 2215 .l1d_cache = &(CPUCacheInfo) { 2216 .type = DATA_CACHE, 2217 .level = 1, 2218 .size = 32 * KiB, 2219 .line_size = 64, 2220 .associativity = 8, 2221 .partitions = 1, 2222 .sets = 64, 2223 .lines_per_tag = 1, 2224 .self_init = 1, 2225 .no_invd_sharing = true, 2226 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2227 }, 2228 .l1i_cache = &(CPUCacheInfo) { 2229 .type = INSTRUCTION_CACHE, 2230 .level = 1, 2231 .size = 32 * KiB, 2232 .line_size = 64, 2233 .associativity = 8, 2234 .partitions = 1, 2235 .sets = 64, 2236 .lines_per_tag = 1, 2237 .self_init = 1, 2238 .no_invd_sharing = true, 2239 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2240 }, 2241 .l2_cache = &(CPUCacheInfo) { 2242 .type = UNIFIED_CACHE, 2243 .level = 2, 2244 .size = 512 * KiB, 2245 .line_size = 64, 2246 .associativity = 8, 2247 .partitions = 1, 2248 .sets = 1024, 2249 .lines_per_tag = 1, 2250 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2251 }, 2252 .l3_cache = &(CPUCacheInfo) { 2253 .type = UNIFIED_CACHE, 2254 .level = 3, 2255 .size = 16 * MiB, 2256 .line_size = 64, 2257 .associativity = 16, 2258 .partitions = 1, 2259 .sets = 16384, 2260 .lines_per_tag = 1, 2261 .self_init = true, 2262 .inclusive = true, 2263 .complex_indexing = true, 2264 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2265 }, 2266 }; 2267 2268 static const CPUCaches epyc_rome_v3_cache_info = { 2269 .l1d_cache = &(CPUCacheInfo) { 2270 .type = DATA_CACHE, 2271 .level = 1, 2272 .size = 32 * KiB, 2273 .line_size = 64, 2274 .associativity = 8, 2275 .partitions = 1, 2276 .sets = 64, 2277 .lines_per_tag = 1, 2278 .self_init = 1, 2279 .no_invd_sharing = true, 2280 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2281 }, 2282 .l1i_cache = &(CPUCacheInfo) { 2283 .type = INSTRUCTION_CACHE, 2284 .level = 1, 2285 .size = 32 * KiB, 2286 .line_size = 64, 2287 .associativity = 8, 2288 .partitions = 1, 2289 .sets = 64, 2290 .lines_per_tag = 1, 2291 .self_init = 1, 2292 .no_invd_sharing = true, 2293 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2294 }, 2295 .l2_cache = &(CPUCacheInfo) { 2296 .type = UNIFIED_CACHE, 2297 .level = 2, 2298 .size = 512 * KiB, 2299 .line_size = 64, 2300 .associativity = 8, 2301 .partitions = 1, 2302 .sets = 1024, 2303 .lines_per_tag = 1, 2304 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2305 }, 2306 .l3_cache = &(CPUCacheInfo) { 2307 .type = UNIFIED_CACHE, 2308 .level = 3, 2309 .size = 16 * MiB, 2310 .line_size = 64, 2311 .associativity = 16, 2312 .partitions = 1, 2313 .sets = 16384, 2314 .lines_per_tag = 1, 2315 .self_init = true, 2316 .inclusive = true, 2317 .complex_indexing = false, 2318 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2319 }, 2320 }; 2321 2322 static const CPUCaches epyc_milan_cache_info = { 2323 .l1d_cache = &(CPUCacheInfo) { 2324 .type = DATA_CACHE, 2325 .level = 1, 2326 .size = 32 * KiB, 2327 .line_size = 64, 2328 .associativity = 8, 2329 .partitions = 1, 2330 .sets = 64, 2331 .lines_per_tag = 1, 2332 .self_init = 1, 2333 .no_invd_sharing = true, 2334 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2335 }, 2336 .l1i_cache = &(CPUCacheInfo) { 2337 .type = INSTRUCTION_CACHE, 2338 .level = 1, 2339 .size = 32 * KiB, 2340 .line_size = 64, 2341 .associativity = 8, 2342 .partitions = 1, 2343 .sets = 64, 2344 .lines_per_tag = 1, 2345 .self_init = 1, 2346 .no_invd_sharing = true, 2347 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2348 }, 2349 .l2_cache = &(CPUCacheInfo) { 2350 .type = UNIFIED_CACHE, 2351 .level = 2, 2352 .size = 512 * KiB, 2353 .line_size = 64, 2354 .associativity = 8, 2355 .partitions = 1, 2356 .sets = 1024, 2357 .lines_per_tag = 1, 2358 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2359 }, 2360 .l3_cache = &(CPUCacheInfo) { 2361 .type = UNIFIED_CACHE, 2362 .level = 3, 2363 .size = 32 * MiB, 2364 .line_size = 64, 2365 .associativity = 16, 2366 .partitions = 1, 2367 .sets = 32768, 2368 .lines_per_tag = 1, 2369 .self_init = true, 2370 .inclusive = true, 2371 .complex_indexing = true, 2372 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2373 }, 2374 }; 2375 2376 static const CPUCaches epyc_milan_v2_cache_info = { 2377 .l1d_cache = &(CPUCacheInfo) { 2378 .type = DATA_CACHE, 2379 .level = 1, 2380 .size = 32 * KiB, 2381 .line_size = 64, 2382 .associativity = 8, 2383 .partitions = 1, 2384 .sets = 64, 2385 .lines_per_tag = 1, 2386 .self_init = 1, 2387 .no_invd_sharing = true, 2388 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2389 }, 2390 .l1i_cache = &(CPUCacheInfo) { 2391 .type = INSTRUCTION_CACHE, 2392 .level = 1, 2393 .size = 32 * KiB, 2394 .line_size = 64, 2395 .associativity = 8, 2396 .partitions = 1, 2397 .sets = 64, 2398 .lines_per_tag = 1, 2399 .self_init = 1, 2400 .no_invd_sharing = true, 2401 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2402 }, 2403 .l2_cache = &(CPUCacheInfo) { 2404 .type = UNIFIED_CACHE, 2405 .level = 2, 2406 .size = 512 * KiB, 2407 .line_size = 64, 2408 .associativity = 8, 2409 .partitions = 1, 2410 .sets = 1024, 2411 .lines_per_tag = 1, 2412 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2413 }, 2414 .l3_cache = &(CPUCacheInfo) { 2415 .type = UNIFIED_CACHE, 2416 .level = 3, 2417 .size = 32 * MiB, 2418 .line_size = 64, 2419 .associativity = 16, 2420 .partitions = 1, 2421 .sets = 32768, 2422 .lines_per_tag = 1, 2423 .self_init = true, 2424 .inclusive = true, 2425 .complex_indexing = false, 2426 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2427 }, 2428 }; 2429 2430 static const CPUCaches epyc_genoa_cache_info = { 2431 .l1d_cache = &(CPUCacheInfo) { 2432 .type = DATA_CACHE, 2433 .level = 1, 2434 .size = 32 * KiB, 2435 .line_size = 64, 2436 .associativity = 8, 2437 .partitions = 1, 2438 .sets = 64, 2439 .lines_per_tag = 1, 2440 .self_init = 1, 2441 .no_invd_sharing = true, 2442 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2443 }, 2444 .l1i_cache = &(CPUCacheInfo) { 2445 .type = INSTRUCTION_CACHE, 2446 .level = 1, 2447 .size = 32 * KiB, 2448 .line_size = 64, 2449 .associativity = 8, 2450 .partitions = 1, 2451 .sets = 64, 2452 .lines_per_tag = 1, 2453 .self_init = 1, 2454 .no_invd_sharing = true, 2455 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2456 }, 2457 .l2_cache = &(CPUCacheInfo) { 2458 .type = UNIFIED_CACHE, 2459 .level = 2, 2460 .size = 1 * MiB, 2461 .line_size = 64, 2462 .associativity = 8, 2463 .partitions = 1, 2464 .sets = 2048, 2465 .lines_per_tag = 1, 2466 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2467 }, 2468 .l3_cache = &(CPUCacheInfo) { 2469 .type = UNIFIED_CACHE, 2470 .level = 3, 2471 .size = 32 * MiB, 2472 .line_size = 64, 2473 .associativity = 16, 2474 .partitions = 1, 2475 .sets = 32768, 2476 .lines_per_tag = 1, 2477 .self_init = true, 2478 .inclusive = true, 2479 .complex_indexing = false, 2480 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2481 }, 2482 }; 2483 2484 /* The following VMX features are not supported by KVM and are left out in the 2485 * CPU definitions: 2486 * 2487 * Dual-monitor support (all processors) 2488 * Entry to SMM 2489 * Deactivate dual-monitor treatment 2490 * Number of CR3-target values 2491 * Shutdown activity state 2492 * Wait-for-SIPI activity state 2493 * PAUSE-loop exiting (Westmere and newer) 2494 * EPT-violation #VE (Broadwell and newer) 2495 * Inject event with insn length=0 (Skylake and newer) 2496 * Conceal non-root operation from PT 2497 * Conceal VM exits from PT 2498 * Conceal VM entries from PT 2499 * Enable ENCLS exiting 2500 * Mode-based execute control (XS/XU) 2501 * TSC scaling (Skylake Server and newer) 2502 * GPA translation for PT (IceLake and newer) 2503 * User wait and pause 2504 * ENCLV exiting 2505 * Load IA32_RTIT_CTL 2506 * Clear IA32_RTIT_CTL 2507 * Advanced VM-exit information for EPT violations 2508 * Sub-page write permissions 2509 * PT in VMX operation 2510 */ 2511 2512 static const X86CPUDefinition builtin_x86_defs[] = { 2513 { 2514 .name = "qemu64", 2515 .level = 0xd, 2516 .vendor = CPUID_VENDOR_AMD, 2517 .family = 15, 2518 .model = 107, 2519 .stepping = 1, 2520 .features[FEAT_1_EDX] = 2521 PPRO_FEATURES | 2522 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2523 CPUID_PSE36, 2524 .features[FEAT_1_ECX] = 2525 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2526 .features[FEAT_8000_0001_EDX] = 2527 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2528 .features[FEAT_8000_0001_ECX] = 2529 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2530 .xlevel = 0x8000000A, 2531 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2532 }, 2533 { 2534 .name = "phenom", 2535 .level = 5, 2536 .vendor = CPUID_VENDOR_AMD, 2537 .family = 16, 2538 .model = 2, 2539 .stepping = 3, 2540 /* Missing: CPUID_HT */ 2541 .features[FEAT_1_EDX] = 2542 PPRO_FEATURES | 2543 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2544 CPUID_PSE36 | CPUID_VME, 2545 .features[FEAT_1_ECX] = 2546 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2547 CPUID_EXT_POPCNT, 2548 .features[FEAT_8000_0001_EDX] = 2549 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2550 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2551 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2552 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2553 CPUID_EXT3_CR8LEG, 2554 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2555 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2556 .features[FEAT_8000_0001_ECX] = 2557 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2558 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2559 /* Missing: CPUID_SVM_LBRV */ 2560 .features[FEAT_SVM] = 2561 CPUID_SVM_NPT, 2562 .xlevel = 0x8000001A, 2563 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2564 }, 2565 { 2566 .name = "core2duo", 2567 .level = 10, 2568 .vendor = CPUID_VENDOR_INTEL, 2569 .family = 6, 2570 .model = 15, 2571 .stepping = 11, 2572 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2573 .features[FEAT_1_EDX] = 2574 PPRO_FEATURES | 2575 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2576 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2577 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2578 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2579 .features[FEAT_1_ECX] = 2580 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2581 CPUID_EXT_CX16, 2582 .features[FEAT_8000_0001_EDX] = 2583 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2584 .features[FEAT_8000_0001_ECX] = 2585 CPUID_EXT3_LAHF_LM, 2586 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2587 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2588 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2589 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2590 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2591 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2592 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2593 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2594 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2595 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2596 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2597 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2598 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2599 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2600 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2601 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2602 .features[FEAT_VMX_SECONDARY_CTLS] = 2603 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2604 .xlevel = 0x80000008, 2605 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2606 }, 2607 { 2608 .name = "kvm64", 2609 .level = 0xd, 2610 .vendor = CPUID_VENDOR_INTEL, 2611 .family = 15, 2612 .model = 6, 2613 .stepping = 1, 2614 /* Missing: CPUID_HT */ 2615 .features[FEAT_1_EDX] = 2616 PPRO_FEATURES | CPUID_VME | 2617 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2618 CPUID_PSE36, 2619 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2620 .features[FEAT_1_ECX] = 2621 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2622 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2623 .features[FEAT_8000_0001_EDX] = 2624 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2625 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2626 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2627 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2628 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2629 .features[FEAT_8000_0001_ECX] = 2630 0, 2631 /* VMX features from Cedar Mill/Prescott */ 2632 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2633 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2634 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2635 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2636 VMX_PIN_BASED_NMI_EXITING, 2637 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2638 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2639 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2640 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2641 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2642 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2643 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2644 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2645 .xlevel = 0x80000008, 2646 .model_id = "Common KVM processor" 2647 }, 2648 { 2649 .name = "qemu32", 2650 .level = 4, 2651 .vendor = CPUID_VENDOR_INTEL, 2652 .family = 6, 2653 .model = 6, 2654 .stepping = 3, 2655 .features[FEAT_1_EDX] = 2656 PPRO_FEATURES, 2657 .features[FEAT_1_ECX] = 2658 CPUID_EXT_SSE3, 2659 .xlevel = 0x80000004, 2660 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2661 }, 2662 { 2663 .name = "kvm32", 2664 .level = 5, 2665 .vendor = CPUID_VENDOR_INTEL, 2666 .family = 15, 2667 .model = 6, 2668 .stepping = 1, 2669 .features[FEAT_1_EDX] = 2670 PPRO_FEATURES | CPUID_VME | 2671 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2672 .features[FEAT_1_ECX] = 2673 CPUID_EXT_SSE3, 2674 .features[FEAT_8000_0001_ECX] = 2675 0, 2676 /* VMX features from Yonah */ 2677 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2678 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2679 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2680 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2681 VMX_PIN_BASED_NMI_EXITING, 2682 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2683 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2684 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2685 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2686 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2687 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2688 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2689 .xlevel = 0x80000008, 2690 .model_id = "Common 32-bit KVM processor" 2691 }, 2692 { 2693 .name = "coreduo", 2694 .level = 10, 2695 .vendor = CPUID_VENDOR_INTEL, 2696 .family = 6, 2697 .model = 14, 2698 .stepping = 8, 2699 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2700 .features[FEAT_1_EDX] = 2701 PPRO_FEATURES | CPUID_VME | 2702 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2703 CPUID_SS, 2704 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2705 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2706 .features[FEAT_1_ECX] = 2707 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2708 .features[FEAT_8000_0001_EDX] = 2709 CPUID_EXT2_NX, 2710 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2711 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2712 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2713 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2714 VMX_PIN_BASED_NMI_EXITING, 2715 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2716 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2717 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2718 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2719 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2720 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2721 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2722 .xlevel = 0x80000008, 2723 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2724 }, 2725 { 2726 .name = "486", 2727 .level = 1, 2728 .vendor = CPUID_VENDOR_INTEL, 2729 .family = 4, 2730 .model = 8, 2731 .stepping = 0, 2732 .features[FEAT_1_EDX] = 2733 I486_FEATURES, 2734 .xlevel = 0, 2735 .model_id = "", 2736 }, 2737 { 2738 .name = "pentium", 2739 .level = 1, 2740 .vendor = CPUID_VENDOR_INTEL, 2741 .family = 5, 2742 .model = 4, 2743 .stepping = 3, 2744 .features[FEAT_1_EDX] = 2745 PENTIUM_FEATURES, 2746 .xlevel = 0, 2747 .model_id = "", 2748 }, 2749 { 2750 .name = "pentium2", 2751 .level = 2, 2752 .vendor = CPUID_VENDOR_INTEL, 2753 .family = 6, 2754 .model = 5, 2755 .stepping = 2, 2756 .features[FEAT_1_EDX] = 2757 PENTIUM2_FEATURES, 2758 .xlevel = 0, 2759 .model_id = "", 2760 }, 2761 { 2762 .name = "pentium3", 2763 .level = 3, 2764 .vendor = CPUID_VENDOR_INTEL, 2765 .family = 6, 2766 .model = 7, 2767 .stepping = 3, 2768 .features[FEAT_1_EDX] = 2769 PENTIUM3_FEATURES, 2770 .xlevel = 0, 2771 .model_id = "", 2772 }, 2773 { 2774 .name = "athlon", 2775 .level = 2, 2776 .vendor = CPUID_VENDOR_AMD, 2777 .family = 6, 2778 .model = 2, 2779 .stepping = 3, 2780 .features[FEAT_1_EDX] = 2781 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2782 CPUID_MCA, 2783 .features[FEAT_8000_0001_EDX] = 2784 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2785 .xlevel = 0x80000008, 2786 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2787 }, 2788 { 2789 .name = "n270", 2790 .level = 10, 2791 .vendor = CPUID_VENDOR_INTEL, 2792 .family = 6, 2793 .model = 28, 2794 .stepping = 2, 2795 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2796 .features[FEAT_1_EDX] = 2797 PPRO_FEATURES | 2798 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2799 CPUID_ACPI | CPUID_SS, 2800 /* Some CPUs got no CPUID_SEP */ 2801 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2802 * CPUID_EXT_XTPR */ 2803 .features[FEAT_1_ECX] = 2804 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2805 CPUID_EXT_MOVBE, 2806 .features[FEAT_8000_0001_EDX] = 2807 CPUID_EXT2_NX, 2808 .features[FEAT_8000_0001_ECX] = 2809 CPUID_EXT3_LAHF_LM, 2810 .xlevel = 0x80000008, 2811 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2812 }, 2813 { 2814 .name = "Conroe", 2815 .level = 10, 2816 .vendor = CPUID_VENDOR_INTEL, 2817 .family = 6, 2818 .model = 15, 2819 .stepping = 3, 2820 .features[FEAT_1_EDX] = 2821 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2822 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2823 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2824 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2825 CPUID_DE | CPUID_FP87, 2826 .features[FEAT_1_ECX] = 2827 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2828 .features[FEAT_8000_0001_EDX] = 2829 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2830 .features[FEAT_8000_0001_ECX] = 2831 CPUID_EXT3_LAHF_LM, 2832 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2833 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2834 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2835 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2836 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2837 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2838 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2839 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2840 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2841 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2842 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2843 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2844 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2845 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2846 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2847 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2848 .features[FEAT_VMX_SECONDARY_CTLS] = 2849 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2850 .xlevel = 0x80000008, 2851 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2852 }, 2853 { 2854 .name = "Penryn", 2855 .level = 10, 2856 .vendor = CPUID_VENDOR_INTEL, 2857 .family = 6, 2858 .model = 23, 2859 .stepping = 3, 2860 .features[FEAT_1_EDX] = 2861 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2862 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2863 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2864 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2865 CPUID_DE | CPUID_FP87, 2866 .features[FEAT_1_ECX] = 2867 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2868 CPUID_EXT_SSE3, 2869 .features[FEAT_8000_0001_EDX] = 2870 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2871 .features[FEAT_8000_0001_ECX] = 2872 CPUID_EXT3_LAHF_LM, 2873 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2874 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2875 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2876 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2877 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2878 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2879 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2880 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2881 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2882 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2883 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2884 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2885 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2886 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2887 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2888 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2889 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2890 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2891 .features[FEAT_VMX_SECONDARY_CTLS] = 2892 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2893 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2894 .xlevel = 0x80000008, 2895 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2896 }, 2897 { 2898 .name = "Nehalem", 2899 .level = 11, 2900 .vendor = CPUID_VENDOR_INTEL, 2901 .family = 6, 2902 .model = 26, 2903 .stepping = 3, 2904 .features[FEAT_1_EDX] = 2905 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2906 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2907 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2908 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2909 CPUID_DE | CPUID_FP87, 2910 .features[FEAT_1_ECX] = 2911 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2912 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2913 .features[FEAT_8000_0001_EDX] = 2914 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2915 .features[FEAT_8000_0001_ECX] = 2916 CPUID_EXT3_LAHF_LM, 2917 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2918 MSR_VMX_BASIC_TRUE_CTLS, 2919 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2920 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2921 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2922 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2923 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2924 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2925 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2926 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2927 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2928 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2929 .features[FEAT_VMX_EXIT_CTLS] = 2930 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2931 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2932 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2933 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2934 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2935 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2936 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2937 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2938 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2939 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2940 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2941 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2942 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2943 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2944 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2945 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2946 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2947 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2948 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2949 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2950 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2951 .features[FEAT_VMX_SECONDARY_CTLS] = 2952 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2953 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2954 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2955 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2956 VMX_SECONDARY_EXEC_ENABLE_VPID, 2957 .xlevel = 0x80000008, 2958 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2959 .versions = (X86CPUVersionDefinition[]) { 2960 { .version = 1 }, 2961 { 2962 .version = 2, 2963 .alias = "Nehalem-IBRS", 2964 .props = (PropValue[]) { 2965 { "spec-ctrl", "on" }, 2966 { "model-id", 2967 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2968 { /* end of list */ } 2969 } 2970 }, 2971 { /* end of list */ } 2972 } 2973 }, 2974 { 2975 .name = "Westmere", 2976 .level = 11, 2977 .vendor = CPUID_VENDOR_INTEL, 2978 .family = 6, 2979 .model = 44, 2980 .stepping = 1, 2981 .features[FEAT_1_EDX] = 2982 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2983 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2984 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2985 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2986 CPUID_DE | CPUID_FP87, 2987 .features[FEAT_1_ECX] = 2988 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2989 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2990 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2991 .features[FEAT_8000_0001_EDX] = 2992 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2993 .features[FEAT_8000_0001_ECX] = 2994 CPUID_EXT3_LAHF_LM, 2995 .features[FEAT_6_EAX] = 2996 CPUID_6_EAX_ARAT, 2997 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2998 MSR_VMX_BASIC_TRUE_CTLS, 2999 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3000 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3001 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3002 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3003 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3004 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3005 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3006 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3007 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3008 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3009 .features[FEAT_VMX_EXIT_CTLS] = 3010 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3011 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3012 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3013 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3014 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3015 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3016 MSR_VMX_MISC_STORE_LMA, 3017 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3018 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3019 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3020 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3021 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3022 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3023 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3024 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3025 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3026 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3027 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3028 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3029 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3030 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3031 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3032 .features[FEAT_VMX_SECONDARY_CTLS] = 3033 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3034 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3035 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3036 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3037 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3038 .xlevel = 0x80000008, 3039 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3040 .versions = (X86CPUVersionDefinition[]) { 3041 { .version = 1 }, 3042 { 3043 .version = 2, 3044 .alias = "Westmere-IBRS", 3045 .props = (PropValue[]) { 3046 { "spec-ctrl", "on" }, 3047 { "model-id", 3048 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3049 { /* end of list */ } 3050 } 3051 }, 3052 { /* end of list */ } 3053 } 3054 }, 3055 { 3056 .name = "SandyBridge", 3057 .level = 0xd, 3058 .vendor = CPUID_VENDOR_INTEL, 3059 .family = 6, 3060 .model = 42, 3061 .stepping = 1, 3062 .features[FEAT_1_EDX] = 3063 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3064 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3065 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3066 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3067 CPUID_DE | CPUID_FP87, 3068 .features[FEAT_1_ECX] = 3069 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3070 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3071 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3072 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3073 CPUID_EXT_SSE3, 3074 .features[FEAT_8000_0001_EDX] = 3075 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3076 CPUID_EXT2_SYSCALL, 3077 .features[FEAT_8000_0001_ECX] = 3078 CPUID_EXT3_LAHF_LM, 3079 .features[FEAT_XSAVE] = 3080 CPUID_XSAVE_XSAVEOPT, 3081 .features[FEAT_6_EAX] = 3082 CPUID_6_EAX_ARAT, 3083 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3084 MSR_VMX_BASIC_TRUE_CTLS, 3085 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3086 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3087 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3088 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3089 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3090 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3091 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3092 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3093 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3094 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3095 .features[FEAT_VMX_EXIT_CTLS] = 3096 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3097 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3098 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3099 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3100 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3101 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3102 MSR_VMX_MISC_STORE_LMA, 3103 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3104 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3105 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3106 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3107 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3108 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3109 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3110 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3111 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3112 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3113 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3114 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3115 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3116 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3117 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3118 .features[FEAT_VMX_SECONDARY_CTLS] = 3119 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3120 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3121 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3122 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3123 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3124 .xlevel = 0x80000008, 3125 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3126 .versions = (X86CPUVersionDefinition[]) { 3127 { .version = 1 }, 3128 { 3129 .version = 2, 3130 .alias = "SandyBridge-IBRS", 3131 .props = (PropValue[]) { 3132 { "spec-ctrl", "on" }, 3133 { "model-id", 3134 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3135 { /* end of list */ } 3136 } 3137 }, 3138 { /* end of list */ } 3139 } 3140 }, 3141 { 3142 .name = "IvyBridge", 3143 .level = 0xd, 3144 .vendor = CPUID_VENDOR_INTEL, 3145 .family = 6, 3146 .model = 58, 3147 .stepping = 9, 3148 .features[FEAT_1_EDX] = 3149 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3150 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3151 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3152 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3153 CPUID_DE | CPUID_FP87, 3154 .features[FEAT_1_ECX] = 3155 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3156 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3157 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3158 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3159 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3160 .features[FEAT_7_0_EBX] = 3161 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3162 CPUID_7_0_EBX_ERMS, 3163 .features[FEAT_8000_0001_EDX] = 3164 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3165 CPUID_EXT2_SYSCALL, 3166 .features[FEAT_8000_0001_ECX] = 3167 CPUID_EXT3_LAHF_LM, 3168 .features[FEAT_XSAVE] = 3169 CPUID_XSAVE_XSAVEOPT, 3170 .features[FEAT_6_EAX] = 3171 CPUID_6_EAX_ARAT, 3172 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3173 MSR_VMX_BASIC_TRUE_CTLS, 3174 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3175 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3176 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3177 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3178 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3179 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3180 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3181 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3182 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3183 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3184 .features[FEAT_VMX_EXIT_CTLS] = 3185 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3186 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3187 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3188 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3189 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3190 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3191 MSR_VMX_MISC_STORE_LMA, 3192 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3193 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3194 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3195 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3196 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3197 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3198 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3199 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3200 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3201 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3202 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3203 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3204 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3205 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3206 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3207 .features[FEAT_VMX_SECONDARY_CTLS] = 3208 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3209 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3210 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3211 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3212 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3213 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3214 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3215 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3216 .xlevel = 0x80000008, 3217 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3218 .versions = (X86CPUVersionDefinition[]) { 3219 { .version = 1 }, 3220 { 3221 .version = 2, 3222 .alias = "IvyBridge-IBRS", 3223 .props = (PropValue[]) { 3224 { "spec-ctrl", "on" }, 3225 { "model-id", 3226 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3227 { /* end of list */ } 3228 } 3229 }, 3230 { /* end of list */ } 3231 } 3232 }, 3233 { 3234 .name = "Haswell", 3235 .level = 0xd, 3236 .vendor = CPUID_VENDOR_INTEL, 3237 .family = 6, 3238 .model = 60, 3239 .stepping = 4, 3240 .features[FEAT_1_EDX] = 3241 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3242 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3243 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3244 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3245 CPUID_DE | CPUID_FP87, 3246 .features[FEAT_1_ECX] = 3247 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3248 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3249 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3250 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3251 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3252 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3253 .features[FEAT_8000_0001_EDX] = 3254 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3255 CPUID_EXT2_SYSCALL, 3256 .features[FEAT_8000_0001_ECX] = 3257 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3258 .features[FEAT_7_0_EBX] = 3259 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3260 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3261 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3262 CPUID_7_0_EBX_RTM, 3263 .features[FEAT_XSAVE] = 3264 CPUID_XSAVE_XSAVEOPT, 3265 .features[FEAT_6_EAX] = 3266 CPUID_6_EAX_ARAT, 3267 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3268 MSR_VMX_BASIC_TRUE_CTLS, 3269 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3270 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3271 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3272 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3273 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3274 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3275 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3276 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3277 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3278 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3279 .features[FEAT_VMX_EXIT_CTLS] = 3280 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3281 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3282 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3283 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3284 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3285 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3286 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3287 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3288 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3289 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3290 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3291 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3292 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3293 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3294 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3295 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3296 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3297 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3298 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3299 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3300 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3301 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3302 .features[FEAT_VMX_SECONDARY_CTLS] = 3303 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3304 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3305 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3306 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3307 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3308 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3309 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3310 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3311 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3312 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3313 .xlevel = 0x80000008, 3314 .model_id = "Intel Core Processor (Haswell)", 3315 .versions = (X86CPUVersionDefinition[]) { 3316 { .version = 1 }, 3317 { 3318 .version = 2, 3319 .alias = "Haswell-noTSX", 3320 .props = (PropValue[]) { 3321 { "hle", "off" }, 3322 { "rtm", "off" }, 3323 { "stepping", "1" }, 3324 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3325 { /* end of list */ } 3326 }, 3327 }, 3328 { 3329 .version = 3, 3330 .alias = "Haswell-IBRS", 3331 .props = (PropValue[]) { 3332 /* Restore TSX features removed by -v2 above */ 3333 { "hle", "on" }, 3334 { "rtm", "on" }, 3335 /* 3336 * Haswell and Haswell-IBRS had stepping=4 in 3337 * QEMU 4.0 and older 3338 */ 3339 { "stepping", "4" }, 3340 { "spec-ctrl", "on" }, 3341 { "model-id", 3342 "Intel Core Processor (Haswell, IBRS)" }, 3343 { /* end of list */ } 3344 } 3345 }, 3346 { 3347 .version = 4, 3348 .alias = "Haswell-noTSX-IBRS", 3349 .props = (PropValue[]) { 3350 { "hle", "off" }, 3351 { "rtm", "off" }, 3352 /* spec-ctrl was already enabled by -v3 above */ 3353 { "stepping", "1" }, 3354 { "model-id", 3355 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3356 { /* end of list */ } 3357 } 3358 }, 3359 { /* end of list */ } 3360 } 3361 }, 3362 { 3363 .name = "Broadwell", 3364 .level = 0xd, 3365 .vendor = CPUID_VENDOR_INTEL, 3366 .family = 6, 3367 .model = 61, 3368 .stepping = 2, 3369 .features[FEAT_1_EDX] = 3370 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3371 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3372 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3373 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3374 CPUID_DE | CPUID_FP87, 3375 .features[FEAT_1_ECX] = 3376 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3377 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3378 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3379 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3380 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3381 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3382 .features[FEAT_8000_0001_EDX] = 3383 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3384 CPUID_EXT2_SYSCALL, 3385 .features[FEAT_8000_0001_ECX] = 3386 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3387 .features[FEAT_7_0_EBX] = 3388 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3389 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3390 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3391 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3392 CPUID_7_0_EBX_SMAP, 3393 .features[FEAT_XSAVE] = 3394 CPUID_XSAVE_XSAVEOPT, 3395 .features[FEAT_6_EAX] = 3396 CPUID_6_EAX_ARAT, 3397 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3398 MSR_VMX_BASIC_TRUE_CTLS, 3399 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3400 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3401 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3402 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3403 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3404 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3405 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3406 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3407 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3408 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3409 .features[FEAT_VMX_EXIT_CTLS] = 3410 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3411 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3412 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3413 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3414 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3415 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3416 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3417 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3418 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3419 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3420 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3421 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3422 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3423 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3424 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3425 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3426 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3427 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3428 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3429 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3430 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3431 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3432 .features[FEAT_VMX_SECONDARY_CTLS] = 3433 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3434 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3435 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3436 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3437 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3438 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3439 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3440 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3441 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3442 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3443 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3444 .xlevel = 0x80000008, 3445 .model_id = "Intel Core Processor (Broadwell)", 3446 .versions = (X86CPUVersionDefinition[]) { 3447 { .version = 1 }, 3448 { 3449 .version = 2, 3450 .alias = "Broadwell-noTSX", 3451 .props = (PropValue[]) { 3452 { "hle", "off" }, 3453 { "rtm", "off" }, 3454 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3455 { /* end of list */ } 3456 }, 3457 }, 3458 { 3459 .version = 3, 3460 .alias = "Broadwell-IBRS", 3461 .props = (PropValue[]) { 3462 /* Restore TSX features removed by -v2 above */ 3463 { "hle", "on" }, 3464 { "rtm", "on" }, 3465 { "spec-ctrl", "on" }, 3466 { "model-id", 3467 "Intel Core Processor (Broadwell, IBRS)" }, 3468 { /* end of list */ } 3469 } 3470 }, 3471 { 3472 .version = 4, 3473 .alias = "Broadwell-noTSX-IBRS", 3474 .props = (PropValue[]) { 3475 { "hle", "off" }, 3476 { "rtm", "off" }, 3477 /* spec-ctrl was already enabled by -v3 above */ 3478 { "model-id", 3479 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3480 { /* end of list */ } 3481 } 3482 }, 3483 { /* end of list */ } 3484 } 3485 }, 3486 { 3487 .name = "Skylake-Client", 3488 .level = 0xd, 3489 .vendor = CPUID_VENDOR_INTEL, 3490 .family = 6, 3491 .model = 94, 3492 .stepping = 3, 3493 .features[FEAT_1_EDX] = 3494 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3495 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3496 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3497 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3498 CPUID_DE | CPUID_FP87, 3499 .features[FEAT_1_ECX] = 3500 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3501 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3502 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3503 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3504 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3505 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3506 .features[FEAT_8000_0001_EDX] = 3507 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3508 CPUID_EXT2_SYSCALL, 3509 .features[FEAT_8000_0001_ECX] = 3510 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3511 .features[FEAT_7_0_EBX] = 3512 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3513 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3514 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3515 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3516 CPUID_7_0_EBX_SMAP, 3517 /* XSAVES is added in version 4 */ 3518 .features[FEAT_XSAVE] = 3519 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3520 CPUID_XSAVE_XGETBV1, 3521 .features[FEAT_6_EAX] = 3522 CPUID_6_EAX_ARAT, 3523 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3524 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3525 MSR_VMX_BASIC_TRUE_CTLS, 3526 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3527 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3528 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3529 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3530 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3531 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3532 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3533 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3534 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3535 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3536 .features[FEAT_VMX_EXIT_CTLS] = 3537 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3538 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3539 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3540 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3541 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3542 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3543 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3544 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3545 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3546 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3547 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3548 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3549 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3550 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3551 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3552 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3553 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3554 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3555 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3556 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3557 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3558 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3559 .features[FEAT_VMX_SECONDARY_CTLS] = 3560 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3561 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3562 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3563 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3564 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3565 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3566 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3567 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3568 .xlevel = 0x80000008, 3569 .model_id = "Intel Core Processor (Skylake)", 3570 .versions = (X86CPUVersionDefinition[]) { 3571 { .version = 1 }, 3572 { 3573 .version = 2, 3574 .alias = "Skylake-Client-IBRS", 3575 .props = (PropValue[]) { 3576 { "spec-ctrl", "on" }, 3577 { "model-id", 3578 "Intel Core Processor (Skylake, IBRS)" }, 3579 { /* end of list */ } 3580 } 3581 }, 3582 { 3583 .version = 3, 3584 .alias = "Skylake-Client-noTSX-IBRS", 3585 .props = (PropValue[]) { 3586 { "hle", "off" }, 3587 { "rtm", "off" }, 3588 { "model-id", 3589 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3590 { /* end of list */ } 3591 } 3592 }, 3593 { 3594 .version = 4, 3595 .note = "IBRS, XSAVES, no TSX", 3596 .props = (PropValue[]) { 3597 { "xsaves", "on" }, 3598 { "vmx-xsaves", "on" }, 3599 { /* end of list */ } 3600 } 3601 }, 3602 { /* end of list */ } 3603 } 3604 }, 3605 { 3606 .name = "Skylake-Server", 3607 .level = 0xd, 3608 .vendor = CPUID_VENDOR_INTEL, 3609 .family = 6, 3610 .model = 85, 3611 .stepping = 4, 3612 .features[FEAT_1_EDX] = 3613 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3614 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3615 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3616 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3617 CPUID_DE | CPUID_FP87, 3618 .features[FEAT_1_ECX] = 3619 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3620 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3621 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3622 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3623 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3624 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3625 .features[FEAT_8000_0001_EDX] = 3626 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3627 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3628 .features[FEAT_8000_0001_ECX] = 3629 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3630 .features[FEAT_7_0_EBX] = 3631 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3632 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3633 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3634 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3635 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3636 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3637 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3638 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3639 .features[FEAT_7_0_ECX] = 3640 CPUID_7_0_ECX_PKU, 3641 /* XSAVES is added in version 5 */ 3642 .features[FEAT_XSAVE] = 3643 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3644 CPUID_XSAVE_XGETBV1, 3645 .features[FEAT_6_EAX] = 3646 CPUID_6_EAX_ARAT, 3647 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3648 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3649 MSR_VMX_BASIC_TRUE_CTLS, 3650 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3651 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3652 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3653 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3654 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3655 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3656 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3657 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3658 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3659 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3660 .features[FEAT_VMX_EXIT_CTLS] = 3661 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3662 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3663 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3664 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3665 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3666 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3667 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3668 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3669 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3670 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3671 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3672 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3673 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3674 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3675 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3676 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3677 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3678 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3679 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3680 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3681 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3682 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3683 .features[FEAT_VMX_SECONDARY_CTLS] = 3684 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3685 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3686 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3687 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3688 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3689 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3690 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3691 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3692 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3693 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3694 .xlevel = 0x80000008, 3695 .model_id = "Intel Xeon Processor (Skylake)", 3696 .versions = (X86CPUVersionDefinition[]) { 3697 { .version = 1 }, 3698 { 3699 .version = 2, 3700 .alias = "Skylake-Server-IBRS", 3701 .props = (PropValue[]) { 3702 /* clflushopt was not added to Skylake-Server-IBRS */ 3703 /* TODO: add -v3 including clflushopt */ 3704 { "clflushopt", "off" }, 3705 { "spec-ctrl", "on" }, 3706 { "model-id", 3707 "Intel Xeon Processor (Skylake, IBRS)" }, 3708 { /* end of list */ } 3709 } 3710 }, 3711 { 3712 .version = 3, 3713 .alias = "Skylake-Server-noTSX-IBRS", 3714 .props = (PropValue[]) { 3715 { "hle", "off" }, 3716 { "rtm", "off" }, 3717 { "model-id", 3718 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3719 { /* end of list */ } 3720 } 3721 }, 3722 { 3723 .version = 4, 3724 .note = "IBRS, EPT switching, no TSX", 3725 .props = (PropValue[]) { 3726 { "vmx-eptp-switching", "on" }, 3727 { /* end of list */ } 3728 } 3729 }, 3730 { 3731 .version = 5, 3732 .note = "IBRS, XSAVES, EPT switching, no TSX", 3733 .props = (PropValue[]) { 3734 { "xsaves", "on" }, 3735 { "vmx-xsaves", "on" }, 3736 { /* end of list */ } 3737 } 3738 }, 3739 { /* end of list */ } 3740 } 3741 }, 3742 { 3743 .name = "Cascadelake-Server", 3744 .level = 0xd, 3745 .vendor = CPUID_VENDOR_INTEL, 3746 .family = 6, 3747 .model = 85, 3748 .stepping = 6, 3749 .features[FEAT_1_EDX] = 3750 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3751 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3752 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3753 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3754 CPUID_DE | CPUID_FP87, 3755 .features[FEAT_1_ECX] = 3756 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3757 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3758 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3759 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3760 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3761 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3762 .features[FEAT_8000_0001_EDX] = 3763 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3764 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3765 .features[FEAT_8000_0001_ECX] = 3766 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3767 .features[FEAT_7_0_EBX] = 3768 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3769 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3770 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3771 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3772 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3773 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3774 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3775 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3776 .features[FEAT_7_0_ECX] = 3777 CPUID_7_0_ECX_PKU | 3778 CPUID_7_0_ECX_AVX512VNNI, 3779 .features[FEAT_7_0_EDX] = 3780 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3781 /* XSAVES is added in version 5 */ 3782 .features[FEAT_XSAVE] = 3783 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3784 CPUID_XSAVE_XGETBV1, 3785 .features[FEAT_6_EAX] = 3786 CPUID_6_EAX_ARAT, 3787 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3788 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3789 MSR_VMX_BASIC_TRUE_CTLS, 3790 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3791 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3792 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3793 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3794 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3795 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3796 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3797 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3798 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3799 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3800 .features[FEAT_VMX_EXIT_CTLS] = 3801 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3802 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3803 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3804 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3805 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3806 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3807 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3808 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3809 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3810 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3811 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3812 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3813 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3814 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3815 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3816 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3817 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3818 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3819 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3820 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3821 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3822 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3823 .features[FEAT_VMX_SECONDARY_CTLS] = 3824 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3825 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3826 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3827 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3828 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3829 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3830 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3831 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3832 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3833 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3834 .xlevel = 0x80000008, 3835 .model_id = "Intel Xeon Processor (Cascadelake)", 3836 .versions = (X86CPUVersionDefinition[]) { 3837 { .version = 1 }, 3838 { .version = 2, 3839 .note = "ARCH_CAPABILITIES", 3840 .props = (PropValue[]) { 3841 { "arch-capabilities", "on" }, 3842 { "rdctl-no", "on" }, 3843 { "ibrs-all", "on" }, 3844 { "skip-l1dfl-vmentry", "on" }, 3845 { "mds-no", "on" }, 3846 { /* end of list */ } 3847 }, 3848 }, 3849 { .version = 3, 3850 .alias = "Cascadelake-Server-noTSX", 3851 .note = "ARCH_CAPABILITIES, no TSX", 3852 .props = (PropValue[]) { 3853 { "hle", "off" }, 3854 { "rtm", "off" }, 3855 { /* end of list */ } 3856 }, 3857 }, 3858 { .version = 4, 3859 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 3860 .props = (PropValue[]) { 3861 { "vmx-eptp-switching", "on" }, 3862 { /* end of list */ } 3863 }, 3864 }, 3865 { .version = 5, 3866 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3867 .props = (PropValue[]) { 3868 { "xsaves", "on" }, 3869 { "vmx-xsaves", "on" }, 3870 { /* end of list */ } 3871 }, 3872 }, 3873 { /* end of list */ } 3874 } 3875 }, 3876 { 3877 .name = "Cooperlake", 3878 .level = 0xd, 3879 .vendor = CPUID_VENDOR_INTEL, 3880 .family = 6, 3881 .model = 85, 3882 .stepping = 10, 3883 .features[FEAT_1_EDX] = 3884 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3885 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3886 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3887 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3888 CPUID_DE | CPUID_FP87, 3889 .features[FEAT_1_ECX] = 3890 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3891 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3892 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3893 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3894 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3895 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3896 .features[FEAT_8000_0001_EDX] = 3897 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3898 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3899 .features[FEAT_8000_0001_ECX] = 3900 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3901 .features[FEAT_7_0_EBX] = 3902 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3903 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3904 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3905 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3906 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3907 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3908 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3909 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3910 .features[FEAT_7_0_ECX] = 3911 CPUID_7_0_ECX_PKU | 3912 CPUID_7_0_ECX_AVX512VNNI, 3913 .features[FEAT_7_0_EDX] = 3914 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3915 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3916 .features[FEAT_ARCH_CAPABILITIES] = 3917 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3918 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3919 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3920 .features[FEAT_7_1_EAX] = 3921 CPUID_7_1_EAX_AVX512_BF16, 3922 /* XSAVES is added in version 2 */ 3923 .features[FEAT_XSAVE] = 3924 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3925 CPUID_XSAVE_XGETBV1, 3926 .features[FEAT_6_EAX] = 3927 CPUID_6_EAX_ARAT, 3928 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3929 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3930 MSR_VMX_BASIC_TRUE_CTLS, 3931 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3932 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3933 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3934 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3935 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3936 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3937 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3938 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3939 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3940 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3941 .features[FEAT_VMX_EXIT_CTLS] = 3942 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3943 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3944 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3945 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3946 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3947 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3948 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3949 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3950 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3951 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3952 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3953 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3954 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3955 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3956 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3957 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3958 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3959 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3960 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3961 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3962 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3963 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3964 .features[FEAT_VMX_SECONDARY_CTLS] = 3965 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3966 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3967 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3968 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3969 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3970 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3971 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3972 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3973 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3974 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3975 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3976 .xlevel = 0x80000008, 3977 .model_id = "Intel Xeon Processor (Cooperlake)", 3978 .versions = (X86CPUVersionDefinition[]) { 3979 { .version = 1 }, 3980 { .version = 2, 3981 .note = "XSAVES", 3982 .props = (PropValue[]) { 3983 { "xsaves", "on" }, 3984 { "vmx-xsaves", "on" }, 3985 { /* end of list */ } 3986 }, 3987 }, 3988 { /* end of list */ } 3989 } 3990 }, 3991 { 3992 .name = "Icelake-Server", 3993 .level = 0xd, 3994 .vendor = CPUID_VENDOR_INTEL, 3995 .family = 6, 3996 .model = 134, 3997 .stepping = 0, 3998 .features[FEAT_1_EDX] = 3999 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4000 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4001 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4002 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4003 CPUID_DE | CPUID_FP87, 4004 .features[FEAT_1_ECX] = 4005 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4006 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4007 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4008 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4009 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4010 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4011 .features[FEAT_8000_0001_EDX] = 4012 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4013 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4014 .features[FEAT_8000_0001_ECX] = 4015 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4016 .features[FEAT_8000_0008_EBX] = 4017 CPUID_8000_0008_EBX_WBNOINVD, 4018 .features[FEAT_7_0_EBX] = 4019 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4020 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4021 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4022 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4023 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4024 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4025 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4026 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4027 .features[FEAT_7_0_ECX] = 4028 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4029 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4030 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4031 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4032 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4033 .features[FEAT_7_0_EDX] = 4034 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4035 /* XSAVES is added in version 5 */ 4036 .features[FEAT_XSAVE] = 4037 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4038 CPUID_XSAVE_XGETBV1, 4039 .features[FEAT_6_EAX] = 4040 CPUID_6_EAX_ARAT, 4041 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4042 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4043 MSR_VMX_BASIC_TRUE_CTLS, 4044 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4045 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4046 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4047 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4048 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4049 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4050 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4051 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4052 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4053 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4054 .features[FEAT_VMX_EXIT_CTLS] = 4055 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4056 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4057 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4058 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4059 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4060 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4061 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4062 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4063 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4064 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4065 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4066 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4067 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4068 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4069 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4070 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4071 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4072 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4073 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4074 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4075 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4076 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4077 .features[FEAT_VMX_SECONDARY_CTLS] = 4078 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4079 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4080 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4081 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4082 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4083 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4084 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4085 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4086 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4087 .xlevel = 0x80000008, 4088 .model_id = "Intel Xeon Processor (Icelake)", 4089 .versions = (X86CPUVersionDefinition[]) { 4090 { .version = 1 }, 4091 { 4092 .version = 2, 4093 .note = "no TSX", 4094 .alias = "Icelake-Server-noTSX", 4095 .props = (PropValue[]) { 4096 { "hle", "off" }, 4097 { "rtm", "off" }, 4098 { /* end of list */ } 4099 }, 4100 }, 4101 { 4102 .version = 3, 4103 .props = (PropValue[]) { 4104 { "arch-capabilities", "on" }, 4105 { "rdctl-no", "on" }, 4106 { "ibrs-all", "on" }, 4107 { "skip-l1dfl-vmentry", "on" }, 4108 { "mds-no", "on" }, 4109 { "pschange-mc-no", "on" }, 4110 { "taa-no", "on" }, 4111 { /* end of list */ } 4112 }, 4113 }, 4114 { 4115 .version = 4, 4116 .props = (PropValue[]) { 4117 { "sha-ni", "on" }, 4118 { "avx512ifma", "on" }, 4119 { "rdpid", "on" }, 4120 { "fsrm", "on" }, 4121 { "vmx-rdseed-exit", "on" }, 4122 { "vmx-pml", "on" }, 4123 { "vmx-eptp-switching", "on" }, 4124 { "model", "106" }, 4125 { /* end of list */ } 4126 }, 4127 }, 4128 { 4129 .version = 5, 4130 .note = "XSAVES", 4131 .props = (PropValue[]) { 4132 { "xsaves", "on" }, 4133 { "vmx-xsaves", "on" }, 4134 { /* end of list */ } 4135 }, 4136 }, 4137 { 4138 .version = 6, 4139 .note = "5-level EPT", 4140 .props = (PropValue[]) { 4141 { "vmx-page-walk-5", "on" }, 4142 { /* end of list */ } 4143 }, 4144 }, 4145 { 4146 .version = 7, 4147 .note = "TSX, taa-no", 4148 .props = (PropValue[]) { 4149 /* Restore TSX features removed by -v2 above */ 4150 { "hle", "on" }, 4151 { "rtm", "on" }, 4152 { /* end of list */ } 4153 }, 4154 }, 4155 { /* end of list */ } 4156 } 4157 }, 4158 { 4159 .name = "SapphireRapids", 4160 .level = 0x20, 4161 .vendor = CPUID_VENDOR_INTEL, 4162 .family = 6, 4163 .model = 143, 4164 .stepping = 4, 4165 /* 4166 * please keep the ascending order so that we can have a clear view of 4167 * bit position of each feature. 4168 */ 4169 .features[FEAT_1_EDX] = 4170 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4171 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4172 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4173 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4174 CPUID_SSE | CPUID_SSE2, 4175 .features[FEAT_1_ECX] = 4176 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4177 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4178 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4179 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4180 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4181 .features[FEAT_8000_0001_EDX] = 4182 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4183 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4184 .features[FEAT_8000_0001_ECX] = 4185 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4186 .features[FEAT_8000_0008_EBX] = 4187 CPUID_8000_0008_EBX_WBNOINVD, 4188 .features[FEAT_7_0_EBX] = 4189 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4190 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4191 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4192 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4193 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4194 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4195 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4196 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4197 .features[FEAT_7_0_ECX] = 4198 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4199 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4200 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4201 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4202 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4203 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4204 .features[FEAT_7_0_EDX] = 4205 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4206 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4207 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4208 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4209 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4210 .features[FEAT_ARCH_CAPABILITIES] = 4211 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4212 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4213 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4214 .features[FEAT_XSAVE] = 4215 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4216 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4217 .features[FEAT_6_EAX] = 4218 CPUID_6_EAX_ARAT, 4219 .features[FEAT_7_1_EAX] = 4220 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4221 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4222 .features[FEAT_VMX_BASIC] = 4223 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4224 .features[FEAT_VMX_ENTRY_CTLS] = 4225 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4226 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4227 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4228 .features[FEAT_VMX_EPT_VPID_CAPS] = 4229 MSR_VMX_EPT_EXECONLY | 4230 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4231 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4232 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4233 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4234 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4235 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4236 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4237 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4238 .features[FEAT_VMX_EXIT_CTLS] = 4239 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4240 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4241 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4242 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4243 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4244 .features[FEAT_VMX_MISC] = 4245 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4246 MSR_VMX_MISC_VMWRITE_VMEXIT, 4247 .features[FEAT_VMX_PINBASED_CTLS] = 4248 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4249 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4250 VMX_PIN_BASED_POSTED_INTR, 4251 .features[FEAT_VMX_PROCBASED_CTLS] = 4252 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4253 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4254 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4255 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4256 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4257 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4258 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4259 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4260 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4261 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4262 VMX_CPU_BASED_PAUSE_EXITING | 4263 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4264 .features[FEAT_VMX_SECONDARY_CTLS] = 4265 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4266 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4267 VMX_SECONDARY_EXEC_RDTSCP | 4268 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4269 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4270 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4271 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4272 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4273 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4274 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4275 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4276 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4277 VMX_SECONDARY_EXEC_XSAVES, 4278 .features[FEAT_VMX_VMFUNC] = 4279 MSR_VMX_VMFUNC_EPT_SWITCHING, 4280 .xlevel = 0x80000008, 4281 .model_id = "Intel Xeon Processor (SapphireRapids)", 4282 .versions = (X86CPUVersionDefinition[]) { 4283 { .version = 1 }, 4284 { 4285 .version = 2, 4286 .props = (PropValue[]) { 4287 { "sbdr-ssdp-no", "on" }, 4288 { "fbsdp-no", "on" }, 4289 { "psdp-no", "on" }, 4290 { /* end of list */ } 4291 } 4292 }, 4293 { 4294 .version = 3, 4295 .props = (PropValue[]) { 4296 { "ss", "on" }, 4297 { "tsc-adjust", "on" }, 4298 { "cldemote", "on" }, 4299 { "movdiri", "on" }, 4300 { "movdir64b", "on" }, 4301 { /* end of list */ } 4302 } 4303 }, 4304 { /* end of list */ } 4305 } 4306 }, 4307 { 4308 .name = "GraniteRapids", 4309 .level = 0x20, 4310 .vendor = CPUID_VENDOR_INTEL, 4311 .family = 6, 4312 .model = 173, 4313 .stepping = 0, 4314 /* 4315 * please keep the ascending order so that we can have a clear view of 4316 * bit position of each feature. 4317 */ 4318 .features[FEAT_1_EDX] = 4319 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4320 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4321 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4322 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4323 CPUID_SSE | CPUID_SSE2, 4324 .features[FEAT_1_ECX] = 4325 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4326 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4327 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4328 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4329 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4330 .features[FEAT_8000_0001_EDX] = 4331 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4332 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4333 .features[FEAT_8000_0001_ECX] = 4334 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4335 .features[FEAT_8000_0008_EBX] = 4336 CPUID_8000_0008_EBX_WBNOINVD, 4337 .features[FEAT_7_0_EBX] = 4338 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4339 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4340 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4341 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4342 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4343 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4344 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4345 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4346 .features[FEAT_7_0_ECX] = 4347 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4348 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4349 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4350 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4351 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4352 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4353 .features[FEAT_7_0_EDX] = 4354 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4355 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4356 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4357 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4358 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4359 .features[FEAT_ARCH_CAPABILITIES] = 4360 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4361 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4362 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4363 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4364 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4365 .features[FEAT_XSAVE] = 4366 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4367 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4368 .features[FEAT_6_EAX] = 4369 CPUID_6_EAX_ARAT, 4370 .features[FEAT_7_1_EAX] = 4371 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4372 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4373 CPUID_7_1_EAX_AMX_FP16, 4374 .features[FEAT_7_1_EDX] = 4375 CPUID_7_1_EDX_PREFETCHITI, 4376 .features[FEAT_7_2_EDX] = 4377 CPUID_7_2_EDX_MCDT_NO, 4378 .features[FEAT_VMX_BASIC] = 4379 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4380 .features[FEAT_VMX_ENTRY_CTLS] = 4381 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4382 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4383 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4384 .features[FEAT_VMX_EPT_VPID_CAPS] = 4385 MSR_VMX_EPT_EXECONLY | 4386 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4387 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4388 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4389 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4390 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4391 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4392 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4393 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4394 .features[FEAT_VMX_EXIT_CTLS] = 4395 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4396 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4397 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4398 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4399 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4400 .features[FEAT_VMX_MISC] = 4401 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4402 MSR_VMX_MISC_VMWRITE_VMEXIT, 4403 .features[FEAT_VMX_PINBASED_CTLS] = 4404 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4405 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4406 VMX_PIN_BASED_POSTED_INTR, 4407 .features[FEAT_VMX_PROCBASED_CTLS] = 4408 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4409 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4410 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4411 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4412 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4413 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4414 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4415 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4416 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4417 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4418 VMX_CPU_BASED_PAUSE_EXITING | 4419 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4420 .features[FEAT_VMX_SECONDARY_CTLS] = 4421 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4422 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4423 VMX_SECONDARY_EXEC_RDTSCP | 4424 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4425 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4426 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4427 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4428 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4429 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4430 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4431 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4432 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4433 VMX_SECONDARY_EXEC_XSAVES, 4434 .features[FEAT_VMX_VMFUNC] = 4435 MSR_VMX_VMFUNC_EPT_SWITCHING, 4436 .xlevel = 0x80000008, 4437 .model_id = "Intel Xeon Processor (GraniteRapids)", 4438 .versions = (X86CPUVersionDefinition[]) { 4439 { .version = 1 }, 4440 { 4441 .version = 2, 4442 .props = (PropValue[]) { 4443 { "ss", "on" }, 4444 { "tsc-adjust", "on" }, 4445 { "cldemote", "on" }, 4446 { "movdiri", "on" }, 4447 { "movdir64b", "on" }, 4448 { "avx10", "on" }, 4449 { "avx10-128", "on" }, 4450 { "avx10-256", "on" }, 4451 { "avx10-512", "on" }, 4452 { "avx10-version", "1" }, 4453 { "stepping", "1" }, 4454 { /* end of list */ } 4455 } 4456 }, 4457 { /* end of list */ }, 4458 }, 4459 }, 4460 { 4461 .name = "SierraForest", 4462 .level = 0x23, 4463 .vendor = CPUID_VENDOR_INTEL, 4464 .family = 6, 4465 .model = 175, 4466 .stepping = 0, 4467 /* 4468 * please keep the ascending order so that we can have a clear view of 4469 * bit position of each feature. 4470 */ 4471 .features[FEAT_1_EDX] = 4472 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4473 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4474 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4475 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4476 CPUID_SSE | CPUID_SSE2, 4477 .features[FEAT_1_ECX] = 4478 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4479 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4480 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4481 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4482 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4483 .features[FEAT_8000_0001_EDX] = 4484 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4485 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4486 .features[FEAT_8000_0001_ECX] = 4487 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4488 .features[FEAT_8000_0008_EBX] = 4489 CPUID_8000_0008_EBX_WBNOINVD, 4490 .features[FEAT_7_0_EBX] = 4491 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4492 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4493 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4494 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4495 CPUID_7_0_EBX_SHA_NI, 4496 .features[FEAT_7_0_ECX] = 4497 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4498 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4499 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4500 .features[FEAT_7_0_EDX] = 4501 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4502 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4503 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4504 .features[FEAT_ARCH_CAPABILITIES] = 4505 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4506 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4507 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4508 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4509 MSR_ARCH_CAP_PBRSB_NO, 4510 .features[FEAT_XSAVE] = 4511 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4512 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4513 .features[FEAT_6_EAX] = 4514 CPUID_6_EAX_ARAT, 4515 .features[FEAT_7_1_EAX] = 4516 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4517 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4518 .features[FEAT_7_1_EDX] = 4519 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4520 .features[FEAT_7_2_EDX] = 4521 CPUID_7_2_EDX_MCDT_NO, 4522 .features[FEAT_VMX_BASIC] = 4523 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4524 .features[FEAT_VMX_ENTRY_CTLS] = 4525 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4526 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4527 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4528 .features[FEAT_VMX_EPT_VPID_CAPS] = 4529 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4530 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4531 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4532 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4533 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4534 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4535 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4536 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4537 .features[FEAT_VMX_EXIT_CTLS] = 4538 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4539 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4540 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4541 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4542 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4543 .features[FEAT_VMX_MISC] = 4544 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4545 MSR_VMX_MISC_VMWRITE_VMEXIT, 4546 .features[FEAT_VMX_PINBASED_CTLS] = 4547 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4548 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4549 VMX_PIN_BASED_POSTED_INTR, 4550 .features[FEAT_VMX_PROCBASED_CTLS] = 4551 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4552 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4553 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4554 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4555 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4556 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4557 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4558 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4559 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4560 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4561 VMX_CPU_BASED_PAUSE_EXITING | 4562 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4563 .features[FEAT_VMX_SECONDARY_CTLS] = 4564 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4565 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4566 VMX_SECONDARY_EXEC_RDTSCP | 4567 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4568 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4569 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4570 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4571 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4572 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4573 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4574 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4575 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4576 VMX_SECONDARY_EXEC_XSAVES, 4577 .features[FEAT_VMX_VMFUNC] = 4578 MSR_VMX_VMFUNC_EPT_SWITCHING, 4579 .xlevel = 0x80000008, 4580 .model_id = "Intel Xeon Processor (SierraForest)", 4581 .versions = (X86CPUVersionDefinition[]) { 4582 { .version = 1 }, 4583 { 4584 .version = 2, 4585 .props = (PropValue[]) { 4586 { "ss", "on" }, 4587 { "tsc-adjust", "on" }, 4588 { "cldemote", "on" }, 4589 { "movdiri", "on" }, 4590 { "movdir64b", "on" }, 4591 { "gds-no", "on" }, 4592 { "rfds-no", "on" }, 4593 { "lam", "on" }, 4594 { "intel-psfd", "on"}, 4595 { "ipred-ctrl", "on"}, 4596 { "rrsba-ctrl", "on"}, 4597 { "bhi-ctrl", "on"}, 4598 { "stepping", "3" }, 4599 { /* end of list */ } 4600 } 4601 }, 4602 { /* end of list */ }, 4603 }, 4604 }, 4605 { 4606 .name = "ClearwaterForest", 4607 .level = 0x23, 4608 .xlevel = 0x80000008, 4609 .vendor = CPUID_VENDOR_INTEL, 4610 .family = 6, 4611 .model = 221, 4612 .stepping = 0, 4613 /* 4614 * please keep the ascending order so that we can have a clear view of 4615 * bit position of each feature. 4616 */ 4617 .features[FEAT_1_EDX] = 4618 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4619 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4620 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4621 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4622 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 4623 .features[FEAT_1_ECX] = 4624 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4625 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4626 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4627 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4628 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4629 .features[FEAT_8000_0001_EDX] = 4630 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4631 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4632 .features[FEAT_8000_0001_ECX] = 4633 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4634 .features[FEAT_8000_0008_EBX] = 4635 CPUID_8000_0008_EBX_WBNOINVD, 4636 .features[FEAT_7_0_EBX] = 4637 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 4638 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4639 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4640 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4641 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4642 CPUID_7_0_EBX_SHA_NI, 4643 .features[FEAT_7_0_ECX] = 4644 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4645 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4646 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 4647 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 4648 CPUID_7_0_ECX_MOVDIR64B, 4649 .features[FEAT_7_0_EDX] = 4650 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4651 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4652 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4653 .features[FEAT_ARCH_CAPABILITIES] = 4654 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4655 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4656 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4657 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4658 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 4659 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 4660 .features[FEAT_XSAVE] = 4661 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4662 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4663 .features[FEAT_6_EAX] = 4664 CPUID_6_EAX_ARAT, 4665 .features[FEAT_7_1_EAX] = 4666 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 4667 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4668 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 4669 CPUID_7_1_EAX_LAM, 4670 .features[FEAT_7_1_EDX] = 4671 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 4672 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 4673 .features[FEAT_7_2_EDX] = 4674 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 4675 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 4676 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 4677 .features[FEAT_VMX_BASIC] = 4678 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4679 .features[FEAT_VMX_ENTRY_CTLS] = 4680 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4681 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4682 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4683 .features[FEAT_VMX_EPT_VPID_CAPS] = 4684 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4685 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4686 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4687 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4688 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4689 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4690 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4691 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4692 .features[FEAT_VMX_EXIT_CTLS] = 4693 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4694 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4695 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4696 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4697 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4698 .features[FEAT_VMX_MISC] = 4699 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4700 MSR_VMX_MISC_VMWRITE_VMEXIT, 4701 .features[FEAT_VMX_PINBASED_CTLS] = 4702 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4703 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4704 VMX_PIN_BASED_POSTED_INTR, 4705 .features[FEAT_VMX_PROCBASED_CTLS] = 4706 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4707 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4708 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4709 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4710 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4711 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4712 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4713 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4714 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4715 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4716 VMX_CPU_BASED_PAUSE_EXITING | 4717 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4718 .features[FEAT_VMX_SECONDARY_CTLS] = 4719 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4720 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4721 VMX_SECONDARY_EXEC_RDTSCP | 4722 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4723 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4724 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4725 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4726 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4727 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4728 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4729 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4730 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4731 VMX_SECONDARY_EXEC_XSAVES, 4732 .features[FEAT_VMX_VMFUNC] = 4733 MSR_VMX_VMFUNC_EPT_SWITCHING, 4734 .model_id = "Intel Xeon Processor (ClearwaterForest)", 4735 .versions = (X86CPUVersionDefinition[]) { 4736 { .version = 1 }, 4737 { /* end of list */ }, 4738 }, 4739 }, 4740 { 4741 .name = "Denverton", 4742 .level = 21, 4743 .vendor = CPUID_VENDOR_INTEL, 4744 .family = 6, 4745 .model = 95, 4746 .stepping = 1, 4747 .features[FEAT_1_EDX] = 4748 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4749 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4750 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4751 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4752 CPUID_SSE | CPUID_SSE2, 4753 .features[FEAT_1_ECX] = 4754 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4755 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4756 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4757 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4758 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4759 .features[FEAT_8000_0001_EDX] = 4760 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4761 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4762 .features[FEAT_8000_0001_ECX] = 4763 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4764 .features[FEAT_7_0_EBX] = 4765 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4766 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4767 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4768 .features[FEAT_7_0_EDX] = 4769 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4770 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4771 /* XSAVES is added in version 3 */ 4772 .features[FEAT_XSAVE] = 4773 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4774 .features[FEAT_6_EAX] = 4775 CPUID_6_EAX_ARAT, 4776 .features[FEAT_ARCH_CAPABILITIES] = 4777 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4778 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4779 MSR_VMX_BASIC_TRUE_CTLS, 4780 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4781 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4782 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4783 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4784 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4785 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4786 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4787 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4788 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4789 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4790 .features[FEAT_VMX_EXIT_CTLS] = 4791 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4792 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4793 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4794 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4795 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4796 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4797 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4798 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4799 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4800 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4801 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4802 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4803 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4804 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4805 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4806 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4807 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4808 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4809 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4810 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4811 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4812 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4813 .features[FEAT_VMX_SECONDARY_CTLS] = 4814 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4815 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4816 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4817 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4818 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4819 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4820 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4821 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4822 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4823 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4824 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4825 .xlevel = 0x80000008, 4826 .model_id = "Intel Atom Processor (Denverton)", 4827 .versions = (X86CPUVersionDefinition[]) { 4828 { .version = 1 }, 4829 { 4830 .version = 2, 4831 .note = "no MPX, no MONITOR", 4832 .props = (PropValue[]) { 4833 { "monitor", "off" }, 4834 { "mpx", "off" }, 4835 { /* end of list */ }, 4836 }, 4837 }, 4838 { 4839 .version = 3, 4840 .note = "XSAVES, no MPX, no MONITOR", 4841 .props = (PropValue[]) { 4842 { "xsaves", "on" }, 4843 { "vmx-xsaves", "on" }, 4844 { /* end of list */ }, 4845 }, 4846 }, 4847 { /* end of list */ }, 4848 }, 4849 }, 4850 { 4851 .name = "Snowridge", 4852 .level = 27, 4853 .vendor = CPUID_VENDOR_INTEL, 4854 .family = 6, 4855 .model = 134, 4856 .stepping = 1, 4857 .features[FEAT_1_EDX] = 4858 /* missing: CPUID_PN CPUID_IA64 */ 4859 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4860 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4861 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4862 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4863 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4864 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4865 CPUID_MMX | 4866 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4867 .features[FEAT_1_ECX] = 4868 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4869 CPUID_EXT_SSSE3 | 4870 CPUID_EXT_CX16 | 4871 CPUID_EXT_SSE41 | 4872 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4873 CPUID_EXT_POPCNT | 4874 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4875 CPUID_EXT_RDRAND, 4876 .features[FEAT_8000_0001_EDX] = 4877 CPUID_EXT2_SYSCALL | 4878 CPUID_EXT2_NX | 4879 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4880 CPUID_EXT2_LM, 4881 .features[FEAT_8000_0001_ECX] = 4882 CPUID_EXT3_LAHF_LM | 4883 CPUID_EXT3_3DNOWPREFETCH, 4884 .features[FEAT_7_0_EBX] = 4885 CPUID_7_0_EBX_FSGSBASE | 4886 CPUID_7_0_EBX_SMEP | 4887 CPUID_7_0_EBX_ERMS | 4888 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4889 CPUID_7_0_EBX_RDSEED | 4890 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4891 CPUID_7_0_EBX_CLWB | 4892 CPUID_7_0_EBX_SHA_NI, 4893 .features[FEAT_7_0_ECX] = 4894 CPUID_7_0_ECX_UMIP | 4895 /* missing bit 5 */ 4896 CPUID_7_0_ECX_GFNI | 4897 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4898 CPUID_7_0_ECX_MOVDIR64B, 4899 .features[FEAT_7_0_EDX] = 4900 CPUID_7_0_EDX_SPEC_CTRL | 4901 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4902 CPUID_7_0_EDX_CORE_CAPABILITY, 4903 .features[FEAT_CORE_CAPABILITY] = 4904 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4905 /* XSAVES is added in version 3 */ 4906 .features[FEAT_XSAVE] = 4907 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4908 CPUID_XSAVE_XGETBV1, 4909 .features[FEAT_6_EAX] = 4910 CPUID_6_EAX_ARAT, 4911 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4912 MSR_VMX_BASIC_TRUE_CTLS, 4913 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4914 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4915 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4916 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4917 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4918 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4919 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4920 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4921 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4922 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4923 .features[FEAT_VMX_EXIT_CTLS] = 4924 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4925 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4926 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4927 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4928 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4929 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4930 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4931 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4932 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4933 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4934 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4935 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4936 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4937 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4938 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4939 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4940 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4941 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4942 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4943 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4944 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4945 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4946 .features[FEAT_VMX_SECONDARY_CTLS] = 4947 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4948 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4949 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4950 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4951 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4952 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4953 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4954 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4955 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4956 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4957 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4958 .xlevel = 0x80000008, 4959 .model_id = "Intel Atom Processor (SnowRidge)", 4960 .versions = (X86CPUVersionDefinition[]) { 4961 { .version = 1 }, 4962 { 4963 .version = 2, 4964 .props = (PropValue[]) { 4965 { "mpx", "off" }, 4966 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4967 { /* end of list */ }, 4968 }, 4969 }, 4970 { 4971 .version = 3, 4972 .note = "XSAVES, no MPX", 4973 .props = (PropValue[]) { 4974 { "xsaves", "on" }, 4975 { "vmx-xsaves", "on" }, 4976 { /* end of list */ }, 4977 }, 4978 }, 4979 { 4980 .version = 4, 4981 .note = "no split lock detect, no core-capability", 4982 .props = (PropValue[]) { 4983 { "split-lock-detect", "off" }, 4984 { "core-capability", "off" }, 4985 { /* end of list */ }, 4986 }, 4987 }, 4988 { /* end of list */ }, 4989 }, 4990 }, 4991 { 4992 .name = "KnightsMill", 4993 .level = 0xd, 4994 .vendor = CPUID_VENDOR_INTEL, 4995 .family = 6, 4996 .model = 133, 4997 .stepping = 0, 4998 .features[FEAT_1_EDX] = 4999 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 5000 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5001 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5002 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5003 CPUID_PSE | CPUID_DE | CPUID_FP87, 5004 .features[FEAT_1_ECX] = 5005 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5006 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 5007 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 5008 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5009 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 5010 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5011 .features[FEAT_8000_0001_EDX] = 5012 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5013 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5014 .features[FEAT_8000_0001_ECX] = 5015 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5016 .features[FEAT_7_0_EBX] = 5017 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5018 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5019 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 5020 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 5021 CPUID_7_0_EBX_AVX512ER, 5022 .features[FEAT_7_0_ECX] = 5023 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 5024 .features[FEAT_7_0_EDX] = 5025 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 5026 .features[FEAT_XSAVE] = 5027 CPUID_XSAVE_XSAVEOPT, 5028 .features[FEAT_6_EAX] = 5029 CPUID_6_EAX_ARAT, 5030 .xlevel = 0x80000008, 5031 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5032 }, 5033 { 5034 .name = "Opteron_G1", 5035 .level = 5, 5036 .vendor = CPUID_VENDOR_AMD, 5037 .family = 15, 5038 .model = 6, 5039 .stepping = 1, 5040 .features[FEAT_1_EDX] = 5041 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5042 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5043 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5044 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5045 CPUID_DE | CPUID_FP87, 5046 .features[FEAT_1_ECX] = 5047 CPUID_EXT_SSE3, 5048 .features[FEAT_8000_0001_EDX] = 5049 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5050 .xlevel = 0x80000008, 5051 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5052 }, 5053 { 5054 .name = "Opteron_G2", 5055 .level = 5, 5056 .vendor = CPUID_VENDOR_AMD, 5057 .family = 15, 5058 .model = 6, 5059 .stepping = 1, 5060 .features[FEAT_1_EDX] = 5061 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5062 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5063 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5064 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5065 CPUID_DE | CPUID_FP87, 5066 .features[FEAT_1_ECX] = 5067 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5068 .features[FEAT_8000_0001_EDX] = 5069 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5070 .features[FEAT_8000_0001_ECX] = 5071 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5072 .xlevel = 0x80000008, 5073 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5074 }, 5075 { 5076 .name = "Opteron_G3", 5077 .level = 5, 5078 .vendor = CPUID_VENDOR_AMD, 5079 .family = 16, 5080 .model = 2, 5081 .stepping = 3, 5082 .features[FEAT_1_EDX] = 5083 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5084 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5085 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5086 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5087 CPUID_DE | CPUID_FP87, 5088 .features[FEAT_1_ECX] = 5089 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5090 CPUID_EXT_SSE3, 5091 .features[FEAT_8000_0001_EDX] = 5092 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5093 CPUID_EXT2_RDTSCP, 5094 .features[FEAT_8000_0001_ECX] = 5095 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5096 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5097 .xlevel = 0x80000008, 5098 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5099 }, 5100 { 5101 .name = "Opteron_G4", 5102 .level = 0xd, 5103 .vendor = CPUID_VENDOR_AMD, 5104 .family = 21, 5105 .model = 1, 5106 .stepping = 2, 5107 .features[FEAT_1_EDX] = 5108 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5109 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5110 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5111 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5112 CPUID_DE | CPUID_FP87, 5113 .features[FEAT_1_ECX] = 5114 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5115 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5116 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5117 CPUID_EXT_SSE3, 5118 .features[FEAT_8000_0001_EDX] = 5119 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5120 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5121 .features[FEAT_8000_0001_ECX] = 5122 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5123 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5124 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5125 CPUID_EXT3_LAHF_LM, 5126 .features[FEAT_SVM] = 5127 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5128 /* no xsaveopt! */ 5129 .xlevel = 0x8000001A, 5130 .model_id = "AMD Opteron 62xx class CPU", 5131 }, 5132 { 5133 .name = "Opteron_G5", 5134 .level = 0xd, 5135 .vendor = CPUID_VENDOR_AMD, 5136 .family = 21, 5137 .model = 2, 5138 .stepping = 0, 5139 .features[FEAT_1_EDX] = 5140 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5141 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5142 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5143 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5144 CPUID_DE | CPUID_FP87, 5145 .features[FEAT_1_ECX] = 5146 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5147 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5148 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5149 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5150 .features[FEAT_8000_0001_EDX] = 5151 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5152 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5153 .features[FEAT_8000_0001_ECX] = 5154 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5155 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5156 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5157 CPUID_EXT3_LAHF_LM, 5158 .features[FEAT_SVM] = 5159 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5160 /* no xsaveopt! */ 5161 .xlevel = 0x8000001A, 5162 .model_id = "AMD Opteron 63xx class CPU", 5163 }, 5164 { 5165 .name = "EPYC", 5166 .level = 0xd, 5167 .vendor = CPUID_VENDOR_AMD, 5168 .family = 23, 5169 .model = 1, 5170 .stepping = 2, 5171 .features[FEAT_1_EDX] = 5172 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5173 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5174 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5175 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5176 CPUID_VME | CPUID_FP87, 5177 .features[FEAT_1_ECX] = 5178 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5179 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5180 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5181 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5182 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5183 .features[FEAT_8000_0001_EDX] = 5184 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5185 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5186 CPUID_EXT2_SYSCALL, 5187 .features[FEAT_8000_0001_ECX] = 5188 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5189 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5190 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5191 CPUID_EXT3_TOPOEXT, 5192 .features[FEAT_7_0_EBX] = 5193 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5194 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5195 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5196 CPUID_7_0_EBX_SHA_NI, 5197 .features[FEAT_XSAVE] = 5198 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5199 CPUID_XSAVE_XGETBV1, 5200 .features[FEAT_6_EAX] = 5201 CPUID_6_EAX_ARAT, 5202 .features[FEAT_SVM] = 5203 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5204 .xlevel = 0x8000001E, 5205 .model_id = "AMD EPYC Processor", 5206 .cache_info = &epyc_cache_info, 5207 .versions = (X86CPUVersionDefinition[]) { 5208 { .version = 1 }, 5209 { 5210 .version = 2, 5211 .alias = "EPYC-IBPB", 5212 .props = (PropValue[]) { 5213 { "ibpb", "on" }, 5214 { "model-id", 5215 "AMD EPYC Processor (with IBPB)" }, 5216 { /* end of list */ } 5217 } 5218 }, 5219 { 5220 .version = 3, 5221 .props = (PropValue[]) { 5222 { "ibpb", "on" }, 5223 { "perfctr-core", "on" }, 5224 { "clzero", "on" }, 5225 { "xsaveerptr", "on" }, 5226 { "xsaves", "on" }, 5227 { "model-id", 5228 "AMD EPYC Processor" }, 5229 { /* end of list */ } 5230 } 5231 }, 5232 { 5233 .version = 4, 5234 .props = (PropValue[]) { 5235 { "model-id", 5236 "AMD EPYC-v4 Processor" }, 5237 { /* end of list */ } 5238 }, 5239 .cache_info = &epyc_v4_cache_info 5240 }, 5241 { /* end of list */ } 5242 } 5243 }, 5244 { 5245 .name = "Dhyana", 5246 .level = 0xd, 5247 .vendor = CPUID_VENDOR_HYGON, 5248 .family = 24, 5249 .model = 0, 5250 .stepping = 1, 5251 .features[FEAT_1_EDX] = 5252 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5253 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5254 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5255 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5256 CPUID_VME | CPUID_FP87, 5257 .features[FEAT_1_ECX] = 5258 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5259 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5260 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5261 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5262 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5263 .features[FEAT_8000_0001_EDX] = 5264 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5265 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5266 CPUID_EXT2_SYSCALL, 5267 .features[FEAT_8000_0001_ECX] = 5268 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5269 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5270 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5271 CPUID_EXT3_TOPOEXT, 5272 .features[FEAT_8000_0008_EBX] = 5273 CPUID_8000_0008_EBX_IBPB, 5274 .features[FEAT_7_0_EBX] = 5275 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5276 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5277 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5278 /* XSAVES is added in version 2 */ 5279 .features[FEAT_XSAVE] = 5280 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5281 CPUID_XSAVE_XGETBV1, 5282 .features[FEAT_6_EAX] = 5283 CPUID_6_EAX_ARAT, 5284 .features[FEAT_SVM] = 5285 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5286 .xlevel = 0x8000001E, 5287 .model_id = "Hygon Dhyana Processor", 5288 .cache_info = &epyc_cache_info, 5289 .versions = (X86CPUVersionDefinition[]) { 5290 { .version = 1 }, 5291 { .version = 2, 5292 .note = "XSAVES", 5293 .props = (PropValue[]) { 5294 { "xsaves", "on" }, 5295 { /* end of list */ } 5296 }, 5297 }, 5298 { /* end of list */ } 5299 } 5300 }, 5301 { 5302 .name = "EPYC-Rome", 5303 .level = 0xd, 5304 .vendor = CPUID_VENDOR_AMD, 5305 .family = 23, 5306 .model = 49, 5307 .stepping = 0, 5308 .features[FEAT_1_EDX] = 5309 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5310 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5311 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5312 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5313 CPUID_VME | CPUID_FP87, 5314 .features[FEAT_1_ECX] = 5315 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5316 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5317 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5318 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5319 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5320 .features[FEAT_8000_0001_EDX] = 5321 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5322 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5323 CPUID_EXT2_SYSCALL, 5324 .features[FEAT_8000_0001_ECX] = 5325 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5326 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5327 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5328 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5329 .features[FEAT_8000_0008_EBX] = 5330 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5331 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5332 CPUID_8000_0008_EBX_STIBP, 5333 .features[FEAT_7_0_EBX] = 5334 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5335 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5336 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5337 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5338 .features[FEAT_7_0_ECX] = 5339 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5340 .features[FEAT_XSAVE] = 5341 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5342 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5343 .features[FEAT_6_EAX] = 5344 CPUID_6_EAX_ARAT, 5345 .features[FEAT_SVM] = 5346 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5347 .xlevel = 0x8000001E, 5348 .model_id = "AMD EPYC-Rome Processor", 5349 .cache_info = &epyc_rome_cache_info, 5350 .versions = (X86CPUVersionDefinition[]) { 5351 { .version = 1 }, 5352 { 5353 .version = 2, 5354 .props = (PropValue[]) { 5355 { "ibrs", "on" }, 5356 { "amd-ssbd", "on" }, 5357 { /* end of list */ } 5358 } 5359 }, 5360 { 5361 .version = 3, 5362 .props = (PropValue[]) { 5363 { "model-id", 5364 "AMD EPYC-Rome-v3 Processor" }, 5365 { /* end of list */ } 5366 }, 5367 .cache_info = &epyc_rome_v3_cache_info 5368 }, 5369 { 5370 .version = 4, 5371 .props = (PropValue[]) { 5372 /* Erratum 1386 */ 5373 { "model-id", 5374 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5375 { "xsaves", "off" }, 5376 { /* end of list */ } 5377 }, 5378 }, 5379 { /* end of list */ } 5380 } 5381 }, 5382 { 5383 .name = "EPYC-Milan", 5384 .level = 0xd, 5385 .vendor = CPUID_VENDOR_AMD, 5386 .family = 25, 5387 .model = 1, 5388 .stepping = 1, 5389 .features[FEAT_1_EDX] = 5390 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5391 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5392 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5393 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5394 CPUID_VME | CPUID_FP87, 5395 .features[FEAT_1_ECX] = 5396 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5397 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5398 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5399 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5400 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5401 CPUID_EXT_PCID, 5402 .features[FEAT_8000_0001_EDX] = 5403 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5404 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5405 CPUID_EXT2_SYSCALL, 5406 .features[FEAT_8000_0001_ECX] = 5407 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5408 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5409 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5410 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5411 .features[FEAT_8000_0008_EBX] = 5412 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5413 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5414 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5415 CPUID_8000_0008_EBX_AMD_SSBD, 5416 .features[FEAT_7_0_EBX] = 5417 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5418 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5419 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5420 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5421 CPUID_7_0_EBX_INVPCID, 5422 .features[FEAT_7_0_ECX] = 5423 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5424 .features[FEAT_7_0_EDX] = 5425 CPUID_7_0_EDX_FSRM, 5426 .features[FEAT_XSAVE] = 5427 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5428 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5429 .features[FEAT_6_EAX] = 5430 CPUID_6_EAX_ARAT, 5431 .features[FEAT_SVM] = 5432 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5433 .xlevel = 0x8000001E, 5434 .model_id = "AMD EPYC-Milan Processor", 5435 .cache_info = &epyc_milan_cache_info, 5436 .versions = (X86CPUVersionDefinition[]) { 5437 { .version = 1 }, 5438 { 5439 .version = 2, 5440 .props = (PropValue[]) { 5441 { "model-id", 5442 "AMD EPYC-Milan-v2 Processor" }, 5443 { "vaes", "on" }, 5444 { "vpclmulqdq", "on" }, 5445 { "stibp-always-on", "on" }, 5446 { "amd-psfd", "on" }, 5447 { "no-nested-data-bp", "on" }, 5448 { "lfence-always-serializing", "on" }, 5449 { "null-sel-clr-base", "on" }, 5450 { /* end of list */ } 5451 }, 5452 .cache_info = &epyc_milan_v2_cache_info 5453 }, 5454 { /* end of list */ } 5455 } 5456 }, 5457 { 5458 .name = "EPYC-Genoa", 5459 .level = 0xd, 5460 .vendor = CPUID_VENDOR_AMD, 5461 .family = 25, 5462 .model = 17, 5463 .stepping = 0, 5464 .features[FEAT_1_EDX] = 5465 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5466 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5467 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5468 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5469 CPUID_VME | CPUID_FP87, 5470 .features[FEAT_1_ECX] = 5471 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5472 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5473 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5474 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5475 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5476 CPUID_EXT_SSE3, 5477 .features[FEAT_8000_0001_EDX] = 5478 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5479 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5480 CPUID_EXT2_SYSCALL, 5481 .features[FEAT_8000_0001_ECX] = 5482 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5483 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5484 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5485 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5486 .features[FEAT_8000_0008_EBX] = 5487 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5488 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5489 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5490 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5491 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5492 .features[FEAT_8000_0021_EAX] = 5493 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5494 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5495 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5496 CPUID_8000_0021_EAX_AUTO_IBRS, 5497 .features[FEAT_7_0_EBX] = 5498 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5499 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5500 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5501 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5502 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5503 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5504 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5505 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5506 .features[FEAT_7_0_ECX] = 5507 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5508 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5509 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5510 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5511 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5512 CPUID_7_0_ECX_RDPID, 5513 .features[FEAT_7_0_EDX] = 5514 CPUID_7_0_EDX_FSRM, 5515 .features[FEAT_7_1_EAX] = 5516 CPUID_7_1_EAX_AVX512_BF16, 5517 .features[FEAT_XSAVE] = 5518 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5519 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5520 .features[FEAT_6_EAX] = 5521 CPUID_6_EAX_ARAT, 5522 .features[FEAT_SVM] = 5523 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5524 CPUID_SVM_SVME_ADDR_CHK, 5525 .xlevel = 0x80000022, 5526 .model_id = "AMD EPYC-Genoa Processor", 5527 .cache_info = &epyc_genoa_cache_info, 5528 }, 5529 { 5530 .name = "YongFeng", 5531 .level = 0x1F, 5532 .vendor = CPUID_VENDOR_ZHAOXIN1, 5533 .family = 7, 5534 .model = 11, 5535 .stepping = 3, 5536 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 5537 .features[FEAT_1_EDX] = 5538 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5539 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5540 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5541 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5542 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 5543 /* 5544 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 5545 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 5546 */ 5547 .features[FEAT_1_ECX] = 5548 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5549 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 5550 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 5551 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 5552 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5553 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5554 .features[FEAT_7_0_EBX] = 5555 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 5556 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 5557 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 5558 CPUID_7_0_EBX_FSGSBASE, 5559 /* missing: CPUID_7_0_ECX_OSPKE */ 5560 .features[FEAT_7_0_ECX] = 5561 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 5562 .features[FEAT_7_0_EDX] = 5563 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 5564 .features[FEAT_8000_0001_EDX] = 5565 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5566 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5567 .features[FEAT_8000_0001_ECX] = 5568 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 5569 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 5570 /* 5571 * TODO: When the Linux kernel introduces other existing definitions 5572 * for this leaf, remember to update the definitions here. 5573 */ 5574 .features[FEAT_C000_0001_EDX] = 5575 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 5576 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 5577 CPUID_C000_0001_EDX_ACE2 | 5578 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 5579 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 5580 .features[FEAT_XSAVE] = 5581 CPUID_XSAVE_XSAVEOPT, 5582 .features[FEAT_ARCH_CAPABILITIES] = 5583 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 5584 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 5585 MSR_ARCH_CAP_SSB_NO, 5586 .features[FEAT_VMX_PROCBASED_CTLS] = 5587 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 5588 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 5589 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 5590 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 5591 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 5592 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 5593 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 5594 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5595 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 5596 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5597 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5598 /* 5599 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 5600 * VMX_SECONDARY_EXEC_TSC_SCALING 5601 */ 5602 .features[FEAT_VMX_SECONDARY_CTLS] = 5603 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5604 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5605 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 5606 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5607 VMX_SECONDARY_EXEC_WBINVD_EXITING | 5608 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5609 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5610 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5611 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5612 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5613 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 5614 VMX_SECONDARY_EXEC_SHADOW_VMCS | 5615 VMX_SECONDARY_EXEC_ENABLE_PML, 5616 .features[FEAT_VMX_PINBASED_CTLS] = 5617 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5618 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5619 VMX_PIN_BASED_POSTED_INTR, 5620 .features[FEAT_VMX_EXIT_CTLS] = 5621 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 5622 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5623 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5624 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5625 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5626 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 5627 .features[FEAT_VMX_ENTRY_CTLS] = 5628 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5629 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5630 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5631 /* 5632 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 5633 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 5634 */ 5635 .features[FEAT_VMX_MISC] = 5636 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5637 MSR_VMX_MISC_VMWRITE_VMEXIT, 5638 /* missing: MSR_VMX_EPT_UC */ 5639 .features[FEAT_VMX_EPT_VPID_CAPS] = 5640 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5641 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5642 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5643 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5644 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 5645 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5646 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5647 .features[FEAT_VMX_BASIC] = 5648 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5649 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5650 .xlevel = 0x80000008, 5651 .model_id = "Zhaoxin YongFeng Processor", 5652 .versions = (X86CPUVersionDefinition[]) { 5653 { .version = 1 }, 5654 { 5655 .version = 2, 5656 .note = "with the correct model number", 5657 .props = (PropValue[]) { 5658 { "model", "0x5b" }, 5659 { /* end of list */ } 5660 } 5661 }, 5662 { /* end of list */ } 5663 } 5664 }, 5665 }; 5666 5667 /* 5668 * We resolve CPU model aliases using -v1 when using "-machine 5669 * none", but this is just for compatibility while libvirt isn't 5670 * adapted to resolve CPU model versions before creating VMs. 5671 * See "Runnability guarantee of CPU models" at 5672 * docs/about/deprecated.rst. 5673 */ 5674 X86CPUVersion default_cpu_version = 1; 5675 5676 void x86_cpu_set_default_version(X86CPUVersion version) 5677 { 5678 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5679 assert(version != CPU_VERSION_AUTO); 5680 default_cpu_version = version; 5681 } 5682 5683 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5684 { 5685 int v = 0; 5686 const X86CPUVersionDefinition *vdef = 5687 x86_cpu_def_get_versions(model->cpudef); 5688 while (vdef->version) { 5689 v = vdef->version; 5690 vdef++; 5691 } 5692 return v; 5693 } 5694 5695 /* Return the actual version being used for a specific CPU model */ 5696 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5697 { 5698 X86CPUVersion v = model->version; 5699 if (v == CPU_VERSION_AUTO) { 5700 v = default_cpu_version; 5701 } 5702 if (v == CPU_VERSION_LATEST) { 5703 return x86_cpu_model_last_version(model); 5704 } 5705 return v; 5706 } 5707 5708 static const Property max_x86_cpu_properties[] = { 5709 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5710 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5711 }; 5712 5713 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5714 { 5715 Object *obj = OBJECT(dev); 5716 5717 if (!object_property_get_int(obj, "family", &error_abort)) { 5718 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5719 object_property_set_int(obj, "family", 15, &error_abort); 5720 object_property_set_int(obj, "model", 107, &error_abort); 5721 object_property_set_int(obj, "stepping", 1, &error_abort); 5722 } else { 5723 object_property_set_int(obj, "family", 6, &error_abort); 5724 object_property_set_int(obj, "model", 6, &error_abort); 5725 object_property_set_int(obj, "stepping", 3, &error_abort); 5726 } 5727 } 5728 5729 x86_cpu_realizefn(dev, errp); 5730 } 5731 5732 static void max_x86_cpu_class_init(ObjectClass *oc, const void *data) 5733 { 5734 DeviceClass *dc = DEVICE_CLASS(oc); 5735 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5736 5737 xcc->ordering = 9; 5738 5739 xcc->model_description = 5740 "Enables all features supported by the accelerator in the current host"; 5741 5742 device_class_set_props(dc, max_x86_cpu_properties); 5743 dc->realize = max_x86_cpu_realize; 5744 } 5745 5746 static void max_x86_cpu_initfn(Object *obj) 5747 { 5748 X86CPU *cpu = X86_CPU(obj); 5749 5750 /* We can't fill the features array here because we don't know yet if 5751 * "migratable" is true or false. 5752 */ 5753 cpu->max_features = true; 5754 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5755 5756 /* 5757 * these defaults are used for TCG and all other accelerators 5758 * besides KVM and HVF, which overwrite these values 5759 */ 5760 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5761 &error_abort); 5762 object_property_set_str(OBJECT(cpu), "model-id", 5763 "QEMU TCG CPU version " QEMU_HW_VERSION, 5764 &error_abort); 5765 } 5766 5767 static const TypeInfo max_x86_cpu_type_info = { 5768 .name = X86_CPU_TYPE_NAME("max"), 5769 .parent = TYPE_X86_CPU, 5770 .instance_init = max_x86_cpu_initfn, 5771 .class_init = max_x86_cpu_class_init, 5772 }; 5773 5774 static char *feature_word_description(FeatureWordInfo *f) 5775 { 5776 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5777 5778 switch (f->type) { 5779 case CPUID_FEATURE_WORD: 5780 { 5781 const char *reg = get_register_name_32(f->cpuid.reg); 5782 assert(reg); 5783 if (!f->cpuid.needs_ecx) { 5784 return g_strdup_printf("CPUID[eax=%02Xh].%s", f->cpuid.eax, reg); 5785 } else { 5786 return g_strdup_printf("CPUID[eax=%02Xh,ecx=%02Xh].%s", 5787 f->cpuid.eax, f->cpuid.ecx, reg); 5788 } 5789 } 5790 case MSR_FEATURE_WORD: 5791 return g_strdup_printf("MSR(%02Xh)", 5792 f->msr.index); 5793 } 5794 5795 return NULL; 5796 } 5797 5798 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5799 { 5800 FeatureWord w; 5801 5802 for (w = 0; w < FEATURE_WORDS; w++) { 5803 if (cpu->filtered_features[w]) { 5804 return true; 5805 } 5806 } 5807 5808 return false; 5809 } 5810 5811 void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5812 const char *verbose_prefix) 5813 { 5814 CPUX86State *env = &cpu->env; 5815 FeatureWordInfo *f = &feature_word_info[w]; 5816 int i; 5817 g_autofree char *feat_word_str = feature_word_description(f); 5818 5819 if (!cpu->force_features) { 5820 env->features[w] &= ~mask; 5821 } 5822 cpu->filtered_features[w] |= mask; 5823 5824 if (!verbose_prefix) { 5825 return; 5826 } 5827 5828 for (i = 0; i < 64; ++i) { 5829 if ((1ULL << i) & mask) { 5830 warn_report("%s: %s%s%s [bit %d]", 5831 verbose_prefix, 5832 feat_word_str, 5833 f->feat_names[i] ? "." : "", 5834 f->feat_names[i] ? f->feat_names[i] : "", i); 5835 } 5836 } 5837 } 5838 5839 void mark_forced_on_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5840 const char *verbose_prefix) 5841 { 5842 CPUX86State *env = &cpu->env; 5843 FeatureWordInfo *f = &feature_word_info[w]; 5844 int i; 5845 5846 if (!cpu->force_features) { 5847 env->features[w] |= mask; 5848 } 5849 5850 cpu->forced_on_features[w] |= mask; 5851 5852 if (!verbose_prefix) { 5853 return; 5854 } 5855 5856 for (i = 0; i < 64; ++i) { 5857 if ((1ULL << i) & mask) { 5858 g_autofree char *feat_word_str = feature_word_description(f); 5859 warn_report("%s: %s%s%s [bit %d]", 5860 verbose_prefix, 5861 feat_word_str, 5862 f->feat_names[i] ? "." : "", 5863 f->feat_names[i] ? f->feat_names[i] : "", i); 5864 } 5865 } 5866 } 5867 5868 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5869 const char *name, void *opaque, 5870 Error **errp) 5871 { 5872 X86CPU *cpu = X86_CPU(obj); 5873 CPUX86State *env = &cpu->env; 5874 uint64_t value; 5875 5876 value = (env->cpuid_version >> 8) & 0xf; 5877 if (value == 0xf) { 5878 value += (env->cpuid_version >> 20) & 0xff; 5879 } 5880 visit_type_uint64(v, name, &value, errp); 5881 } 5882 5883 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5884 const char *name, void *opaque, 5885 Error **errp) 5886 { 5887 X86CPU *cpu = X86_CPU(obj); 5888 CPUX86State *env = &cpu->env; 5889 const uint64_t max = 0xff + 0xf; 5890 uint64_t value; 5891 5892 if (!visit_type_uint64(v, name, &value, errp)) { 5893 return; 5894 } 5895 if (value > max) { 5896 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5897 name ? name : "null", max); 5898 return; 5899 } 5900 5901 env->cpuid_version &= ~0xff00f00; 5902 if (value > 0x0f) { 5903 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5904 } else { 5905 env->cpuid_version |= value << 8; 5906 } 5907 } 5908 5909 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5910 const char *name, void *opaque, 5911 Error **errp) 5912 { 5913 X86CPU *cpu = X86_CPU(obj); 5914 CPUX86State *env = &cpu->env; 5915 uint64_t value; 5916 5917 value = (env->cpuid_version >> 4) & 0xf; 5918 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5919 visit_type_uint64(v, name, &value, errp); 5920 } 5921 5922 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5923 const char *name, void *opaque, 5924 Error **errp) 5925 { 5926 X86CPU *cpu = X86_CPU(obj); 5927 CPUX86State *env = &cpu->env; 5928 const uint64_t max = 0xff; 5929 uint64_t value; 5930 5931 if (!visit_type_uint64(v, name, &value, errp)) { 5932 return; 5933 } 5934 if (value > max) { 5935 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5936 name ? name : "null", max); 5937 return; 5938 } 5939 5940 env->cpuid_version &= ~0xf00f0; 5941 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5942 } 5943 5944 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5945 const char *name, void *opaque, 5946 Error **errp) 5947 { 5948 X86CPU *cpu = X86_CPU(obj); 5949 CPUX86State *env = &cpu->env; 5950 uint64_t value; 5951 5952 value = env->cpuid_version & 0xf; 5953 visit_type_uint64(v, name, &value, errp); 5954 } 5955 5956 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5957 const char *name, void *opaque, 5958 Error **errp) 5959 { 5960 X86CPU *cpu = X86_CPU(obj); 5961 CPUX86State *env = &cpu->env; 5962 const uint64_t max = 0xf; 5963 uint64_t value; 5964 5965 if (!visit_type_uint64(v, name, &value, errp)) { 5966 return; 5967 } 5968 if (value > max) { 5969 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5970 name ? name : "null", max); 5971 return; 5972 } 5973 5974 env->cpuid_version &= ~0xf; 5975 env->cpuid_version |= value & 0xf; 5976 } 5977 5978 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5979 { 5980 X86CPU *cpu = X86_CPU(obj); 5981 CPUX86State *env = &cpu->env; 5982 char *value; 5983 5984 value = g_malloc(CPUID_VENDOR_SZ + 1); 5985 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5986 env->cpuid_vendor3); 5987 return value; 5988 } 5989 5990 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5991 Error **errp) 5992 { 5993 X86CPU *cpu = X86_CPU(obj); 5994 CPUX86State *env = &cpu->env; 5995 int i; 5996 5997 if (strlen(value) != CPUID_VENDOR_SZ) { 5998 error_setg(errp, "value of property 'vendor' must consist of" 5999 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 6000 return; 6001 } 6002 6003 env->cpuid_vendor1 = 0; 6004 env->cpuid_vendor2 = 0; 6005 env->cpuid_vendor3 = 0; 6006 for (i = 0; i < 4; i++) { 6007 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 6008 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 6009 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 6010 } 6011 } 6012 6013 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 6014 { 6015 X86CPU *cpu = X86_CPU(obj); 6016 CPUX86State *env = &cpu->env; 6017 char *value; 6018 int i; 6019 6020 value = g_malloc(48 + 1); 6021 for (i = 0; i < 48; i++) { 6022 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 6023 } 6024 value[48] = '\0'; 6025 return value; 6026 } 6027 6028 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 6029 Error **errp) 6030 { 6031 X86CPU *cpu = X86_CPU(obj); 6032 CPUX86State *env = &cpu->env; 6033 int c, len, i; 6034 6035 if (model_id == NULL) { 6036 model_id = ""; 6037 } 6038 len = strlen(model_id); 6039 memset(env->cpuid_model, 0, 48); 6040 for (i = 0; i < 48; i++) { 6041 if (i >= len) { 6042 c = '\0'; 6043 } else { 6044 c = (uint8_t)model_id[i]; 6045 } 6046 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 6047 } 6048 } 6049 6050 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 6051 void *opaque, Error **errp) 6052 { 6053 X86CPU *cpu = X86_CPU(obj); 6054 int64_t value; 6055 6056 value = cpu->env.tsc_khz * 1000; 6057 visit_type_int(v, name, &value, errp); 6058 } 6059 6060 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 6061 void *opaque, Error **errp) 6062 { 6063 X86CPU *cpu = X86_CPU(obj); 6064 const int64_t max = INT64_MAX; 6065 int64_t value; 6066 6067 if (!visit_type_int(v, name, &value, errp)) { 6068 return; 6069 } 6070 if (value < 0 || value > max) { 6071 error_setg(errp, "parameter '%s' can be at most %" PRId64, 6072 name ? name : "null", max); 6073 return; 6074 } 6075 6076 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 6077 } 6078 6079 /* Generic getter for "feature-words" and "filtered-features" properties */ 6080 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 6081 const char *name, void *opaque, 6082 Error **errp) 6083 { 6084 uint64_t *array = (uint64_t *)opaque; 6085 FeatureWord w; 6086 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 6087 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 6088 X86CPUFeatureWordInfoList *list = NULL; 6089 6090 for (w = 0; w < FEATURE_WORDS; w++) { 6091 FeatureWordInfo *wi = &feature_word_info[w]; 6092 /* 6093 * We didn't have MSR features when "feature-words" was 6094 * introduced. Therefore skipped other type entries. 6095 */ 6096 if (wi->type != CPUID_FEATURE_WORD) { 6097 continue; 6098 } 6099 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 6100 qwi->cpuid_input_eax = wi->cpuid.eax; 6101 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 6102 qwi->cpuid_input_ecx = wi->cpuid.ecx; 6103 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 6104 qwi->features = array[w]; 6105 6106 /* List will be in reverse order, but order shouldn't matter */ 6107 list_entries[w].next = list; 6108 list_entries[w].value = &word_infos[w]; 6109 list = &list_entries[w]; 6110 } 6111 6112 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 6113 } 6114 6115 /* Convert all '_' in a feature string option name to '-', to make feature 6116 * name conform to QOM property naming rule, which uses '-' instead of '_'. 6117 */ 6118 static inline void feat2prop(char *s) 6119 { 6120 while ((s = strchr(s, '_'))) { 6121 *s = '-'; 6122 } 6123 } 6124 6125 /* Return the feature property name for a feature flag bit */ 6126 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 6127 { 6128 const char *name; 6129 /* XSAVE components are automatically enabled by other features, 6130 * so return the original feature name instead 6131 */ 6132 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 6133 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 6134 6135 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 6136 x86_ext_save_areas[comp].bits) { 6137 w = x86_ext_save_areas[comp].feature; 6138 bitnr = ctz32(x86_ext_save_areas[comp].bits); 6139 } 6140 } 6141 6142 assert(bitnr < 64); 6143 assert(w < FEATURE_WORDS); 6144 name = feature_word_info[w].feat_names[bitnr]; 6145 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 6146 return name; 6147 } 6148 6149 /* Compatibility hack to maintain legacy +-feat semantic, 6150 * where +-feat overwrites any feature set by 6151 * feat=on|feat even if the later is parsed after +-feat 6152 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 6153 */ 6154 static GList *plus_features, *minus_features; 6155 6156 static gint compare_string(gconstpointer a, gconstpointer b) 6157 { 6158 return g_strcmp0(a, b); 6159 } 6160 6161 /* Parse "+feature,-feature,feature=foo" CPU feature string 6162 */ 6163 static void x86_cpu_parse_featurestr(const char *typename, char *features, 6164 Error **errp) 6165 { 6166 char *featurestr; /* Single 'key=value" string being parsed */ 6167 static bool cpu_globals_initialized; 6168 bool ambiguous = false; 6169 6170 if (cpu_globals_initialized) { 6171 return; 6172 } 6173 cpu_globals_initialized = true; 6174 6175 if (!features) { 6176 return; 6177 } 6178 6179 for (featurestr = strtok(features, ","); 6180 featurestr; 6181 featurestr = strtok(NULL, ",")) { 6182 const char *name; 6183 const char *val = NULL; 6184 char *eq = NULL; 6185 char num[32]; 6186 GlobalProperty *prop; 6187 6188 /* Compatibility syntax: */ 6189 if (featurestr[0] == '+') { 6190 plus_features = g_list_append(plus_features, 6191 g_strdup(featurestr + 1)); 6192 continue; 6193 } else if (featurestr[0] == '-') { 6194 minus_features = g_list_append(minus_features, 6195 g_strdup(featurestr + 1)); 6196 continue; 6197 } 6198 6199 eq = strchr(featurestr, '='); 6200 if (eq) { 6201 *eq++ = 0; 6202 val = eq; 6203 } else { 6204 val = "on"; 6205 } 6206 6207 feat2prop(featurestr); 6208 name = featurestr; 6209 6210 if (g_list_find_custom(plus_features, name, compare_string)) { 6211 warn_report("Ambiguous CPU model string. " 6212 "Don't mix both \"+%s\" and \"%s=%s\"", 6213 name, name, val); 6214 ambiguous = true; 6215 } 6216 if (g_list_find_custom(minus_features, name, compare_string)) { 6217 warn_report("Ambiguous CPU model string. " 6218 "Don't mix both \"-%s\" and \"%s=%s\"", 6219 name, name, val); 6220 ambiguous = true; 6221 } 6222 6223 /* Special case: */ 6224 if (!strcmp(name, "tsc-freq")) { 6225 int ret; 6226 uint64_t tsc_freq; 6227 6228 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 6229 if (ret < 0 || tsc_freq > INT64_MAX) { 6230 error_setg(errp, "bad numerical value %s", val); 6231 return; 6232 } 6233 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 6234 val = num; 6235 name = "tsc-frequency"; 6236 } 6237 6238 prop = g_new0(typeof(*prop), 1); 6239 prop->driver = typename; 6240 prop->property = g_strdup(name); 6241 prop->value = g_strdup(val); 6242 qdev_prop_register_global(prop); 6243 } 6244 6245 if (ambiguous) { 6246 warn_report("Compatibility of ambiguous CPU model " 6247 "strings won't be kept on future QEMU versions"); 6248 } 6249 } 6250 6251 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 6252 6253 /* Build a list with the name of all features on a feature word array */ 6254 static void x86_cpu_list_feature_names(FeatureWordArray features, 6255 strList **list) 6256 { 6257 strList **tail = list; 6258 FeatureWord w; 6259 6260 for (w = 0; w < FEATURE_WORDS; w++) { 6261 uint64_t filtered = features[w]; 6262 int i; 6263 for (i = 0; i < 64; i++) { 6264 if (filtered & (1ULL << i)) { 6265 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 6266 } 6267 } 6268 } 6269 } 6270 6271 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 6272 const char *name, void *opaque, 6273 Error **errp) 6274 { 6275 X86CPU *xc = X86_CPU(obj); 6276 strList *result = NULL; 6277 6278 x86_cpu_list_feature_names(xc->filtered_features, &result); 6279 visit_type_strList(v, "unavailable-features", &result, errp); 6280 } 6281 6282 /* Print all cpuid feature names in featureset 6283 */ 6284 static void listflags(GList *features) 6285 { 6286 size_t len = 0; 6287 GList *tmp; 6288 6289 for (tmp = features; tmp; tmp = tmp->next) { 6290 const char *name = tmp->data; 6291 if ((len + strlen(name) + 1) >= 75) { 6292 qemu_printf("\n"); 6293 len = 0; 6294 } 6295 qemu_printf("%s%s", len == 0 ? " " : " ", name); 6296 len += strlen(name) + 1; 6297 } 6298 qemu_printf("\n"); 6299 } 6300 6301 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 6302 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d) 6303 { 6304 ObjectClass *class_a = (ObjectClass *)a; 6305 ObjectClass *class_b = (ObjectClass *)b; 6306 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 6307 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 6308 int ret; 6309 6310 if (cc_a->ordering != cc_b->ordering) { 6311 ret = cc_a->ordering - cc_b->ordering; 6312 } else { 6313 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 6314 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 6315 ret = strcmp(name_a, name_b); 6316 } 6317 return ret; 6318 } 6319 6320 static GSList *get_sorted_cpu_model_list(void) 6321 { 6322 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 6323 list = g_slist_sort_with_data(list, x86_cpu_list_compare, NULL); 6324 return list; 6325 } 6326 6327 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 6328 { 6329 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 6330 char *r = object_property_get_str(obj, "model-id", &error_abort); 6331 object_unref(obj); 6332 return r; 6333 } 6334 6335 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 6336 { 6337 X86CPUVersion version; 6338 6339 if (!cc->model || !cc->model->is_alias) { 6340 return NULL; 6341 } 6342 version = x86_cpu_model_resolve_version(cc->model); 6343 if (version <= 0) { 6344 return NULL; 6345 } 6346 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 6347 } 6348 6349 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 6350 { 6351 ObjectClass *oc = data; 6352 X86CPUClass *cc = X86_CPU_CLASS(oc); 6353 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6354 g_autofree char *desc = g_strdup(cc->model_description); 6355 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6356 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6357 6358 if (!desc && alias_of) { 6359 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6360 desc = g_strdup("(alias configured by machine type)"); 6361 } else { 6362 desc = g_strdup_printf("(alias of %s)", alias_of); 6363 } 6364 } 6365 if (!desc && cc->model && cc->model->note) { 6366 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6367 } 6368 if (!desc) { 6369 desc = g_strdup(model_id); 6370 } 6371 6372 if (cc->model && cc->model->cpudef->deprecation_note) { 6373 g_autofree char *olddesc = desc; 6374 desc = g_strdup_printf("%s (deprecated)", olddesc); 6375 } 6376 6377 qemu_printf(" %-20s %s\n", name, desc); 6378 } 6379 6380 static gint strcmp_wrap(gconstpointer a, gconstpointer b, gpointer d) 6381 { 6382 return strcmp(a, b); 6383 } 6384 6385 /* list available CPU models and flags */ 6386 static void x86_cpu_list(void) 6387 { 6388 int i, j; 6389 GSList *list; 6390 GList *names = NULL; 6391 6392 qemu_printf("Available CPUs:\n"); 6393 list = get_sorted_cpu_model_list(); 6394 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6395 g_slist_free(list); 6396 6397 names = NULL; 6398 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6399 FeatureWordInfo *fw = &feature_word_info[i]; 6400 for (j = 0; j < 64; j++) { 6401 if (fw->feat_names[j]) { 6402 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6403 } 6404 } 6405 } 6406 6407 names = g_list_sort_with_data(names, strcmp_wrap, NULL); 6408 6409 qemu_printf("\nRecognized CPUID flags:\n"); 6410 listflags(names); 6411 qemu_printf("\n"); 6412 g_list_free(names); 6413 } 6414 6415 #ifndef CONFIG_USER_ONLY 6416 6417 /* Check for missing features that may prevent the CPU class from 6418 * running using the current machine and accelerator. 6419 */ 6420 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6421 strList **list) 6422 { 6423 strList **tail = list; 6424 X86CPU *xc; 6425 Error *err = NULL; 6426 6427 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6428 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6429 return; 6430 } 6431 6432 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6433 6434 x86_cpu_expand_features(xc, &err); 6435 if (err) { 6436 /* Errors at x86_cpu_expand_features should never happen, 6437 * but in case it does, just report the model as not 6438 * runnable at all using the "type" property. 6439 */ 6440 QAPI_LIST_APPEND(tail, g_strdup("type")); 6441 error_free(err); 6442 } 6443 6444 x86_cpu_filter_features(xc, false); 6445 6446 x86_cpu_list_feature_names(xc->filtered_features, tail); 6447 6448 object_unref(OBJECT(xc)); 6449 } 6450 6451 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6452 { 6453 ObjectClass *oc = data; 6454 X86CPUClass *cc = X86_CPU_CLASS(oc); 6455 CpuDefinitionInfoList **cpu_list = user_data; 6456 CpuDefinitionInfo *info; 6457 6458 info = g_malloc0(sizeof(*info)); 6459 info->name = x86_cpu_class_get_model_name(cc); 6460 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6461 info->has_unavailable_features = true; 6462 info->q_typename = g_strdup(object_class_get_name(oc)); 6463 info->migration_safe = cc->migration_safe; 6464 info->has_migration_safe = true; 6465 info->q_static = cc->static_model; 6466 if (cc->model && cc->model->cpudef->deprecation_note) { 6467 info->deprecated = true; 6468 } else { 6469 info->deprecated = false; 6470 } 6471 /* 6472 * Old machine types won't report aliases, so that alias translation 6473 * doesn't break compatibility with previous QEMU versions. 6474 */ 6475 if (default_cpu_version != CPU_VERSION_LEGACY) { 6476 info->alias_of = x86_cpu_class_get_alias_of(cc); 6477 } 6478 6479 QAPI_LIST_PREPEND(*cpu_list, info); 6480 } 6481 6482 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6483 { 6484 CpuDefinitionInfoList *cpu_list = NULL; 6485 GSList *list = get_sorted_cpu_model_list(); 6486 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6487 g_slist_free(list); 6488 return cpu_list; 6489 } 6490 6491 #endif /* !CONFIG_USER_ONLY */ 6492 6493 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6494 { 6495 FeatureWordInfo *wi = &feature_word_info[w]; 6496 uint64_t r = 0; 6497 uint64_t unavail = 0; 6498 6499 if (kvm_enabled()) { 6500 switch (wi->type) { 6501 case CPUID_FEATURE_WORD: 6502 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6503 wi->cpuid.ecx, 6504 wi->cpuid.reg); 6505 break; 6506 case MSR_FEATURE_WORD: 6507 r = kvm_arch_get_supported_msr_feature(kvm_state, 6508 wi->msr.index); 6509 break; 6510 } 6511 } else if (hvf_enabled()) { 6512 if (wi->type != CPUID_FEATURE_WORD) { 6513 return 0; 6514 } 6515 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6516 wi->cpuid.ecx, 6517 wi->cpuid.reg); 6518 } else if (tcg_enabled()) { 6519 r = wi->tcg_features; 6520 } else { 6521 return ~0; 6522 } 6523 6524 switch (w) { 6525 #ifndef TARGET_X86_64 6526 case FEAT_8000_0001_EDX: 6527 /* 6528 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6529 * way for userspace to get out of its 32-bit jail, we can leave 6530 * the LM bit set. 6531 */ 6532 unavail = tcg_enabled() 6533 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6534 : CPUID_EXT2_LM; 6535 break; 6536 #endif 6537 6538 case FEAT_8000_0007_EBX: 6539 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6540 /* Disable AMD machine check architecture for Intel CPU. */ 6541 unavail = ~0; 6542 } 6543 break; 6544 6545 case FEAT_7_0_EBX: 6546 #ifndef CONFIG_USER_ONLY 6547 if (!check_sgx_support()) { 6548 unavail = CPUID_7_0_EBX_SGX; 6549 } 6550 #endif 6551 break; 6552 case FEAT_7_0_ECX: 6553 #ifndef CONFIG_USER_ONLY 6554 if (!check_sgx_support()) { 6555 unavail = CPUID_7_0_ECX_SGX_LC; 6556 } 6557 #endif 6558 break; 6559 6560 default: 6561 break; 6562 } 6563 6564 r &= ~unavail; 6565 if (cpu && cpu->migratable) { 6566 r &= x86_cpu_get_migratable_flags(cpu, w); 6567 } 6568 return r; 6569 } 6570 6571 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6572 uint32_t *eax, uint32_t *ebx, 6573 uint32_t *ecx, uint32_t *edx) 6574 { 6575 if (kvm_enabled()) { 6576 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6577 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6578 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6579 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6580 } else if (hvf_enabled()) { 6581 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6582 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6583 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6584 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6585 } else { 6586 *eax = 0; 6587 *ebx = 0; 6588 *ecx = 0; 6589 *edx = 0; 6590 } 6591 } 6592 6593 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6594 uint32_t *eax, uint32_t *ebx, 6595 uint32_t *ecx, uint32_t *edx) 6596 { 6597 uint32_t level, unused; 6598 6599 /* Only return valid host leaves. */ 6600 switch (func) { 6601 case 2: 6602 case 4: 6603 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6604 break; 6605 case 0x80000005: 6606 case 0x80000006: 6607 case 0x8000001d: 6608 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6609 break; 6610 default: 6611 return; 6612 } 6613 6614 if (func > level) { 6615 *eax = 0; 6616 *ebx = 0; 6617 *ecx = 0; 6618 *edx = 0; 6619 } else { 6620 host_cpuid(func, index, eax, ebx, ecx, edx); 6621 } 6622 } 6623 6624 /* 6625 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6626 */ 6627 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6628 { 6629 PropValue *pv; 6630 for (pv = props; pv->prop; pv++) { 6631 if (!pv->value) { 6632 continue; 6633 } 6634 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6635 &error_abort); 6636 } 6637 } 6638 6639 /* 6640 * Apply properties for the CPU model version specified in model. 6641 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6642 */ 6643 6644 static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) 6645 { 6646 const X86CPUVersionDefinition *vdef; 6647 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6648 6649 if (version == CPU_VERSION_LEGACY) { 6650 return; 6651 } 6652 6653 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6654 PropValue *p; 6655 6656 for (p = vdef->props; p && p->prop; p++) { 6657 object_property_parse(OBJECT(cpu), p->prop, p->value, 6658 &error_abort); 6659 } 6660 6661 if (vdef->version == version) { 6662 break; 6663 } 6664 } 6665 6666 /* 6667 * If we reached the end of the list, version number was invalid 6668 */ 6669 assert(vdef->version == version); 6670 } 6671 6672 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6673 const X86CPUModel *model) 6674 { 6675 const X86CPUVersionDefinition *vdef; 6676 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6677 const CPUCaches *cache_info = model->cpudef->cache_info; 6678 6679 if (version == CPU_VERSION_LEGACY) { 6680 return cache_info; 6681 } 6682 6683 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6684 if (vdef->cache_info) { 6685 cache_info = vdef->cache_info; 6686 } 6687 6688 if (vdef->version == version) { 6689 break; 6690 } 6691 } 6692 6693 assert(vdef->version == version); 6694 return cache_info; 6695 } 6696 6697 /* 6698 * Load data from X86CPUDefinition into a X86CPU object. 6699 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6700 */ 6701 static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) 6702 { 6703 const X86CPUDefinition *def = model->cpudef; 6704 CPUX86State *env = &cpu->env; 6705 FeatureWord w; 6706 6707 /*NOTE: any property set by this function should be returned by 6708 * x86_cpu_static_props(), so static expansion of 6709 * query-cpu-model-expansion is always complete. 6710 */ 6711 6712 /* CPU models only set _minimum_ values for level/xlevel: */ 6713 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6714 &error_abort); 6715 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6716 &error_abort); 6717 6718 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6719 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6720 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6721 &error_abort); 6722 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6723 &error_abort); 6724 for (w = 0; w < FEATURE_WORDS; w++) { 6725 env->features[w] = def->features[w]; 6726 } 6727 6728 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6729 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6730 6731 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6732 6733 /* sysenter isn't supported in compatibility mode on AMD, 6734 * syscall isn't supported in compatibility mode on Intel. 6735 * Normally we advertise the actual CPU vendor, but you can 6736 * override this using the 'vendor' property if you want to use 6737 * KVM's sysenter/syscall emulation in compatibility mode and 6738 * when doing cross vendor migration 6739 */ 6740 6741 /* 6742 * vendor property is set here but then overloaded with the 6743 * host cpu vendor for KVM and HVF. 6744 */ 6745 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6746 6747 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 6748 &error_abort); 6749 6750 x86_cpu_apply_version_props(cpu, model); 6751 6752 /* 6753 * Properties in versioned CPU model are not user specified features. 6754 * We can simply clear env->user_features here since it will be filled later 6755 * in x86_cpu_expand_features() based on plus_features and minus_features. 6756 */ 6757 memset(&env->user_features, 0, sizeof(env->user_features)); 6758 } 6759 6760 static const gchar *x86_gdb_arch_name(CPUState *cs) 6761 { 6762 #ifdef TARGET_X86_64 6763 return "i386:x86-64"; 6764 #else 6765 return "i386"; 6766 #endif 6767 } 6768 6769 static void x86_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 6770 { 6771 const X86CPUModel *model = data; 6772 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6773 CPUClass *cc = CPU_CLASS(oc); 6774 6775 xcc->model = model; 6776 xcc->migration_safe = true; 6777 cc->deprecation_note = model->cpudef->deprecation_note; 6778 } 6779 6780 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6781 { 6782 g_autofree char *typename = x86_cpu_type_name(name); 6783 TypeInfo ti = { 6784 .name = typename, 6785 .parent = TYPE_X86_CPU, 6786 .class_init = x86_cpu_cpudef_class_init, 6787 .class_data = model, 6788 }; 6789 6790 type_register_static(&ti); 6791 } 6792 6793 6794 /* 6795 * register builtin_x86_defs; 6796 * "max", "base" and subclasses ("host") are not registered here. 6797 * See x86_cpu_register_types for all model registrations. 6798 */ 6799 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6800 { 6801 X86CPUModel *m; 6802 const X86CPUVersionDefinition *vdef; 6803 6804 /* AMD aliases are handled at runtime based on CPUID vendor, so 6805 * they shouldn't be set on the CPU model table. 6806 */ 6807 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6808 /* catch mistakes instead of silently truncating model_id when too long */ 6809 assert(def->model_id && strlen(def->model_id) <= 48); 6810 6811 /* Unversioned model: */ 6812 m = g_new0(X86CPUModel, 1); 6813 m->cpudef = def; 6814 m->version = CPU_VERSION_AUTO; 6815 m->is_alias = true; 6816 x86_register_cpu_model_type(def->name, m); 6817 6818 /* Versioned models: */ 6819 6820 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6821 g_autofree char *name = 6822 x86_cpu_versioned_model_name(def, vdef->version); 6823 6824 m = g_new0(X86CPUModel, 1); 6825 m->cpudef = def; 6826 m->version = vdef->version; 6827 m->note = vdef->note; 6828 x86_register_cpu_model_type(name, m); 6829 6830 if (vdef->alias) { 6831 X86CPUModel *am = g_new0(X86CPUModel, 1); 6832 am->cpudef = def; 6833 am->version = vdef->version; 6834 am->is_alias = true; 6835 x86_register_cpu_model_type(vdef->alias, am); 6836 } 6837 } 6838 6839 } 6840 6841 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6842 { 6843 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6844 return 57; /* 57 bits virtual */ 6845 } else { 6846 return 48; /* 48 bits virtual */ 6847 } 6848 } 6849 6850 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6851 uint32_t *eax, uint32_t *ebx, 6852 uint32_t *ecx, uint32_t *edx) 6853 { 6854 X86CPU *cpu = env_archcpu(env); 6855 CPUState *cs = env_cpu(env); 6856 uint32_t limit; 6857 uint32_t signature[3]; 6858 X86CPUTopoInfo *topo_info = &env->topo_info; 6859 uint32_t threads_per_pkg; 6860 6861 threads_per_pkg = x86_threads_per_pkg(topo_info); 6862 6863 /* Calculate & apply limits for different index ranges */ 6864 if (index >= 0xC0000000) { 6865 limit = env->cpuid_xlevel2; 6866 } else if (index >= 0x80000000) { 6867 limit = env->cpuid_xlevel; 6868 } else if (index >= 0x40000000) { 6869 limit = 0x40000001; 6870 } else { 6871 limit = env->cpuid_level; 6872 } 6873 6874 if (index > limit) { 6875 /* Intel documentation states that invalid EAX input will 6876 * return the same information as EAX=cpuid_level 6877 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6878 */ 6879 index = env->cpuid_level; 6880 } 6881 6882 switch(index) { 6883 case 0: 6884 *eax = env->cpuid_level; 6885 *ebx = env->cpuid_vendor1; 6886 *edx = env->cpuid_vendor2; 6887 *ecx = env->cpuid_vendor3; 6888 break; 6889 case 1: 6890 *eax = env->cpuid_version; 6891 *ebx = (cpu->apic_id << 24) | 6892 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6893 *ecx = env->features[FEAT_1_ECX]; 6894 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6895 *ecx |= CPUID_EXT_OSXSAVE; 6896 } 6897 *edx = env->features[FEAT_1_EDX]; 6898 if (threads_per_pkg > 1) { 6899 *ebx |= threads_per_pkg << 16; 6900 } 6901 if (!cpu->enable_pmu) { 6902 *ecx &= ~CPUID_EXT_PDCM; 6903 } 6904 break; 6905 case 2: 6906 /* cache info: needed for Pentium Pro compatibility */ 6907 if (cpu->cache_info_passthrough) { 6908 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6909 break; 6910 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6911 *eax = *ebx = *ecx = *edx = 0; 6912 break; 6913 } 6914 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6915 *ebx = 0; 6916 if (!cpu->enable_l3_cache) { 6917 *ecx = 0; 6918 } else { 6919 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6920 } 6921 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6922 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6923 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6924 break; 6925 case 4: 6926 /* cache info: needed for Core compatibility */ 6927 if (cpu->cache_info_passthrough) { 6928 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6929 /* 6930 * QEMU has its own number of cores/logical cpus, 6931 * set 24..14, 31..26 bit to configured values 6932 */ 6933 if (*eax & 31) { 6934 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6935 6936 *eax &= ~0xFC000000; 6937 *eax |= max_core_ids_in_package(topo_info) << 26; 6938 if (host_vcpus_per_cache > threads_per_pkg) { 6939 *eax &= ~0x3FFC000; 6940 6941 /* Share the cache at package level. */ 6942 *eax |= max_thread_ids_for_cache(topo_info, 6943 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 6944 } 6945 } 6946 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6947 *eax = *ebx = *ecx = *edx = 0; 6948 } else { 6949 *eax = 0; 6950 6951 switch (count) { 6952 case 0: /* L1 dcache info */ 6953 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6954 topo_info, 6955 eax, ebx, ecx, edx); 6956 if (!cpu->l1_cache_per_core) { 6957 *eax &= ~MAKE_64BIT_MASK(14, 12); 6958 } 6959 break; 6960 case 1: /* L1 icache info */ 6961 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6962 topo_info, 6963 eax, ebx, ecx, edx); 6964 if (!cpu->l1_cache_per_core) { 6965 *eax &= ~MAKE_64BIT_MASK(14, 12); 6966 } 6967 break; 6968 case 2: /* L2 cache info */ 6969 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6970 topo_info, 6971 eax, ebx, ecx, edx); 6972 break; 6973 case 3: /* L3 cache info */ 6974 if (cpu->enable_l3_cache) { 6975 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6976 topo_info, 6977 eax, ebx, ecx, edx); 6978 break; 6979 } 6980 /* fall through */ 6981 default: /* end of info */ 6982 *eax = *ebx = *ecx = *edx = 0; 6983 break; 6984 } 6985 } 6986 break; 6987 case 5: 6988 /* MONITOR/MWAIT Leaf */ 6989 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6990 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6991 *ecx = cpu->mwait.ecx; /* flags */ 6992 *edx = cpu->mwait.edx; /* mwait substates */ 6993 break; 6994 case 6: 6995 /* Thermal and Power Leaf */ 6996 *eax = env->features[FEAT_6_EAX]; 6997 *ebx = 0; 6998 *ecx = 0; 6999 *edx = 0; 7000 break; 7001 case 7: 7002 /* Structured Extended Feature Flags Enumeration Leaf */ 7003 if (count == 0) { 7004 /* Maximum ECX value for sub-leaves */ 7005 *eax = env->cpuid_level_func7; 7006 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 7007 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 7008 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 7009 *ecx |= CPUID_7_0_ECX_OSPKE; 7010 } 7011 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 7012 } else if (count == 1) { 7013 *eax = env->features[FEAT_7_1_EAX]; 7014 *edx = env->features[FEAT_7_1_EDX]; 7015 *ebx = 0; 7016 *ecx = 0; 7017 } else if (count == 2) { 7018 *edx = env->features[FEAT_7_2_EDX]; 7019 *eax = 0; 7020 *ebx = 0; 7021 *ecx = 0; 7022 } else { 7023 *eax = 0; 7024 *ebx = 0; 7025 *ecx = 0; 7026 *edx = 0; 7027 } 7028 break; 7029 case 9: 7030 /* Direct Cache Access Information Leaf */ 7031 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 7032 *ebx = 0; 7033 *ecx = 0; 7034 *edx = 0; 7035 break; 7036 case 0xA: 7037 /* Architectural Performance Monitoring Leaf */ 7038 if (cpu->enable_pmu) { 7039 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 7040 } else { 7041 *eax = 0; 7042 *ebx = 0; 7043 *ecx = 0; 7044 *edx = 0; 7045 } 7046 break; 7047 case 0xB: 7048 /* Extended Topology Enumeration Leaf */ 7049 if (!cpu->enable_cpuid_0xb) { 7050 *eax = *ebx = *ecx = *edx = 0; 7051 break; 7052 } 7053 7054 *ecx = count & 0xff; 7055 *edx = cpu->apic_id; 7056 7057 switch (count) { 7058 case 0: 7059 *eax = apicid_core_offset(topo_info); 7060 *ebx = topo_info->threads_per_core; 7061 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 7062 break; 7063 case 1: 7064 *eax = apicid_pkg_offset(topo_info); 7065 *ebx = threads_per_pkg; 7066 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 7067 break; 7068 default: 7069 *eax = 0; 7070 *ebx = 0; 7071 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 7072 } 7073 7074 assert(!(*eax & ~0x1f)); 7075 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 7076 break; 7077 case 0x1C: 7078 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7079 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 7080 *edx = 0; 7081 } 7082 break; 7083 case 0x1F: 7084 /* V2 Extended Topology Enumeration Leaf */ 7085 if (!x86_has_cpuid_0x1f(cpu)) { 7086 *eax = *ebx = *ecx = *edx = 0; 7087 break; 7088 } 7089 7090 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 7091 break; 7092 case 0xD: { 7093 /* Processor Extended State */ 7094 *eax = 0; 7095 *ebx = 0; 7096 *ecx = 0; 7097 *edx = 0; 7098 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7099 break; 7100 } 7101 7102 if (count == 0) { 7103 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 7104 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 7105 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 7106 /* 7107 * The initial value of xcr0 and ebx == 0, On host without kvm 7108 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 7109 * even through guest update xcr0, this will crash some legacy guest 7110 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 7111 */ 7112 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 7113 } else if (count == 1) { 7114 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 7115 x86_cpu_xsave_xss_components(cpu); 7116 7117 *eax = env->features[FEAT_XSAVE]; 7118 *ebx = xsave_area_size(xstate, true); 7119 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 7120 *edx = env->features[FEAT_XSAVE_XSS_HI]; 7121 if (kvm_enabled() && cpu->enable_pmu && 7122 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 7123 (*eax & CPUID_XSAVE_XSAVES)) { 7124 *ecx |= XSTATE_ARCH_LBR_MASK; 7125 } else { 7126 *ecx &= ~XSTATE_ARCH_LBR_MASK; 7127 } 7128 } else if (count == 0xf && cpu->enable_pmu 7129 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7130 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 7131 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 7132 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 7133 7134 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 7135 *eax = esa->size; 7136 *ebx = esa->offset; 7137 *ecx = esa->ecx & 7138 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 7139 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 7140 *eax = esa->size; 7141 *ebx = 0; 7142 *ecx = 1; 7143 } 7144 } 7145 break; 7146 } 7147 case 0x12: 7148 #ifndef CONFIG_USER_ONLY 7149 if (!kvm_enabled() || 7150 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 7151 *eax = *ebx = *ecx = *edx = 0; 7152 break; 7153 } 7154 7155 /* 7156 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 7157 * the EPC properties, e.g. confidentiality and integrity, from the 7158 * host's first EPC section, i.e. assume there is one EPC section or 7159 * that all EPC sections have the same security properties. 7160 */ 7161 if (count > 1) { 7162 uint64_t epc_addr, epc_size; 7163 7164 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 7165 *eax = *ebx = *ecx = *edx = 0; 7166 break; 7167 } 7168 host_cpuid(index, 2, eax, ebx, ecx, edx); 7169 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 7170 *ebx = (uint32_t)(epc_addr >> 32); 7171 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 7172 *edx = (uint32_t)(epc_size >> 32); 7173 break; 7174 } 7175 7176 /* 7177 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 7178 * and KVM, i.e. QEMU cannot emulate features to override what KVM 7179 * supports. Features can be further restricted by userspace, but not 7180 * made more permissive. 7181 */ 7182 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 7183 7184 if (count == 0) { 7185 *eax &= env->features[FEAT_SGX_12_0_EAX]; 7186 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 7187 } else { 7188 *eax &= env->features[FEAT_SGX_12_1_EAX]; 7189 *ebx &= 0; /* ebx reserve */ 7190 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 7191 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 7192 7193 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 7194 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 7195 7196 /* Access to PROVISIONKEY requires additional credentials. */ 7197 if ((*eax & (1U << 4)) && 7198 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 7199 *eax &= ~(1U << 4); 7200 } 7201 } 7202 #endif 7203 break; 7204 case 0x14: { 7205 /* Intel Processor Trace Enumeration */ 7206 *eax = 0; 7207 *ebx = 0; 7208 *ecx = 0; 7209 *edx = 0; 7210 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 7211 !kvm_enabled()) { 7212 break; 7213 } 7214 7215 /* 7216 * If these are changed, they should stay in sync with 7217 * x86_cpu_filter_features(). 7218 */ 7219 if (count == 0) { 7220 *eax = INTEL_PT_MAX_SUBLEAF; 7221 *ebx = INTEL_PT_MINIMAL_EBX; 7222 *ecx = INTEL_PT_MINIMAL_ECX; 7223 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 7224 *ecx |= CPUID_14_0_ECX_LIP; 7225 } 7226 } else if (count == 1) { 7227 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 7228 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 7229 } 7230 break; 7231 } 7232 case 0x1D: { 7233 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 7234 *eax = 0; 7235 *ebx = 0; 7236 *ecx = 0; 7237 *edx = 0; 7238 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7239 break; 7240 } 7241 7242 if (count == 0) { 7243 /* Highest numbered palette subleaf */ 7244 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 7245 } else if (count == 1) { 7246 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 7247 (INTEL_AMX_BYTES_PER_TILE << 16); 7248 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 7249 *ecx = INTEL_AMX_TILE_MAX_ROWS; 7250 } 7251 break; 7252 } 7253 case 0x1E: { 7254 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 7255 *eax = 0; 7256 *ebx = 0; 7257 *ecx = 0; 7258 *edx = 0; 7259 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7260 break; 7261 } 7262 7263 if (count == 0) { 7264 /* Highest numbered palette subleaf */ 7265 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 7266 } 7267 break; 7268 } 7269 case 0x24: { 7270 *eax = 0; 7271 *ebx = 0; 7272 *ecx = 0; 7273 *edx = 0; 7274 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 7275 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 7276 } 7277 break; 7278 } 7279 case 0x40000000: 7280 /* 7281 * CPUID code in kvm_arch_init_vcpu() ignores stuff 7282 * set here, but we restrict to TCG none the less. 7283 */ 7284 if (tcg_enabled() && cpu->expose_tcg) { 7285 memcpy(signature, "TCGTCGTCGTCG", 12); 7286 *eax = 0x40000001; 7287 *ebx = signature[0]; 7288 *ecx = signature[1]; 7289 *edx = signature[2]; 7290 } else { 7291 *eax = 0; 7292 *ebx = 0; 7293 *ecx = 0; 7294 *edx = 0; 7295 } 7296 break; 7297 case 0x40000001: 7298 *eax = 0; 7299 *ebx = 0; 7300 *ecx = 0; 7301 *edx = 0; 7302 break; 7303 case 0x80000000: 7304 *eax = env->cpuid_xlevel; 7305 *ebx = env->cpuid_vendor1; 7306 *edx = env->cpuid_vendor2; 7307 *ecx = env->cpuid_vendor3; 7308 break; 7309 case 0x80000001: 7310 *eax = env->cpuid_version; 7311 *ebx = 0; 7312 *ecx = env->features[FEAT_8000_0001_ECX]; 7313 *edx = env->features[FEAT_8000_0001_EDX]; 7314 7315 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 7316 !(env->hflags & HF_LMA_MASK)) { 7317 *edx &= ~CPUID_EXT2_SYSCALL; 7318 } 7319 break; 7320 case 0x80000002: 7321 case 0x80000003: 7322 case 0x80000004: 7323 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 7324 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 7325 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 7326 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 7327 break; 7328 case 0x80000005: 7329 /* cache info (L1 cache) */ 7330 if (cpu->cache_info_passthrough) { 7331 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7332 break; 7333 } 7334 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 7335 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 7336 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 7337 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7338 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7339 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7340 break; 7341 case 0x80000006: 7342 /* cache info (L2 cache) */ 7343 if (cpu->cache_info_passthrough) { 7344 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7345 break; 7346 } 7347 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7348 (L2_DTLB_2M_ENTRIES << 16) | 7349 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7350 (L2_ITLB_2M_ENTRIES); 7351 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7352 (L2_DTLB_4K_ENTRIES << 16) | 7353 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7354 (L2_ITLB_4K_ENTRIES); 7355 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7356 cpu->enable_l3_cache ? 7357 env->cache_info_amd.l3_cache : NULL, 7358 ecx, edx); 7359 break; 7360 case 0x80000007: 7361 *eax = 0; 7362 *ebx = env->features[FEAT_8000_0007_EBX]; 7363 *ecx = 0; 7364 *edx = env->features[FEAT_8000_0007_EDX]; 7365 break; 7366 case 0x80000008: 7367 /* virtual & phys address size in low 2 bytes. */ 7368 *eax = cpu->phys_bits; 7369 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7370 /* 64 bit processor */ 7371 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7372 *eax |= (cpu->guest_phys_bits << 16); 7373 } 7374 *ebx = env->features[FEAT_8000_0008_EBX]; 7375 if (threads_per_pkg > 1) { 7376 /* 7377 * Bits 15:12 is "The number of bits in the initial 7378 * Core::X86::Apic::ApicId[ApicId] value that indicate 7379 * thread ID within a package". 7380 * Bits 7:0 is "The number of threads in the package is NC+1" 7381 */ 7382 *ecx = (apicid_pkg_offset(topo_info) << 12) | 7383 (threads_per_pkg - 1); 7384 } else { 7385 *ecx = 0; 7386 } 7387 *edx = 0; 7388 break; 7389 case 0x8000000A: 7390 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7391 *eax = 0x00000001; /* SVM Revision */ 7392 *ebx = 0x00000010; /* nr of ASIDs */ 7393 *ecx = 0; 7394 *edx = env->features[FEAT_SVM]; /* optional features */ 7395 } else { 7396 *eax = 0; 7397 *ebx = 0; 7398 *ecx = 0; 7399 *edx = 0; 7400 } 7401 break; 7402 case 0x8000001D: 7403 *eax = 0; 7404 if (cpu->cache_info_passthrough) { 7405 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7406 break; 7407 } 7408 switch (count) { 7409 case 0: /* L1 dcache info */ 7410 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7411 topo_info, eax, ebx, ecx, edx); 7412 break; 7413 case 1: /* L1 icache info */ 7414 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7415 topo_info, eax, ebx, ecx, edx); 7416 break; 7417 case 2: /* L2 cache info */ 7418 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7419 topo_info, eax, ebx, ecx, edx); 7420 break; 7421 case 3: /* L3 cache info */ 7422 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7423 topo_info, eax, ebx, ecx, edx); 7424 break; 7425 default: /* end of info */ 7426 *eax = *ebx = *ecx = *edx = 0; 7427 break; 7428 } 7429 if (cpu->amd_topoext_features_only) { 7430 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7431 } 7432 break; 7433 case 0x8000001E: 7434 if (cpu->core_id <= 255) { 7435 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 7436 } else { 7437 *eax = 0; 7438 *ebx = 0; 7439 *ecx = 0; 7440 *edx = 0; 7441 } 7442 break; 7443 case 0x80000022: 7444 *eax = *ebx = *ecx = *edx = 0; 7445 /* AMD Extended Performance Monitoring and Debug */ 7446 if (kvm_enabled() && cpu->enable_pmu && 7447 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7448 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7449 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7450 R_EBX) & 0xf; 7451 } 7452 break; 7453 case 0xC0000000: 7454 *eax = env->cpuid_xlevel2; 7455 *ebx = 0; 7456 *ecx = 0; 7457 *edx = 0; 7458 break; 7459 case 0xC0000001: 7460 /* Support for VIA CPU's CPUID instruction */ 7461 *eax = env->cpuid_version; 7462 *ebx = 0; 7463 *ecx = 0; 7464 *edx = env->features[FEAT_C000_0001_EDX]; 7465 break; 7466 case 0xC0000002: 7467 case 0xC0000003: 7468 case 0xC0000004: 7469 /* Reserved for the future, and now filled with zero */ 7470 *eax = 0; 7471 *ebx = 0; 7472 *ecx = 0; 7473 *edx = 0; 7474 break; 7475 case 0x8000001F: 7476 *eax = *ebx = *ecx = *edx = 0; 7477 if (sev_enabled()) { 7478 *eax = 0x2; 7479 *eax |= sev_es_enabled() ? 0x8 : 0; 7480 *eax |= sev_snp_enabled() ? 0x10 : 0; 7481 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7482 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7483 } 7484 break; 7485 case 0x80000021: 7486 *eax = *ebx = *ecx = *edx = 0; 7487 *eax = env->features[FEAT_8000_0021_EAX]; 7488 *ebx = env->features[FEAT_8000_0021_EBX]; 7489 break; 7490 default: 7491 /* reserved values: zero */ 7492 *eax = 0; 7493 *ebx = 0; 7494 *ecx = 0; 7495 *edx = 0; 7496 break; 7497 } 7498 } 7499 7500 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7501 { 7502 #ifndef CONFIG_USER_ONLY 7503 /* Those default values are defined in Skylake HW */ 7504 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7505 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7506 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7507 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7508 #endif 7509 } 7510 7511 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7512 { 7513 if (!esa->size) { 7514 return false; 7515 } 7516 7517 if (env->features[esa->feature] & esa->bits) { 7518 return true; 7519 } 7520 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7521 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7522 return true; 7523 } 7524 7525 return false; 7526 } 7527 7528 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7529 { 7530 CPUState *cs = CPU(obj); 7531 X86CPU *cpu = X86_CPU(cs); 7532 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7533 CPUX86State *env = &cpu->env; 7534 target_ulong cr4; 7535 uint64_t xcr0; 7536 int i; 7537 7538 if (xcc->parent_phases.hold) { 7539 xcc->parent_phases.hold(obj, type); 7540 } 7541 7542 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7543 7544 if (tcg_enabled()) { 7545 cpu_init_fp_statuses(env); 7546 } 7547 7548 env->old_exception = -1; 7549 7550 /* init to reset state */ 7551 env->int_ctl = 0; 7552 env->hflags2 |= HF2_GIF_MASK; 7553 env->hflags2 |= HF2_VGIF_MASK; 7554 env->hflags &= ~HF_GUEST_MASK; 7555 7556 cpu_x86_update_cr0(env, 0x60000010); 7557 env->a20_mask = ~0x0; 7558 env->smbase = 0x30000; 7559 env->msr_smi_count = 0; 7560 7561 env->idt.limit = 0xffff; 7562 env->gdt.limit = 0xffff; 7563 env->ldt.limit = 0xffff; 7564 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7565 env->tr.limit = 0xffff; 7566 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7567 7568 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7569 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7570 DESC_R_MASK | DESC_A_MASK); 7571 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7572 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7573 DESC_A_MASK); 7574 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7575 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7576 DESC_A_MASK); 7577 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7578 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7579 DESC_A_MASK); 7580 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7581 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7582 DESC_A_MASK); 7583 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7584 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7585 DESC_A_MASK); 7586 7587 env->eip = 0xfff0; 7588 env->regs[R_EDX] = env->cpuid_version; 7589 7590 env->eflags = 0x2; 7591 7592 /* FPU init */ 7593 for (i = 0; i < 8; i++) { 7594 env->fptags[i] = 1; 7595 } 7596 cpu_set_fpuc(env, 0x37f); 7597 7598 env->mxcsr = 0x1f80; 7599 /* All units are in INIT state. */ 7600 env->xstate_bv = 0; 7601 7602 env->pat = 0x0007040600070406ULL; 7603 7604 if (kvm_enabled()) { 7605 /* 7606 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7607 * a new CPU, use 1 instead to force a reset. 7608 */ 7609 if (env->tsc != 0) { 7610 env->tsc = 1; 7611 } 7612 } else { 7613 env->tsc = 0; 7614 } 7615 7616 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7617 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7618 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7619 } 7620 7621 memset(env->dr, 0, sizeof(env->dr)); 7622 env->dr[6] = DR6_FIXED_1; 7623 env->dr[7] = DR7_FIXED_1; 7624 cpu_breakpoint_remove_all(cs, BP_CPU); 7625 cpu_watchpoint_remove_all(cs, BP_CPU); 7626 7627 cr4 = 0; 7628 xcr0 = XSTATE_FP_MASK; 7629 7630 #ifdef CONFIG_USER_ONLY 7631 /* Enable all the features for user-mode. */ 7632 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7633 xcr0 |= XSTATE_SSE_MASK; 7634 } 7635 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7636 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7637 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7638 continue; 7639 } 7640 if (cpuid_has_xsave_feature(env, esa)) { 7641 xcr0 |= 1ull << i; 7642 } 7643 } 7644 7645 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7646 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7647 } 7648 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7649 cr4 |= CR4_FSGSBASE_MASK; 7650 } 7651 #endif 7652 7653 env->xcr0 = xcr0; 7654 cpu_x86_update_cr4(env, cr4); 7655 7656 /* 7657 * SDM 11.11.5 requires: 7658 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7659 * - IA32_MTRR_PHYSMASKn.V = 0 7660 * All other bits are undefined. For simplification, zero it all. 7661 */ 7662 env->mtrr_deftype = 0; 7663 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7664 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7665 7666 env->interrupt_injected = -1; 7667 env->exception_nr = -1; 7668 env->exception_pending = 0; 7669 env->exception_injected = 0; 7670 env->exception_has_payload = false; 7671 env->exception_payload = 0; 7672 env->nmi_injected = false; 7673 env->triple_fault_pending = false; 7674 #if !defined(CONFIG_USER_ONLY) 7675 /* We hard-wire the BSP to the first CPU. */ 7676 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7677 7678 cs->halted = !cpu_is_bsp(cpu); 7679 7680 if (kvm_enabled()) { 7681 kvm_arch_reset_vcpu(cpu); 7682 } 7683 7684 x86_cpu_set_sgxlepubkeyhash(env); 7685 7686 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7687 7688 #endif 7689 } 7690 7691 void x86_cpu_after_reset(X86CPU *cpu) 7692 { 7693 #ifndef CONFIG_USER_ONLY 7694 if (kvm_enabled()) { 7695 kvm_arch_after_reset_vcpu(cpu); 7696 } 7697 7698 if (cpu->apic_state) { 7699 device_cold_reset(cpu->apic_state); 7700 } 7701 #endif 7702 } 7703 7704 static void mce_init(X86CPU *cpu) 7705 { 7706 CPUX86State *cenv = &cpu->env; 7707 unsigned int bank; 7708 7709 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7710 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7711 (CPUID_MCE | CPUID_MCA)) { 7712 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7713 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7714 cenv->mcg_ctl = ~(uint64_t)0; 7715 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7716 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7717 } 7718 } 7719 } 7720 7721 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7722 { 7723 if (*min < value) { 7724 *min = value; 7725 } 7726 } 7727 7728 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7729 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7730 { 7731 CPUX86State *env = &cpu->env; 7732 FeatureWordInfo *fi = &feature_word_info[w]; 7733 uint32_t eax = fi->cpuid.eax; 7734 uint32_t region = eax & 0xF0000000; 7735 7736 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7737 if (!env->features[w]) { 7738 return; 7739 } 7740 7741 switch (region) { 7742 case 0x00000000: 7743 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7744 break; 7745 case 0x80000000: 7746 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7747 break; 7748 case 0xC0000000: 7749 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7750 break; 7751 } 7752 7753 if (eax == 7) { 7754 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7755 fi->cpuid.ecx); 7756 } 7757 } 7758 7759 /* Calculate XSAVE components based on the configured CPU feature flags */ 7760 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7761 { 7762 CPUX86State *env = &cpu->env; 7763 int i; 7764 uint64_t mask; 7765 static bool request_perm; 7766 7767 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7768 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7769 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7770 env->features[FEAT_XSAVE_XSS_LO] = 0; 7771 env->features[FEAT_XSAVE_XSS_HI] = 0; 7772 return; 7773 } 7774 7775 mask = 0; 7776 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7777 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7778 if (cpuid_has_xsave_feature(env, esa)) { 7779 mask |= (1ULL << i); 7780 } 7781 } 7782 7783 /* Only request permission for first vcpu */ 7784 if (kvm_enabled() && !request_perm) { 7785 kvm_request_xsave_components(cpu, mask); 7786 request_perm = true; 7787 } 7788 7789 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7790 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7791 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7792 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7793 } 7794 7795 /***** Steps involved on loading and filtering CPUID data 7796 * 7797 * When initializing and realizing a CPU object, the steps 7798 * involved in setting up CPUID data are: 7799 * 7800 * 1) Loading CPU model definition (X86CPUDefinition). This is 7801 * implemented by x86_cpu_load_model() and should be completely 7802 * transparent, as it is done automatically by instance_init. 7803 * No code should need to look at X86CPUDefinition structs 7804 * outside instance_init. 7805 * 7806 * 2) CPU expansion. This is done by realize before CPUID 7807 * filtering, and will make sure host/accelerator data is 7808 * loaded for CPU models that depend on host capabilities 7809 * (e.g. "host"). Done by x86_cpu_expand_features(). 7810 * 7811 * 3) CPUID filtering. This initializes extra data related to 7812 * CPUID, and checks if the host supports all capabilities 7813 * required by the CPU. Runnability of a CPU model is 7814 * determined at this step. Done by x86_cpu_filter_features(). 7815 * 7816 * Some operations don't require all steps to be performed. 7817 * More precisely: 7818 * 7819 * - CPU instance creation (instance_init) will run only CPU 7820 * model loading. CPU expansion can't run at instance_init-time 7821 * because host/accelerator data may be not available yet. 7822 * - CPU realization will perform both CPU model expansion and CPUID 7823 * filtering, and return an error in case one of them fails. 7824 * - query-cpu-definitions needs to run all 3 steps. It needs 7825 * to run CPUID filtering, as the 'unavailable-features' 7826 * field is set based on the filtering results. 7827 * - The query-cpu-model-expansion QMP command only needs to run 7828 * CPU model loading and CPU expansion. It should not filter 7829 * any CPUID data based on host capabilities. 7830 */ 7831 7832 /* Expand CPU configuration data, based on configured features 7833 * and host/accelerator capabilities when appropriate. 7834 */ 7835 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7836 { 7837 CPUX86State *env = &cpu->env; 7838 FeatureWord w; 7839 int i; 7840 GList *l; 7841 7842 for (l = plus_features; l; l = l->next) { 7843 const char *prop = l->data; 7844 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7845 return; 7846 } 7847 } 7848 7849 for (l = minus_features; l; l = l->next) { 7850 const char *prop = l->data; 7851 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7852 return; 7853 } 7854 } 7855 7856 /*TODO: Now cpu->max_features doesn't overwrite features 7857 * set using QOM properties, and we can convert 7858 * plus_features & minus_features to global properties 7859 * inside x86_cpu_parse_featurestr() too. 7860 */ 7861 if (cpu->max_features) { 7862 for (w = 0; w < FEATURE_WORDS; w++) { 7863 /* Override only features that weren't set explicitly 7864 * by the user. 7865 */ 7866 env->features[w] |= 7867 x86_cpu_get_supported_feature_word(cpu, w) & 7868 ~env->user_features[w] & 7869 ~feature_word_info[w].no_autoenable_flags; 7870 } 7871 7872 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 7873 uint32_t eax, ebx, ecx, edx; 7874 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 7875 env->avx10_version = ebx & 0xff; 7876 } 7877 } 7878 7879 if (x86_threads_per_pkg(&env->topo_info) > 1) { 7880 env->features[FEAT_1_EDX] |= CPUID_HT; 7881 7882 /* 7883 * The Linux kernel checks for the CMPLegacy bit and 7884 * discards multiple thread information if it is set. 7885 * So don't set it here for Intel (and other processors 7886 * following Intel's behavior) to make Linux guests happy. 7887 */ 7888 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 7889 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 7890 } 7891 } 7892 7893 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7894 FeatureDep *d = &feature_dependencies[i]; 7895 if (!(env->features[d->from.index] & d->from.mask)) { 7896 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7897 7898 /* Not an error unless the dependent feature was added explicitly. */ 7899 mark_unavailable_features(cpu, d->to.index, 7900 unavailable_features & env->user_features[d->to.index], 7901 "This feature depends on other features that were not requested"); 7902 7903 env->features[d->to.index] &= ~unavailable_features; 7904 } 7905 } 7906 7907 if (!kvm_enabled() || !cpu->expose_kvm) { 7908 env->features[FEAT_KVM] = 0; 7909 } 7910 7911 x86_cpu_enable_xsave_components(cpu); 7912 7913 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7914 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7915 if (cpu->full_cpuid_auto_level) { 7916 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7917 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7918 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7919 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7920 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7921 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7922 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7923 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7924 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7925 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7926 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7927 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7928 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7929 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7930 7931 /* Intel Processor Trace requires CPUID[0x14] */ 7932 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7933 if (cpu->intel_pt_auto_level) { 7934 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7935 } else if (cpu->env.cpuid_min_level < 0x14) { 7936 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7937 CPUID_7_0_EBX_INTEL_PT, 7938 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7939 } 7940 } 7941 7942 /* 7943 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7944 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7945 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7946 * cpu->vendor_cpuid_only has been unset for compatibility with older 7947 * machine types. 7948 */ 7949 if (x86_has_cpuid_0x1f(cpu) && 7950 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7951 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7952 } 7953 7954 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 7955 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7956 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 7957 } 7958 7959 /* SVM requires CPUID[0x8000000A] */ 7960 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7961 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7962 } 7963 7964 /* SEV requires CPUID[0x8000001F] */ 7965 if (sev_enabled()) { 7966 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7967 } 7968 7969 if (env->features[FEAT_8000_0021_EAX]) { 7970 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7971 } 7972 7973 /* SGX requires CPUID[0x12] for EPC enumeration */ 7974 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7975 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7976 } 7977 } 7978 7979 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7980 if (env->cpuid_level_func7 == UINT32_MAX) { 7981 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7982 } 7983 if (env->cpuid_level == UINT32_MAX) { 7984 env->cpuid_level = env->cpuid_min_level; 7985 } 7986 if (env->cpuid_xlevel == UINT32_MAX) { 7987 env->cpuid_xlevel = env->cpuid_min_xlevel; 7988 } 7989 if (env->cpuid_xlevel2 == UINT32_MAX) { 7990 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7991 } 7992 7993 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7994 return; 7995 } 7996 } 7997 7998 /* 7999 * Finishes initialization of CPUID data, filters CPU feature 8000 * words based on host availability of each feature. 8001 * 8002 * Returns: true if any flag is not supported by the host, false otherwise. 8003 */ 8004 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 8005 { 8006 CPUX86State *env = &cpu->env; 8007 FeatureWord w; 8008 const char *prefix = NULL; 8009 bool have_filtered_features; 8010 8011 uint32_t eax_0, ebx_0, ecx_0, edx_0; 8012 uint32_t eax_1, ebx_1, ecx_1, edx_1; 8013 8014 if (verbose) { 8015 prefix = accel_uses_host_cpuid() 8016 ? "host doesn't support requested feature" 8017 : "TCG doesn't support requested feature"; 8018 } 8019 8020 for (w = 0; w < FEATURE_WORDS; w++) { 8021 uint64_t host_feat = 8022 x86_cpu_get_supported_feature_word(NULL, w); 8023 uint64_t requested_features = env->features[w]; 8024 uint64_t unavailable_features = requested_features & ~host_feat; 8025 mark_unavailable_features(cpu, w, unavailable_features, prefix); 8026 } 8027 8028 /* 8029 * Check that KVM actually allows the processor tracing features that 8030 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 8031 */ 8032 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 8033 kvm_enabled()) { 8034 x86_cpu_get_supported_cpuid(0x14, 0, 8035 &eax_0, &ebx_0, &ecx_0, &edx_0); 8036 x86_cpu_get_supported_cpuid(0x14, 1, 8037 &eax_1, &ebx_1, &ecx_1, &edx_1); 8038 8039 if (!eax_0 || 8040 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 8041 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 8042 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 8043 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 8044 INTEL_PT_ADDR_RANGES_NUM) || 8045 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 8046 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 8047 ((ecx_0 & CPUID_14_0_ECX_LIP) != 8048 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 8049 /* 8050 * Processor Trace capabilities aren't configurable, so if the 8051 * host can't emulate the capabilities we report on 8052 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 8053 */ 8054 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 8055 } 8056 } 8057 8058 have_filtered_features = x86_cpu_have_filtered_features(cpu); 8059 8060 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 8061 x86_cpu_get_supported_cpuid(0x24, 0, 8062 &eax_0, &ebx_0, &ecx_0, &edx_0); 8063 uint8_t version = ebx_0 & 0xff; 8064 8065 if (version < env->avx10_version) { 8066 if (prefix) { 8067 warn_report("%s: avx10.%d. Adjust to avx10.%d", 8068 prefix, env->avx10_version, version); 8069 } 8070 env->avx10_version = version; 8071 have_filtered_features = true; 8072 } 8073 } else if (env->avx10_version) { 8074 if (prefix) { 8075 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 8076 } 8077 have_filtered_features = true; 8078 } 8079 8080 return have_filtered_features; 8081 } 8082 8083 static void x86_cpu_hyperv_realize(X86CPU *cpu) 8084 { 8085 size_t len; 8086 8087 /* Hyper-V vendor id */ 8088 if (!cpu->hyperv_vendor) { 8089 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 8090 &error_abort); 8091 } 8092 len = strlen(cpu->hyperv_vendor); 8093 if (len > 12) { 8094 warn_report("hv-vendor-id truncated to 12 characters"); 8095 len = 12; 8096 } 8097 memset(cpu->hyperv_vendor_id, 0, 12); 8098 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 8099 8100 /* 'Hv#1' interface identification*/ 8101 cpu->hyperv_interface_id[0] = 0x31237648; 8102 cpu->hyperv_interface_id[1] = 0; 8103 cpu->hyperv_interface_id[2] = 0; 8104 cpu->hyperv_interface_id[3] = 0; 8105 8106 /* Hypervisor implementation limits */ 8107 cpu->hyperv_limits[0] = 64; 8108 cpu->hyperv_limits[1] = 0; 8109 cpu->hyperv_limits[2] = 0; 8110 } 8111 8112 #ifndef CONFIG_USER_ONLY 8113 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 8114 Error **errp) 8115 { 8116 CPUX86State *env = &cpu->env; 8117 CpuTopologyLevel level; 8118 8119 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 8120 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8121 env->cache_info_cpuid4.l1d_cache->share_level = level; 8122 env->cache_info_amd.l1d_cache->share_level = level; 8123 } else { 8124 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8125 env->cache_info_cpuid4.l1d_cache->share_level); 8126 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8127 env->cache_info_amd.l1d_cache->share_level); 8128 } 8129 8130 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 8131 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8132 env->cache_info_cpuid4.l1i_cache->share_level = level; 8133 env->cache_info_amd.l1i_cache->share_level = level; 8134 } else { 8135 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8136 env->cache_info_cpuid4.l1i_cache->share_level); 8137 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8138 env->cache_info_amd.l1i_cache->share_level); 8139 } 8140 8141 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 8142 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8143 env->cache_info_cpuid4.l2_cache->share_level = level; 8144 env->cache_info_amd.l2_cache->share_level = level; 8145 } else { 8146 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8147 env->cache_info_cpuid4.l2_cache->share_level); 8148 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8149 env->cache_info_amd.l2_cache->share_level); 8150 } 8151 8152 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 8153 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8154 env->cache_info_cpuid4.l3_cache->share_level = level; 8155 env->cache_info_amd.l3_cache->share_level = level; 8156 } else { 8157 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8158 env->cache_info_cpuid4.l3_cache->share_level); 8159 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8160 env->cache_info_amd.l3_cache->share_level); 8161 } 8162 8163 if (!machine_check_smp_cache(ms, errp)) { 8164 return false; 8165 } 8166 return true; 8167 } 8168 #endif 8169 8170 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 8171 { 8172 CPUState *cs = CPU(dev); 8173 X86CPU *cpu = X86_CPU(dev); 8174 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8175 CPUX86State *env = &cpu->env; 8176 Error *local_err = NULL; 8177 unsigned requested_lbr_fmt; 8178 8179 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 8180 /* Use pc-relative instructions in system-mode */ 8181 tcg_cflags_set(cs, CF_PCREL); 8182 #endif 8183 8184 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 8185 error_setg(errp, "apic-id property was not initialized properly"); 8186 return; 8187 } 8188 8189 /* 8190 * Process Hyper-V enlightenments. 8191 * Note: this currently has to happen before the expansion of CPU features. 8192 */ 8193 x86_cpu_hyperv_realize(cpu); 8194 8195 x86_cpu_expand_features(cpu, &local_err); 8196 if (local_err) { 8197 goto out; 8198 } 8199 8200 /* 8201 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 8202 * with user-provided setting. 8203 */ 8204 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 8205 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 8206 error_setg(errp, "invalid lbr-fmt"); 8207 return; 8208 } 8209 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 8210 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 8211 } 8212 8213 /* 8214 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 8215 * 3)vPMU LBR format matches that of host setting. 8216 */ 8217 requested_lbr_fmt = 8218 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 8219 if (requested_lbr_fmt && kvm_enabled()) { 8220 uint64_t host_perf_cap = 8221 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 8222 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 8223 8224 if (!cpu->enable_pmu) { 8225 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 8226 return; 8227 } 8228 if (requested_lbr_fmt != host_lbr_fmt) { 8229 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 8230 "the host value (0x%x).", 8231 requested_lbr_fmt, host_lbr_fmt); 8232 return; 8233 } 8234 } 8235 8236 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 8237 if (cpu->enforce_cpuid) { 8238 error_setg(&local_err, 8239 accel_uses_host_cpuid() ? 8240 "Host doesn't support requested features" : 8241 "TCG doesn't support requested features"); 8242 goto out; 8243 } 8244 } 8245 8246 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 8247 * CPUID[1].EDX. 8248 */ 8249 if (IS_AMD_CPU(env)) { 8250 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 8251 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 8252 & CPUID_EXT2_AMD_ALIASES); 8253 } 8254 8255 x86_cpu_set_sgxlepubkeyhash(env); 8256 8257 /* 8258 * note: the call to the framework needs to happen after feature expansion, 8259 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 8260 * These may be set by the accel-specific code, 8261 * and the results are subsequently checked / assumed in this function. 8262 */ 8263 cpu_exec_realizefn(cs, &local_err); 8264 if (local_err != NULL) { 8265 error_propagate(errp, local_err); 8266 return; 8267 } 8268 8269 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 8270 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8271 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 8272 goto out; 8273 } 8274 8275 if (cpu->guest_phys_bits == -1) { 8276 /* 8277 * If it was not set by the user, or by the accelerator via 8278 * cpu_exec_realizefn, clear. 8279 */ 8280 cpu->guest_phys_bits = 0; 8281 } 8282 8283 if (cpu->ucode_rev == 0) { 8284 /* 8285 * The default is the same as KVM's. Note that this check 8286 * needs to happen after the evenual setting of ucode_rev in 8287 * accel-specific code in cpu_exec_realizefn. 8288 */ 8289 if (IS_AMD_CPU(env)) { 8290 cpu->ucode_rev = 0x01000065; 8291 } else { 8292 cpu->ucode_rev = 0x100000000ULL; 8293 } 8294 } 8295 8296 /* 8297 * mwait extended info: needed for Core compatibility 8298 * We always wake on interrupt even if host does not have the capability. 8299 * 8300 * requires the accel-specific code in cpu_exec_realizefn to 8301 * have already acquired the CPUID data into cpu->mwait. 8302 */ 8303 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 8304 8305 /* 8306 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 8307 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8308 * based on inputs (sockets,cores,threads), it is still better to give 8309 * users a warning. 8310 */ 8311 if (IS_AMD_CPU(env) && 8312 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8313 env->topo_info.threads_per_core > 1) { 8314 warn_report_once("This family of AMD CPU doesn't support " 8315 "hyperthreading(%d). Please configure -smp " 8316 "options properly or try enabling topoext " 8317 "feature.", env->topo_info.threads_per_core); 8318 } 8319 8320 /* For 64bit systems think about the number of physical bits to present. 8321 * ideally this should be the same as the host; anything other than matching 8322 * the host can cause incorrect guest behaviour. 8323 * QEMU used to pick the magic value of 40 bits that corresponds to 8324 * consumer AMD devices but nothing else. 8325 * 8326 * Note that this code assumes features expansion has already been done 8327 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 8328 * phys_bits adjustments to match the host have been already done in 8329 * accel-specific code in cpu_exec_realizefn. 8330 */ 8331 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8332 if (cpu->phys_bits && 8333 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 8334 cpu->phys_bits < 32)) { 8335 error_setg(errp, "phys-bits should be between 32 and %u " 8336 " (but is %u)", 8337 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 8338 return; 8339 } 8340 /* 8341 * 0 means it was not explicitly set by the user (or by machine 8342 * compat_props or by the host code in host-cpu.c). 8343 * In this case, the default is the value used by TCG (40). 8344 */ 8345 if (cpu->phys_bits == 0) { 8346 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 8347 } 8348 if (cpu->guest_phys_bits && 8349 (cpu->guest_phys_bits > cpu->phys_bits || 8350 cpu->guest_phys_bits < 32)) { 8351 error_setg(errp, "guest-phys-bits should be between 32 and %u " 8352 " (but is %u)", 8353 cpu->phys_bits, cpu->guest_phys_bits); 8354 return; 8355 } 8356 } else { 8357 /* For 32 bit systems don't use the user set value, but keep 8358 * phys_bits consistent with what we tell the guest. 8359 */ 8360 if (cpu->phys_bits != 0) { 8361 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 8362 return; 8363 } 8364 if (cpu->guest_phys_bits != 0) { 8365 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 8366 return; 8367 } 8368 8369 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 8370 cpu->phys_bits = 36; 8371 } else { 8372 cpu->phys_bits = 32; 8373 } 8374 } 8375 8376 /* Cache information initialization */ 8377 if (!cpu->legacy_cache) { 8378 const CPUCaches *cache_info = 8379 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 8380 8381 if (!xcc->model || !cache_info) { 8382 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8383 error_setg(errp, 8384 "CPU model '%s' doesn't support legacy-cache=off", name); 8385 return; 8386 } 8387 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 8388 *cache_info; 8389 } else { 8390 /* Build legacy cache information */ 8391 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 8392 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 8393 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 8394 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 8395 8396 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 8397 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 8398 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 8399 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 8400 8401 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 8402 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 8403 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 8404 env->cache_info_amd.l3_cache = &legacy_l3_cache; 8405 } 8406 8407 #ifndef CONFIG_USER_ONLY 8408 MachineState *ms = MACHINE(qdev_get_machine()); 8409 MachineClass *mc = MACHINE_GET_CLASS(ms); 8410 8411 if (mc->smp_props.has_caches) { 8412 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 8413 return; 8414 } 8415 } 8416 8417 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 8418 8419 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 8420 x86_cpu_apic_create(cpu, &local_err); 8421 if (local_err != NULL) { 8422 goto out; 8423 } 8424 } 8425 #endif 8426 8427 mce_init(cpu); 8428 8429 x86_cpu_gdb_init(cs); 8430 qemu_init_vcpu(cs); 8431 8432 #ifndef CONFIG_USER_ONLY 8433 x86_cpu_apic_realize(cpu, &local_err); 8434 if (local_err != NULL) { 8435 goto out; 8436 } 8437 #endif /* !CONFIG_USER_ONLY */ 8438 cpu_reset(cs); 8439 8440 xcc->parent_realize(dev, &local_err); 8441 8442 out: 8443 if (local_err != NULL) { 8444 error_propagate(errp, local_err); 8445 return; 8446 } 8447 } 8448 8449 static void x86_cpu_unrealizefn(DeviceState *dev) 8450 { 8451 X86CPU *cpu = X86_CPU(dev); 8452 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8453 8454 #ifndef CONFIG_USER_ONLY 8455 cpu_remove_sync(CPU(dev)); 8456 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8457 #endif 8458 8459 if (cpu->apic_state) { 8460 object_unparent(OBJECT(cpu->apic_state)); 8461 cpu->apic_state = NULL; 8462 } 8463 8464 xcc->parent_unrealize(dev); 8465 } 8466 8467 typedef struct BitProperty { 8468 FeatureWord w; 8469 uint64_t mask; 8470 } BitProperty; 8471 8472 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8473 void *opaque, Error **errp) 8474 { 8475 X86CPU *cpu = X86_CPU(obj); 8476 BitProperty *fp = opaque; 8477 uint64_t f = cpu->env.features[fp->w]; 8478 bool value = (f & fp->mask) == fp->mask; 8479 visit_type_bool(v, name, &value, errp); 8480 } 8481 8482 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8483 void *opaque, Error **errp) 8484 { 8485 DeviceState *dev = DEVICE(obj); 8486 X86CPU *cpu = X86_CPU(obj); 8487 BitProperty *fp = opaque; 8488 bool value; 8489 8490 if (dev->realized) { 8491 qdev_prop_set_after_realize(dev, name, errp); 8492 return; 8493 } 8494 8495 if (!visit_type_bool(v, name, &value, errp)) { 8496 return; 8497 } 8498 8499 if (value) { 8500 cpu->env.features[fp->w] |= fp->mask; 8501 } else { 8502 cpu->env.features[fp->w] &= ~fp->mask; 8503 } 8504 cpu->env.user_features[fp->w] |= fp->mask; 8505 } 8506 8507 /* Register a boolean property to get/set a single bit in a uint32_t field. 8508 * 8509 * The same property name can be registered multiple times to make it affect 8510 * multiple bits in the same FeatureWord. In that case, the getter will return 8511 * true only if all bits are set. 8512 */ 8513 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8514 const char *prop_name, 8515 FeatureWord w, 8516 int bitnr) 8517 { 8518 ObjectClass *oc = OBJECT_CLASS(xcc); 8519 BitProperty *fp; 8520 ObjectProperty *op; 8521 uint64_t mask = (1ULL << bitnr); 8522 8523 op = object_class_property_find(oc, prop_name); 8524 if (op) { 8525 fp = op->opaque; 8526 assert(fp->w == w); 8527 fp->mask |= mask; 8528 } else { 8529 fp = g_new0(BitProperty, 1); 8530 fp->w = w; 8531 fp->mask = mask; 8532 object_class_property_add(oc, prop_name, "bool", 8533 x86_cpu_get_bit_prop, 8534 x86_cpu_set_bit_prop, 8535 NULL, fp); 8536 } 8537 } 8538 8539 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8540 FeatureWord w, 8541 int bitnr) 8542 { 8543 FeatureWordInfo *fi = &feature_word_info[w]; 8544 const char *name = fi->feat_names[bitnr]; 8545 8546 if (!name) { 8547 return; 8548 } 8549 8550 /* Property names should use "-" instead of "_". 8551 * Old names containing underscores are registered as aliases 8552 * using object_property_add_alias() 8553 */ 8554 assert(!strchr(name, '_')); 8555 /* aliases don't use "|" delimiters anymore, they are registered 8556 * manually using object_property_add_alias() */ 8557 assert(!strchr(name, '|')); 8558 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8559 } 8560 8561 static void x86_cpu_post_initfn(Object *obj) 8562 { 8563 static bool first = true; 8564 uint64_t supported_xcr0; 8565 int i; 8566 8567 if (first) { 8568 first = false; 8569 8570 supported_xcr0 = 8571 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 8572 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 8573 8574 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 8575 ExtSaveArea *esa = &x86_ext_save_areas[i]; 8576 8577 if (!(supported_xcr0 & (1 << i))) { 8578 esa->size = 0; 8579 } 8580 } 8581 } 8582 8583 accel_cpu_instance_init(CPU(obj)); 8584 8585 #ifndef CONFIG_USER_ONLY 8586 if (current_machine && current_machine->cgs) { 8587 x86_confidential_guest_cpu_instance_init( 8588 X86_CONFIDENTIAL_GUEST(current_machine->cgs), (CPU(obj))); 8589 } 8590 #endif 8591 } 8592 8593 static void x86_cpu_init_default_topo(X86CPU *cpu) 8594 { 8595 CPUX86State *env = &cpu->env; 8596 8597 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 8598 8599 /* thread, core and socket levels are set by default. */ 8600 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 8601 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 8602 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 8603 } 8604 8605 static void x86_cpu_initfn(Object *obj) 8606 { 8607 X86CPU *cpu = X86_CPU(obj); 8608 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8609 CPUX86State *env = &cpu->env; 8610 8611 x86_cpu_init_default_topo(cpu); 8612 8613 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8614 x86_cpu_get_feature_words, 8615 NULL, NULL, (void *)env->features); 8616 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8617 x86_cpu_get_feature_words, 8618 NULL, NULL, (void *)cpu->filtered_features); 8619 8620 object_property_add_alias(obj, "sse3", obj, "pni"); 8621 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8622 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8623 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8624 object_property_add_alias(obj, "xd", obj, "nx"); 8625 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8626 object_property_add_alias(obj, "i64", obj, "lm"); 8627 8628 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8629 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8630 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8631 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8632 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8633 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8634 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8635 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8636 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8637 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8638 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8639 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8640 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8641 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8642 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8643 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8644 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8645 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8646 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8647 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8648 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8649 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8650 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8651 8652 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8653 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8654 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8655 8656 if (xcc->model) { 8657 x86_cpu_load_model(cpu, xcc->model); 8658 } 8659 } 8660 8661 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8662 { 8663 X86CPU *cpu = X86_CPU(cs); 8664 8665 return cpu->apic_id; 8666 } 8667 8668 #if !defined(CONFIG_USER_ONLY) 8669 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8670 { 8671 X86CPU *cpu = X86_CPU(cs); 8672 8673 return cpu->env.cr[0] & CR0_PG_MASK; 8674 } 8675 #endif /* !CONFIG_USER_ONLY */ 8676 8677 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8678 { 8679 X86CPU *cpu = X86_CPU(cs); 8680 8681 cpu->env.eip = value; 8682 } 8683 8684 static vaddr x86_cpu_get_pc(CPUState *cs) 8685 { 8686 X86CPU *cpu = X86_CPU(cs); 8687 8688 /* Match cpu_get_tb_cpu_state. */ 8689 return cpu->env.eip + cpu->env.segs[R_CS].base; 8690 } 8691 8692 #if !defined(CONFIG_USER_ONLY) 8693 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8694 { 8695 X86CPU *cpu = X86_CPU(cs); 8696 CPUX86State *env = &cpu->env; 8697 8698 if (interrupt_request & CPU_INTERRUPT_POLL) { 8699 return CPU_INTERRUPT_POLL; 8700 } 8701 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8702 return CPU_INTERRUPT_SIPI; 8703 } 8704 8705 if (env->hflags2 & HF2_GIF_MASK) { 8706 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8707 !(env->hflags & HF_SMM_MASK)) { 8708 return CPU_INTERRUPT_SMI; 8709 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8710 !(env->hflags2 & HF2_NMI_MASK)) { 8711 return CPU_INTERRUPT_NMI; 8712 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8713 return CPU_INTERRUPT_MCE; 8714 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8715 (((env->hflags2 & HF2_VINTR_MASK) && 8716 (env->hflags2 & HF2_HIF_MASK)) || 8717 (!(env->hflags2 & HF2_VINTR_MASK) && 8718 (env->eflags & IF_MASK && 8719 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8720 return CPU_INTERRUPT_HARD; 8721 } else if (env->hflags2 & HF2_VGIF_MASK) { 8722 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8723 (env->eflags & IF_MASK) && 8724 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8725 return CPU_INTERRUPT_VIRQ; 8726 } 8727 } 8728 } 8729 8730 return 0; 8731 } 8732 8733 static bool x86_cpu_has_work(CPUState *cs) 8734 { 8735 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8736 } 8737 #endif /* !CONFIG_USER_ONLY */ 8738 8739 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8740 { 8741 X86CPU *cpu = X86_CPU(cs); 8742 CPUX86State *env = &cpu->env; 8743 8744 info->endian = BFD_ENDIAN_LITTLE; 8745 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8746 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8747 : bfd_mach_i386_i8086); 8748 8749 info->cap_arch = CS_ARCH_X86; 8750 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8751 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8752 : CS_MODE_16); 8753 info->cap_insn_unit = 1; 8754 info->cap_insn_split = 8; 8755 } 8756 8757 void x86_update_hflags(CPUX86State *env) 8758 { 8759 uint32_t hflags; 8760 #define HFLAG_COPY_MASK \ 8761 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8762 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8763 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8764 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8765 8766 hflags = env->hflags & HFLAG_COPY_MASK; 8767 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8768 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8769 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8770 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8771 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8772 8773 if (env->cr[4] & CR4_OSFXSR_MASK) { 8774 hflags |= HF_OSFXSR_MASK; 8775 } 8776 8777 if (env->efer & MSR_EFER_LMA) { 8778 hflags |= HF_LMA_MASK; 8779 } 8780 8781 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8782 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8783 } else { 8784 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8785 (DESC_B_SHIFT - HF_CS32_SHIFT); 8786 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8787 (DESC_B_SHIFT - HF_SS32_SHIFT); 8788 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8789 !(hflags & HF_CS32_MASK)) { 8790 hflags |= HF_ADDSEG_MASK; 8791 } else { 8792 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8793 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8794 } 8795 } 8796 env->hflags = hflags; 8797 } 8798 8799 static const Property x86_cpu_properties[] = { 8800 #ifdef CONFIG_USER_ONLY 8801 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8802 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8803 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8804 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8805 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8806 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8807 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8808 #else 8809 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8810 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8811 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8812 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8813 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8814 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8815 #endif 8816 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8817 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8818 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8819 8820 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8821 HYPERV_SPINLOCK_NEVER_NOTIFY), 8822 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8823 HYPERV_FEAT_RELAXED, 0), 8824 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8825 HYPERV_FEAT_VAPIC, 0), 8826 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8827 HYPERV_FEAT_TIME, 0), 8828 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8829 HYPERV_FEAT_CRASH, 0), 8830 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8831 HYPERV_FEAT_RESET, 0), 8832 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8833 HYPERV_FEAT_VPINDEX, 0), 8834 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8835 HYPERV_FEAT_RUNTIME, 0), 8836 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8837 HYPERV_FEAT_SYNIC, 0), 8838 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8839 HYPERV_FEAT_STIMER, 0), 8840 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8841 HYPERV_FEAT_FREQUENCIES, 0), 8842 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8843 HYPERV_FEAT_REENLIGHTENMENT, 0), 8844 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8845 HYPERV_FEAT_TLBFLUSH, 0), 8846 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8847 HYPERV_FEAT_EVMCS, 0), 8848 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8849 HYPERV_FEAT_IPI, 0), 8850 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8851 HYPERV_FEAT_STIMER_DIRECT, 0), 8852 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8853 HYPERV_FEAT_AVIC, 0), 8854 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8855 HYPERV_FEAT_MSR_BITMAP, 0), 8856 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8857 HYPERV_FEAT_XMM_INPUT, 0), 8858 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8859 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8860 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8861 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8862 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8863 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8864 #ifdef CONFIG_SYNDBG 8865 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8866 HYPERV_FEAT_SYNDBG, 0), 8867 #endif 8868 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8869 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8870 8871 /* WS2008R2 identify by default */ 8872 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8873 0x3839), 8874 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8875 0x000A), 8876 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8877 0x0000), 8878 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8879 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8880 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8881 8882 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8883 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8884 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8885 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8886 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8887 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8888 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8889 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8890 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8891 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8892 UINT32_MAX), 8893 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8894 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8895 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8896 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8897 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8898 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8899 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 8900 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8901 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8902 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8903 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8904 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8905 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8906 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8907 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8908 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8909 false), 8910 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8911 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8912 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8913 true), 8914 /* 8915 * lecacy_cache defaults to true unless the CPU model provides its 8916 * own cache information (see x86_cpu_load_def()). 8917 */ 8918 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8919 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8920 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8921 8922 /* 8923 * From "Requirements for Implementing the Microsoft 8924 * Hypervisor Interface": 8925 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8926 * 8927 * "Starting with Windows Server 2012 and Windows 8, if 8928 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8929 * the hypervisor imposes no specific limit to the number of VPs. 8930 * In this case, Windows Server 2012 guest VMs may use more than 8931 * 64 VPs, up to the maximum supported number of processors applicable 8932 * to the specific Windows version being used." 8933 */ 8934 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8935 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8936 false), 8937 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8938 true), 8939 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8940 }; 8941 8942 #ifndef CONFIG_USER_ONLY 8943 #include "hw/core/sysemu-cpu-ops.h" 8944 8945 static const struct SysemuCPUOps i386_sysemu_ops = { 8946 .has_work = x86_cpu_has_work, 8947 .get_memory_mapping = x86_cpu_get_memory_mapping, 8948 .get_paging_enabled = x86_cpu_get_paging_enabled, 8949 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8950 .asidx_from_attrs = x86_asidx_from_attrs, 8951 .get_crash_info = x86_cpu_get_crash_info, 8952 .write_elf32_note = x86_cpu_write_elf32_note, 8953 .write_elf64_note = x86_cpu_write_elf64_note, 8954 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8955 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8956 .legacy_vmsd = &vmstate_x86_cpu, 8957 }; 8958 #endif 8959 8960 static void x86_cpu_common_class_init(ObjectClass *oc, const void *data) 8961 { 8962 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8963 CPUClass *cc = CPU_CLASS(oc); 8964 DeviceClass *dc = DEVICE_CLASS(oc); 8965 ResettableClass *rc = RESETTABLE_CLASS(oc); 8966 FeatureWord w; 8967 8968 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8969 &xcc->parent_realize); 8970 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8971 &xcc->parent_unrealize); 8972 device_class_set_props(dc, x86_cpu_properties); 8973 8974 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8975 &xcc->parent_phases); 8976 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8977 8978 cc->class_by_name = x86_cpu_class_by_name; 8979 cc->list_cpus = x86_cpu_list; 8980 cc->parse_features = x86_cpu_parse_featurestr; 8981 cc->dump_state = x86_cpu_dump_state; 8982 cc->set_pc = x86_cpu_set_pc; 8983 cc->get_pc = x86_cpu_get_pc; 8984 cc->gdb_read_register = x86_cpu_gdb_read_register; 8985 cc->gdb_write_register = x86_cpu_gdb_write_register; 8986 cc->get_arch_id = x86_cpu_get_arch_id; 8987 8988 #ifndef CONFIG_USER_ONLY 8989 cc->sysemu_ops = &i386_sysemu_ops; 8990 #endif /* !CONFIG_USER_ONLY */ 8991 #ifdef CONFIG_TCG 8992 cc->tcg_ops = &x86_tcg_ops; 8993 #endif /* CONFIG_TCG */ 8994 8995 cc->gdb_arch_name = x86_gdb_arch_name; 8996 #ifdef TARGET_X86_64 8997 cc->gdb_core_xml_file = "i386-64bit.xml"; 8998 #else 8999 cc->gdb_core_xml_file = "i386-32bit.xml"; 9000 #endif 9001 cc->disas_set_info = x86_disas_set_info; 9002 9003 dc->user_creatable = true; 9004 9005 object_class_property_add(oc, "family", "int", 9006 x86_cpuid_version_get_family, 9007 x86_cpuid_version_set_family, NULL, NULL); 9008 object_class_property_add(oc, "model", "int", 9009 x86_cpuid_version_get_model, 9010 x86_cpuid_version_set_model, NULL, NULL); 9011 object_class_property_add(oc, "stepping", "int", 9012 x86_cpuid_version_get_stepping, 9013 x86_cpuid_version_set_stepping, NULL, NULL); 9014 object_class_property_add_str(oc, "vendor", 9015 x86_cpuid_get_vendor, 9016 x86_cpuid_set_vendor); 9017 object_class_property_add_str(oc, "model-id", 9018 x86_cpuid_get_model_id, 9019 x86_cpuid_set_model_id); 9020 object_class_property_add(oc, "tsc-frequency", "int", 9021 x86_cpuid_get_tsc_freq, 9022 x86_cpuid_set_tsc_freq, NULL, NULL); 9023 /* 9024 * The "unavailable-features" property has the same semantics as 9025 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 9026 * QMP command: they list the features that would have prevented the 9027 * CPU from running if the "enforce" flag was set. 9028 */ 9029 object_class_property_add(oc, "unavailable-features", "strList", 9030 x86_cpu_get_unavailable_features, 9031 NULL, NULL, NULL); 9032 9033 #if !defined(CONFIG_USER_ONLY) 9034 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 9035 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 9036 #endif 9037 9038 for (w = 0; w < FEATURE_WORDS; w++) { 9039 int bitnr; 9040 for (bitnr = 0; bitnr < 64; bitnr++) { 9041 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 9042 } 9043 } 9044 } 9045 9046 static const TypeInfo x86_cpu_type_info = { 9047 .name = TYPE_X86_CPU, 9048 .parent = TYPE_CPU, 9049 .instance_size = sizeof(X86CPU), 9050 .instance_align = __alignof(X86CPU), 9051 .instance_init = x86_cpu_initfn, 9052 .instance_post_init = x86_cpu_post_initfn, 9053 9054 .abstract = true, 9055 .class_size = sizeof(X86CPUClass), 9056 .class_init = x86_cpu_common_class_init, 9057 }; 9058 9059 /* "base" CPU model, used by query-cpu-model-expansion */ 9060 static void x86_cpu_base_class_init(ObjectClass *oc, const void *data) 9061 { 9062 X86CPUClass *xcc = X86_CPU_CLASS(oc); 9063 9064 xcc->static_model = true; 9065 xcc->migration_safe = true; 9066 xcc->model_description = "base CPU model type with no features enabled"; 9067 xcc->ordering = 8; 9068 } 9069 9070 static const TypeInfo x86_base_cpu_type_info = { 9071 .name = X86_CPU_TYPE_NAME("base"), 9072 .parent = TYPE_X86_CPU, 9073 .class_init = x86_cpu_base_class_init, 9074 }; 9075 9076 static void x86_cpu_register_types(void) 9077 { 9078 int i; 9079 9080 type_register_static(&x86_cpu_type_info); 9081 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 9082 x86_register_cpudef_types(&builtin_x86_defs[i]); 9083 } 9084 type_register_static(&max_x86_cpu_type_info); 9085 type_register_static(&x86_base_cpu_type_info); 9086 } 9087 9088 type_init(x86_cpu_register_types) 9089