1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2.1 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20#### 21# Field definitions 22#### 23 24%assemble_sr3 13:1 14:2 25%assemble_sr3x 13:1 14:2 !function=expand_sr3x 26 27%assemble_11a 4:12 0:1 !function=expand_11a 28%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 29%assemble_12a 3:13 0:1 !function=expand_12a 30%assemble_16 0:16 !function=expand_16 31%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 32%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 33%assemble_sp 14:2 !function=sp0_if_wide 34 35%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 36 37%lowsign_11 0:s1 1:10 38 39%sm_imm 16:10 !function=expand_sm_imm 40 41%rm64 1:1 16:5 42%rt64 6:1 0:5 43%ra64 7:1 21:5 44%rb64 12:1 16:5 45%rc64 8:1 13:3 9:2 46%rc32 13:3 9:2 47 48%im5_0 0:s1 1:4 49%im5_16 16:s1 17:4 50%len5 0:5 !function=assemble_6 51%len6_8 8:1 0:5 !function=assemble_6 52%len6_12 12:1 0:5 !function=assemble_6 53%cpos6_11 11:1 5:5 54%ma_to_m 5:1 13:1 !function=ma_to_m 55%ma2_to_m 2:2 !function=ma_to_m 56%pos_to_m 0:1 !function=pos_to_m 57%neg_to_m 0:1 !function=neg_to_m 58%a_to_m 2:1 !function=neg_to_m 59%cmpbid_c 13:2 !function=cmpbid_c 60%d_5 5:1 !function=pa20_d 61%d_11 11:1 !function=pa20_d 62%d_13 13:1 !function=pa20_d 63 64#### 65# Argument set definitions 66#### 67 68# All insns that need to form a virtual address should use this set. 69&ldst t b x disp sp m scale size 70 71&rr_cf_d t r cf d 72&rrr t r1 r2 73&rrr_cf t r1 r2 cf 74&rrr_cf_d t r1 r2 cf d 75&rrr_sh t r1 r2 sh 76&rrr_cf_d_sh t r1 r2 cf d sh 77&rri t r i 78&rri_cf t r i cf 79&rri_cf_d t r i cf d 80 81&rrb_c_f disp n c f r1 r2 82&rrb_c_d_f disp n c d f r1 r2 83&rib_c_f disp n c f r i 84&rib_c_d_f disp n c d f r i 85 86#### 87# Format definitions 88#### 89 90@rr_cf_d ...... r:5 ..... cf:4 ...... . t:5 &rr_cf_d d=%d_5 91@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr 92@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 93@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d d=%d_5 94@rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh 95@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_d_sh d=%d_5 96@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d_sh d=%d_5 sh=0 97@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 98@rri_cf_d ...... r:5 t:5 cf:4 . ........... \ 99 &rri_cf_d d=%d_11 i=%lowsign_11 100 101@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 102 &rrb_c_f disp=%assemble_12 103@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ 104 &rrb_c_d_f disp=%assemble_12 105@rib_cf ...... r:5 ..... c:3 ........... n:1 . \ 106 &rib_c_f disp=%assemble_12 i=%im5_16 107@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \ 108 &rib_c_d_f disp=%assemble_12 i=%im5_16 109 110#### 111# System 112#### 113 114break 000000 ----- ----- --- 00000000 ----- 115 116mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 117mtctl 000000 t:5 r:5 --- 11000010 00000 118mtsarcm 000000 01011 r:5 --- 11000110 00000 119mtsm 000000 00000 r:5 000 11000011 00000 120 121mfia 000000 ----- 00000 --- 10100101 t:5 122mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 123mfctl 000000 r:5 00000- e:1 -01000101 t:5 124 125sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma 126 127ldsid 000000 b:5 ----- sp:2 0 10000101 t:5 128 129rsm 000000 .......... 000 01110011 t:5 i=%sm_imm 130ssm 000000 .......... 000 01101011 t:5 i=%sm_imm 131 132rfi 000000 ----- ----- --- 01100000 00000 133rfi_r 000000 ----- ----- --- 01100101 00000 134 135# These are artificial instructions used by QEMU firmware. 136# They are allocated from the unassigned instruction space. 137halt 1111 1111 1111 1101 1110 1010 1101 0000 138reset 1111 1111 1111 1101 1110 1010 1101 0001 139getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 140 141#### 142# Memory Management 143#### 144 145@addrx ...... b:5 x:5 .. ........ m:1 ..... \ 146 &ldst disp=0 scale=0 t=0 sp=0 size=0 147 148nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp 149nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index 150nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce 151fic 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a 152fic 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f 153fic 000001 ..... ..... --- 0001011 . ----- @addrx # fice 154nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc 155 156probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 157 158# pa1.x tlb insert instructions 159ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 160ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ 161 sp=%assemble_sr3x data=0 162 163# pcxl and pcxl2 Fast TLB Insert instructions 164ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 165 166# pa2.0 tlb insert idtlbt and iitlbt instructions 167ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 00000 # idtlbt 168 169# pdtlb, pitlb 170pxtlb 000001 b:5 x:5 sp:2 01001000 m:1 ----- \ 171 &ldst disp=0 scale=0 size=0 t=0 172pxtlb 000001 b:5 x:5 ... 0001000 m:1 ----- \ 173 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 174 175# ... pa20 local 176pxtlb_l 000001 b:5 x:5 sp:2 01011000 m:1 ----- \ 177 &ldst disp=0 scale=0 size=0 t=0 178pxtlb_l 000001 b:5 x:5 ... 0011000 m:1 ----- \ 179 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 180 181# pdtlbe, pitlbe 182pxtlbe 000001 b:5 x:5 sp:2 01001001 m:1 ----- \ 183 &ldst disp=0 scale=0 size=0 t=0 184pxtlbe 000001 b:5 x:5 ... 0001001 m:1 ----- \ 185 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 186 187lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ 188 &ldst disp=0 scale=0 size=0 189 190lci 000001 ----- ----- -- 01001100 0 t:5 191 192#### 193# Arith/Log 194#### 195 196andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d 197and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d 198or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d 199xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d 200uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d 201ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 202cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d 203uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d 204uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d 205dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d 206dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d 207 208add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh 209add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh 210add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh 211{ 212 add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 213 hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh 214} 215add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 216 217sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d 218sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d 219sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d 220sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d 221{ 222 sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d 223 hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh 224} 225sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d 226 227ldil 001000 t:5 ..................... i=%assemble_21 228addil 001010 r:5 ..................... i=%assemble_21 229ldo 001101 b:5 t:5 ................ i=%assemble_16 230 231addi 101101 ..... ..... .... 0 ........... @rri_cf 232addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf 233addi_tc 101100 ..... ..... .... 0 ........... @rri_cf 234addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf 235 236subi 100101 ..... ..... .... 0 ........... @rri_cf 237subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf 238 239cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d 240 241hadd 000010 ..... ..... 00000011 11 0 ..... @rrr 242hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr 243hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr 244 245havg 000010 ..... ..... 00000010 11 0 ..... @rrr 246 247hshl 111110 00000 r:5 100010 i:4 0 t:5 &rri 248hshr_s 111110 r:5 00000 110011 i:4 0 t:5 &rri 249hshr_u 111110 r:5 00000 110010 i:4 0 t:5 &rri 250 251hsub 000010 ..... ..... 00000001 11 0 ..... @rrr 252hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr 253hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr 254 255mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr 256mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr 257mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr 258mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr 259 260permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5 261 262#### 263# Index Mem 264#### 265 266@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0 267@ldim5 ...... b:5 ..... sp:2 ......... t:5 \ 268 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m 269@stim5 ...... b:5 t:5 sp:2 ......... ..... \ 270 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m 271 272ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 273ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx 274st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 275ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2 276ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2 277ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3 278ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3 279lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2 280lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2 281lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3 282lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3 283sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 284sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3 285stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 286stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0 287 288@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ 289 &ldst t=%rt64 disp=0 size=2 290@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ 291 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2 292 293fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx 294fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi 295fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx 296fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi 297 298@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ 299 &ldst disp=0 size=3 300@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ 301 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3 302 303fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx 304fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi 305fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx 306fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi 307 308#### 309# Offset Mem 310#### 311 312@ldstim11 ...... b:5 t:5 ................ \ 313 &ldst sp=%assemble_sp disp=%assemble_11a \ 314 m=%ma2_to_m x=0 scale=0 size=3 315@ldstim14 ...... b:5 t:5 ................ \ 316 &ldst sp=%assemble_sp disp=%assemble_16 \ 317 x=0 scale=0 m=0 318@ldstim14m ...... b:5 t:5 ................ \ 319 &ldst sp=%assemble_sp disp=%assemble_16 \ 320 x=0 scale=0 m=%neg_to_m 321@ldstim12m ...... b:5 t:5 ................ \ 322 &ldst sp=%assemble_sp disp=%assemble_12a \ 323 x=0 scale=0 m=%pos_to_m 324 325# LDB, LDH, LDW, LDWM 326ld 010000 ..... ..... .. .............. @ldstim14 size=0 327ld 010001 ..... ..... .. .............. @ldstim14 size=1 328ld 010010 ..... ..... .. .............. @ldstim14 size=2 329ld 010011 ..... ..... .. .............. @ldstim14m size=2 330ld 010111 ..... ..... .. ...........10. @ldstim12m size=2 331 332# STB, STH, STW, STWM 333st 011000 ..... ..... .. .............. @ldstim14 size=0 334st 011001 ..... ..... .. .............. @ldstim14 size=1 335st 011010 ..... ..... .. .............. @ldstim14 size=2 336st 011011 ..... ..... .. .............. @ldstim14m size=2 337st 011111 ..... ..... .. ...........10. @ldstim12m size=2 338 339fldw 010110 b:5 ..... ................ \ 340 &ldst disp=%assemble_12a sp=%assemble_sp \ 341 t=%rm64 m=%a_to_m x=0 scale=0 size=2 342fldw 010111 b:5 ..... .............0.. \ 343 &ldst disp=%assemble_12a sp=%assemble_sp \ 344 t=%rm64 m=0 x=0 scale=0 size=2 345 346fstw 011110 b:5 ..... ................ \ 347 &ldst disp=%assemble_12a sp=%assemble_sp \ 348 t=%rm64 m=%a_to_m x=0 scale=0 size=2 349fstw 011111 b:5 ..... .............0.. \ 350 &ldst disp=%assemble_12a sp=%assemble_sp \ 351 t=%rm64 m=0 x=0 scale=0 size=2 352 353ld 010100 ..... ..... .. ............0. @ldstim11 354fldd 010100 ..... ..... .. ............1. @ldstim11 355 356st 011100 ..... ..... .. ............0. @ldstim11 357fstd 011100 ..... ..... .. ............1. @ldstim11 358 359#### 360# Floating-point Multiply Add 361#### 362 363&mpyadd rm1 rm2 ta ra tm 364@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd 365 366fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd 367fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd 368fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd 369fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd 370 371#### 372# Conditional Branches 373#### 374 375bb_sar 110000 00000 r:5 c:1 1 . ........... n:1 . \ 376 disp=%assemble_12 d=%d_13 377bb_imm 110001 p:5 r:5 c:1 1 . ........... n:1 . \ 378 disp=%assemble_12 d=%d_13 379 380movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 381movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 382 383cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0 384cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1 385cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0 386cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1 387cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0 388cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1 389cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \ 390 &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16 391 392addb 101000 ..... ..... ... ........... . . @rrb_cf f=0 393addb 101010 ..... ..... ... ........... . . @rrb_cf f=1 394addbi 101001 ..... ..... ... ........... . . @rib_cf f=0 395addbi 101011 ..... ..... ... ........... . . @rib_cf f=1 396 397#### 398# Shift, Extract, Deposit 399#### 400 401shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 402shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0 403shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ 404 d=1 cpos=%cpos6_11 405 406extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5 407extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8 408extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=0 len=%len5 409extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \ 410 d=1 len=%len6_12 pos=%cpos6_11 411 412dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5 413dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8 414dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5 415dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \ 416 d=1 len=%len6_12 cpos=%cpos6_11 417depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \ 418 i=%im5_16 len=%len6_8 419depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \ 420 d=0 i=%im5_16 len=%len5 421depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \ 422 d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11 423 424#### 425# Branch External 426#### 427 428&BE b l n disp sp 429@be ...... b:5 ..... ... ........... n:1 . \ 430 &BE disp=%assemble_17 sp=%assemble_sr3 431 432be 111000 ..... ..... ... ........... . . @be l=0 433be 111001 ..... ..... ... ........... . . @be l=31 434 435#### 436# Branch 437#### 438 439&BL l n disp 440@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 441 442# B,L and B,L,PUSH 443bl 111010 ..... ..... 000 ........... . . @bl 444bl 111010 ..... ..... 100 ........... . . @bl 445# B,L (long displacement) 446bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ 447 disp=%assemble_22 448b_gate 111010 ..... ..... 001 ........... . . @bl 449blr 111010 l:5 x:5 010 00000000000 n:1 0 450nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts 451nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/pushnom 452bv 111010 b:5 x:5 110 00000000000 n:1 0 453bve 111010 b:5 00000 110 10000000000 n:1 - l=0 454bve 111010 b:5 00000 111 10000000000 n:1 - l=2 455 456#### 457# FP Fused Multiple-Add 458#### 459 460fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \ 461 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64 462fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 463 464#### 465# FP operations 466#### 467 468&fclass01 r t 469&fclass2 r1 r2 c y 470&fclass3 r1 r2 t 471 472@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01 473@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01 474@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2 475@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3 476 477@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \ 478 &fclass01 r=%ra64 t=%rt64 479@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01 480 481@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \ 482 &fclass01 r=%ra64 t=%rt64 483@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64 484@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64 485@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01 486 487@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \ 488 &fclass2 r1=%ra64 r2=%rb64 489@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2 490 491@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ 492 &fclass3 r1=%ra64 r2=%rb64 t=%rt64 493@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3 494 495# Floating point class 0 496 497fid_f 001100 00000 00000 000 00 000000 00000 498 499fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 500fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 501fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0 502frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 503fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 504fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0 505 506fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0 507fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0 508fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0 509frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 510fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 511fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0 512 513fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0 514fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0 515fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0 516frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 517fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 518fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0 519 520fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0 521fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0 522fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0 523frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 524fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 525fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0 526 527# Floating point class 1 528 529# float/float 530fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1 531fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1 532 533fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1 534fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1 535 536# int/float 537fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1 538fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1 539fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1 540fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1 541 542fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1 543fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1 544fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1 545fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1 546 547# float/int 548fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1 549fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1 550fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1 551fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1 552 553fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1 554fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1 555fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1 556fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1 557 558# float/int truncate 559fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1 560fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1 561fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1 562fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1 563 564fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1 565fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1 566fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1 567fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1 568 569# uint/float 570fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 571fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 572fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 573fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 574 575fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 576fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1 577fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1 578fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1 579 580# float/int 581fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 582fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 583fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1 584fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1 585 586fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1 587fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1 588fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1 589fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1 590 591# float/int truncate 592fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1 593fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1 594fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1 595fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1 596 597fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1 598fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1 599fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1 600fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1 601 602# Floating point class 2 603 604ftest 001100 00000 00000 y:3 00 10000 1 c:5 605 606fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2 607fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2 608 609fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2 610fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2 611 612# Floating point class 3 613 614fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3 615fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3 616fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3 617fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3 618 619fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3 620fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3 621fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3 622fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3 623 624fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3 625fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3 626fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3 627fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3 628 629fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3 630fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3 631fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3 632fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 633 634xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 635 636# diag 637{ 638 [ 639 diag_btlb 000101 00 0000 0000 0000 0001 0000 0000 640 diag_cout 000101 00 0000 0000 0000 0001 0000 0001 641 ] 642 diag_unimp 000101 i:26 643} 644