1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2.1 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20#### 21# Field definitions 22#### 23 24%assemble_sr3 13:1 14:2 25%assemble_sr3x 13:1 14:2 !function=expand_sr3x 26 27%assemble_11a 0:s1 4:10 !function=expand_shl3 28%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 29%assemble_12a 0:s1 3:11 !function=expand_shl2 30%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 31%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 32 33%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 34 35%lowsign_11 0:s1 1:10 36%lowsign_14 0:s1 1:13 37 38%sm_imm 16:10 !function=expand_sm_imm 39 40%rm64 1:1 16:5 41%rt64 6:1 0:5 42%ra64 7:1 21:5 43%rb64 12:1 16:5 44%rc64 8:1 13:3 9:2 45%rc32 13:3 9:2 46 47%im5_0 0:s1 1:4 48%im5_16 16:s1 17:4 49%len5 0:5 !function=assemble_6 50%len6_8 8:1 0:5 !function=assemble_6 51%len6_12 12:1 0:5 !function=assemble_6 52%cpos6_11 11:1 5:5 53%ma_to_m 5:1 13:1 !function=ma_to_m 54%ma2_to_m 2:2 !function=ma_to_m 55%pos_to_m 0:1 !function=pos_to_m 56%neg_to_m 0:1 !function=neg_to_m 57%a_to_m 2:1 !function=neg_to_m 58%cmpbid_c 13:2 !function=cmpbid_c 59 60#### 61# Argument set definitions 62#### 63 64# All insns that need to form a virtual address should use this set. 65&ldst t b x disp sp m scale size 66 67&rr_cf_d t r cf d 68&rrr_cf t r1 r2 cf 69&rrr_cf_d t r1 r2 cf d 70&rrr_cf_d_sh t r1 r2 cf d sh 71&rri_cf t r i cf 72&rri_cf_d t r i cf d 73 74&rrb_c_f disp n c f r1 r2 75&rrb_c_d_f disp n c d f r1 r2 76&rib_c_f disp n c f r i 77&rib_c_d_f disp n c d f r i 78 79#### 80# Format definitions 81#### 82 83@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d 84@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 85@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d 86@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh 87@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0 88@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 89@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 90 91@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 92 &rrb_c_f disp=%assemble_12 93@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ 94 &rrb_c_d_f disp=%assemble_12 95@rib_cf ...... r:5 ..... c:3 ........... n:1 . \ 96 &rib_c_f disp=%assemble_12 i=%im5_16 97@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \ 98 &rib_c_d_f disp=%assemble_12 i=%im5_16 99 100#### 101# System 102#### 103 104break 000000 ----- ----- --- 00000000 ----- 105 106mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 107mtctl 000000 t:5 r:5 --- 11000010 00000 108mtsarcm 000000 01011 r:5 --- 11000110 00000 109mtsm 000000 00000 r:5 000 11000011 00000 110 111mfia 000000 ----- 00000 --- 10100101 t:5 112mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 113mfctl 000000 r:5 00000- e:1 -01000101 t:5 114 115sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma 116 117ldsid 000000 b:5 ----- sp:2 0 10000101 t:5 118 119rsm 000000 .......... 000 01110011 t:5 i=%sm_imm 120ssm 000000 .......... 000 01101011 t:5 i=%sm_imm 121 122rfi 000000 ----- ----- --- 01100000 00000 123rfi_r 000000 ----- ----- --- 01100101 00000 124 125# These are artificial instructions used by QEMU firmware. 126# They are allocated from the unassigned instruction space. 127halt 1111 1111 1111 1101 1110 1010 1101 0000 128reset 1111 1111 1111 1101 1110 1010 1101 0001 129getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 130 131#### 132# Memory Management 133#### 134 135@addrx ...... b:5 x:5 .. ........ m:1 ..... \ 136 &ldst disp=0 scale=0 t=0 sp=0 size=0 137 138nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp 139nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index 140nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce 141nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a 142nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f 143nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice 144nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc 145 146probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 147 148ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 149ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ 150 sp=%assemble_sr3x data=0 151 152# pcxl and pcxl2 Fast TLB Insert instructions 153ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 154 155pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1 156pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ 157 sp=%assemble_sr3x data=0 158 159lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ 160 &ldst disp=0 scale=0 size=0 161 162lci 000001 ----- ----- -- 01001100 0 t:5 163 164#### 165# Arith/Log 166#### 167 168andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d 169and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d 170or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d 171xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d 172uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d 173ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 174cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d 175uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d 176uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d 177dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d 178dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d 179 180add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh 181add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh 182add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh 183add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 184add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 185 186sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d 187sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d 188sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d 189sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d 190sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d 191sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d 192 193ldil 001000 t:5 ..................... i=%assemble_21 194addil 001010 r:5 ..................... i=%assemble_21 195ldo 001101 b:5 t:5 -- .............. i=%lowsign_14 196 197addi 101101 ..... ..... .... 0 ........... @rri_cf 198addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf 199addi_tc 101100 ..... ..... .... 0 ........... @rri_cf 200addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf 201 202subi 100101 ..... ..... .... 0 ........... @rri_cf 203subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf 204 205cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d 206 207#### 208# Index Mem 209#### 210 211@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0 212@ldim5 ...... b:5 ..... sp:2 ......... t:5 \ 213 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m 214@stim5 ...... b:5 t:5 sp:2 ......... ..... \ 215 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m 216 217ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 218ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx 219st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 220ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2 221ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2 222ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3 223ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3 224lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2 225lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2 226lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3 227lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3 228sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 229sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3 230stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 231stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0 232 233@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ 234 &ldst t=%rt64 disp=0 size=2 235@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ 236 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2 237 238fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx 239fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi 240fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx 241fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi 242 243@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ 244 &ldst disp=0 size=3 245@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ 246 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3 247 248fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx 249fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi 250fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx 251fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi 252 253#### 254# Offset Mem 255#### 256 257@ldstim11 ...... b:5 t:5 sp:2 .............. \ 258 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 259@ldstim14 ...... b:5 t:5 sp:2 .............. \ 260 &ldst disp=%lowsign_14 x=0 scale=0 m=0 261@ldstim14m ...... b:5 t:5 sp:2 .............. \ 262 &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m 263@ldstim12m ...... b:5 t:5 sp:2 .............. \ 264 &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m 265 266# LDB, LDH, LDW, LDWM 267ld 010000 ..... ..... .. .............. @ldstim14 size=0 268ld 010001 ..... ..... .. .............. @ldstim14 size=1 269ld 010010 ..... ..... .. .............. @ldstim14 size=2 270ld 010011 ..... ..... .. .............. @ldstim14m size=2 271ld 010111 ..... ..... .. ...........10. @ldstim12m size=2 272 273# STB, STH, STW, STWM 274st 011000 ..... ..... .. .............. @ldstim14 size=0 275st 011001 ..... ..... .. .............. @ldstim14 size=1 276st 011010 ..... ..... .. .............. @ldstim14 size=2 277st 011011 ..... ..... .. .............. @ldstim14m size=2 278st 011111 ..... ..... .. ...........10. @ldstim12m size=2 279 280fldw 010110 b:5 ..... sp:2 .............. \ 281 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 282fldw 010111 b:5 ..... sp:2 ...........0.. \ 283 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 284 285fstw 011110 b:5 ..... sp:2 .............. \ 286 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 287fstw 011111 b:5 ..... sp:2 ...........0.. \ 288 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 289 290ld 010100 ..... ..... .. ............0. @ldstim11 291fldd 010100 ..... ..... .. ............1. @ldstim11 292 293st 011100 ..... ..... .. ............0. @ldstim11 294fstd 011100 ..... ..... .. ............1. @ldstim11 295 296#### 297# Floating-point Multiply Add 298#### 299 300&mpyadd rm1 rm2 ta ra tm 301@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd 302 303fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd 304fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd 305fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd 306fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd 307 308#### 309# Conditional Branches 310#### 311 312bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 313bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 314 315movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 316movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 317 318cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0 319cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1 320cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0 321cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1 322cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0 323cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1 324cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \ 325 &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16 326 327addb 101000 ..... ..... ... ........... . . @rrb_cf f=0 328addb 101010 ..... ..... ... ........... . . @rrb_cf f=1 329addbi 101001 ..... ..... ... ........... . . @rib_cf f=0 330addbi 101011 ..... ..... ... ........... . . @rib_cf f=1 331 332#### 333# Shift, Extract, Deposit 334#### 335 336shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 337shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0 338shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ 339 d=1 cpos=%cpos6_11 340 341extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5 342extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8 343extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=0 len=%len5 344extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \ 345 d=1 len=%len6_12 pos=%cpos6_11 346 347dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5 348dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8 349dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5 350dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \ 351 d=1 len=%len6_12 cpos=%cpos6_11 352depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \ 353 i=%im5_16 len=%len6_8 354depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \ 355 d=0 i=%im5_16 len=%len5 356depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \ 357 d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11 358 359#### 360# Branch External 361#### 362 363&BE b l n disp sp 364@be ...... b:5 ..... ... ........... n:1 . \ 365 &BE disp=%assemble_17 sp=%assemble_sr3 366 367be 111000 ..... ..... ... ........... . . @be l=0 368be 111001 ..... ..... ... ........... . . @be l=31 369 370#### 371# Branch 372#### 373 374&BL l n disp 375@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 376 377# B,L and B,L,PUSH 378bl 111010 ..... ..... 000 ........... . . @bl 379bl 111010 ..... ..... 100 ........... . . @bl 380# B,L (long displacement) 381bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ 382 disp=%assemble_22 383b_gate 111010 ..... ..... 001 ........... . . @bl 384blr 111010 l:5 x:5 010 00000000000 n:1 0 385nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts 386nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/pushnom 387bv 111010 b:5 x:5 110 00000000000 n:1 0 388bve 111010 b:5 00000 110 10000000000 n:1 - l=0 389bve 111010 b:5 00000 111 10000000000 n:1 - l=2 390 391#### 392# FP Fused Multiple-Add 393#### 394 395fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \ 396 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64 397fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 398 399#### 400# FP operations 401#### 402 403&fclass01 r t 404&fclass2 r1 r2 c y 405&fclass3 r1 r2 t 406 407@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01 408@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01 409@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2 410@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3 411 412@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \ 413 &fclass01 r=%ra64 t=%rt64 414@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01 415 416@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \ 417 &fclass01 r=%ra64 t=%rt64 418@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64 419@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64 420@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01 421 422@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \ 423 &fclass2 r1=%ra64 r2=%rb64 424@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2 425 426@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ 427 &fclass3 r1=%ra64 r2=%rb64 t=%rt64 428@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 429 430# Floating point class 0 431 432fid_f 001100 00000 00000 000 00 000000 00000 433 434fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 435fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 436fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0 437frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 438fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 439fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0 440 441fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0 442fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0 443fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0 444frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 445fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 446fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0 447 448fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0 449fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0 450fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0 451frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 452fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 453fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0 454 455fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0 456fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0 457fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0 458frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 459fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 460fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0 461 462# Floating point class 1 463 464# float/float 465fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1 466fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1 467 468fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1 469fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1 470 471# int/float 472fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1 473fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1 474fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1 475fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1 476 477fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1 478fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1 479fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1 480fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1 481 482# float/int 483fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1 484fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1 485fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1 486fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1 487 488fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1 489fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1 490fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1 491fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1 492 493# float/int truncate 494fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1 495fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1 496fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1 497fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1 498 499fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1 500fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1 501fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1 502fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1 503 504# uint/float 505fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 506fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 507fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 508fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 509 510fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 511fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1 512fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1 513fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1 514 515# float/int 516fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 517fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 518fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1 519fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1 520 521fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1 522fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1 523fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1 524fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1 525 526# float/int truncate 527fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1 528fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1 529fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1 530fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1 531 532fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1 533fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1 534fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1 535fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1 536 537# Floating point class 2 538 539ftest 001100 00000 00000 y:3 00 10000 1 c:5 540 541fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2 542fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2 543 544fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2 545fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2 546 547# Floating point class 3 548 549fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3 550fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3 551fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3 552fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3 553 554fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3 555fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3 556fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3 557fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3 558 559fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3 560fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3 561fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3 562fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3 563 564fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3 565fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3 566fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3 567fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 568 569xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 570 571# diag 572diag 000101 i:26 573