1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2.1 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20#### 21# Field definitions 22#### 23 24%assemble_sr3 13:1 14:2 25%assemble_sr3x 13:1 14:2 !function=expand_sr3x 26 27%assemble_11a 0:s1 4:10 !function=expand_shl3 28%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 29%assemble_12a 0:s1 3:11 !function=expand_shl2 30%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 31%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 32 33%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 34 35%lowsign_11 0:s1 1:10 36%lowsign_14 0:s1 1:13 37 38%sm_imm 16:10 !function=expand_sm_imm 39 40%rm64 1:1 16:5 41%rt64 6:1 0:5 42%ra64 7:1 21:5 43%rb64 12:1 16:5 44%rc64 8:1 13:3 9:2 45%rc32 13:3 9:2 46 47%im5_0 0:s1 1:4 48%im5_16 16:s1 17:4 49%len5 0:5 !function=assemble_6 50%len6_8 8:1 0:5 !function=assemble_6 51%len6_12 12:1 0:5 !function=assemble_6 52%cpos6_11 11:1 5:5 53%ma_to_m 5:1 13:1 !function=ma_to_m 54%ma2_to_m 2:2 !function=ma_to_m 55%pos_to_m 0:1 !function=pos_to_m 56%neg_to_m 0:1 !function=neg_to_m 57%a_to_m 2:1 !function=neg_to_m 58%cmpbid_c 13:2 !function=cmpbid_c 59 60#### 61# Argument set definitions 62#### 63 64# All insns that need to form a virtual address should use this set. 65&ldst t b x disp sp m scale size 66 67&rr_cf_d t r cf d 68&rrr t r1 r2 69&rrr_cf t r1 r2 cf 70&rrr_cf_d t r1 r2 cf d 71&rrr_cf_d_sh t r1 r2 cf d sh 72&rri_cf t r i cf 73&rri_cf_d t r i cf d 74 75&rrb_c_f disp n c f r1 r2 76&rrb_c_d_f disp n c d f r1 r2 77&rib_c_f disp n c f r i 78&rib_c_d_f disp n c d f r i 79 80#### 81# Format definitions 82#### 83 84@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d 85@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr 86@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 87@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d 88@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh 89@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0 90@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 91@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 92 93@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 94 &rrb_c_f disp=%assemble_12 95@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ 96 &rrb_c_d_f disp=%assemble_12 97@rib_cf ...... r:5 ..... c:3 ........... n:1 . \ 98 &rib_c_f disp=%assemble_12 i=%im5_16 99@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \ 100 &rib_c_d_f disp=%assemble_12 i=%im5_16 101 102#### 103# System 104#### 105 106break 000000 ----- ----- --- 00000000 ----- 107 108mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 109mtctl 000000 t:5 r:5 --- 11000010 00000 110mtsarcm 000000 01011 r:5 --- 11000110 00000 111mtsm 000000 00000 r:5 000 11000011 00000 112 113mfia 000000 ----- 00000 --- 10100101 t:5 114mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 115mfctl 000000 r:5 00000- e:1 -01000101 t:5 116 117sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma 118 119ldsid 000000 b:5 ----- sp:2 0 10000101 t:5 120 121rsm 000000 .......... 000 01110011 t:5 i=%sm_imm 122ssm 000000 .......... 000 01101011 t:5 i=%sm_imm 123 124rfi 000000 ----- ----- --- 01100000 00000 125rfi_r 000000 ----- ----- --- 01100101 00000 126 127# These are artificial instructions used by QEMU firmware. 128# They are allocated from the unassigned instruction space. 129halt 1111 1111 1111 1101 1110 1010 1101 0000 130reset 1111 1111 1111 1101 1110 1010 1101 0001 131getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 132 133#### 134# Memory Management 135#### 136 137@addrx ...... b:5 x:5 .. ........ m:1 ..... \ 138 &ldst disp=0 scale=0 t=0 sp=0 size=0 139 140nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp 141nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index 142nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce 143nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a 144nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f 145nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice 146nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc 147 148probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 149 150# pa1.x tlb insert instructions 151ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 152ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ 153 sp=%assemble_sr3x data=0 154 155# pcxl and pcxl2 Fast TLB Insert instructions 156ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 157 158# pa2.0 tlb insert idtlbt and iitlbt instructions 159ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 00000 # idtlbt 160 161pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1 162pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ 163 sp=%assemble_sr3x data=0 164 165lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ 166 &ldst disp=0 scale=0 size=0 167 168lci 000001 ----- ----- -- 01001100 0 t:5 169 170#### 171# Arith/Log 172#### 173 174andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d 175and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d 176or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d 177xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d 178uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d 179ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 180cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d 181uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d 182uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d 183dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d 184dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d 185 186add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh 187add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh 188add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh 189add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 190add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 191 192sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d 193sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d 194sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d 195sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d 196sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d 197sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d 198 199ldil 001000 t:5 ..................... i=%assemble_21 200addil 001010 r:5 ..................... i=%assemble_21 201ldo 001101 b:5 t:5 -- .............. i=%lowsign_14 202 203addi 101101 ..... ..... .... 0 ........... @rri_cf 204addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf 205addi_tc 101100 ..... ..... .... 0 ........... @rri_cf 206addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf 207 208subi 100101 ..... ..... .... 0 ........... @rri_cf 209subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf 210 211cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d 212 213hadd 000010 ..... ..... 00000011 11 0 ..... @rrr 214hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr 215hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr 216 217hsub 000010 ..... ..... 00000001 11 0 ..... @rrr 218hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr 219hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr 220 221#### 222# Index Mem 223#### 224 225@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0 226@ldim5 ...... b:5 ..... sp:2 ......... t:5 \ 227 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m 228@stim5 ...... b:5 t:5 sp:2 ......... ..... \ 229 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m 230 231ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 232ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx 233st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 234ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2 235ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2 236ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3 237ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3 238lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2 239lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2 240lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3 241lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3 242sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 243sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3 244stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 245stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0 246 247@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ 248 &ldst t=%rt64 disp=0 size=2 249@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ 250 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2 251 252fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx 253fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi 254fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx 255fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi 256 257@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ 258 &ldst disp=0 size=3 259@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ 260 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3 261 262fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx 263fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi 264fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx 265fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi 266 267#### 268# Offset Mem 269#### 270 271@ldstim11 ...... b:5 t:5 sp:2 .............. \ 272 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 273@ldstim14 ...... b:5 t:5 sp:2 .............. \ 274 &ldst disp=%lowsign_14 x=0 scale=0 m=0 275@ldstim14m ...... b:5 t:5 sp:2 .............. \ 276 &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m 277@ldstim12m ...... b:5 t:5 sp:2 .............. \ 278 &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m 279 280# LDB, LDH, LDW, LDWM 281ld 010000 ..... ..... .. .............. @ldstim14 size=0 282ld 010001 ..... ..... .. .............. @ldstim14 size=1 283ld 010010 ..... ..... .. .............. @ldstim14 size=2 284ld 010011 ..... ..... .. .............. @ldstim14m size=2 285ld 010111 ..... ..... .. ...........10. @ldstim12m size=2 286 287# STB, STH, STW, STWM 288st 011000 ..... ..... .. .............. @ldstim14 size=0 289st 011001 ..... ..... .. .............. @ldstim14 size=1 290st 011010 ..... ..... .. .............. @ldstim14 size=2 291st 011011 ..... ..... .. .............. @ldstim14m size=2 292st 011111 ..... ..... .. ...........10. @ldstim12m size=2 293 294fldw 010110 b:5 ..... sp:2 .............. \ 295 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 296fldw 010111 b:5 ..... sp:2 ...........0.. \ 297 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 298 299fstw 011110 b:5 ..... sp:2 .............. \ 300 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 301fstw 011111 b:5 ..... sp:2 ...........0.. \ 302 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 303 304ld 010100 ..... ..... .. ............0. @ldstim11 305fldd 010100 ..... ..... .. ............1. @ldstim11 306 307st 011100 ..... ..... .. ............0. @ldstim11 308fstd 011100 ..... ..... .. ............1. @ldstim11 309 310#### 311# Floating-point Multiply Add 312#### 313 314&mpyadd rm1 rm2 ta ra tm 315@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd 316 317fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd 318fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd 319fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd 320fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd 321 322#### 323# Conditional Branches 324#### 325 326bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 327bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 328 329movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 330movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 331 332cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0 333cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1 334cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0 335cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1 336cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0 337cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1 338cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \ 339 &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16 340 341addb 101000 ..... ..... ... ........... . . @rrb_cf f=0 342addb 101010 ..... ..... ... ........... . . @rrb_cf f=1 343addbi 101001 ..... ..... ... ........... . . @rib_cf f=0 344addbi 101011 ..... ..... ... ........... . . @rib_cf f=1 345 346#### 347# Shift, Extract, Deposit 348#### 349 350shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 351shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0 352shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ 353 d=1 cpos=%cpos6_11 354 355extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5 356extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8 357extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=0 len=%len5 358extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \ 359 d=1 len=%len6_12 pos=%cpos6_11 360 361dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5 362dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8 363dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5 364dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \ 365 d=1 len=%len6_12 cpos=%cpos6_11 366depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \ 367 i=%im5_16 len=%len6_8 368depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \ 369 d=0 i=%im5_16 len=%len5 370depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \ 371 d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11 372 373#### 374# Branch External 375#### 376 377&BE b l n disp sp 378@be ...... b:5 ..... ... ........... n:1 . \ 379 &BE disp=%assemble_17 sp=%assemble_sr3 380 381be 111000 ..... ..... ... ........... . . @be l=0 382be 111001 ..... ..... ... ........... . . @be l=31 383 384#### 385# Branch 386#### 387 388&BL l n disp 389@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 390 391# B,L and B,L,PUSH 392bl 111010 ..... ..... 000 ........... . . @bl 393bl 111010 ..... ..... 100 ........... . . @bl 394# B,L (long displacement) 395bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ 396 disp=%assemble_22 397b_gate 111010 ..... ..... 001 ........... . . @bl 398blr 111010 l:5 x:5 010 00000000000 n:1 0 399nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts 400nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/pushnom 401bv 111010 b:5 x:5 110 00000000000 n:1 0 402bve 111010 b:5 00000 110 10000000000 n:1 - l=0 403bve 111010 b:5 00000 111 10000000000 n:1 - l=2 404 405#### 406# FP Fused Multiple-Add 407#### 408 409fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \ 410 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64 411fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 412 413#### 414# FP operations 415#### 416 417&fclass01 r t 418&fclass2 r1 r2 c y 419&fclass3 r1 r2 t 420 421@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01 422@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01 423@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2 424@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3 425 426@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \ 427 &fclass01 r=%ra64 t=%rt64 428@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01 429 430@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \ 431 &fclass01 r=%ra64 t=%rt64 432@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64 433@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64 434@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01 435 436@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \ 437 &fclass2 r1=%ra64 r2=%rb64 438@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2 439 440@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ 441 &fclass3 r1=%ra64 r2=%rb64 t=%rt64 442@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3 443 444# Floating point class 0 445 446fid_f 001100 00000 00000 000 00 000000 00000 447 448fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 449fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 450fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0 451frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 452fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 453fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0 454 455fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0 456fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0 457fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0 458frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 459fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 460fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0 461 462fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0 463fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0 464fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0 465frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 466fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 467fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0 468 469fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0 470fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0 471fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0 472frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 473fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 474fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0 475 476# Floating point class 1 477 478# float/float 479fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1 480fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1 481 482fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1 483fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1 484 485# int/float 486fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1 487fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1 488fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1 489fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1 490 491fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1 492fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1 493fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1 494fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1 495 496# float/int 497fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1 498fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1 499fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1 500fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1 501 502fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1 503fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1 504fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1 505fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1 506 507# float/int truncate 508fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1 509fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1 510fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1 511fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1 512 513fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1 514fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1 515fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1 516fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1 517 518# uint/float 519fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 520fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 521fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 522fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 523 524fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 525fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1 526fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1 527fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1 528 529# float/int 530fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 531fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 532fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1 533fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1 534 535fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1 536fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1 537fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1 538fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1 539 540# float/int truncate 541fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1 542fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1 543fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1 544fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1 545 546fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1 547fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1 548fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1 549fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1 550 551# Floating point class 2 552 553ftest 001100 00000 00000 y:3 00 10000 1 c:5 554 555fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2 556fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2 557 558fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2 559fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2 560 561# Floating point class 3 562 563fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3 564fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3 565fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3 566fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3 567 568fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3 569fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3 570fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3 571fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3 572 573fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3 574fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3 575fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3 576fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3 577 578fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3 579fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3 580fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3 581fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 582 583xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 584 585# diag 586diag 000101 i:26 587