1 /* 2 * HPPA emulation cpu helpers for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "fpu/softfloat.h" 24 #include "exec/exec-all.h" 25 #include "exec/helper-proto.h" 26 #include "qemu/qemu-print.h" 27 28 target_ureg cpu_hppa_get_psw(CPUHPPAState *env) 29 { 30 target_ureg psw; 31 target_ureg mask1 = (target_ureg)-1 / 0xf; 32 target_ureg maskf = (target_ureg)-1 / 0xffff * 0xf; 33 34 /* Fold carry bits down to 8 consecutive bits. */ 35 /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^i^^^j^^^k^^^l^^^m^^^n^^^o^^^p^^^^ */ 36 /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^^ */ 37 psw = (env->psw_cb >> 4) & mask1; 38 /* .......b...c...d...e...f...g...h...i...j...k...l...m...n...o...p */ 39 /* .......b...c...d...e...f...g...h */ 40 psw |= psw >> 3; 41 /* .......b..bc..cd..de..ef..fg..gh..hi..ij..jk..kl..lm..mn..no..op */ 42 /* .......b..bc..cd..de..ef..fg..gh */ 43 psw |= psw >> 6; 44 psw &= maskf; 45 /* .............bcd............efgh............ijkl............mnop */ 46 /* .............bcd............efgh */ 47 psw |= psw >> 12; 48 /* .............bcd.........bcdefgh........efghijkl........ijklmnop */ 49 /* .............bcd.........bcdefgh */ 50 psw |= env->psw_cb_msb << (TARGET_REGISTER_BITS == 64 ? 39 : 7); 51 /* .............bcd........abcdefgh........efghijkl........ijklmnop */ 52 /* .............bcd........abcdefgh */ 53 54 /* For hppa64, the two 8-bit fields are discontiguous. */ 55 if (hppa_is_pa20(env)) { 56 psw = (psw & 0xff00000000ull) | ((psw & 0xff) << 8); 57 } else { 58 psw = (psw & 0xff) << 8; 59 } 60 61 psw |= env->psw_n * PSW_N; 62 psw |= (env->psw_v < 0) * PSW_V; 63 psw |= env->psw; 64 65 return psw; 66 } 67 68 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) 69 { 70 uint64_t reserved; 71 target_ureg cb = 0; 72 73 /* Do not allow reserved bits to be set. */ 74 if (hppa_is_pa20(env)) { 75 reserved = MAKE_64BIT_MASK(40, 24) | MAKE_64BIT_MASK(28, 4); 76 reserved |= PSW_G; /* PA1.x only */ 77 reserved |= PSW_E; /* not implemented */ 78 } else { 79 reserved = MAKE_64BIT_MASK(32, 32) | MAKE_64BIT_MASK(28, 2); 80 reserved |= PSW_O | PSW_W; /* PA2.0 only */ 81 reserved |= PSW_E | PSW_Y | PSW_Z; /* not implemented */ 82 } 83 psw &= ~reserved; 84 85 env->psw = psw & ~(PSW_N | PSW_V | PSW_CB); 86 env->psw_n = (psw / PSW_N) & 1; 87 env->psw_v = -((psw / PSW_V) & 1); 88 89 #if TARGET_REGISTER_BITS == 32 90 env->psw_cb_msb = (psw >> 15) & 1; 91 #else 92 env->psw_cb_msb = (psw >> 39) & 1; 93 cb |= ((psw >> 38) & 1) << 60; 94 cb |= ((psw >> 37) & 1) << 56; 95 cb |= ((psw >> 36) & 1) << 52; 96 cb |= ((psw >> 35) & 1) << 48; 97 cb |= ((psw >> 34) & 1) << 44; 98 cb |= ((psw >> 33) & 1) << 40; 99 cb |= ((psw >> 32) & 1) << 36; 100 cb |= ((psw >> 15) & 1) << 32; 101 #endif 102 cb |= ((psw >> 14) & 1) << 28; 103 cb |= ((psw >> 13) & 1) << 24; 104 cb |= ((psw >> 12) & 1) << 20; 105 cb |= ((psw >> 11) & 1) << 16; 106 cb |= ((psw >> 10) & 1) << 12; 107 cb |= ((psw >> 9) & 1) << 8; 108 cb |= ((psw >> 8) & 1) << 4; 109 env->psw_cb = cb; 110 } 111 112 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) 113 { 114 CPUHPPAState *env = cpu_env(cs); 115 target_ureg psw = cpu_hppa_get_psw(env); 116 target_ureg psw_cb; 117 char psw_c[20]; 118 int i, w; 119 uint64_t m; 120 121 if (hppa_is_pa20(env)) { 122 w = 16; 123 m = UINT64_MAX; 124 } else { 125 w = 8; 126 m = UINT32_MAX; 127 } 128 129 qemu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx 130 " IIR %0*" PRIx64 "\n", 131 hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), 132 hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b), 133 w, m & env->cr[CR_IIR]); 134 135 psw_c[0] = (psw & PSW_W ? 'W' : '-'); 136 psw_c[1] = (psw & PSW_E ? 'E' : '-'); 137 psw_c[2] = (psw & PSW_S ? 'S' : '-'); 138 psw_c[3] = (psw & PSW_T ? 'T' : '-'); 139 psw_c[4] = (psw & PSW_H ? 'H' : '-'); 140 psw_c[5] = (psw & PSW_L ? 'L' : '-'); 141 psw_c[6] = (psw & PSW_N ? 'N' : '-'); 142 psw_c[7] = (psw & PSW_X ? 'X' : '-'); 143 psw_c[8] = (psw & PSW_B ? 'B' : '-'); 144 psw_c[9] = (psw & PSW_C ? 'C' : '-'); 145 psw_c[10] = (psw & PSW_V ? 'V' : '-'); 146 psw_c[11] = (psw & PSW_M ? 'M' : '-'); 147 psw_c[12] = (psw & PSW_F ? 'F' : '-'); 148 psw_c[13] = (psw & PSW_R ? 'R' : '-'); 149 psw_c[14] = (psw & PSW_Q ? 'Q' : '-'); 150 psw_c[15] = (psw & PSW_P ? 'P' : '-'); 151 psw_c[16] = (psw & PSW_D ? 'D' : '-'); 152 psw_c[17] = (psw & PSW_I ? 'I' : '-'); 153 psw_c[18] = '\0'; 154 psw_cb = ((env->psw_cb >> 4) & ((target_ureg)-1 / 0xf)) 155 | (env->psw_cb_msb << (TARGET_REGISTER_BITS - 4)); 156 157 qemu_fprintf(f, "PSW %0*" PRIx64 " CB %0*" PRIx64 " %s\n", 158 w, m & psw, w, m & psw_cb, psw_c); 159 160 for (i = 0; i < 32; i++) { 161 qemu_fprintf(f, "GR%02d %0*" PRIx64 "%c", 162 i, w, m & env->gr[i], 163 (i & 3) == 3 ? '\n' : ' '); 164 } 165 #ifndef CONFIG_USER_ONLY 166 for (i = 0; i < 8; i++) { 167 qemu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32), 168 (i & 3) == 3 ? '\n' : ' '); 169 } 170 #endif 171 qemu_fprintf(f, "\n"); 172 173 /* ??? FR */ 174 } 175