1 /* 2 * PA-RISC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HPPA_CPU_H 21 #define HPPA_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-defs.h" 25 #include "exec/cpu-interrupt.h" 26 #include "system/memory.h" 27 #include "qemu/cpu-float.h" 28 #include "qemu/interval-tree.h" 29 #include "hw/registerfields.h" 30 31 #define MMU_ABS_W_IDX 6 32 #define MMU_ABS_IDX 7 33 #define MMU_KERNEL_IDX 8 34 #define MMU_KERNEL_P_IDX 9 35 #define MMU_PL1_IDX 10 36 #define MMU_PL1_P_IDX 11 37 #define MMU_PL2_IDX 12 38 #define MMU_PL2_P_IDX 13 39 #define MMU_USER_IDX 14 40 #define MMU_USER_P_IDX 15 41 42 #define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) < MMU_KERNEL_IDX) 43 #define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2) 44 #define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1) 45 #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX) 46 47 #define PRIV_KERNEL 0 48 #define PRIV_USER 3 49 50 #define TARGET_INSN_START_EXTRA_WORDS 2 51 52 /* No need to flush MMU_ABS*_IDX */ 53 #define HPPA_MMU_FLUSH_MASK \ 54 (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \ 55 1 << MMU_PL1_IDX | 1 << MMU_PL1_P_IDX | \ 56 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \ 57 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX) 58 59 /* Indices to flush for access_id changes. */ 60 #define HPPA_MMU_FLUSH_P_MASK \ 61 (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \ 62 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX) 63 64 /* Hardware exceptions, interrupts, faults, and traps. */ 65 #define EXCP_HPMC 1 /* high priority machine check */ 66 #define EXCP_POWER_FAIL 2 67 #define EXCP_RC 3 /* recovery counter */ 68 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ 69 #define EXCP_LPMC 5 /* low priority machine check */ 70 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ 71 #define EXCP_IMP 7 /* instruction memory protection trap */ 72 #define EXCP_ILL 8 /* illegal instruction trap */ 73 #define EXCP_BREAK 9 /* break instruction */ 74 #define EXCP_PRIV_OPR 10 /* privileged operation trap */ 75 #define EXCP_PRIV_REG 11 /* privileged register trap */ 76 #define EXCP_OVERFLOW 12 /* signed overflow trap */ 77 #define EXCP_COND 13 /* trap-on-condition */ 78 #define EXCP_ASSIST 14 /* assist exception trap */ 79 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ 80 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ 81 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ 82 #define EXCP_DMP 18 /* data memory protection trap */ 83 #define EXCP_DMB 19 /* data memory break trap */ 84 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ 85 #define EXCP_PAGE_REF 21 /* page reference trap */ 86 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ 87 #define EXCP_HPT 23 /* high-privilege transfer trap */ 88 #define EXCP_LPT 24 /* low-privilege transfer trap */ 89 #define EXCP_TB 25 /* taken branch trap */ 90 #define EXCP_DMAR 26 /* data memory access rights trap */ 91 #define EXCP_DMPI 27 /* data memory protection id trap */ 92 #define EXCP_UNALIGN 28 /* unaligned data reference trap */ 93 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ 94 95 /* Exceptions for linux-user emulation. */ 96 #define EXCP_SYSCALL 30 97 #define EXCP_SYSCALL_LWS 31 98 99 /* Emulated hardware TOC button */ 100 #define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */ 101 102 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */ 103 104 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ 105 #define PSW_I 0x00000001 106 #define PSW_D 0x00000002 107 #define PSW_P 0x00000004 108 #define PSW_Q 0x00000008 109 #define PSW_R 0x00000010 110 #define PSW_F 0x00000020 111 #define PSW_G 0x00000040 /* PA1.x only */ 112 #define PSW_O 0x00000080 /* PA2.0 only */ 113 #define PSW_CB 0x0000ff00 114 #define PSW_M 0x00010000 115 #define PSW_V 0x00020000 116 #define PSW_C 0x00040000 117 #define PSW_B 0x00080000 118 #define PSW_X 0x00100000 119 #define PSW_N 0x00200000 120 #define PSW_L 0x00400000 121 #define PSW_H 0x00800000 122 #define PSW_T 0x01000000 123 #define PSW_S 0x02000000 124 #define PSW_E 0x04000000 125 #define PSW_W 0x08000000 /* PA2.0 only */ 126 #define PSW_Z 0x40000000 /* PA1.x only */ 127 #define PSW_Y 0x80000000 /* PA1.x only */ 128 129 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ 130 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) 131 132 /* ssm/rsm instructions number PSW_W and PSW_E differently */ 133 #define PSW_SM_I PSW_I /* Enable External Interrupts */ 134 #define PSW_SM_D PSW_D 135 #define PSW_SM_P PSW_P 136 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ 137 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ 138 #define PSW_SM_E 0x100 139 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ 140 141 #define CR_RC 0 142 #define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ 143 #define PDC_PSW_WIDE_BIT 2 144 #define CR_PID1 8 145 #define CR_PID2 9 146 #define CR_PID3 12 147 #define CR_PID4 13 148 #define CR_SCRCCR 10 149 #define CR_SAR 11 150 #define CR_IVA 14 151 #define CR_EIEM 15 152 #define CR_IT 16 153 #define CR_IIASQ 17 154 #define CR_IIAOQ 18 155 #define CR_IIR 19 156 #define CR_ISR 20 157 #define CR_IOR 21 158 #define CR_IPSW 22 159 #define CR_EIRR 23 160 161 FIELD(FPSR, ENA_I, 0, 1) 162 FIELD(FPSR, ENA_U, 1, 1) 163 FIELD(FPSR, ENA_O, 2, 1) 164 FIELD(FPSR, ENA_Z, 3, 1) 165 FIELD(FPSR, ENA_V, 4, 1) 166 FIELD(FPSR, ENABLES, 0, 5) 167 FIELD(FPSR, D, 5, 1) 168 FIELD(FPSR, T, 6, 1) 169 FIELD(FPSR, RM, 9, 2) 170 FIELD(FPSR, CQ, 11, 11) 171 FIELD(FPSR, CQ0_6, 15, 7) 172 FIELD(FPSR, CQ0_4, 17, 5) 173 FIELD(FPSR, CQ0_2, 19, 3) 174 FIELD(FPSR, CQ0, 21, 1) 175 FIELD(FPSR, CA, 15, 7) 176 FIELD(FPSR, CA0, 21, 1) 177 FIELD(FPSR, C, 26, 1) 178 FIELD(FPSR, FLG_I, 27, 1) 179 FIELD(FPSR, FLG_U, 28, 1) 180 FIELD(FPSR, FLG_O, 29, 1) 181 FIELD(FPSR, FLG_Z, 30, 1) 182 FIELD(FPSR, FLG_V, 31, 1) 183 FIELD(FPSR, FLAGS, 27, 5) 184 185 typedef struct HPPATLBEntry { 186 union { 187 IntervalTreeNode itree; 188 struct HPPATLBEntry *unused_next; 189 }; 190 191 target_ulong pa; 192 193 unsigned entry_valid : 1; 194 195 unsigned u : 1; 196 unsigned t : 1; 197 unsigned d : 1; 198 unsigned b : 1; 199 unsigned ar_type : 3; 200 unsigned ar_pl1 : 2; 201 unsigned ar_pl2 : 2; 202 unsigned access_id : 16; 203 } HPPATLBEntry; 204 205 typedef struct CPUArchState { 206 target_ulong iaoq_f; /* front */ 207 target_ulong iaoq_b; /* back, aka next instruction */ 208 209 target_ulong gr[32]; 210 uint64_t fr[32]; 211 uint64_t sr[8]; /* stored shifted into place for gva */ 212 213 uint32_t psw; /* All psw bits except the following: */ 214 uint32_t psw_xb; /* X and B, in their normal positions */ 215 target_ulong psw_n; /* boolean */ 216 target_long psw_v; /* in bit 31 */ 217 218 /* Splitting the carry-borrow field into the MSB and "the rest", allows 219 * for "the rest" to be deleted when it is unused, but the MSB is in use. 220 * In addition, it's easier to compute carry-in for bit B+1 than it is to 221 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the 222 * host has the appropriate add-with-carry insn to compute the msb). 223 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. 224 */ 225 target_ulong psw_cb; /* in least significant bit of next nibble */ 226 target_ulong psw_cb_msb; /* boolean */ 227 228 uint64_t gva_offset_mask; /* cached address mask based on PSW and %dr2 */ 229 uint64_t iasq_f; 230 uint64_t iasq_b; 231 232 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ 233 float_status fp_status; 234 235 target_ulong cr[32]; /* control registers */ 236 target_ulong cr_back[2]; /* back of cr17/cr18 */ 237 target_ulong shadow[7]; /* shadow registers */ 238 target_ulong dr[32]; /* diagnose registers */ 239 240 /* 241 * During unwind of a memory insn, the base register of the address. 242 * This is used to construct CR_IOR for pa2.0. 243 */ 244 uint32_t unwind_breg; 245 246 /* 247 * ??? The number of entries isn't specified by the architecture. 248 * BTLBs are not supported in 64-bit machines. 249 */ 250 #define PA10_BTLB_FIXED 16 251 #define PA10_BTLB_VARIABLE 0 252 #define HPPA_TLB_ENTRIES 256 253 254 /* Index for round-robin tlb eviction. */ 255 uint32_t tlb_last; 256 257 /* 258 * For pa1.x, the partial initialized, still invalid tlb entry 259 * which has had ITLBA performed, but not yet ITLBP. 260 */ 261 HPPATLBEntry *tlb_partial; 262 263 /* Linked list of all invalid (unused) tlb entries. */ 264 HPPATLBEntry *tlb_unused; 265 266 /* Root of the search tree for all valid tlb entries. */ 267 IntervalTreeRoot tlb_root; 268 269 HPPATLBEntry tlb[HPPA_TLB_ENTRIES]; 270 271 /* Fields up to this point are cleared by a CPU reset */ 272 struct {} end_reset_fields; 273 274 bool is_pa20; 275 276 target_ulong kernel_entry; /* Linux kernel was loaded here */ 277 target_ulong cmdline_or_bootorder; 278 target_ulong initrd_base, initrd_end; 279 } CPUHPPAState; 280 281 /** 282 * HPPACPU: 283 * @env: #CPUHPPAState 284 * 285 * An HPPA CPU. 286 */ 287 struct ArchCPU { 288 CPUState parent_obj; 289 290 CPUHPPAState env; 291 QEMUTimer *alarm_timer; 292 }; 293 294 /** 295 * HPPACPUClass: 296 * @parent_realize: The parent class' realize handler. 297 * @parent_phases: The parent class' reset phase handlers. 298 * 299 * An HPPA CPU model. 300 */ 301 struct HPPACPUClass { 302 CPUClass parent_class; 303 304 DeviceRealize parent_realize; 305 ResettablePhases parent_phases; 306 }; 307 308 #include "exec/cpu-all.h" 309 310 static inline bool hppa_is_pa20(const CPUHPPAState *env) 311 { 312 return env->is_pa20; 313 } 314 315 static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) 316 { 317 return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; 318 } 319 320 void hppa_translate_init(void); 321 void hppa_translate_code(CPUState *cs, TranslationBlock *tb, 322 int *max_insns, vaddr pc, void *host_pc); 323 324 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 325 326 static inline target_ulong hppa_form_gva_mask(uint64_t gva_offset_mask, 327 uint64_t spc, target_ulong off) 328 { 329 #ifdef CONFIG_USER_ONLY 330 return off & gva_offset_mask; 331 #else 332 return spc | (off & gva_offset_mask); 333 #endif 334 } 335 336 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, 337 target_ulong off) 338 { 339 return hppa_form_gva_mask(env->gva_offset_mask, spc, off); 340 } 341 342 hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); 343 hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); 344 345 /* 346 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. 347 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the 348 * same value. 349 */ 350 #define TB_FLAG_SR_SAME PSW_I 351 #define TB_FLAG_PRIV_SHIFT 8 352 #define TB_FLAG_UNALIGN 0x400 353 #define TB_FLAG_SPHASH 0x800 354 #define CS_BASE_DIFFPAGE (1 << 12) 355 #define CS_BASE_DIFFSPACE (1 << 13) 356 357 void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, 358 uint64_t *cs_base, uint32_t *pflags); 359 360 target_ulong cpu_hppa_get_psw(CPUHPPAState *env); 361 void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); 362 void update_gva_offset_mask(CPUHPPAState *env); 363 void cpu_hppa_loaded_fr0(CPUHPPAState *env); 364 365 #ifdef CONFIG_USER_ONLY 366 static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } 367 #else 368 void cpu_hppa_change_prot_id(CPUHPPAState *env); 369 #endif 370 371 int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 372 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 373 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); 374 #ifndef CONFIG_USER_ONLY 375 void hppa_ptlbe(CPUHPPAState *env); 376 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); 377 void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled); 378 bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, 379 MMUAccessType access_type, int mmu_idx, 380 MemOp memop, int size, bool probe, uintptr_t ra); 381 void hppa_cpu_do_interrupt(CPUState *cpu); 382 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); 383 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, 384 int type, MemOp mop, hwaddr *pphys, int *pprot); 385 void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 386 vaddr addr, unsigned size, 387 MMUAccessType access_type, 388 int mmu_idx, MemTxAttrs attrs, 389 MemTxResult response, uintptr_t retaddr); 390 extern const MemoryRegionOps hppa_io_eir_ops; 391 extern const VMStateDescription vmstate_hppa_cpu; 392 void hppa_cpu_alarm_timer(void *); 393 #endif 394 G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); 395 396 #endif /* HPPA_CPU_H */ 397