1 /* 2 * PA-RISC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HPPA_CPU_H 21 #define HPPA_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-common.h" 25 #include "exec/cpu-defs.h" 26 #include "exec/cpu-interrupt.h" 27 #include "system/memory.h" 28 #include "qemu/cpu-float.h" 29 #include "qemu/interval-tree.h" 30 #include "hw/registerfields.h" 31 32 #define MMU_ABS_W_IDX 6 33 #define MMU_ABS_IDX 7 34 #define MMU_KERNEL_IDX 8 35 #define MMU_KERNEL_P_IDX 9 36 #define MMU_PL1_IDX 10 37 #define MMU_PL1_P_IDX 11 38 #define MMU_PL2_IDX 12 39 #define MMU_PL2_P_IDX 13 40 #define MMU_USER_IDX 14 41 #define MMU_USER_P_IDX 15 42 43 #define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) < MMU_KERNEL_IDX) 44 #define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2) 45 #define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1) 46 #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX) 47 48 #define PRIV_KERNEL 0 49 #define PRIV_USER 3 50 51 #define TARGET_INSN_START_EXTRA_WORDS 2 52 53 /* No need to flush MMU_ABS*_IDX */ 54 #define HPPA_MMU_FLUSH_MASK \ 55 (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \ 56 1 << MMU_PL1_IDX | 1 << MMU_PL1_P_IDX | \ 57 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \ 58 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX) 59 60 /* Indices to flush for access_id changes. */ 61 #define HPPA_MMU_FLUSH_P_MASK \ 62 (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \ 63 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX) 64 65 /* Hardware exceptions, interrupts, faults, and traps. */ 66 #define EXCP_HPMC 1 /* high priority machine check */ 67 #define EXCP_POWER_FAIL 2 68 #define EXCP_RC 3 /* recovery counter */ 69 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ 70 #define EXCP_LPMC 5 /* low priority machine check */ 71 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ 72 #define EXCP_IMP 7 /* instruction memory protection trap */ 73 #define EXCP_ILL 8 /* illegal instruction trap */ 74 #define EXCP_BREAK 9 /* break instruction */ 75 #define EXCP_PRIV_OPR 10 /* privileged operation trap */ 76 #define EXCP_PRIV_REG 11 /* privileged register trap */ 77 #define EXCP_OVERFLOW 12 /* signed overflow trap */ 78 #define EXCP_COND 13 /* trap-on-condition */ 79 #define EXCP_ASSIST 14 /* assist exception trap */ 80 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ 81 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ 82 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ 83 #define EXCP_DMP 18 /* data memory protection trap */ 84 #define EXCP_DMB 19 /* data memory break trap */ 85 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ 86 #define EXCP_PAGE_REF 21 /* page reference trap */ 87 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ 88 #define EXCP_HPT 23 /* high-privilege transfer trap */ 89 #define EXCP_LPT 24 /* low-privilege transfer trap */ 90 #define EXCP_TB 25 /* taken branch trap */ 91 #define EXCP_DMAR 26 /* data memory access rights trap */ 92 #define EXCP_DMPI 27 /* data memory protection id trap */ 93 #define EXCP_UNALIGN 28 /* unaligned data reference trap */ 94 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ 95 96 /* Exceptions for linux-user emulation. */ 97 #define EXCP_SYSCALL 30 98 #define EXCP_SYSCALL_LWS 31 99 100 /* Emulated hardware TOC button */ 101 #define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */ 102 103 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */ 104 105 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ 106 #define PSW_I 0x00000001 107 #define PSW_D 0x00000002 108 #define PSW_P 0x00000004 109 #define PSW_Q 0x00000008 110 #define PSW_R 0x00000010 111 #define PSW_F 0x00000020 112 #define PSW_G 0x00000040 /* PA1.x only */ 113 #define PSW_O 0x00000080 /* PA2.0 only */ 114 #define PSW_CB 0x0000ff00 115 #define PSW_M 0x00010000 116 #define PSW_V 0x00020000 117 #define PSW_C 0x00040000 118 #define PSW_B 0x00080000 119 #define PSW_X 0x00100000 120 #define PSW_N 0x00200000 121 #define PSW_L 0x00400000 122 #define PSW_H 0x00800000 123 #define PSW_T 0x01000000 124 #define PSW_S 0x02000000 125 #define PSW_E 0x04000000 126 #define PSW_W 0x08000000 /* PA2.0 only */ 127 #define PSW_Z 0x40000000 /* PA1.x only */ 128 #define PSW_Y 0x80000000 /* PA1.x only */ 129 130 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ 131 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) 132 133 /* ssm/rsm instructions number PSW_W and PSW_E differently */ 134 #define PSW_SM_I PSW_I /* Enable External Interrupts */ 135 #define PSW_SM_D PSW_D 136 #define PSW_SM_P PSW_P 137 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ 138 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ 139 #define PSW_SM_E 0x100 140 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ 141 142 #define CR_RC 0 143 #define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ 144 #define PDC_PSW_WIDE_BIT 2 145 #define CR_PID1 8 146 #define CR_PID2 9 147 #define CR_PID3 12 148 #define CR_PID4 13 149 #define CR_SCRCCR 10 150 #define CR_SAR 11 151 #define CR_IVA 14 152 #define CR_EIEM 15 153 #define CR_IT 16 154 #define CR_IIASQ 17 155 #define CR_IIAOQ 18 156 #define CR_IIR 19 157 #define CR_ISR 20 158 #define CR_IOR 21 159 #define CR_IPSW 22 160 #define CR_EIRR 23 161 162 FIELD(FPSR, ENA_I, 0, 1) 163 FIELD(FPSR, ENA_U, 1, 1) 164 FIELD(FPSR, ENA_O, 2, 1) 165 FIELD(FPSR, ENA_Z, 3, 1) 166 FIELD(FPSR, ENA_V, 4, 1) 167 FIELD(FPSR, ENABLES, 0, 5) 168 FIELD(FPSR, D, 5, 1) 169 FIELD(FPSR, T, 6, 1) 170 FIELD(FPSR, RM, 9, 2) 171 FIELD(FPSR, CQ, 11, 11) 172 FIELD(FPSR, CQ0_6, 15, 7) 173 FIELD(FPSR, CQ0_4, 17, 5) 174 FIELD(FPSR, CQ0_2, 19, 3) 175 FIELD(FPSR, CQ0, 21, 1) 176 FIELD(FPSR, CA, 15, 7) 177 FIELD(FPSR, CA0, 21, 1) 178 FIELD(FPSR, C, 26, 1) 179 FIELD(FPSR, FLG_I, 27, 1) 180 FIELD(FPSR, FLG_U, 28, 1) 181 FIELD(FPSR, FLG_O, 29, 1) 182 FIELD(FPSR, FLG_Z, 30, 1) 183 FIELD(FPSR, FLG_V, 31, 1) 184 FIELD(FPSR, FLAGS, 27, 5) 185 186 typedef struct HPPATLBEntry { 187 union { 188 IntervalTreeNode itree; 189 struct HPPATLBEntry *unused_next; 190 }; 191 192 target_ulong pa; 193 194 unsigned entry_valid : 1; 195 196 unsigned u : 1; 197 unsigned t : 1; 198 unsigned d : 1; 199 unsigned b : 1; 200 unsigned ar_type : 3; 201 unsigned ar_pl1 : 2; 202 unsigned ar_pl2 : 2; 203 unsigned access_id : 16; 204 } HPPATLBEntry; 205 206 typedef struct CPUArchState { 207 target_ulong iaoq_f; /* front */ 208 target_ulong iaoq_b; /* back, aka next instruction */ 209 210 target_ulong gr[32]; 211 uint64_t fr[32]; 212 uint64_t sr[8]; /* stored shifted into place for gva */ 213 214 uint32_t psw; /* All psw bits except the following: */ 215 uint32_t psw_xb; /* X and B, in their normal positions */ 216 target_ulong psw_n; /* boolean */ 217 target_long psw_v; /* in bit 31 */ 218 219 /* Splitting the carry-borrow field into the MSB and "the rest", allows 220 * for "the rest" to be deleted when it is unused, but the MSB is in use. 221 * In addition, it's easier to compute carry-in for bit B+1 than it is to 222 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the 223 * host has the appropriate add-with-carry insn to compute the msb). 224 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. 225 */ 226 target_ulong psw_cb; /* in least significant bit of next nibble */ 227 target_ulong psw_cb_msb; /* boolean */ 228 229 uint64_t gva_offset_mask; /* cached address mask based on PSW and %dr2 */ 230 uint64_t iasq_f; 231 uint64_t iasq_b; 232 233 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ 234 float_status fp_status; 235 236 target_ulong cr[32]; /* control registers */ 237 target_ulong cr_back[2]; /* back of cr17/cr18 */ 238 target_ulong shadow[7]; /* shadow registers */ 239 target_ulong dr[32]; /* diagnose registers */ 240 241 /* 242 * During unwind of a memory insn, the base register of the address. 243 * This is used to construct CR_IOR for pa2.0. 244 */ 245 uint32_t unwind_breg; 246 247 /* 248 * ??? The number of entries isn't specified by the architecture. 249 * BTLBs are not supported in 64-bit machines. 250 */ 251 #define PA10_BTLB_FIXED 16 252 #define PA10_BTLB_VARIABLE 0 253 #define HPPA_TLB_ENTRIES 256 254 255 /* Index for round-robin tlb eviction. */ 256 uint32_t tlb_last; 257 258 /* 259 * For pa1.x, the partial initialized, still invalid tlb entry 260 * which has had ITLBA performed, but not yet ITLBP. 261 */ 262 HPPATLBEntry *tlb_partial; 263 264 /* Linked list of all invalid (unused) tlb entries. */ 265 HPPATLBEntry *tlb_unused; 266 267 /* Root of the search tree for all valid tlb entries. */ 268 IntervalTreeRoot tlb_root; 269 270 HPPATLBEntry tlb[HPPA_TLB_ENTRIES]; 271 272 /* Fields up to this point are cleared by a CPU reset */ 273 struct {} end_reset_fields; 274 275 bool is_pa20; 276 277 target_ulong kernel_entry; /* Linux kernel was loaded here */ 278 target_ulong cmdline_or_bootorder; 279 target_ulong initrd_base, initrd_end; 280 } CPUHPPAState; 281 282 /** 283 * HPPACPU: 284 * @env: #CPUHPPAState 285 * 286 * An HPPA CPU. 287 */ 288 struct ArchCPU { 289 CPUState parent_obj; 290 291 CPUHPPAState env; 292 QEMUTimer *alarm_timer; 293 }; 294 295 /** 296 * HPPACPUClass: 297 * @parent_realize: The parent class' realize handler. 298 * @parent_phases: The parent class' reset phase handlers. 299 * 300 * An HPPA CPU model. 301 */ 302 struct HPPACPUClass { 303 CPUClass parent_class; 304 305 DeviceRealize parent_realize; 306 ResettablePhases parent_phases; 307 }; 308 309 static inline bool hppa_is_pa20(const CPUHPPAState *env) 310 { 311 return env->is_pa20; 312 } 313 314 static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) 315 { 316 return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; 317 } 318 319 void hppa_translate_init(void); 320 void hppa_translate_code(CPUState *cs, TranslationBlock *tb, 321 int *max_insns, vaddr pc, void *host_pc); 322 323 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 324 325 static inline target_ulong hppa_form_gva_mask(uint64_t gva_offset_mask, 326 uint64_t spc, target_ulong off) 327 { 328 #ifdef CONFIG_USER_ONLY 329 return off & gva_offset_mask; 330 #else 331 return spc | (off & gva_offset_mask); 332 #endif 333 } 334 335 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, 336 target_ulong off) 337 { 338 return hppa_form_gva_mask(env->gva_offset_mask, spc, off); 339 } 340 341 hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); 342 hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); 343 344 /* 345 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. 346 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the 347 * same value. 348 */ 349 #define TB_FLAG_SR_SAME PSW_I 350 #define TB_FLAG_PRIV_SHIFT 8 351 #define TB_FLAG_UNALIGN 0x400 352 #define TB_FLAG_SPHASH 0x800 353 #define CS_BASE_DIFFPAGE (1 << 12) 354 #define CS_BASE_DIFFSPACE (1 << 13) 355 356 void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, 357 uint64_t *cs_base, uint32_t *pflags); 358 359 target_ulong cpu_hppa_get_psw(CPUHPPAState *env); 360 void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); 361 void update_gva_offset_mask(CPUHPPAState *env); 362 void cpu_hppa_loaded_fr0(CPUHPPAState *env); 363 364 #ifdef CONFIG_USER_ONLY 365 static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } 366 #else 367 void cpu_hppa_change_prot_id(CPUHPPAState *env); 368 #endif 369 370 int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 371 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 372 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); 373 #ifndef CONFIG_USER_ONLY 374 void hppa_ptlbe(CPUHPPAState *env); 375 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); 376 void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled); 377 bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, 378 MMUAccessType access_type, int mmu_idx, 379 MemOp memop, int size, bool probe, uintptr_t ra); 380 void hppa_cpu_do_interrupt(CPUState *cpu); 381 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); 382 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, 383 int type, MemOp mop, hwaddr *pphys, int *pprot); 384 void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 385 vaddr addr, unsigned size, 386 MMUAccessType access_type, 387 int mmu_idx, MemTxAttrs attrs, 388 MemTxResult response, uintptr_t retaddr); 389 extern const MemoryRegionOps hppa_io_eir_ops; 390 extern const VMStateDescription vmstate_hppa_cpu; 391 void hppa_cpu_alarm_timer(void *); 392 #endif 393 G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); 394 395 #endif /* HPPA_CPU_H */ 396