xref: /qemu/target/hppa/cpu.c (revision 6ff5da16000f908140723e164d33a0b51a6c4162)
1 /*
2  * QEMU HPPA CPU
3  *
4  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see
18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/qemu-print.h"
24 #include "qemu/timer.h"
25 #include "cpu.h"
26 #include "qemu/module.h"
27 #include "exec/exec-all.h"
28 #include "exec/translation-block.h"
29 #include "fpu/softfloat.h"
30 #include "tcg/tcg.h"
31 #include "hw/hppa/hppa_hardware.h"
32 
33 static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
34 {
35     HPPACPU *cpu = HPPA_CPU(cs);
36 
37 #ifdef CONFIG_USER_ONLY
38     value |= PRIV_USER;
39 #endif
40     cpu->env.iaoq_f = value;
41     cpu->env.iaoq_b = value + 4;
42 }
43 
44 static vaddr hppa_cpu_get_pc(CPUState *cs)
45 {
46     CPUHPPAState *env = cpu_env(cs);
47 
48     return hppa_form_gva_mask(env->gva_offset_mask,
49                          (env->psw & PSW_C ? env->iasq_f : 0),
50                          env->iaoq_f & -4);
51 }
52 
53 void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
54                           uint64_t *pcsbase, uint32_t *pflags)
55 {
56     uint32_t flags = 0;
57     uint64_t cs_base = 0;
58 
59     /*
60      * TB lookup assumes that PC contains the complete virtual address.
61      * If we leave space+offset separate, we'll get ITLB misses to an
62      * incomplete virtual address.  This also means that we must separate
63      * out current cpu privilege from the low bits of IAOQ_F.
64      */
65     *pc = hppa_cpu_get_pc(env_cpu(env));
66     flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
67 
68     /*
69      * The only really interesting case is if IAQ_Back is on the same page
70      * as IAQ_Front, so that we can use goto_tb between the blocks.  In all
71      * other cases, we'll be ending the TranslationBlock with one insn and
72      * not linking between them.
73      */
74     if (env->iasq_f != env->iasq_b) {
75         cs_base |= CS_BASE_DIFFSPACE;
76     } else if ((env->iaoq_f ^ env->iaoq_b) & TARGET_PAGE_MASK) {
77         cs_base |= CS_BASE_DIFFPAGE;
78     } else {
79         cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK;
80     }
81 
82     /* ??? E, T, H, L bits need to be here, when implemented.  */
83     flags |= env->psw_n * PSW_N;
84     flags |= env->psw_xb;
85     flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
86 
87 #ifdef CONFIG_USER_ONLY
88     flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
89 #else
90     if ((env->sr[4] == env->sr[5])
91         & (env->sr[4] == env->sr[6])
92         & (env->sr[4] == env->sr[7])) {
93         flags |= TB_FLAG_SR_SAME;
94     }
95     if ((env->psw & PSW_W) &&
96         (env->dr[2] & HPPA64_DIAG_SPHASH_ENABLE)) {
97         flags |= TB_FLAG_SPHASH;
98     }
99 #endif
100 
101     *pcsbase = cs_base;
102     *pflags = flags;
103 }
104 
105 static void hppa_cpu_synchronize_from_tb(CPUState *cs,
106                                          const TranslationBlock *tb)
107 {
108     HPPACPU *cpu = HPPA_CPU(cs);
109 
110     /* IAQ is always up-to-date before goto_tb. */
111     cpu->env.psw_n = (tb->flags & PSW_N) != 0;
112     cpu->env.psw_xb = tb->flags & (PSW_X | PSW_B);
113 }
114 
115 static void hppa_restore_state_to_opc(CPUState *cs,
116                                       const TranslationBlock *tb,
117                                       const uint64_t *data)
118 {
119     CPUHPPAState *env = cpu_env(cs);
120 
121     env->iaoq_f = (env->iaoq_f & TARGET_PAGE_MASK) | data[0];
122     if (data[1] != INT32_MIN) {
123         env->iaoq_b = env->iaoq_f + data[1];
124     }
125     env->unwind_breg = data[2];
126     /*
127      * Since we were executing the instruction at IAOQ_F, and took some
128      * sort of action that provoked the cpu_restore_state, we can infer
129      * that the instruction was not nullified.
130      */
131     env->psw_n = 0;
132 }
133 
134 static bool hppa_cpu_has_work(CPUState *cs)
135 {
136     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
137 }
138 
139 static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch)
140 {
141     CPUHPPAState *env = cpu_env(cs);
142 
143     if (env->psw & (ifetch ? PSW_C : PSW_D)) {
144         return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
145     }
146     /* mmu disabled */
147     return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX;
148 }
149 
150 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
151 {
152     info->mach = bfd_mach_hppa20;
153     info->endian = BFD_ENDIAN_BIG;
154     info->print_insn = print_insn_hppa;
155 }
156 
157 #ifndef CONFIG_USER_ONLY
158 static G_NORETURN
159 void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
160                                   MMUAccessType access_type, int mmu_idx,
161                                   uintptr_t retaddr)
162 {
163     HPPACPU *cpu = HPPA_CPU(cs);
164     CPUHPPAState *env = &cpu->env;
165 
166     cs->exception_index = EXCP_UNALIGN;
167     cpu_restore_state(cs, retaddr);
168     hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx));
169 
170     cpu_loop_exit(cs);
171 }
172 #endif /* CONFIG_USER_ONLY */
173 
174 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
175 {
176     CPUState *cs = CPU(dev);
177     HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev);
178     Error *local_err = NULL;
179 
180     cpu_exec_realizefn(cs, &local_err);
181     if (local_err != NULL) {
182         error_propagate(errp, local_err);
183         return;
184     }
185 
186     qemu_init_vcpu(cs);
187     acc->parent_realize(dev, errp);
188 
189 #ifndef CONFIG_USER_ONLY
190     {
191         HPPACPU *cpu = HPPA_CPU(cs);
192 
193         cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
194                                         hppa_cpu_alarm_timer, cpu);
195         hppa_ptlbe(&cpu->env);
196     }
197 #endif
198 
199     /* Use pc-relative instructions always to simplify the translator. */
200     tcg_cflags_set(cs, CF_PCREL);
201 }
202 
203 static void hppa_cpu_initfn(Object *obj)
204 {
205     CPUHPPAState *env = cpu_env(CPU(obj));
206 
207     env->is_pa20 = !!object_dynamic_cast(obj, TYPE_HPPA64_CPU);
208 }
209 
210 static void hppa_cpu_reset_hold(Object *obj, ResetType type)
211 {
212     HPPACPUClass *scc = HPPA_CPU_GET_CLASS(obj);
213     CPUState *cs = CPU(obj);
214     HPPACPU *cpu = HPPA_CPU(obj);
215     CPUHPPAState *env = &cpu->env;
216 
217     if (scc->parent_phases.hold) {
218         scc->parent_phases.hold(obj, type);
219     }
220     cs->exception_index = -1;
221     cs->halted = 0;
222     cpu_set_pc(cs, 0xf0000004);
223 
224     memset(env, 0, offsetof(CPUHPPAState, end_reset_fields));
225 
226     cpu_hppa_loaded_fr0(env);
227 
228     /* 64-bit machines start with space-register hashing enabled in %dr2 */
229     env->dr[2] = hppa_is_pa20(env) ? HPPA64_DIAG_SPHASH_ENABLE : 0;
230 
231     cpu_hppa_put_psw(env, PSW_M);
232 }
233 
234 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
235 {
236     g_autofree char *typename = g_strconcat(cpu_model, "-cpu", NULL);
237 
238     return object_class_by_name(typename);
239 }
240 
241 #ifndef CONFIG_USER_ONLY
242 #include "hw/core/sysemu-cpu-ops.h"
243 
244 static const struct SysemuCPUOps hppa_sysemu_ops = {
245     .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
246 };
247 #endif
248 
249 #include "accel/tcg/cpu-ops.h"
250 
251 static const TCGCPUOps hppa_tcg_ops = {
252     .initialize = hppa_translate_init,
253     .translate_code = hppa_translate_code,
254     .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
255     .restore_state_to_opc = hppa_restore_state_to_opc,
256 
257 #ifndef CONFIG_USER_ONLY
258     .tlb_fill_align = hppa_cpu_tlb_fill_align,
259     .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
260     .cpu_exec_halt = hppa_cpu_has_work,
261     .do_interrupt = hppa_cpu_do_interrupt,
262     .do_unaligned_access = hppa_cpu_do_unaligned_access,
263     .do_transaction_failed = hppa_cpu_do_transaction_failed,
264 #endif /* !CONFIG_USER_ONLY */
265 };
266 
267 static void hppa_cpu_class_init(ObjectClass *oc, void *data)
268 {
269     DeviceClass *dc = DEVICE_CLASS(oc);
270     CPUClass *cc = CPU_CLASS(oc);
271     HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
272     ResettableClass *rc = RESETTABLE_CLASS(oc);
273 
274     device_class_set_parent_realize(dc, hppa_cpu_realizefn,
275                                     &acc->parent_realize);
276 
277     resettable_class_set_parent_phases(rc, NULL, hppa_cpu_reset_hold, NULL,
278                                        &acc->parent_phases);
279 
280     cc->class_by_name = hppa_cpu_class_by_name;
281     cc->has_work = hppa_cpu_has_work;
282     cc->mmu_index = hppa_cpu_mmu_index;
283     cc->dump_state = hppa_cpu_dump_state;
284     cc->set_pc = hppa_cpu_set_pc;
285     cc->get_pc = hppa_cpu_get_pc;
286     cc->gdb_read_register = hppa_cpu_gdb_read_register;
287     cc->gdb_write_register = hppa_cpu_gdb_write_register;
288 #ifndef CONFIG_USER_ONLY
289     dc->vmsd = &vmstate_hppa_cpu;
290     cc->sysemu_ops = &hppa_sysemu_ops;
291 #endif
292     cc->disas_set_info = hppa_cpu_disas_set_info;
293     cc->gdb_num_core_regs = 128;
294     cc->tcg_ops = &hppa_tcg_ops;
295 }
296 
297 static const TypeInfo hppa_cpu_type_infos[] = {
298     {
299         .name = TYPE_HPPA_CPU,
300         .parent = TYPE_CPU,
301         .instance_size = sizeof(HPPACPU),
302         .instance_align = __alignof(HPPACPU),
303         .instance_init = hppa_cpu_initfn,
304         .abstract = false,
305         .class_size = sizeof(HPPACPUClass),
306         .class_init = hppa_cpu_class_init,
307     },
308     {
309         .name = TYPE_HPPA64_CPU,
310         .parent = TYPE_HPPA_CPU,
311     },
312 };
313 
314 DEFINE_TYPES(hppa_cpu_type_infos)
315