1 /* 2 * PA-RISC cpu parameters for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * SPDX-License-Identifier: LGPL-2.0-or-later 6 */ 7 8 #ifndef HPPA_CPU_PARAM_H 9 #define HPPA_CPU_PARAM_H 10 11 #if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32) 12 # define TARGET_PHYS_ADDR_SPACE_BITS 32 13 # define TARGET_VIRT_ADDR_SPACE_BITS 32 14 #else 15 /* ??? PA-8000 through 8600 have 40 bits; PA-8700 and 8900 have 44 bits. */ 16 # define TARGET_PHYS_ADDR_SPACE_BITS 40 17 # define TARGET_VIRT_ADDR_SPACE_BITS 64 18 #endif 19 20 #define TARGET_PAGE_BITS 12 21 22 /* PA-RISC 1.x processors have a strong memory model. */ 23 /* 24 * ??? While we do not yet implement PA-RISC 2.0, those processors have 25 * a weak memory model, but with TLB bits that force ordering on a per-page 26 * basis. It's probably easier to fall back to a strong memory model. 27 */ 28 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL 29 30 #endif 31