1 /* 2 * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_TRANSLATE_H 19 #define HEXAGON_TRANSLATE_H 20 21 #include "qemu/bitmap.h" 22 #include "qemu/log.h" 23 #include "cpu.h" 24 #include "exec/translator.h" 25 #include "tcg/tcg-op.h" 26 #include "insn.h" 27 #include "internal.h" 28 29 typedef struct DisasContext { 30 DisasContextBase base; 31 Packet *pkt; 32 Insn *insn; 33 uint32_t next_PC; 34 uint32_t mem_idx; 35 uint32_t num_packets; 36 uint32_t num_insns; 37 uint32_t num_hvx_insns; 38 int reg_log[REG_WRITES_MAX]; 39 int reg_log_idx; 40 DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); 41 DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS); 42 int preg_log[PRED_WRITES_MAX]; 43 int preg_log_idx; 44 DECLARE_BITMAP(pregs_written, NUM_PREGS); 45 uint8_t store_width[STORES_MAX]; 46 bool s1_store_processed; 47 int future_vregs_idx; 48 int future_vregs_num[VECTOR_TEMPS_MAX]; 49 int tmp_vregs_idx; 50 int tmp_vregs_num[VECTOR_TEMPS_MAX]; 51 int vreg_log[NUM_VREGS]; 52 int vreg_log_idx; 53 DECLARE_BITMAP(vregs_written, NUM_VREGS); 54 DECLARE_BITMAP(insn_vregs_written, NUM_VREGS); 55 DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS); 56 DECLARE_BITMAP(vregs_updated, NUM_VREGS); 57 DECLARE_BITMAP(vregs_select, NUM_VREGS); 58 DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS); 59 DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS); 60 DECLARE_BITMAP(insn_vregs_read, NUM_VREGS); 61 int qreg_log[NUM_QREGS]; 62 int qreg_log_idx; 63 DECLARE_BITMAP(qregs_written, NUM_QREGS); 64 DECLARE_BITMAP(insn_qregs_written, NUM_QREGS); 65 DECLARE_BITMAP(insn_qregs_read, NUM_QREGS); 66 bool pre_commit; 67 bool need_commit; 68 TCGCond branch_cond; 69 target_ulong branch_dest; 70 bool is_tight_loop; 71 bool short_circuit; 72 bool read_after_write; 73 bool has_hvx_overlap; 74 TCGv new_value[TOTAL_PER_THREAD_REGS]; 75 TCGv new_pred_value[NUM_PREGS]; 76 TCGv branch_taken; 77 TCGv dczero_addr; 78 } DisasContext; 79 80 bool is_gather_store_insn(DisasContext *ctx); 81 82 static inline void ctx_log_pred_write(DisasContext *ctx, int pnum) 83 { 84 if (!test_bit(pnum, ctx->pregs_written)) { 85 ctx->preg_log[ctx->preg_log_idx] = pnum; 86 ctx->preg_log_idx++; 87 set_bit(pnum, ctx->pregs_written); 88 } 89 } 90 91 static inline void ctx_log_pred_read(DisasContext *ctx, int pnum) 92 { 93 if (test_bit(pnum, ctx->pregs_written)) { 94 ctx->read_after_write = true; 95 } 96 } 97 98 static inline void ctx_log_pred_read_new(DisasContext *ctx, int pnum) 99 { 100 g_assert(test_bit(pnum, ctx->pregs_written)); 101 } 102 103 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum, 104 bool is_predicated) 105 { 106 if (rnum == HEX_REG_P3_0_ALIASED) { 107 for (int i = 0; i < NUM_PREGS; i++) { 108 ctx_log_pred_write(ctx, i); 109 } 110 } else { 111 if (!test_bit(rnum, ctx->regs_written)) { 112 ctx->reg_log[ctx->reg_log_idx] = rnum; 113 ctx->reg_log_idx++; 114 set_bit(rnum, ctx->regs_written); 115 } 116 if (is_predicated) { 117 set_bit(rnum, ctx->predicated_regs); 118 } 119 } 120 } 121 122 static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum, 123 bool is_predicated) 124 { 125 ctx_log_reg_write(ctx, rnum, is_predicated); 126 ctx_log_reg_write(ctx, rnum + 1, is_predicated); 127 } 128 129 static inline void ctx_log_reg_read(DisasContext *ctx, int rnum) 130 { 131 if (test_bit(rnum, ctx->regs_written)) { 132 ctx->read_after_write = true; 133 } 134 } 135 136 static inline void ctx_log_reg_read_new(DisasContext *ctx, int rnum) 137 { 138 g_assert(test_bit(rnum, ctx->regs_written)); 139 } 140 141 static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum) 142 { 143 ctx_log_reg_read(ctx, rnum); 144 ctx_log_reg_read(ctx, rnum + 1); 145 } 146 147 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, 148 int num, bool alloc_ok); 149 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, 150 int num, bool alloc_ok); 151 152 static inline void ctx_start_hvx_insn(DisasContext *ctx) 153 { 154 bitmap_zero(ctx->insn_vregs_written, NUM_VREGS); 155 bitmap_zero(ctx->insn_vregs_read, NUM_VREGS); 156 bitmap_zero(ctx->insn_qregs_written, NUM_QREGS); 157 bitmap_zero(ctx->insn_qregs_read, NUM_QREGS); 158 } 159 160 static inline void ctx_log_vreg_write(DisasContext *ctx, 161 int rnum, VRegWriteType type, 162 bool is_predicated, bool has_helper) 163 { 164 if (has_helper) { 165 set_bit(rnum, ctx->insn_vregs_written); 166 if (test_bit(rnum, ctx->insn_vregs_read)) { 167 ctx->has_hvx_overlap = true; 168 } 169 } 170 set_bit(rnum, ctx->vregs_written); 171 if (type != EXT_TMP) { 172 if (!test_bit(rnum, ctx->vregs_updated)) { 173 ctx->vreg_log[ctx->vreg_log_idx] = rnum; 174 ctx->vreg_log_idx++; 175 set_bit(rnum, ctx->vregs_updated); 176 } 177 178 set_bit(rnum, ctx->vregs_updated); 179 if (is_predicated) { 180 set_bit(rnum, ctx->predicated_future_vregs); 181 } 182 } 183 if (type == EXT_NEW) { 184 set_bit(rnum, ctx->vregs_select); 185 } 186 if (type == EXT_TMP) { 187 set_bit(rnum, ctx->vregs_updated_tmp); 188 if (is_predicated) { 189 set_bit(rnum, ctx->predicated_tmp_vregs); 190 } 191 } 192 } 193 194 static inline void ctx_log_vreg_write_pair(DisasContext *ctx, 195 int rnum, VRegWriteType type, 196 bool is_predicated, bool has_helper) 197 { 198 ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated, has_helper); 199 ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated, has_helper); 200 } 201 202 static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum, 203 bool has_helper) 204 { 205 if (has_helper) { 206 set_bit(rnum, ctx->insn_vregs_read); 207 if (test_bit(rnum, ctx->insn_vregs_written)) { 208 ctx->has_hvx_overlap = true; 209 } 210 } 211 if (test_bit(rnum, ctx->vregs_written)) { 212 ctx->read_after_write = true; 213 } 214 } 215 216 static inline void ctx_log_vreg_read_new(DisasContext *ctx, int rnum, 217 bool has_helper) 218 { 219 g_assert(is_gather_store_insn(ctx) || 220 test_bit(rnum, ctx->vregs_updated) || 221 test_bit(rnum, ctx->vregs_select) || 222 test_bit(rnum, ctx->vregs_updated_tmp)); 223 if (has_helper) { 224 set_bit(rnum, ctx->insn_vregs_read); 225 if (test_bit(rnum, ctx->insn_vregs_written)) { 226 ctx->has_hvx_overlap = true; 227 } 228 } 229 if (is_gather_store_insn(ctx)) { 230 ctx->read_after_write = true; 231 } 232 } 233 234 static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum, 235 bool has_helper) 236 { 237 ctx_log_vreg_read(ctx, rnum ^ 0, has_helper); 238 ctx_log_vreg_read(ctx, rnum ^ 1, has_helper); 239 } 240 241 static inline void ctx_log_qreg_write(DisasContext *ctx, 242 int rnum, bool has_helper) 243 { 244 if (has_helper) { 245 set_bit(rnum, ctx->insn_qregs_written); 246 if (test_bit(rnum, ctx->insn_qregs_read)) { 247 ctx->has_hvx_overlap = true; 248 } 249 } 250 set_bit(rnum, ctx->qregs_written); 251 ctx->qreg_log[ctx->qreg_log_idx] = rnum; 252 ctx->qreg_log_idx++; 253 } 254 255 static inline void ctx_log_qreg_read(DisasContext *ctx, 256 int qnum, bool has_helper) 257 { 258 if (has_helper) { 259 set_bit(qnum, ctx->insn_qregs_read); 260 if (test_bit(qnum, ctx->insn_qregs_written)) { 261 ctx->has_hvx_overlap = true; 262 } 263 } 264 if (test_bit(qnum, ctx->qregs_written)) { 265 ctx->read_after_write = true; 266 } 267 } 268 269 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; 270 extern TCGv hex_pred[NUM_PREGS]; 271 extern TCGv hex_slot_cancelled; 272 extern TCGv hex_new_value_usr; 273 extern TCGv hex_store_addr[STORES_MAX]; 274 extern TCGv hex_store_width[STORES_MAX]; 275 extern TCGv hex_store_val32[STORES_MAX]; 276 extern TCGv_i64 hex_store_val64[STORES_MAX]; 277 extern TCGv hex_llsc_addr; 278 extern TCGv hex_llsc_val; 279 extern TCGv_i64 hex_llsc_val_i64; 280 extern TCGv hex_vstore_addr[VSTORES_MAX]; 281 extern TCGv hex_vstore_size[VSTORES_MAX]; 282 extern TCGv hex_vstore_pending[VSTORES_MAX]; 283 284 void process_store(DisasContext *ctx, int slot_num); 285 286 FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, 0, 2) 287 FIELD(PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 2, 1) 288 289 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 0, 1) 290 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1, 1) 291 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1) 292 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED, 3, 1) 293 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED, 4, 1) 294 FIELD(PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, 5, 2) 295 296 #endif 297