1 /*
2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/qemu-print.h"
20 #include "cpu.h"
21 #include "internal.h"
22 #include "exec/translation-block.h"
23 #include "qapi/error.h"
24 #include "hw/qdev-properties.h"
25 #include "fpu/softfloat-helpers.h"
26 #include "tcg/tcg.h"
27 #include "exec/gdbstub.h"
28 #include "accel/tcg/cpu-ops.h"
29
hexagon_v66_cpu_init(Object * obj)30 static void hexagon_v66_cpu_init(Object *obj) { }
hexagon_v67_cpu_init(Object * obj)31 static void hexagon_v67_cpu_init(Object *obj) { }
hexagon_v68_cpu_init(Object * obj)32 static void hexagon_v68_cpu_init(Object *obj) { }
hexagon_v69_cpu_init(Object * obj)33 static void hexagon_v69_cpu_init(Object *obj) { }
hexagon_v71_cpu_init(Object * obj)34 static void hexagon_v71_cpu_init(Object *obj) { }
hexagon_v73_cpu_init(Object * obj)35 static void hexagon_v73_cpu_init(Object *obj) { }
36
hexagon_cpu_class_by_name(const char * cpu_model)37 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
38 {
39 ObjectClass *oc;
40 char *typename;
41 char **cpuname;
42
43 cpuname = g_strsplit(cpu_model, ",", 1);
44 typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]);
45 oc = object_class_by_name(typename);
46 g_strfreev(cpuname);
47 g_free(typename);
48
49 return oc;
50 }
51
52 static const Property hexagon_cpu_properties[] = {
53 DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false),
54 DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 0,
55 qdev_prop_uint32, target_ulong),
56 DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true),
57 };
58
59 const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {
60 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
61 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
62 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
63 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
64 "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1",
65 "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15",
66 "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "hvx_cnt", "c23",
67 "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31",
68 };
69
70 /*
71 * One of the main debugging techniques is to use "-d cpu" and compare against
72 * LLDB output when single stepping. However, the target and qemu put the
73 * stacks at different locations. This is used to compensate so the diff is
74 * cleaner.
75 */
adjust_stack_ptrs(CPUHexagonState * env,target_ulong addr)76 static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
77 {
78 HexagonCPU *cpu = env_archcpu(env);
79 target_ulong stack_adjust = cpu->lldb_stack_adjust;
80 target_ulong stack_start = env->stack_start;
81 target_ulong stack_size = 0x10000;
82
83 if (stack_adjust == 0) {
84 return addr;
85 }
86
87 if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) {
88 return addr - stack_adjust;
89 }
90 return addr;
91 }
92
93 /* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */
read_p3_0(CPUHexagonState * env)94 static target_ulong read_p3_0(CPUHexagonState *env)
95 {
96 int32_t control_reg = 0;
97 int i;
98 for (i = NUM_PREGS - 1; i >= 0; i--) {
99 control_reg <<= 8;
100 control_reg |= env->pred[i] & 0xff;
101 }
102 return control_reg;
103 }
104
print_reg(FILE * f,CPUHexagonState * env,int regnum)105 static void print_reg(FILE *f, CPUHexagonState *env, int regnum)
106 {
107 target_ulong value;
108
109 if (regnum == HEX_REG_P3_0_ALIASED) {
110 value = read_p3_0(env);
111 } else {
112 value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum])
113 : env->gpr[regnum];
114 }
115
116 qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n",
117 hexagon_regnames[regnum], value);
118 }
119
print_vreg(FILE * f,CPUHexagonState * env,int regnum,bool skip_if_zero)120 static void print_vreg(FILE *f, CPUHexagonState *env, int regnum,
121 bool skip_if_zero)
122 {
123 if (skip_if_zero) {
124 bool nonzero_found = false;
125 for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) {
126 if (env->VRegs[regnum].ub[i] != 0) {
127 nonzero_found = true;
128 break;
129 }
130 }
131 if (!nonzero_found) {
132 return;
133 }
134 }
135
136 qemu_fprintf(f, " v%d = ( ", regnum);
137 qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]);
138 for (int i = MAX_VEC_SIZE_BYTES - 2; i >= 0; i--) {
139 qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]);
140 }
141 qemu_fprintf(f, " )\n");
142 }
143
hexagon_debug_vreg(CPUHexagonState * env,int regnum)144 void hexagon_debug_vreg(CPUHexagonState *env, int regnum)
145 {
146 print_vreg(stdout, env, regnum, false);
147 }
148
print_qreg(FILE * f,CPUHexagonState * env,int regnum,bool skip_if_zero)149 static void print_qreg(FILE *f, CPUHexagonState *env, int regnum,
150 bool skip_if_zero)
151 {
152 if (skip_if_zero) {
153 bool nonzero_found = false;
154 for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) {
155 if (env->QRegs[regnum].ub[i] != 0) {
156 nonzero_found = true;
157 break;
158 }
159 }
160 if (!nonzero_found) {
161 return;
162 }
163 }
164
165 qemu_fprintf(f, " q%d = ( ", regnum);
166 qemu_fprintf(f, "0x%02x",
167 env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]);
168 for (int i = MAX_VEC_SIZE_BYTES / 8 - 2; i >= 0; i--) {
169 qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]);
170 }
171 qemu_fprintf(f, " )\n");
172 }
173
hexagon_debug_qreg(CPUHexagonState * env,int regnum)174 void hexagon_debug_qreg(CPUHexagonState *env, int regnum)
175 {
176 print_qreg(stdout, env, regnum, false);
177 }
178
hexagon_dump(CPUHexagonState * env,FILE * f,int flags)179 static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)
180 {
181 HexagonCPU *cpu = env_archcpu(env);
182
183 if (cpu->lldb_compat) {
184 /*
185 * When comparing with LLDB, it doesn't step through single-cycle
186 * hardware loops the same way. So, we just skip them here
187 */
188 if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) {
189 return;
190 }
191 env->last_pc_dumped = env->gpr[HEX_REG_PC];
192 }
193
194 qemu_fprintf(f, "General Purpose Registers = {\n");
195 for (int i = 0; i < 32; i++) {
196 print_reg(f, env, i);
197 }
198 print_reg(f, env, HEX_REG_SA0);
199 print_reg(f, env, HEX_REG_LC0);
200 print_reg(f, env, HEX_REG_SA1);
201 print_reg(f, env, HEX_REG_LC1);
202 print_reg(f, env, HEX_REG_M0);
203 print_reg(f, env, HEX_REG_M1);
204 print_reg(f, env, HEX_REG_USR);
205 print_reg(f, env, HEX_REG_P3_0_ALIASED);
206 print_reg(f, env, HEX_REG_GP);
207 print_reg(f, env, HEX_REG_UGP);
208 print_reg(f, env, HEX_REG_PC);
209 #ifdef CONFIG_USER_ONLY
210 /*
211 * Not modelled in user mode, print junk to minimize the diff's
212 * with LLDB output
213 */
214 qemu_fprintf(f, " cause = 0x000000db\n");
215 qemu_fprintf(f, " badva = 0x00000000\n");
216 qemu_fprintf(f, " cs0 = 0x00000000\n");
217 qemu_fprintf(f, " cs1 = 0x00000000\n");
218 #else
219 print_reg(f, env, HEX_REG_CAUSE);
220 print_reg(f, env, HEX_REG_BADVA);
221 print_reg(f, env, HEX_REG_CS0);
222 print_reg(f, env, HEX_REG_CS1);
223 #endif
224 qemu_fprintf(f, "}\n");
225
226 if (flags & CPU_DUMP_FPU) {
227 qemu_fprintf(f, "Vector Registers = {\n");
228 for (int i = 0; i < NUM_VREGS; i++) {
229 print_vreg(f, env, i, true);
230 }
231 for (int i = 0; i < NUM_QREGS; i++) {
232 print_qreg(f, env, i, true);
233 }
234 qemu_fprintf(f, "}\n");
235 }
236 }
237
hexagon_dump_state(CPUState * cs,FILE * f,int flags)238 static void hexagon_dump_state(CPUState *cs, FILE *f, int flags)
239 {
240 hexagon_dump(cpu_env(cs), f, flags);
241 }
242
hexagon_debug(CPUHexagonState * env)243 void hexagon_debug(CPUHexagonState *env)
244 {
245 hexagon_dump(env, stdout, CPU_DUMP_FPU);
246 }
247
hexagon_cpu_set_pc(CPUState * cs,vaddr value)248 static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
249 {
250 cpu_env(cs)->gpr[HEX_REG_PC] = value;
251 }
252
hexagon_cpu_get_pc(CPUState * cs)253 static vaddr hexagon_cpu_get_pc(CPUState *cs)
254 {
255 return cpu_env(cs)->gpr[HEX_REG_PC];
256 }
257
hexagon_get_tb_cpu_state(CPUState * cs)258 static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs)
259 {
260 CPUHexagonState *env = cpu_env(cs);
261 vaddr pc = env->gpr[HEX_REG_PC];
262 uint32_t hex_flags = 0;
263
264 if (pc == env->gpr[HEX_REG_SA0]) {
265 hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
266 }
267 if (pc & PCALIGN_MASK) {
268 hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0);
269 }
270
271 return (TCGTBCPUState){ .pc = pc, .flags = hex_flags };
272 }
273
hexagon_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)274 static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
275 const TranslationBlock *tb)
276 {
277 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
278 cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc;
279 }
280
hexagon_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)281 static void hexagon_restore_state_to_opc(CPUState *cs,
282 const TranslationBlock *tb,
283 const uint64_t *data)
284 {
285 cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
286 }
287
hexagon_cpu_reset_hold(Object * obj,ResetType type)288 static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
289 {
290 CPUState *cs = CPU(obj);
291 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj);
292 CPUHexagonState *env = cpu_env(cs);
293
294 if (mcc->parent_phases.hold) {
295 mcc->parent_phases.hold(obj, type);
296 }
297
298 set_default_nan_mode(1, &env->fp_status);
299 set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
300 /* Default NaN value: sign bit set, all frac bits set */
301 set_float_default_nan_pattern(0b11111111, &env->fp_status);
302 }
303
hexagon_cpu_disas_set_info(CPUState * s,disassemble_info * info)304 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
305 {
306 info->print_insn = print_insn_hexagon;
307 info->endian = BFD_ENDIAN_LITTLE;
308 }
309
hexagon_cpu_realize(DeviceState * dev,Error ** errp)310 static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
311 {
312 CPUState *cs = CPU(dev);
313 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev);
314 Error *local_err = NULL;
315
316 cpu_exec_realizefn(cs, &local_err);
317 if (local_err != NULL) {
318 error_propagate(errp, local_err);
319 return;
320 }
321
322 gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register,
323 hexagon_hvx_gdb_write_register,
324 gdb_find_static_feature("hexagon-hvx.xml"), 0);
325
326 qemu_init_vcpu(cs);
327 cpu_reset(cs);
328
329 mcc->parent_realize(dev, errp);
330 }
331
hexagon_cpu_mmu_index(CPUState * cs,bool ifetch)332 static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch)
333 {
334 return MMU_USER_IDX;
335 }
336
hexagon_cpu_init(Object * obj)337 static void hexagon_cpu_init(Object *obj)
338 {
339 }
340
341 static const TCGCPUOps hexagon_tcg_ops = {
342 /* MTTCG not yet supported: require strict ordering */
343 .guest_default_memory_order = TCG_MO_ALL,
344 .mttcg_supported = false,
345 .initialize = hexagon_translate_init,
346 .translate_code = hexagon_translate_code,
347 .get_tb_cpu_state = hexagon_get_tb_cpu_state,
348 .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
349 .restore_state_to_opc = hexagon_restore_state_to_opc,
350 .mmu_index = hexagon_cpu_mmu_index,
351 };
352
hexagon_cpu_class_init(ObjectClass * c,const void * data)353 static void hexagon_cpu_class_init(ObjectClass *c, const void *data)
354 {
355 HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);
356 CPUClass *cc = CPU_CLASS(c);
357 DeviceClass *dc = DEVICE_CLASS(c);
358 ResettableClass *rc = RESETTABLE_CLASS(c);
359
360 device_class_set_parent_realize(dc, hexagon_cpu_realize,
361 &mcc->parent_realize);
362
363 device_class_set_props(dc, hexagon_cpu_properties);
364 resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL,
365 &mcc->parent_phases);
366
367 cc->class_by_name = hexagon_cpu_class_by_name;
368 cc->dump_state = hexagon_dump_state;
369 cc->set_pc = hexagon_cpu_set_pc;
370 cc->get_pc = hexagon_cpu_get_pc;
371 cc->gdb_read_register = hexagon_gdb_read_register;
372 cc->gdb_write_register = hexagon_gdb_write_register;
373 cc->gdb_stop_before_watchpoint = true;
374 cc->gdb_core_xml_file = "hexagon-core.xml";
375 cc->disas_set_info = hexagon_cpu_disas_set_info;
376 cc->tcg_ops = &hexagon_tcg_ops;
377 }
378
379 #define DEFINE_CPU(type_name, initfn) \
380 { \
381 .name = type_name, \
382 .parent = TYPE_HEXAGON_CPU, \
383 .instance_init = initfn \
384 }
385
386 static const TypeInfo hexagon_cpu_type_infos[] = {
387 {
388 .name = TYPE_HEXAGON_CPU,
389 .parent = TYPE_CPU,
390 .instance_size = sizeof(HexagonCPU),
391 .instance_align = __alignof(HexagonCPU),
392 .instance_init = hexagon_cpu_init,
393 .abstract = true,
394 .class_size = sizeof(HexagonCPUClass),
395 .class_init = hexagon_cpu_class_init,
396 },
397 DEFINE_CPU(TYPE_HEXAGON_CPU_V66, hexagon_v66_cpu_init),
398 DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init),
399 DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init),
400 DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init),
401 DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init),
402 DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init),
403 };
404
405 DEFINE_TYPES(hexagon_cpu_type_infos)
406