1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/qemu-print.h" 20 #include "cpu.h" 21 #include "internal.h" 22 #include "exec/exec-all.h" 23 #include "exec/translation-block.h" 24 #include "qapi/error.h" 25 #include "hw/qdev-properties.h" 26 #include "fpu/softfloat-helpers.h" 27 #include "tcg/tcg.h" 28 #include "exec/gdbstub.h" 29 30 static void hexagon_v66_cpu_init(Object *obj) { } 31 static void hexagon_v67_cpu_init(Object *obj) { } 32 static void hexagon_v68_cpu_init(Object *obj) { } 33 static void hexagon_v69_cpu_init(Object *obj) { } 34 static void hexagon_v71_cpu_init(Object *obj) { } 35 static void hexagon_v73_cpu_init(Object *obj) { } 36 37 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) 38 { 39 ObjectClass *oc; 40 char *typename; 41 char **cpuname; 42 43 cpuname = g_strsplit(cpu_model, ",", 1); 44 typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]); 45 oc = object_class_by_name(typename); 46 g_strfreev(cpuname); 47 g_free(typename); 48 49 return oc; 50 } 51 52 static const Property hexagon_cpu_properties[] = { 53 DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false), 54 DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 0, 55 qdev_prop_uint32, target_ulong), 56 DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true), 57 DEFINE_PROP_END_OF_LIST() 58 }; 59 60 const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { 61 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 62 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 63 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 64 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 65 "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1", 66 "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15", 67 "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "hvx_cnt", "c23", 68 "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31", 69 }; 70 71 /* 72 * One of the main debugging techniques is to use "-d cpu" and compare against 73 * LLDB output when single stepping. However, the target and qemu put the 74 * stacks at different locations. This is used to compensate so the diff is 75 * cleaner. 76 */ 77 static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr) 78 { 79 HexagonCPU *cpu = env_archcpu(env); 80 target_ulong stack_adjust = cpu->lldb_stack_adjust; 81 target_ulong stack_start = env->stack_start; 82 target_ulong stack_size = 0x10000; 83 84 if (stack_adjust == 0) { 85 return addr; 86 } 87 88 if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) { 89 return addr - stack_adjust; 90 } 91 return addr; 92 } 93 94 /* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */ 95 static target_ulong read_p3_0(CPUHexagonState *env) 96 { 97 int32_t control_reg = 0; 98 int i; 99 for (i = NUM_PREGS - 1; i >= 0; i--) { 100 control_reg <<= 8; 101 control_reg |= env->pred[i] & 0xff; 102 } 103 return control_reg; 104 } 105 106 static void print_reg(FILE *f, CPUHexagonState *env, int regnum) 107 { 108 target_ulong value; 109 110 if (regnum == HEX_REG_P3_0_ALIASED) { 111 value = read_p3_0(env); 112 } else { 113 value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum]) 114 : env->gpr[regnum]; 115 } 116 117 qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n", 118 hexagon_regnames[regnum], value); 119 } 120 121 static void print_vreg(FILE *f, CPUHexagonState *env, int regnum, 122 bool skip_if_zero) 123 { 124 if (skip_if_zero) { 125 bool nonzero_found = false; 126 for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) { 127 if (env->VRegs[regnum].ub[i] != 0) { 128 nonzero_found = true; 129 break; 130 } 131 } 132 if (!nonzero_found) { 133 return; 134 } 135 } 136 137 qemu_fprintf(f, " v%d = ( ", regnum); 138 qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]); 139 for (int i = MAX_VEC_SIZE_BYTES - 2; i >= 0; i--) { 140 qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]); 141 } 142 qemu_fprintf(f, " )\n"); 143 } 144 145 void hexagon_debug_vreg(CPUHexagonState *env, int regnum) 146 { 147 print_vreg(stdout, env, regnum, false); 148 } 149 150 static void print_qreg(FILE *f, CPUHexagonState *env, int regnum, 151 bool skip_if_zero) 152 { 153 if (skip_if_zero) { 154 bool nonzero_found = false; 155 for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { 156 if (env->QRegs[regnum].ub[i] != 0) { 157 nonzero_found = true; 158 break; 159 } 160 } 161 if (!nonzero_found) { 162 return; 163 } 164 } 165 166 qemu_fprintf(f, " q%d = ( ", regnum); 167 qemu_fprintf(f, "0x%02x", 168 env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]); 169 for (int i = MAX_VEC_SIZE_BYTES / 8 - 2; i >= 0; i--) { 170 qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]); 171 } 172 qemu_fprintf(f, " )\n"); 173 } 174 175 void hexagon_debug_qreg(CPUHexagonState *env, int regnum) 176 { 177 print_qreg(stdout, env, regnum, false); 178 } 179 180 static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags) 181 { 182 HexagonCPU *cpu = env_archcpu(env); 183 184 if (cpu->lldb_compat) { 185 /* 186 * When comparing with LLDB, it doesn't step through single-cycle 187 * hardware loops the same way. So, we just skip them here 188 */ 189 if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) { 190 return; 191 } 192 env->last_pc_dumped = env->gpr[HEX_REG_PC]; 193 } 194 195 qemu_fprintf(f, "General Purpose Registers = {\n"); 196 for (int i = 0; i < 32; i++) { 197 print_reg(f, env, i); 198 } 199 print_reg(f, env, HEX_REG_SA0); 200 print_reg(f, env, HEX_REG_LC0); 201 print_reg(f, env, HEX_REG_SA1); 202 print_reg(f, env, HEX_REG_LC1); 203 print_reg(f, env, HEX_REG_M0); 204 print_reg(f, env, HEX_REG_M1); 205 print_reg(f, env, HEX_REG_USR); 206 print_reg(f, env, HEX_REG_P3_0_ALIASED); 207 print_reg(f, env, HEX_REG_GP); 208 print_reg(f, env, HEX_REG_UGP); 209 print_reg(f, env, HEX_REG_PC); 210 #ifdef CONFIG_USER_ONLY 211 /* 212 * Not modelled in user mode, print junk to minimize the diff's 213 * with LLDB output 214 */ 215 qemu_fprintf(f, " cause = 0x000000db\n"); 216 qemu_fprintf(f, " badva = 0x00000000\n"); 217 qemu_fprintf(f, " cs0 = 0x00000000\n"); 218 qemu_fprintf(f, " cs1 = 0x00000000\n"); 219 #else 220 print_reg(f, env, HEX_REG_CAUSE); 221 print_reg(f, env, HEX_REG_BADVA); 222 print_reg(f, env, HEX_REG_CS0); 223 print_reg(f, env, HEX_REG_CS1); 224 #endif 225 qemu_fprintf(f, "}\n"); 226 227 if (flags & CPU_DUMP_FPU) { 228 qemu_fprintf(f, "Vector Registers = {\n"); 229 for (int i = 0; i < NUM_VREGS; i++) { 230 print_vreg(f, env, i, true); 231 } 232 for (int i = 0; i < NUM_QREGS; i++) { 233 print_qreg(f, env, i, true); 234 } 235 qemu_fprintf(f, "}\n"); 236 } 237 } 238 239 static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) 240 { 241 hexagon_dump(cpu_env(cs), f, flags); 242 } 243 244 void hexagon_debug(CPUHexagonState *env) 245 { 246 hexagon_dump(env, stdout, CPU_DUMP_FPU); 247 } 248 249 static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) 250 { 251 cpu_env(cs)->gpr[HEX_REG_PC] = value; 252 } 253 254 static vaddr hexagon_cpu_get_pc(CPUState *cs) 255 { 256 return cpu_env(cs)->gpr[HEX_REG_PC]; 257 } 258 259 static void hexagon_cpu_synchronize_from_tb(CPUState *cs, 260 const TranslationBlock *tb) 261 { 262 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 263 cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc; 264 } 265 266 static bool hexagon_cpu_has_work(CPUState *cs) 267 { 268 return true; 269 } 270 271 static void hexagon_restore_state_to_opc(CPUState *cs, 272 const TranslationBlock *tb, 273 const uint64_t *data) 274 { 275 cpu_env(cs)->gpr[HEX_REG_PC] = data[0]; 276 } 277 278 static void hexagon_cpu_reset_hold(Object *obj, ResetType type) 279 { 280 CPUState *cs = CPU(obj); 281 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj); 282 CPUHexagonState *env = cpu_env(cs); 283 284 if (mcc->parent_phases.hold) { 285 mcc->parent_phases.hold(obj, type); 286 } 287 288 set_default_nan_mode(1, &env->fp_status); 289 set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); 290 /* Default NaN value: sign bit set, all frac bits set */ 291 set_float_default_nan_pattern(0b11111111, &env->fp_status); 292 } 293 294 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) 295 { 296 info->print_insn = print_insn_hexagon; 297 } 298 299 static void hexagon_cpu_realize(DeviceState *dev, Error **errp) 300 { 301 CPUState *cs = CPU(dev); 302 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev); 303 Error *local_err = NULL; 304 305 cpu_exec_realizefn(cs, &local_err); 306 if (local_err != NULL) { 307 error_propagate(errp, local_err); 308 return; 309 } 310 311 gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register, 312 hexagon_hvx_gdb_write_register, 313 gdb_find_static_feature("hexagon-hvx.xml"), 0); 314 315 qemu_init_vcpu(cs); 316 cpu_reset(cs); 317 318 mcc->parent_realize(dev, errp); 319 } 320 321 static void hexagon_cpu_init(Object *obj) 322 { 323 } 324 325 #include "hw/core/tcg-cpu-ops.h" 326 327 static const TCGCPUOps hexagon_tcg_ops = { 328 .initialize = hexagon_translate_init, 329 .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, 330 .restore_state_to_opc = hexagon_restore_state_to_opc, 331 }; 332 333 static void hexagon_cpu_class_init(ObjectClass *c, void *data) 334 { 335 HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c); 336 CPUClass *cc = CPU_CLASS(c); 337 DeviceClass *dc = DEVICE_CLASS(c); 338 ResettableClass *rc = RESETTABLE_CLASS(c); 339 340 device_class_set_parent_realize(dc, hexagon_cpu_realize, 341 &mcc->parent_realize); 342 343 device_class_set_props(dc, hexagon_cpu_properties); 344 resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL, 345 &mcc->parent_phases); 346 347 cc->class_by_name = hexagon_cpu_class_by_name; 348 cc->has_work = hexagon_cpu_has_work; 349 cc->dump_state = hexagon_dump_state; 350 cc->set_pc = hexagon_cpu_set_pc; 351 cc->get_pc = hexagon_cpu_get_pc; 352 cc->gdb_read_register = hexagon_gdb_read_register; 353 cc->gdb_write_register = hexagon_gdb_write_register; 354 cc->gdb_stop_before_watchpoint = true; 355 cc->gdb_core_xml_file = "hexagon-core.xml"; 356 cc->disas_set_info = hexagon_cpu_disas_set_info; 357 cc->tcg_ops = &hexagon_tcg_ops; 358 } 359 360 #define DEFINE_CPU(type_name, initfn) \ 361 { \ 362 .name = type_name, \ 363 .parent = TYPE_HEXAGON_CPU, \ 364 .instance_init = initfn \ 365 } 366 367 static const TypeInfo hexagon_cpu_type_infos[] = { 368 { 369 .name = TYPE_HEXAGON_CPU, 370 .parent = TYPE_CPU, 371 .instance_size = sizeof(HexagonCPU), 372 .instance_align = __alignof(HexagonCPU), 373 .instance_init = hexagon_cpu_init, 374 .abstract = true, 375 .class_size = sizeof(HexagonCPUClass), 376 .class_init = hexagon_cpu_class_init, 377 }, 378 DEFINE_CPU(TYPE_HEXAGON_CPU_V66, hexagon_v66_cpu_init), 379 DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), 380 DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init), 381 DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init), 382 DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init), 383 DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init), 384 }; 385 386 DEFINE_TYPES(hexagon_cpu_type_infos) 387