1 /* 2 * QEMU AVR CPU helpers 3 * 4 * Copyright (c) 2016-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 26 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 27 { 28 bool ret = false; 29 CPUClass *cc = CPU_GET_CLASS(cs); 30 AVRCPU *cpu = AVR_CPU(cs); 31 CPUAVRState *env = &cpu->env; 32 33 if (interrupt_request & CPU_INTERRUPT_RESET) { 34 if (cpu_interrupts_enabled(env)) { 35 cs->exception_index = EXCP_RESET; 36 cc->do_interrupt(cs); 37 38 cs->interrupt_request &= ~CPU_INTERRUPT_RESET; 39 40 ret = true; 41 } 42 } 43 if (interrupt_request & CPU_INTERRUPT_HARD) { 44 if (cpu_interrupts_enabled(env) && env->intsrc != 0) { 45 int index = ctz32(env->intsrc); 46 cs->exception_index = EXCP_INT(index); 47 cc->do_interrupt(cs); 48 49 env->intsrc &= env->intsrc - 1; /* clear the interrupt */ 50 cs->interrupt_request &= ~CPU_INTERRUPT_HARD; 51 52 ret = true; 53 } 54 } 55 return ret; 56 } 57 58 void avr_cpu_do_interrupt(CPUState *cs) 59 { 60 AVRCPU *cpu = AVR_CPU(cs); 61 CPUAVRState *env = &cpu->env; 62 63 uint32_t ret = env->pc_w; 64 int vector = 0; 65 int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1; 66 int base = 0; 67 68 if (cs->exception_index == EXCP_RESET) { 69 vector = 0; 70 } else if (env->intsrc != 0) { 71 vector = ctz32(env->intsrc) + 1; 72 } 73 74 if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { 75 cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); 76 cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); 77 cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16); 78 } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { 79 cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); 80 cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); 81 } else { 82 cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); 83 } 84 85 env->pc_w = base + vector * size; 86 env->sregI = 0; /* clear Global Interrupt Flag */ 87 88 cs->exception_index = -1; 89 } 90 91 int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, 92 int len, bool is_write) 93 { 94 return cpu_memory_rw_debug(cs, addr, buf, len, is_write); 95 } 96 97 hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 98 { 99 return addr; /* I assume 1:1 address correspondance */ 100 } 101 102 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 103 MMUAccessType access_type, int mmu_idx, 104 bool probe, uintptr_t retaddr) 105 { 106 int prot = 0; 107 MemTxAttrs attrs = {}; 108 uint32_t paddr; 109 110 address &= TARGET_PAGE_MASK; 111 112 if (mmu_idx == MMU_CODE_IDX) { 113 /* access to code in flash */ 114 paddr = OFFSET_CODE + address; 115 prot = PAGE_READ | PAGE_EXEC; 116 if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) { 117 error_report("execution left flash memory"); 118 abort(); 119 } 120 } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { 121 /* 122 * access to CPU registers, exit and rebuilt this TB to use full access 123 * incase it touches specially handled registers like SREG or SP 124 */ 125 AVRCPU *cpu = AVR_CPU(cs); 126 CPUAVRState *env = &cpu->env; 127 env->fullacc = 1; 128 cpu_loop_exit_restore(cs, retaddr); 129 } else { 130 /* access to memory. nothing special */ 131 paddr = OFFSET_DATA + address; 132 prot = PAGE_READ | PAGE_WRITE; 133 } 134 135 tlb_set_page_with_attrs(cs, address, paddr, attrs, prot, 136 mmu_idx, TARGET_PAGE_SIZE); 137 138 return true; 139 } 140