xref: /qemu/target/avr/helper.c (revision 204a7bd85686601e7c60d1d23502540a8d9661bb) 
1 /*
2  * QEMU AVR CPU helpers
3  *
4  * Copyright (c) 2016-2020 Michael Rolnik
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see
18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qemu/log.h"
23 #include "qemu/error-report.h"
24 #include "cpu.h"
25 #include "accel/tcg/cpu-ops.h"
26 #include "exec/cputlb.h"
27 #include "exec/page-protection.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/address-spaces.h"
30 #include "exec/helper-proto.h"
31 
32 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
33 {
34     CPUAVRState *env = cpu_env(cs);
35 
36     /*
37      * We cannot separate a skip from the next instruction,
38      * as the skip would not be preserved across the interrupt.
39      * Separating the two insn normally only happens at page boundaries.
40      */
41     if (env->skip) {
42         return false;
43     }
44 
45     if (interrupt_request & CPU_INTERRUPT_RESET) {
46         if (cpu_interrupts_enabled(env)) {
47             cs->exception_index = EXCP_RESET;
48             avr_cpu_do_interrupt(cs);
49 
50             cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
51             return true;
52         }
53     }
54     if (interrupt_request & CPU_INTERRUPT_HARD) {
55         if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
56             int index = ctz64(env->intsrc);
57             cs->exception_index = EXCP_INT(index);
58             avr_cpu_do_interrupt(cs);
59 
60             env->intsrc &= env->intsrc - 1; /* clear the interrupt */
61             if (!env->intsrc) {
62                 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
63             }
64             return true;
65         }
66     }
67     return false;
68 }
69 
70 void avr_cpu_do_interrupt(CPUState *cs)
71 {
72     CPUAVRState *env = cpu_env(cs);
73 
74     uint32_t ret = env->pc_w;
75     int vector = 0;
76     int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
77     int base = 0;
78 
79     if (cs->exception_index == EXCP_RESET) {
80         vector = 0;
81     } else if (env->intsrc != 0) {
82         vector = ctz64(env->intsrc) + 1;
83     }
84 
85     if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
86         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
87         cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
88         cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
89     } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
90         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
91         cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
92     } else {
93         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
94     }
95 
96     env->pc_w = base + vector * size;
97     env->sregI = 0; /* clear Global Interrupt Flag */
98 
99     cs->exception_index = -1;
100 }
101 
102 hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
103 {
104     return addr; /* I assume 1:1 address correspondence */
105 }
106 
107 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
108                       MMUAccessType access_type, int mmu_idx,
109                       bool probe, uintptr_t retaddr)
110 {
111     int prot;
112     uint32_t paddr;
113 
114     address &= TARGET_PAGE_MASK;
115 
116     if (mmu_idx == MMU_CODE_IDX) {
117         /* Access to code in flash. */
118         paddr = OFFSET_CODE + address;
119         prot = PAGE_READ | PAGE_EXEC;
120         if (paddr >= OFFSET_DATA) {
121             /*
122              * This should not be possible via any architectural operations.
123              * There is certainly not an exception that we can deliver.
124              * Accept probing that might come from generic code.
125              */
126             if (probe) {
127                 return false;
128             }
129             error_report("execution left flash memory");
130             abort();
131         }
132     } else {
133         /* Access to memory. */
134         paddr = OFFSET_DATA + address;
135         prot = PAGE_READ | PAGE_WRITE;
136     }
137 
138     tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
139     return true;
140 }
141 
142 /*
143  *  helpers
144  */
145 
146 void helper_sleep(CPUAVRState *env)
147 {
148     CPUState *cs = env_cpu(env);
149 
150     cs->exception_index = EXCP_HLT;
151     cpu_loop_exit(cs);
152 }
153 
154 void helper_unsupported(CPUAVRState *env)
155 {
156     CPUState *cs = env_cpu(env);
157 
158     /*
159      *  I count not find what happens on the real platform, so
160      *  it's EXCP_DEBUG for meanwhile
161      */
162     cs->exception_index = EXCP_DEBUG;
163     if (qemu_loglevel_mask(LOG_UNIMP)) {
164         qemu_log("UNSUPPORTED\n");
165         cpu_dump_state(cs, stderr, 0);
166     }
167     cpu_loop_exit(cs);
168 }
169 
170 void helper_debug(CPUAVRState *env)
171 {
172     CPUState *cs = env_cpu(env);
173 
174     cs->exception_index = EXCP_DEBUG;
175     cpu_loop_exit(cs);
176 }
177 
178 void helper_break(CPUAVRState *env)
179 {
180     CPUState *cs = env_cpu(env);
181 
182     cs->exception_index = EXCP_DEBUG;
183     cpu_loop_exit(cs);
184 }
185 
186 void helper_wdr(CPUAVRState *env)
187 {
188     qemu_log_mask(LOG_UNIMP, "WDG reset (not implemented)\n");
189 }
190 
191 /*
192  * The first 32 bytes of the data space are mapped to the cpu regs.
193  * We cannot write these from normal store operations because TCG
194  * does not expect global temps to be modified -- a global may be
195  * live in a host cpu register across the store.  We can however
196  * read these, as TCG does make sure the global temps are saved
197  * in case the load operation traps.
198  */
199 
200 static uint64_t avr_cpu_reg1_read(void *opaque, hwaddr addr, unsigned size)
201 {
202     CPUAVRState *env = opaque;
203 
204     assert(addr < 32);
205     return env->r[addr];
206 }
207 
208 /*
209  * The range 0x38-0x3f of the i/o space is mapped to cpu regs.
210  * As above, we cannot write these from normal store operations.
211  */
212 
213 static uint64_t avr_cpu_reg2_read(void *opaque, hwaddr addr, unsigned size)
214 {
215     CPUAVRState *env = opaque;
216 
217     switch (addr) {
218     case REG_38_RAMPD:
219         return 0xff & (env->rampD >> 16);
220     case REG_38_RAMPX:
221         return 0xff & (env->rampX >> 16);
222     case REG_38_RAMPY:
223         return 0xff & (env->rampY >> 16);
224     case REG_38_RAMPZ:
225         return 0xff & (env->rampZ >> 16);
226     case REG_38_EIDN:
227         return 0xff & (env->eind >> 16);
228     case REG_38_SPL:
229         return env->sp & 0x00ff;
230     case REG_38_SPH:
231         return 0xff & (env->sp >> 8);
232     case REG_38_SREG:
233         return cpu_get_sreg(env);
234     }
235     g_assert_not_reached();
236 }
237 
238 static void avr_cpu_trap_write(void *opaque, hwaddr addr,
239                                uint64_t data64, unsigned size)
240 {
241     CPUAVRState *env = opaque;
242     CPUState *cs = env_cpu(env);
243 
244     env->fullacc = true;
245     cpu_loop_exit_restore(cs, cs->mem_io_pc);
246 }
247 
248 const MemoryRegionOps avr_cpu_reg1 = {
249     .read = avr_cpu_reg1_read,
250     .write = avr_cpu_trap_write,
251     .endianness = DEVICE_NATIVE_ENDIAN,
252     .valid.min_access_size = 1,
253     .valid.max_access_size = 1,
254 };
255 
256 const MemoryRegionOps avr_cpu_reg2 = {
257     .read = avr_cpu_reg2_read,
258     .write = avr_cpu_trap_write,
259     .endianness = DEVICE_NATIVE_ENDIAN,
260     .valid.min_access_size = 1,
261     .valid.max_access_size = 1,
262 };
263 
264 /*
265  *  this function implements ST instruction when there is a possibility to write
266  *  into a CPU register
267  */
268 void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
269 {
270     env->fullacc = false;
271 
272     switch (addr) {
273     case 0 ... 31:
274         /* CPU registers */
275         env->r[addr] = data;
276         break;
277 
278     case REG_38_RAMPD + 0x38 + NUMBER_OF_CPU_REGISTERS:
279         if (avr_feature(env, AVR_FEATURE_RAMPD)) {
280             env->rampD = data << 16;
281         }
282         break;
283     case REG_38_RAMPX + 0x38 + NUMBER_OF_CPU_REGISTERS:
284         if (avr_feature(env, AVR_FEATURE_RAMPX)) {
285             env->rampX = data << 16;
286         }
287         break;
288     case REG_38_RAMPY + 0x38 + NUMBER_OF_CPU_REGISTERS:
289         if (avr_feature(env, AVR_FEATURE_RAMPY)) {
290             env->rampY = data << 16;
291         }
292         break;
293     case REG_38_RAMPZ + 0x38 + NUMBER_OF_CPU_REGISTERS:
294         if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
295             env->rampZ = data << 16;
296         }
297         break;
298     case REG_38_EIDN + 0x38 + NUMBER_OF_CPU_REGISTERS:
299         env->eind = data << 16;
300         break;
301     case REG_38_SPL + 0x38 + NUMBER_OF_CPU_REGISTERS:
302         env->sp = (env->sp & 0xff00) | data;
303         break;
304     case REG_38_SPH + 0x38 + NUMBER_OF_CPU_REGISTERS:
305         if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
306             env->sp = (env->sp & 0x00ff) | (data << 8);
307         }
308         break;
309     case REG_38_SREG + 0x38 + NUMBER_OF_CPU_REGISTERS:
310         cpu_set_sreg(env, data);
311         break;
312 
313     default:
314         address_space_stb(&address_space_memory, OFFSET_DATA + addr, data,
315                           MEMTXATTRS_UNSPECIFIED, NULL);
316         break;
317     }
318 }
319