1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2016-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #ifndef QEMU_AVR_CPU_H 22 #define QEMU_AVR_CPU_H 23 24 #include "cpu-qom.h" 25 #include "exec/cpu-defs.h" 26 #include "system/memory.h" 27 28 #ifdef CONFIG_USER_ONLY 29 #error "AVR 8-bit does not support user mode" 30 #endif 31 32 #define CPU_RESOLVING_TYPE TYPE_AVR_CPU 33 34 /* 35 * AVR has two memory spaces, data & code. 36 * e.g. both have 0 address 37 * ST/LD instructions access data space 38 * LPM/SPM and instruction fetching access code memory space 39 */ 40 #define MMU_CODE_IDX 0 41 #define MMU_DATA_IDX 1 42 43 #define EXCP_RESET 1 44 #define EXCP_INT(n) (EXCP_RESET + (n) + 1) 45 46 /* Number of CPU registers */ 47 #define NUMBER_OF_CPU_REGISTERS 32 48 49 /* CPU registers mapped into i/o ports 0x38-0x3f. */ 50 #define REG_38_RAMPD 0 51 #define REG_38_RAMPX 1 52 #define REG_38_RAMPY 2 53 #define REG_38_RAMPZ 3 54 #define REG_38_EIDN 4 55 #define REG_38_SPL 5 56 #define REG_38_SPH 6 57 #define REG_38_SREG 7 58 59 /* 60 * Offsets of AVR memory regions in host memory space. 61 * 62 * This is needed because the AVR has separate code and data address 63 * spaces that both have start from zero but have to go somewhere in 64 * host memory. 65 * 66 * It's also useful to know where some things are, like the IO registers. 67 */ 68 /* Flash program memory */ 69 #define OFFSET_CODE 0x00000000 70 /* CPU registers, IO registers, and SRAM */ 71 #define OFFSET_DATA 0x00800000 72 /* 73 * IO registers, including status register, stack pointer, and memory 74 * mapped peripherals, mapped just after CPU registers 75 */ 76 #define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS) 77 78 typedef enum AVRFeature { 79 AVR_FEATURE_SRAM, 80 81 AVR_FEATURE_1_BYTE_PC, 82 AVR_FEATURE_2_BYTE_PC, 83 AVR_FEATURE_3_BYTE_PC, 84 85 AVR_FEATURE_1_BYTE_SP, 86 AVR_FEATURE_2_BYTE_SP, 87 88 AVR_FEATURE_BREAK, 89 AVR_FEATURE_DES, 90 AVR_FEATURE_RMW, /* Read Modify Write - XCH LAC LAS LAT */ 91 92 AVR_FEATURE_EIJMP_EICALL, 93 AVR_FEATURE_IJMP_ICALL, 94 AVR_FEATURE_JMP_CALL, 95 96 AVR_FEATURE_ADIW_SBIW, 97 98 AVR_FEATURE_SPM, 99 AVR_FEATURE_SPMX, 100 101 AVR_FEATURE_ELPMX, 102 AVR_FEATURE_ELPM, 103 AVR_FEATURE_LPMX, 104 AVR_FEATURE_LPM, 105 106 AVR_FEATURE_MOVW, 107 AVR_FEATURE_MUL, 108 AVR_FEATURE_RAMPD, 109 AVR_FEATURE_RAMPX, 110 AVR_FEATURE_RAMPY, 111 AVR_FEATURE_RAMPZ, 112 } AVRFeature; 113 114 typedef struct CPUArchState { 115 uint32_t pc_w; /* 0x003fffff up to 22 bits */ 116 117 uint32_t sregC; /* 0x00000001 1 bit */ 118 uint32_t sregZ; /* 0x00000001 1 bit */ 119 uint32_t sregN; /* 0x00000001 1 bit */ 120 uint32_t sregV; /* 0x00000001 1 bit */ 121 uint32_t sregS; /* 0x00000001 1 bit */ 122 uint32_t sregH; /* 0x00000001 1 bit */ 123 uint32_t sregT; /* 0x00000001 1 bit */ 124 uint32_t sregI; /* 0x00000001 1 bit */ 125 126 uint32_t rampD; /* 0x00ff0000 8 bits */ 127 uint32_t rampX; /* 0x00ff0000 8 bits */ 128 uint32_t rampY; /* 0x00ff0000 8 bits */ 129 uint32_t rampZ; /* 0x00ff0000 8 bits */ 130 uint32_t eind; /* 0x00ff0000 8 bits */ 131 132 uint32_t r[NUMBER_OF_CPU_REGISTERS]; /* 8 bits each */ 133 uint32_t sp; /* 16 bits */ 134 135 uint32_t skip; /* if set skip instruction */ 136 137 uint64_t intsrc; /* interrupt sources */ 138 bool fullacc; /* CPU/MEM if true MEM only otherwise */ 139 140 uint64_t features; 141 } CPUAVRState; 142 143 /** 144 * AVRCPU: 145 * @env: #CPUAVRState 146 * 147 * A AVR CPU. 148 */ 149 struct ArchCPU { 150 CPUState parent_obj; 151 152 CPUAVRState env; 153 154 MemoryRegion cpu_reg1; 155 MemoryRegion cpu_reg2; 156 157 /* Initial value of stack pointer */ 158 uint32_t init_sp; 159 }; 160 161 /** 162 * AVRCPUClass: 163 * @parent_realize: The parent class' realize handler. 164 * @parent_phases: The parent class' reset phase handlers. 165 * 166 * A AVR CPU model. 167 */ 168 struct AVRCPUClass { 169 CPUClass parent_class; 170 171 DeviceRealize parent_realize; 172 ResettablePhases parent_phases; 173 }; 174 175 extern const struct VMStateDescription vms_avr_cpu; 176 177 void avr_cpu_do_interrupt(CPUState *cpu); 178 bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req); 179 hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 180 int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 181 int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 182 int avr_print_insn(bfd_vma addr, disassemble_info *info); 183 vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); 184 185 static inline int avr_feature(CPUAVRState *env, AVRFeature feature) 186 { 187 return (env->features & (1U << feature)) != 0; 188 } 189 190 static inline void set_avr_feature(CPUAVRState *env, int feature) 191 { 192 env->features |= (1U << feature); 193 } 194 195 void avr_cpu_tcg_init(void); 196 void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb, 197 int *max_insns, vaddr pc, void *host_pc); 198 199 int cpu_avr_exec(CPUState *cpu); 200 201 enum { 202 TB_FLAGS_FULL_ACCESS = 1, 203 TB_FLAGS_SKIP = 2, 204 }; 205 206 static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, 207 uint64_t *cs_base, uint32_t *pflags) 208 { 209 uint32_t flags = 0; 210 211 *pc = env->pc_w * 2; 212 *cs_base = 0; 213 214 if (env->fullacc) { 215 flags |= TB_FLAGS_FULL_ACCESS; 216 } 217 if (env->skip) { 218 flags |= TB_FLAGS_SKIP; 219 } 220 221 *pflags = flags; 222 } 223 224 static inline int cpu_interrupts_enabled(CPUAVRState *env) 225 { 226 return env->sregI != 0; 227 } 228 229 static inline uint8_t cpu_get_sreg(CPUAVRState *env) 230 { 231 return (env->sregC) << 0 232 | (env->sregZ) << 1 233 | (env->sregN) << 2 234 | (env->sregV) << 3 235 | (env->sregS) << 4 236 | (env->sregH) << 5 237 | (env->sregT) << 6 238 | (env->sregI) << 7; 239 } 240 241 static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg) 242 { 243 env->sregC = (sreg >> 0) & 0x01; 244 env->sregZ = (sreg >> 1) & 0x01; 245 env->sregN = (sreg >> 2) & 0x01; 246 env->sregV = (sreg >> 3) & 0x01; 247 env->sregS = (sreg >> 4) & 0x01; 248 env->sregH = (sreg >> 5) & 0x01; 249 env->sregT = (sreg >> 6) & 0x01; 250 env->sregI = (sreg >> 7) & 0x01; 251 } 252 253 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 254 MMUAccessType access_type, int mmu_idx, 255 bool probe, uintptr_t retaddr); 256 257 extern const MemoryRegionOps avr_cpu_reg1; 258 extern const MemoryRegionOps avr_cpu_reg2; 259 260 #include "exec/cpu-all.h" 261 262 #endif /* QEMU_AVR_CPU_H */ 263