1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2016-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #ifndef QEMU_AVR_CPU_H 22 #define QEMU_AVR_CPU_H 23 24 #include "cpu-qom.h" 25 #include "exec/cpu-common.h" 26 #include "exec/cpu-defs.h" 27 #include "exec/cpu-interrupt.h" 28 #include "system/memory.h" 29 30 #ifdef CONFIG_USER_ONLY 31 #error "AVR 8-bit does not support user mode" 32 #endif 33 34 #define CPU_RESOLVING_TYPE TYPE_AVR_CPU 35 36 /* 37 * AVR has two memory spaces, data & code. 38 * e.g. both have 0 address 39 * ST/LD instructions access data space 40 * LPM/SPM and instruction fetching access code memory space 41 */ 42 #define MMU_CODE_IDX 0 43 #define MMU_DATA_IDX 1 44 45 #define EXCP_RESET 1 46 #define EXCP_INT(n) (EXCP_RESET + (n) + 1) 47 48 /* Number of CPU registers */ 49 #define NUMBER_OF_CPU_REGISTERS 32 50 51 /* CPU registers mapped into i/o ports 0x38-0x3f. */ 52 #define REG_38_RAMPD 0 53 #define REG_38_RAMPX 1 54 #define REG_38_RAMPY 2 55 #define REG_38_RAMPZ 3 56 #define REG_38_EIDN 4 57 #define REG_38_SPL 5 58 #define REG_38_SPH 6 59 #define REG_38_SREG 7 60 61 /* 62 * Offsets of AVR memory regions in host memory space. 63 * 64 * This is needed because the AVR has separate code and data address 65 * spaces that both have start from zero but have to go somewhere in 66 * host memory. 67 * 68 * It's also useful to know where some things are, like the IO registers. 69 */ 70 /* Flash program memory */ 71 #define OFFSET_CODE 0x00000000 72 /* CPU registers, IO registers, and SRAM */ 73 #define OFFSET_DATA 0x00800000 74 /* 75 * IO registers, including status register, stack pointer, and memory 76 * mapped peripherals, mapped just after CPU registers 77 */ 78 #define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS) 79 80 typedef enum AVRFeature { 81 AVR_FEATURE_SRAM, 82 83 AVR_FEATURE_1_BYTE_PC, 84 AVR_FEATURE_2_BYTE_PC, 85 AVR_FEATURE_3_BYTE_PC, 86 87 AVR_FEATURE_1_BYTE_SP, 88 AVR_FEATURE_2_BYTE_SP, 89 90 AVR_FEATURE_BREAK, 91 AVR_FEATURE_DES, 92 AVR_FEATURE_RMW, /* Read Modify Write - XCH LAC LAS LAT */ 93 94 AVR_FEATURE_EIJMP_EICALL, 95 AVR_FEATURE_IJMP_ICALL, 96 AVR_FEATURE_JMP_CALL, 97 98 AVR_FEATURE_ADIW_SBIW, 99 100 AVR_FEATURE_SPM, 101 AVR_FEATURE_SPMX, 102 103 AVR_FEATURE_ELPMX, 104 AVR_FEATURE_ELPM, 105 AVR_FEATURE_LPMX, 106 AVR_FEATURE_LPM, 107 108 AVR_FEATURE_MOVW, 109 AVR_FEATURE_MUL, 110 AVR_FEATURE_RAMPD, 111 AVR_FEATURE_RAMPX, 112 AVR_FEATURE_RAMPY, 113 AVR_FEATURE_RAMPZ, 114 } AVRFeature; 115 116 typedef struct CPUArchState { 117 uint32_t pc_w; /* 0x003fffff up to 22 bits */ 118 119 uint32_t sregC; /* 0x00000001 1 bit */ 120 uint32_t sregZ; /* 0x00000001 1 bit */ 121 uint32_t sregN; /* 0x00000001 1 bit */ 122 uint32_t sregV; /* 0x00000001 1 bit */ 123 uint32_t sregS; /* 0x00000001 1 bit */ 124 uint32_t sregH; /* 0x00000001 1 bit */ 125 uint32_t sregT; /* 0x00000001 1 bit */ 126 uint32_t sregI; /* 0x00000001 1 bit */ 127 128 uint32_t rampD; /* 0x00ff0000 8 bits */ 129 uint32_t rampX; /* 0x00ff0000 8 bits */ 130 uint32_t rampY; /* 0x00ff0000 8 bits */ 131 uint32_t rampZ; /* 0x00ff0000 8 bits */ 132 uint32_t eind; /* 0x00ff0000 8 bits */ 133 134 uint32_t r[NUMBER_OF_CPU_REGISTERS]; /* 8 bits each */ 135 uint32_t sp; /* 16 bits */ 136 137 uint32_t skip; /* if set skip instruction */ 138 139 uint64_t intsrc; /* interrupt sources */ 140 bool fullacc; /* CPU/MEM if true MEM only otherwise */ 141 142 uint64_t features; 143 } CPUAVRState; 144 145 /** 146 * AVRCPU: 147 * @env: #CPUAVRState 148 * 149 * A AVR CPU. 150 */ 151 struct ArchCPU { 152 CPUState parent_obj; 153 154 CPUAVRState env; 155 156 MemoryRegion cpu_reg1; 157 MemoryRegion cpu_reg2; 158 159 /* Initial value of stack pointer */ 160 uint32_t init_sp; 161 }; 162 163 /** 164 * AVRCPUClass: 165 * @parent_realize: The parent class' realize handler. 166 * @parent_phases: The parent class' reset phase handlers. 167 * 168 * A AVR CPU model. 169 */ 170 struct AVRCPUClass { 171 CPUClass parent_class; 172 173 DeviceRealize parent_realize; 174 ResettablePhases parent_phases; 175 }; 176 177 extern const struct VMStateDescription vms_avr_cpu; 178 179 void avr_cpu_do_interrupt(CPUState *cpu); 180 bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req); 181 hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 182 int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 183 int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 184 int avr_print_insn(bfd_vma addr, disassemble_info *info); 185 vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); 186 187 static inline int avr_feature(CPUAVRState *env, AVRFeature feature) 188 { 189 return (env->features & (1U << feature)) != 0; 190 } 191 192 static inline void set_avr_feature(CPUAVRState *env, int feature) 193 { 194 env->features |= (1U << feature); 195 } 196 197 void avr_cpu_tcg_init(void); 198 void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb, 199 int *max_insns, vaddr pc, void *host_pc); 200 201 int cpu_avr_exec(CPUState *cpu); 202 203 enum { 204 TB_FLAGS_FULL_ACCESS = 1, 205 TB_FLAGS_SKIP = 2, 206 }; 207 208 static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, 209 uint64_t *cs_base, uint32_t *pflags) 210 { 211 uint32_t flags = 0; 212 213 *pc = env->pc_w * 2; 214 *cs_base = 0; 215 216 if (env->fullacc) { 217 flags |= TB_FLAGS_FULL_ACCESS; 218 } 219 if (env->skip) { 220 flags |= TB_FLAGS_SKIP; 221 } 222 223 *pflags = flags; 224 } 225 226 static inline int cpu_interrupts_enabled(CPUAVRState *env) 227 { 228 return env->sregI != 0; 229 } 230 231 static inline uint8_t cpu_get_sreg(CPUAVRState *env) 232 { 233 return (env->sregC) << 0 234 | (env->sregZ) << 1 235 | (env->sregN) << 2 236 | (env->sregV) << 3 237 | (env->sregS) << 4 238 | (env->sregH) << 5 239 | (env->sregT) << 6 240 | (env->sregI) << 7; 241 } 242 243 static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg) 244 { 245 env->sregC = (sreg >> 0) & 0x01; 246 env->sregZ = (sreg >> 1) & 0x01; 247 env->sregN = (sreg >> 2) & 0x01; 248 env->sregV = (sreg >> 3) & 0x01; 249 env->sregS = (sreg >> 4) & 0x01; 250 env->sregH = (sreg >> 5) & 0x01; 251 env->sregT = (sreg >> 6) & 0x01; 252 env->sregI = (sreg >> 7) & 0x01; 253 } 254 255 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 256 MMUAccessType access_type, int mmu_idx, 257 bool probe, uintptr_t retaddr); 258 259 extern const MemoryRegionOps avr_cpu_reg1; 260 extern const MemoryRegionOps avr_cpu_reg2; 261 262 #endif /* QEMU_AVR_CPU_H */ 263