1*c8c0d267SMichael Rolnik /* 2*c8c0d267SMichael Rolnik * QEMU AVR CPU 3*c8c0d267SMichael Rolnik * 4*c8c0d267SMichael Rolnik * Copyright (c) 2016-2020 Michael Rolnik 5*c8c0d267SMichael Rolnik * 6*c8c0d267SMichael Rolnik * This library is free software; you can redistribute it and/or 7*c8c0d267SMichael Rolnik * modify it under the terms of the GNU Lesser General Public 8*c8c0d267SMichael Rolnik * License as published by the Free Software Foundation; either 9*c8c0d267SMichael Rolnik * version 2.1 of the License, or (at your option) any later version. 10*c8c0d267SMichael Rolnik * 11*c8c0d267SMichael Rolnik * This library is distributed in the hope that it will be useful, 12*c8c0d267SMichael Rolnik * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*c8c0d267SMichael Rolnik * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14*c8c0d267SMichael Rolnik * Lesser General Public License for more details. 15*c8c0d267SMichael Rolnik * 16*c8c0d267SMichael Rolnik * You should have received a copy of the GNU Lesser General Public 17*c8c0d267SMichael Rolnik * License along with this library; if not, see 18*c8c0d267SMichael Rolnik * <http://www.gnu.org/licenses/lgpl-2.1.html> 19*c8c0d267SMichael Rolnik */ 20*c8c0d267SMichael Rolnik 21*c8c0d267SMichael Rolnik #ifndef QEMU_AVR_CPU_H 22*c8c0d267SMichael Rolnik #define QEMU_AVR_CPU_H 23*c8c0d267SMichael Rolnik 24*c8c0d267SMichael Rolnik #include "exec/cpu-defs.h" 25*c8c0d267SMichael Rolnik 26*c8c0d267SMichael Rolnik #define TCG_GUEST_DEFAULT_MO 0 27*c8c0d267SMichael Rolnik 28*c8c0d267SMichael Rolnik /* 29*c8c0d267SMichael Rolnik * AVR has two memory spaces, data & code. 30*c8c0d267SMichael Rolnik * e.g. both have 0 address 31*c8c0d267SMichael Rolnik * ST/LD instructions access data space 32*c8c0d267SMichael Rolnik * LPM/SPM and instruction fetching access code memory space 33*c8c0d267SMichael Rolnik */ 34*c8c0d267SMichael Rolnik #define MMU_CODE_IDX 0 35*c8c0d267SMichael Rolnik #define MMU_DATA_IDX 1 36*c8c0d267SMichael Rolnik 37*c8c0d267SMichael Rolnik #define EXCP_RESET 1 38*c8c0d267SMichael Rolnik #define EXCP_INT(n) (EXCP_RESET + (n) + 1) 39*c8c0d267SMichael Rolnik 40*c8c0d267SMichael Rolnik /* Number of CPU registers */ 41*c8c0d267SMichael Rolnik #define NUMBER_OF_CPU_REGISTERS 32 42*c8c0d267SMichael Rolnik /* Number of IO registers accessible by ld/st/in/out */ 43*c8c0d267SMichael Rolnik #define NUMBER_OF_IO_REGISTERS 64 44*c8c0d267SMichael Rolnik 45*c8c0d267SMichael Rolnik /* 46*c8c0d267SMichael Rolnik * Offsets of AVR memory regions in host memory space. 47*c8c0d267SMichael Rolnik * 48*c8c0d267SMichael Rolnik * This is needed because the AVR has separate code and data address 49*c8c0d267SMichael Rolnik * spaces that both have start from zero but have to go somewhere in 50*c8c0d267SMichael Rolnik * host memory. 51*c8c0d267SMichael Rolnik * 52*c8c0d267SMichael Rolnik * It's also useful to know where some things are, like the IO registers. 53*c8c0d267SMichael Rolnik */ 54*c8c0d267SMichael Rolnik /* Flash program memory */ 55*c8c0d267SMichael Rolnik #define OFFSET_CODE 0x00000000 56*c8c0d267SMichael Rolnik /* CPU registers, IO registers, and SRAM */ 57*c8c0d267SMichael Rolnik #define OFFSET_DATA 0x00800000 58*c8c0d267SMichael Rolnik /* CPU registers specifically, these are mapped at the start of data */ 59*c8c0d267SMichael Rolnik #define OFFSET_CPU_REGISTERS OFFSET_DATA 60*c8c0d267SMichael Rolnik /* 61*c8c0d267SMichael Rolnik * IO registers, including status register, stack pointer, and memory 62*c8c0d267SMichael Rolnik * mapped peripherals, mapped just after CPU registers 63*c8c0d267SMichael Rolnik */ 64*c8c0d267SMichael Rolnik #define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS) 65*c8c0d267SMichael Rolnik 66*c8c0d267SMichael Rolnik #endif /* !defined (QEMU_AVR_CPU_H) */ 67