1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "exec/exec-all.h" 25 #include "exec/translation-block.h" 26 #include "cpu.h" 27 #include "disas/dis-asm.h" 28 #include "tcg/debug-assert.h" 29 #include "hw/qdev-properties.h" 30 31 static void avr_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 AVRCPU *cpu = AVR_CPU(cs); 34 35 cpu->env.pc_w = value / 2; /* internally PC points to words */ 36 } 37 38 static vaddr avr_cpu_get_pc(CPUState *cs) 39 { 40 AVRCPU *cpu = AVR_CPU(cs); 41 42 return cpu->env.pc_w * 2; 43 } 44 45 static bool avr_cpu_has_work(CPUState *cs) 46 { 47 return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) 48 && cpu_interrupts_enabled(cpu_env(cs)); 49 } 50 51 static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) 52 { 53 return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; 54 } 55 56 static void avr_cpu_synchronize_from_tb(CPUState *cs, 57 const TranslationBlock *tb) 58 { 59 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 60 cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */ 61 } 62 63 static void avr_restore_state_to_opc(CPUState *cs, 64 const TranslationBlock *tb, 65 const uint64_t *data) 66 { 67 cpu_env(cs)->pc_w = data[0]; 68 } 69 70 static void avr_cpu_reset_hold(Object *obj, ResetType type) 71 { 72 CPUState *cs = CPU(obj); 73 AVRCPU *cpu = AVR_CPU(cs); 74 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(obj); 75 CPUAVRState *env = &cpu->env; 76 77 if (mcc->parent_phases.hold) { 78 mcc->parent_phases.hold(obj, type); 79 } 80 81 env->pc_w = 0; 82 env->sregI = 1; 83 env->sregC = 0; 84 env->sregZ = 0; 85 env->sregN = 0; 86 env->sregV = 0; 87 env->sregS = 0; 88 env->sregH = 0; 89 env->sregT = 0; 90 91 env->rampD = 0; 92 env->rampX = 0; 93 env->rampY = 0; 94 env->rampZ = 0; 95 env->eind = 0; 96 env->sp = cpu->init_sp; 97 98 env->skip = 0; 99 100 memset(env->r, 0, sizeof(env->r)); 101 } 102 103 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 104 { 105 info->mach = bfd_arch_avr; 106 info->print_insn = avr_print_insn; 107 } 108 109 static void avr_cpu_realizefn(DeviceState *dev, Error **errp) 110 { 111 CPUState *cs = CPU(dev); 112 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); 113 Error *local_err = NULL; 114 115 cpu_exec_realizefn(cs, &local_err); 116 if (local_err != NULL) { 117 error_propagate(errp, local_err); 118 return; 119 } 120 qemu_init_vcpu(cs); 121 cpu_reset(cs); 122 123 mcc->parent_realize(dev, errp); 124 } 125 126 static void avr_cpu_set_int(void *opaque, int irq, int level) 127 { 128 AVRCPU *cpu = opaque; 129 CPUAVRState *env = &cpu->env; 130 CPUState *cs = CPU(cpu); 131 uint64_t mask = (1ull << irq); 132 133 if (level) { 134 env->intsrc |= mask; 135 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 136 } else { 137 env->intsrc &= ~mask; 138 if (env->intsrc == 0) { 139 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 140 } 141 } 142 } 143 144 static void avr_cpu_initfn(Object *obj) 145 { 146 AVRCPU *cpu = AVR_CPU(obj); 147 148 /* Set the number of interrupts supported by the CPU. */ 149 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 150 sizeof(cpu->env.intsrc) * 8); 151 } 152 153 static const Property avr_cpu_properties[] = { 154 DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0), 155 }; 156 157 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) 158 { 159 return object_class_by_name(cpu_model); 160 } 161 162 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) 163 { 164 CPUAVRState *env = cpu_env(cs); 165 int i; 166 167 qemu_fprintf(f, "\n"); 168 qemu_fprintf(f, "PC: %06x\n", env->pc_w * 2); /* PC points to words */ 169 qemu_fprintf(f, "SP: %04x\n", env->sp); 170 qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16); 171 qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16); 172 qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16); 173 qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16); 174 qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16); 175 qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]); 176 qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]); 177 qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]); 178 qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n", 179 env->sregI ? 'I' : '-', 180 env->sregT ? 'T' : '-', 181 env->sregH ? 'H' : '-', 182 env->sregS ? 'S' : '-', 183 env->sregV ? 'V' : '-', 184 env->sregN ? '-' : 'N', /* Zf has negative logic */ 185 env->sregZ ? 'Z' : '-', 186 env->sregC ? 'I' : '-'); 187 qemu_fprintf(f, "SKIP: %02x\n", env->skip); 188 189 qemu_fprintf(f, "\n"); 190 for (i = 0; i < ARRAY_SIZE(env->r); i++) { 191 qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]); 192 193 if ((i % 8) == 7) { 194 qemu_fprintf(f, "\n"); 195 } 196 } 197 qemu_fprintf(f, "\n"); 198 } 199 200 #include "hw/core/sysemu-cpu-ops.h" 201 202 static const struct SysemuCPUOps avr_sysemu_ops = { 203 .get_phys_page_debug = avr_cpu_get_phys_page_debug, 204 }; 205 206 #include "hw/core/tcg-cpu-ops.h" 207 208 static const TCGCPUOps avr_tcg_ops = { 209 .initialize = avr_cpu_tcg_init, 210 .translate_code = avr_cpu_translate_code, 211 .synchronize_from_tb = avr_cpu_synchronize_from_tb, 212 .restore_state_to_opc = avr_restore_state_to_opc, 213 .cpu_exec_interrupt = avr_cpu_exec_interrupt, 214 .cpu_exec_halt = avr_cpu_has_work, 215 .tlb_fill = avr_cpu_tlb_fill, 216 .do_interrupt = avr_cpu_do_interrupt, 217 }; 218 219 static void avr_cpu_class_init(ObjectClass *oc, void *data) 220 { 221 DeviceClass *dc = DEVICE_CLASS(oc); 222 CPUClass *cc = CPU_CLASS(oc); 223 AVRCPUClass *mcc = AVR_CPU_CLASS(oc); 224 ResettableClass *rc = RESETTABLE_CLASS(oc); 225 226 device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize); 227 228 device_class_set_props(dc, avr_cpu_properties); 229 230 resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL, 231 &mcc->parent_phases); 232 233 cc->class_by_name = avr_cpu_class_by_name; 234 235 cc->has_work = avr_cpu_has_work; 236 cc->mmu_index = avr_cpu_mmu_index; 237 cc->dump_state = avr_cpu_dump_state; 238 cc->set_pc = avr_cpu_set_pc; 239 cc->get_pc = avr_cpu_get_pc; 240 dc->vmsd = &vms_avr_cpu; 241 cc->sysemu_ops = &avr_sysemu_ops; 242 cc->disas_set_info = avr_cpu_disas_set_info; 243 cc->gdb_read_register = avr_cpu_gdb_read_register; 244 cc->gdb_write_register = avr_cpu_gdb_write_register; 245 cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint; 246 cc->gdb_core_xml_file = "avr-cpu.xml"; 247 cc->tcg_ops = &avr_tcg_ops; 248 } 249 250 /* 251 * Setting features of AVR core type avr5 252 * -------------------------------------- 253 * 254 * This type of AVR core is present in the following AVR MCUs: 255 * 256 * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c, 257 * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162, 258 * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, 259 * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, 260 * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb, 261 * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323, 262 * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, 263 * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, 264 * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa, 265 * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1, 266 * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644, 267 * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, 268 * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, 269 * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p, 270 * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2, 271 * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216, 272 * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000 273 */ 274 static void avr_avr5_initfn(Object *obj) 275 { 276 CPUAVRState *env = cpu_env(CPU(obj)); 277 278 set_avr_feature(env, AVR_FEATURE_LPM); 279 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 280 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 281 set_avr_feature(env, AVR_FEATURE_SRAM); 282 set_avr_feature(env, AVR_FEATURE_BREAK); 283 284 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 285 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 286 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 287 set_avr_feature(env, AVR_FEATURE_LPMX); 288 set_avr_feature(env, AVR_FEATURE_MOVW); 289 set_avr_feature(env, AVR_FEATURE_MUL); 290 } 291 292 /* 293 * Setting features of AVR core type avr51 294 * -------------------------------------- 295 * 296 * This type of AVR core is present in the following AVR MCUs: 297 * 298 * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p, 299 * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 300 * at90usb1287 301 */ 302 static void avr_avr51_initfn(Object *obj) 303 { 304 CPUAVRState *env = cpu_env(CPU(obj)); 305 306 set_avr_feature(env, AVR_FEATURE_LPM); 307 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 308 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 309 set_avr_feature(env, AVR_FEATURE_SRAM); 310 set_avr_feature(env, AVR_FEATURE_BREAK); 311 312 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 313 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 314 set_avr_feature(env, AVR_FEATURE_RAMPZ); 315 set_avr_feature(env, AVR_FEATURE_ELPMX); 316 set_avr_feature(env, AVR_FEATURE_ELPM); 317 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 318 set_avr_feature(env, AVR_FEATURE_LPMX); 319 set_avr_feature(env, AVR_FEATURE_MOVW); 320 set_avr_feature(env, AVR_FEATURE_MUL); 321 } 322 323 /* 324 * Setting features of AVR core type avr6 325 * -------------------------------------- 326 * 327 * This type of AVR core is present in the following AVR MCUs: 328 * 329 * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2 330 */ 331 static void avr_avr6_initfn(Object *obj) 332 { 333 CPUAVRState *env = cpu_env(CPU(obj)); 334 335 set_avr_feature(env, AVR_FEATURE_LPM); 336 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 337 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 338 set_avr_feature(env, AVR_FEATURE_SRAM); 339 set_avr_feature(env, AVR_FEATURE_BREAK); 340 341 set_avr_feature(env, AVR_FEATURE_3_BYTE_PC); 342 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 343 set_avr_feature(env, AVR_FEATURE_RAMPZ); 344 set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL); 345 set_avr_feature(env, AVR_FEATURE_ELPMX); 346 set_avr_feature(env, AVR_FEATURE_ELPM); 347 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 348 set_avr_feature(env, AVR_FEATURE_LPMX); 349 set_avr_feature(env, AVR_FEATURE_MOVW); 350 set_avr_feature(env, AVR_FEATURE_MUL); 351 } 352 353 typedef struct AVRCPUInfo { 354 const char *name; 355 void (*initfn)(Object *obj); 356 } AVRCPUInfo; 357 358 359 #define DEFINE_AVR_CPU_TYPE(model, initfn) \ 360 { \ 361 .parent = TYPE_AVR_CPU, \ 362 .instance_init = initfn, \ 363 .name = AVR_CPU_TYPE_NAME(model), \ 364 } 365 366 static const TypeInfo avr_cpu_type_info[] = { 367 { 368 .name = TYPE_AVR_CPU, 369 .parent = TYPE_CPU, 370 .instance_size = sizeof(AVRCPU), 371 .instance_align = __alignof(AVRCPU), 372 .instance_init = avr_cpu_initfn, 373 .class_size = sizeof(AVRCPUClass), 374 .class_init = avr_cpu_class_init, 375 .abstract = true, 376 }, 377 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), 378 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), 379 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), 380 }; 381 382 DEFINE_TYPES(avr_cpu_type_info) 383