1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "exec/exec-all.h" 25 #include "exec/translation-block.h" 26 #include "exec/address-spaces.h" 27 #include "cpu.h" 28 #include "disas/dis-asm.h" 29 #include "tcg/debug-assert.h" 30 #include "hw/qdev-properties.h" 31 32 static void avr_cpu_set_pc(CPUState *cs, vaddr value) 33 { 34 AVRCPU *cpu = AVR_CPU(cs); 35 36 cpu->env.pc_w = value / 2; /* internally PC points to words */ 37 } 38 39 static vaddr avr_cpu_get_pc(CPUState *cs) 40 { 41 AVRCPU *cpu = AVR_CPU(cs); 42 43 return cpu->env.pc_w * 2; 44 } 45 46 static bool avr_cpu_has_work(CPUState *cs) 47 { 48 return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) 49 && cpu_interrupts_enabled(cpu_env(cs)); 50 } 51 52 static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) 53 { 54 return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; 55 } 56 57 static void avr_cpu_synchronize_from_tb(CPUState *cs, 58 const TranslationBlock *tb) 59 { 60 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 61 cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */ 62 } 63 64 static void avr_restore_state_to_opc(CPUState *cs, 65 const TranslationBlock *tb, 66 const uint64_t *data) 67 { 68 cpu_env(cs)->pc_w = data[0]; 69 } 70 71 static void avr_cpu_reset_hold(Object *obj, ResetType type) 72 { 73 CPUState *cs = CPU(obj); 74 AVRCPU *cpu = AVR_CPU(cs); 75 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(obj); 76 CPUAVRState *env = &cpu->env; 77 78 if (mcc->parent_phases.hold) { 79 mcc->parent_phases.hold(obj, type); 80 } 81 82 env->pc_w = 0; 83 env->sregI = 1; 84 env->sregC = 0; 85 env->sregZ = 0; 86 env->sregN = 0; 87 env->sregV = 0; 88 env->sregS = 0; 89 env->sregH = 0; 90 env->sregT = 0; 91 92 env->rampD = 0; 93 env->rampX = 0; 94 env->rampY = 0; 95 env->rampZ = 0; 96 env->eind = 0; 97 env->sp = cpu->init_sp; 98 99 env->skip = 0; 100 101 memset(env->r, 0, sizeof(env->r)); 102 } 103 104 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 105 { 106 info->endian = BFD_ENDIAN_LITTLE; 107 info->mach = bfd_arch_avr; 108 info->print_insn = avr_print_insn; 109 } 110 111 static void avr_cpu_realizefn(DeviceState *dev, Error **errp) 112 { 113 CPUState *cs = CPU(dev); 114 CPUAVRState *env = cpu_env(cs); 115 AVRCPU *cpu = env_archcpu(env); 116 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); 117 Error *local_err = NULL; 118 119 cpu_exec_realizefn(cs, &local_err); 120 if (local_err != NULL) { 121 error_propagate(errp, local_err); 122 return; 123 } 124 qemu_init_vcpu(cs); 125 cpu_reset(cs); 126 127 mcc->parent_realize(dev, errp); 128 129 /* 130 * Two blocks in the low data space loop back into cpu registers. 131 */ 132 memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env, 133 "avr-cpu-reg1", 32); 134 memory_region_add_subregion(get_system_memory(), 135 OFFSET_DATA, &cpu->cpu_reg1); 136 137 memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env, 138 "avr-cpu-reg2", 8); 139 memory_region_add_subregion(get_system_memory(), 140 OFFSET_DATA + 0x58, &cpu->cpu_reg2); 141 } 142 143 static void avr_cpu_set_int(void *opaque, int irq, int level) 144 { 145 AVRCPU *cpu = opaque; 146 CPUAVRState *env = &cpu->env; 147 CPUState *cs = CPU(cpu); 148 uint64_t mask = (1ull << irq); 149 150 if (level) { 151 env->intsrc |= mask; 152 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 153 } else { 154 env->intsrc &= ~mask; 155 if (env->intsrc == 0) { 156 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 157 } 158 } 159 } 160 161 static void avr_cpu_initfn(Object *obj) 162 { 163 AVRCPU *cpu = AVR_CPU(obj); 164 165 /* Set the number of interrupts supported by the CPU. */ 166 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 167 sizeof(cpu->env.intsrc) * 8); 168 } 169 170 static const Property avr_cpu_properties[] = { 171 DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0), 172 }; 173 174 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) 175 { 176 return object_class_by_name(cpu_model); 177 } 178 179 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) 180 { 181 CPUAVRState *env = cpu_env(cs); 182 int i; 183 184 qemu_fprintf(f, "\n"); 185 qemu_fprintf(f, "PC: %06x\n", env->pc_w * 2); /* PC points to words */ 186 qemu_fprintf(f, "SP: %04x\n", env->sp); 187 qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16); 188 qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16); 189 qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16); 190 qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16); 191 qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16); 192 qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]); 193 qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]); 194 qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]); 195 qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n", 196 env->sregI ? 'I' : '-', 197 env->sregT ? 'T' : '-', 198 env->sregH ? 'H' : '-', 199 env->sregS ? 'S' : '-', 200 env->sregV ? 'V' : '-', 201 env->sregN ? '-' : 'N', /* Zf has negative logic */ 202 env->sregZ ? 'Z' : '-', 203 env->sregC ? 'I' : '-'); 204 qemu_fprintf(f, "SKIP: %02x\n", env->skip); 205 206 qemu_fprintf(f, "\n"); 207 for (i = 0; i < ARRAY_SIZE(env->r); i++) { 208 qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]); 209 210 if ((i % 8) == 7) { 211 qemu_fprintf(f, "\n"); 212 } 213 } 214 qemu_fprintf(f, "\n"); 215 } 216 217 #include "hw/core/sysemu-cpu-ops.h" 218 219 static const struct SysemuCPUOps avr_sysemu_ops = { 220 .has_work = avr_cpu_has_work, 221 .get_phys_page_debug = avr_cpu_get_phys_page_debug, 222 }; 223 224 #include "accel/tcg/cpu-ops.h" 225 226 static const TCGCPUOps avr_tcg_ops = { 227 .initialize = avr_cpu_tcg_init, 228 .translate_code = avr_cpu_translate_code, 229 .synchronize_from_tb = avr_cpu_synchronize_from_tb, 230 .restore_state_to_opc = avr_restore_state_to_opc, 231 .cpu_exec_interrupt = avr_cpu_exec_interrupt, 232 .cpu_exec_halt = avr_cpu_has_work, 233 .tlb_fill = avr_cpu_tlb_fill, 234 .do_interrupt = avr_cpu_do_interrupt, 235 }; 236 237 static void avr_cpu_class_init(ObjectClass *oc, void *data) 238 { 239 DeviceClass *dc = DEVICE_CLASS(oc); 240 CPUClass *cc = CPU_CLASS(oc); 241 AVRCPUClass *mcc = AVR_CPU_CLASS(oc); 242 ResettableClass *rc = RESETTABLE_CLASS(oc); 243 244 device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize); 245 246 device_class_set_props(dc, avr_cpu_properties); 247 248 resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL, 249 &mcc->parent_phases); 250 251 cc->class_by_name = avr_cpu_class_by_name; 252 253 cc->mmu_index = avr_cpu_mmu_index; 254 cc->dump_state = avr_cpu_dump_state; 255 cc->set_pc = avr_cpu_set_pc; 256 cc->get_pc = avr_cpu_get_pc; 257 dc->vmsd = &vms_avr_cpu; 258 cc->sysemu_ops = &avr_sysemu_ops; 259 cc->disas_set_info = avr_cpu_disas_set_info; 260 cc->gdb_read_register = avr_cpu_gdb_read_register; 261 cc->gdb_write_register = avr_cpu_gdb_write_register; 262 cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint; 263 cc->gdb_core_xml_file = "avr-cpu.xml"; 264 cc->tcg_ops = &avr_tcg_ops; 265 } 266 267 /* 268 * Setting features of AVR core type avr5 269 * -------------------------------------- 270 * 271 * This type of AVR core is present in the following AVR MCUs: 272 * 273 * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c, 274 * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162, 275 * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, 276 * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, 277 * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb, 278 * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323, 279 * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, 280 * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, 281 * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa, 282 * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1, 283 * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644, 284 * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, 285 * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, 286 * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p, 287 * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2, 288 * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216, 289 * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000 290 */ 291 static void avr_avr5_initfn(Object *obj) 292 { 293 CPUAVRState *env = cpu_env(CPU(obj)); 294 295 set_avr_feature(env, AVR_FEATURE_LPM); 296 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 297 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 298 set_avr_feature(env, AVR_FEATURE_SRAM); 299 set_avr_feature(env, AVR_FEATURE_BREAK); 300 301 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 302 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 303 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 304 set_avr_feature(env, AVR_FEATURE_LPMX); 305 set_avr_feature(env, AVR_FEATURE_MOVW); 306 set_avr_feature(env, AVR_FEATURE_MUL); 307 } 308 309 /* 310 * Setting features of AVR core type avr51 311 * -------------------------------------- 312 * 313 * This type of AVR core is present in the following AVR MCUs: 314 * 315 * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p, 316 * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 317 * at90usb1287 318 */ 319 static void avr_avr51_initfn(Object *obj) 320 { 321 CPUAVRState *env = cpu_env(CPU(obj)); 322 323 set_avr_feature(env, AVR_FEATURE_LPM); 324 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 325 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 326 set_avr_feature(env, AVR_FEATURE_SRAM); 327 set_avr_feature(env, AVR_FEATURE_BREAK); 328 329 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 330 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 331 set_avr_feature(env, AVR_FEATURE_RAMPZ); 332 set_avr_feature(env, AVR_FEATURE_ELPMX); 333 set_avr_feature(env, AVR_FEATURE_ELPM); 334 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 335 set_avr_feature(env, AVR_FEATURE_LPMX); 336 set_avr_feature(env, AVR_FEATURE_MOVW); 337 set_avr_feature(env, AVR_FEATURE_MUL); 338 } 339 340 /* 341 * Setting features of AVR core type avr6 342 * -------------------------------------- 343 * 344 * This type of AVR core is present in the following AVR MCUs: 345 * 346 * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2 347 */ 348 static void avr_avr6_initfn(Object *obj) 349 { 350 CPUAVRState *env = cpu_env(CPU(obj)); 351 352 set_avr_feature(env, AVR_FEATURE_LPM); 353 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 354 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 355 set_avr_feature(env, AVR_FEATURE_SRAM); 356 set_avr_feature(env, AVR_FEATURE_BREAK); 357 358 set_avr_feature(env, AVR_FEATURE_3_BYTE_PC); 359 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 360 set_avr_feature(env, AVR_FEATURE_RAMPZ); 361 set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL); 362 set_avr_feature(env, AVR_FEATURE_ELPMX); 363 set_avr_feature(env, AVR_FEATURE_ELPM); 364 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 365 set_avr_feature(env, AVR_FEATURE_LPMX); 366 set_avr_feature(env, AVR_FEATURE_MOVW); 367 set_avr_feature(env, AVR_FEATURE_MUL); 368 } 369 370 typedef struct AVRCPUInfo { 371 const char *name; 372 void (*initfn)(Object *obj); 373 } AVRCPUInfo; 374 375 376 #define DEFINE_AVR_CPU_TYPE(model, initfn) \ 377 { \ 378 .parent = TYPE_AVR_CPU, \ 379 .instance_init = initfn, \ 380 .name = AVR_CPU_TYPE_NAME(model), \ 381 } 382 383 static const TypeInfo avr_cpu_type_info[] = { 384 { 385 .name = TYPE_AVR_CPU, 386 .parent = TYPE_CPU, 387 .instance_size = sizeof(AVRCPU), 388 .instance_align = __alignof(AVRCPU), 389 .instance_init = avr_cpu_initfn, 390 .class_size = sizeof(AVRCPUClass), 391 .class_init = avr_cpu_class_init, 392 .abstract = true, 393 }, 394 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), 395 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), 396 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), 397 }; 398 399 DEFINE_TYPES(avr_cpu_type_info) 400