178e138bcSPeter Maydell# AArch32 VFP instruction descriptions (conditional insns) 278e138bcSPeter Maydell# 378e138bcSPeter Maydell# Copyright (c) 2019 Linaro, Ltd 478e138bcSPeter Maydell# 578e138bcSPeter Maydell# This library is free software; you can redistribute it and/or 678e138bcSPeter Maydell# modify it under the terms of the GNU Lesser General Public 778e138bcSPeter Maydell# License as published by the Free Software Foundation; either 878e138bcSPeter Maydell# version 2 of the License, or (at your option) any later version. 978e138bcSPeter Maydell# 1078e138bcSPeter Maydell# This library is distributed in the hope that it will be useful, 1178e138bcSPeter Maydell# but WITHOUT ANY WARRANTY; without even the implied warranty of 1278e138bcSPeter Maydell# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1378e138bcSPeter Maydell# Lesser General Public License for more details. 1478e138bcSPeter Maydell# 1578e138bcSPeter Maydell# You should have received a copy of the GNU Lesser General Public 1678e138bcSPeter Maydell# License along with this library; if not, see <http://www.gnu.org/licenses/>. 1778e138bcSPeter Maydell 1878e138bcSPeter Maydell# 1978e138bcSPeter Maydell# This file is processed by scripts/decodetree.py 2078e138bcSPeter Maydell# 2178e138bcSPeter Maydell# Encodings for the conditional VFP instructions are here: 2278e138bcSPeter Maydell# generally anything matching A32 2378e138bcSPeter Maydell# cccc 11.. .... .... .... 101. .... .... 2478e138bcSPeter Maydell# and T32 2578e138bcSPeter Maydell# 1110 110. .... .... .... 101. .... .... 2678e138bcSPeter Maydell# 1110 1110 .... .... .... 101. .... .... 2778e138bcSPeter Maydell# (but those patterns might also cover some Neon instructions, 2878e138bcSPeter Maydell# which do not live in this file.) 299851ed92SPeter Maydell 309851ed92SPeter Maydell# VFP registers have an odd encoding with a four-bit field 319851ed92SPeter Maydell# and a one-bit field which are assembled in different orders 329851ed92SPeter Maydell# depending on whether the register is double or single precision. 339851ed92SPeter Maydell# Each individual instruction function must do the checks for 349851ed92SPeter Maydell# "double register selected but CPU does not have double support" 359851ed92SPeter Maydell# and "double register number has bit 4 set but CPU does not 369851ed92SPeter Maydell# support D16-D31" (which should UNDEF). 379851ed92SPeter Maydell%vm_dp 5:1 0:4 389851ed92SPeter Maydell%vm_sp 0:4 5:1 399851ed92SPeter Maydell%vn_dp 7:1 16:4 409851ed92SPeter Maydell%vn_sp 16:4 7:1 419851ed92SPeter Maydell%vd_dp 22:1 12:4 429851ed92SPeter Maydell%vd_sp 12:4 22:1 439851ed92SPeter Maydell 449851ed92SPeter Maydell%vmov_idx_b 21:1 5:2 459851ed92SPeter Maydell%vmov_idx_h 21:1 6:1 469851ed92SPeter Maydell 479bee50b4SPeter Maydell%vmov_imm 16:4 0:4 489bee50b4SPeter Maydell 49906b60faSRichard Henderson@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp 50906b60faSRichard Henderson@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp 51906b60faSRichard Henderson 52906b60faSRichard Henderson@vfp_dm_ss ................................ vm=%vm_sp vd=%vd_sp 53906b60faSRichard Henderson@vfp_dm_dd ................................ vm=%vm_dp vd=%vd_dp 54906b60faSRichard Henderson@vfp_dm_ds ................................ vm=%vm_sp vd=%vd_dp 55906b60faSRichard Henderson@vfp_dm_sd ................................ vm=%vm_dp vd=%vd_sp 56906b60faSRichard Henderson 579851ed92SPeter Maydell# VMOV scalar to general-purpose register; note that this does 589851ed92SPeter Maydell# include some Neon cases. 599851ed92SPeter MaydellVMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \ 609851ed92SPeter Maydell vn=%vn_dp size=0 index=%vmov_idx_b 619851ed92SPeter MaydellVMOV_to_gp ---- 1110 u:1 0. 1 .... rt:4 1011 ..1 1 0000 \ 629851ed92SPeter Maydell vn=%vn_dp size=1 index=%vmov_idx_h 639851ed92SPeter MaydellVMOV_to_gp ---- 1110 0 0 index:1 1 .... rt:4 1011 .00 1 0000 \ 649851ed92SPeter Maydell vn=%vn_dp size=2 u=0 659851ed92SPeter Maydell 669851ed92SPeter MaydellVMOV_from_gp ---- 1110 0 1. 0 .... rt:4 1011 ... 1 0000 \ 679851ed92SPeter Maydell vn=%vn_dp size=0 index=%vmov_idx_b 689851ed92SPeter MaydellVMOV_from_gp ---- 1110 0 0. 0 .... rt:4 1011 ..1 1 0000 \ 699851ed92SPeter Maydell vn=%vn_dp size=1 index=%vmov_idx_h 709851ed92SPeter MaydellVMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \ 719851ed92SPeter Maydell vn=%vn_dp size=2 729851ed92SPeter Maydell 739851ed92SPeter MaydellVDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \ 749851ed92SPeter Maydell vn=%vn_dp 75a9ab5001SPeter Maydell 76a9ab5001SPeter MaydellVMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 77906b60faSRichard HendersonVMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp 7881f68110SPeter Maydell 79906b60faSRichard HendersonVMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp 80906b60faSRichard HendersonVMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp 8179b02a3bSPeter Maydell 82274afbb1SPeter MaydellVLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp 83906b60faSRichard HendersonVLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp 84906b60faSRichard HendersonVLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp 85fa288de2SPeter Maydell 86fa288de2SPeter Maydell# We split the load/store multiple up into two patterns to avoid 87fa288de2SPeter Maydell# overlap with other insns in the "Advanced SIMD load/store and 64-bit move" 88fa288de2SPeter Maydell# grouping: 89fa288de2SPeter Maydell# P=0 U=0 W=0 is 64-bit VMOV 90fa288de2SPeter Maydell# P=1 W=0 is VLDR/VSTR 91fa288de2SPeter Maydell# P=U W=1 is UNDEF 92fa288de2SPeter Maydell# leaving P=0 U=1 W=x and P=1 U=0 W=1 for load/store multiple. 93fa288de2SPeter Maydell# These include FSTM/FLDM. 94fa288de2SPeter MaydellVLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \ 95fa288de2SPeter Maydell vd=%vd_sp p=0 u=1 96fa288de2SPeter MaydellVLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \ 97fa288de2SPeter Maydell vd=%vd_dp p=0 u=1 98fa288de2SPeter Maydell 99fa288de2SPeter MaydellVLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \ 100fa288de2SPeter Maydell vd=%vd_sp p=1 u=0 w=1 101fa288de2SPeter MaydellVLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \ 102fa288de2SPeter Maydell vd=%vd_dp p=1 u=0 w=1 103266bd25cSPeter Maydell 104266bd25cSPeter Maydell# 3-register VFP data-processing; bits [23,21:20,6] identify the operation. 105e7cb0dedSPeter MaydellVMLA_hp ---- 1110 0.00 .... .... 1001 .0.0 .... @vfp_dnm_s 106906b60faSRichard HendersonVMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s 107906b60faSRichard HendersonVMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d 108e7258280SPeter Maydell 109e7cb0dedSPeter MaydellVMLS_hp ---- 1110 0.00 .... .... 1001 .1.0 .... @vfp_dnm_s 110906b60faSRichard HendersonVMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s 111906b60faSRichard HendersonVMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d 112c54a416cSPeter Maydell 113e7cb0dedSPeter MaydellVNMLS_hp ---- 1110 0.01 .... .... 1001 .0.0 .... @vfp_dnm_s 114906b60faSRichard HendersonVNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s 115906b60faSRichard HendersonVNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d 1168a483533SPeter Maydell 117e7cb0dedSPeter MaydellVNMLA_hp ---- 1110 0.01 .... .... 1001 .1.0 .... @vfp_dnm_s 118906b60faSRichard HendersonVNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s 119906b60faSRichard HendersonVNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d 12088c5188cSPeter Maydell 121120a0eb3SPeter MaydellVMUL_hp ---- 1110 0.10 .... .... 1001 .0.0 .... @vfp_dnm_s 122906b60faSRichard HendersonVMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s 123906b60faSRichard HendersonVMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d 12443c4be12SPeter Maydell 125e7cb0dedSPeter MaydellVNMUL_hp ---- 1110 0.10 .... .... 1001 .1.0 .... @vfp_dnm_s 126906b60faSRichard HendersonVNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s 127906b60faSRichard HendersonVNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d 128ce28b303SPeter Maydell 129120a0eb3SPeter MaydellVADD_hp ---- 1110 0.11 .... .... 1001 .0.0 .... @vfp_dnm_s 130906b60faSRichard HendersonVADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s 131906b60faSRichard HendersonVADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d 1328fec9a11SPeter Maydell 133120a0eb3SPeter MaydellVSUB_hp ---- 1110 0.11 .... .... 1001 .1.0 .... @vfp_dnm_s 134906b60faSRichard HendersonVSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s 135906b60faSRichard HendersonVSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d 136519ee7aeSPeter Maydell 137120a0eb3SPeter MaydellVDIV_hp ---- 1110 1.00 .... .... 1001 .0.0 .... @vfp_dnm_s 138906b60faSRichard HendersonVDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s 139906b60faSRichard HendersonVDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d 140d4893b01SPeter Maydell 1419886fe28SPeter MaydellVFMA_hp ---- 1110 1.10 .... .... 1001 .0. 0 .... @vfp_dnm_s 1429886fe28SPeter MaydellVFMS_hp ---- 1110 1.10 .... .... 1001 .1. 0 .... @vfp_dnm_s 1439886fe28SPeter MaydellVFNMA_hp ---- 1110 1.01 .... .... 1001 .0. 0 .... @vfp_dnm_s 1449886fe28SPeter MaydellVFNMS_hp ---- 1110 1.01 .... .... 1001 .1. 0 .... @vfp_dnm_s 1459886fe28SPeter Maydell 146d486f830SRichard HendersonVFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s 147d486f830SRichard HendersonVFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s 148d486f830SRichard HendersonVFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s 149d486f830SRichard HendersonVFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s 150d486f830SRichard Henderson 151d486f830SRichard HendersonVFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d 152d486f830SRichard HendersonVFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d 153d486f830SRichard HendersonVFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d 154d486f830SRichard HendersonVFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d 155b518c753SPeter Maydell 15628c28728SPeter MaydellVMOV_imm_hp ---- 1110 1.11 .... .... 1001 0000 .... \ 15728c28728SPeter Maydell vd=%vd_sp imm=%vmov_imm 1589bee50b4SPeter MaydellVMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ 1599bee50b4SPeter Maydell vd=%vd_sp imm=%vmov_imm 1609bee50b4SPeter MaydellVMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \ 1619bee50b4SPeter Maydell vd=%vd_dp imm=%vmov_imm 16290287e22SPeter Maydell 163906b60faSRichard HendersonVMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss 164906b60faSRichard HendersonVMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd 16517552b97SPeter Maydell 166ce2d65a5SPeter MaydellVABS_hp ---- 1110 1.11 0000 .... 1001 11.0 .... @vfp_dm_ss 167906b60faSRichard HendersonVABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss 168906b60faSRichard HendersonVABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd 1691882651aSPeter Maydell 170ce2d65a5SPeter MaydellVNEG_hp ---- 1110 1.11 0001 .... 1001 01.0 .... @vfp_dm_ss 171906b60faSRichard HendersonVNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss 172906b60faSRichard HendersonVNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd 173b8474540SPeter Maydell 174ce2d65a5SPeter MaydellVSQRT_hp ---- 1110 1.11 0001 .... 1001 11.0 .... @vfp_dm_ss 175906b60faSRichard HendersonVSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss 176906b60faSRichard HendersonVSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd 177386bba23SPeter Maydell 1781b88b054SPeter MaydellVCMP_hp ---- 1110 1.11 010 z:1 .... 1001 e:1 1.0 .... \ 1791b88b054SPeter Maydell vd=%vd_sp vm=%vm_sp 180386bba23SPeter MaydellVCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \ 181386bba23SPeter Maydell vd=%vd_sp vm=%vm_sp 182386bba23SPeter MaydellVCMP_dp ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \ 183386bba23SPeter Maydell vd=%vd_dp vm=%vm_dp 184b623d803SPeter Maydell 185b623d803SPeter Maydell# VCVTT and VCVTB from f16: Vd format depends on size bit; Vm is always vm_sp 186b623d803SPeter MaydellVCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \ 187b623d803SPeter Maydell vd=%vd_sp vm=%vm_sp 188b623d803SPeter MaydellVCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \ 189b623d803SPeter Maydell vd=%vd_dp vm=%vm_sp 190cdfd14e8SPeter Maydell 191906b60faSRichard Henderson# VCVTB and VCVTT to f16: Vd format is always vd_sp; 192906b60faSRichard Henderson# Vm format depends on size bit 193cdfd14e8SPeter MaydellVCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \ 194cdfd14e8SPeter Maydell vd=%vd_sp vm=%vm_sp 195cdfd14e8SPeter MaydellVCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ 196cdfd14e8SPeter Maydell vd=%vd_sp vm=%vm_dp 197e25155f5SPeter Maydell 198906b60faSRichard HendersonVRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss 199906b60faSRichard HendersonVRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd 200e25155f5SPeter Maydell 201906b60faSRichard HendersonVRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss 202906b60faSRichard HendersonVRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd 203e25155f5SPeter Maydell 204906b60faSRichard HendersonVRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss 205906b60faSRichard HendersonVRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd 2066ed7e49cSPeter Maydell 207906b60faSRichard Henderson# VCVT between single and double: 208906b60faSRichard Henderson# Vm precision depends on size; Vd is its reverse 209906b60faSRichard HendersonVCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds 210906b60faSRichard HendersonVCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd 2118fc9d891SPeter Maydell 2128fc9d891SPeter Maydell# VCVT from integer to floating point: Vm always single; Vd depends on size 213*0094e9f4SPeter MaydellVCVT_int_hp ---- 1110 1.11 1000 .... 1001 s:1 1.0 .... \ 214*0094e9f4SPeter Maydell vd=%vd_sp vm=%vm_sp 2158fc9d891SPeter MaydellVCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ 2168fc9d891SPeter Maydell vd=%vd_sp vm=%vm_sp 2178fc9d891SPeter MaydellVCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \ 2188fc9d891SPeter Maydell vd=%vd_dp vm=%vm_sp 21992073e94SPeter Maydell 22092073e94SPeter Maydell# VJCVT is always dp to sp 221906b60faSRichard HendersonVJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd 222e3d6f429SPeter Maydell 223e3d6f429SPeter Maydell# VCVT between floating-point and fixed-point. The immediate value 224e3d6f429SPeter Maydell# is in the same format as a Vm single-precision register number. 225e3d6f429SPeter Maydell# We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field 226e3d6f429SPeter Maydell# for the convenience of the trans_VCVT_fix functions. 227e3d6f429SPeter Maydell%vcvt_fix_op 18:1 16:1 7:1 228e3d6f429SPeter MaydellVCVT_fix_sp ---- 1110 1.11 1.1. .... 1010 .1.0 .... \ 229e3d6f429SPeter Maydell vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op 230e3d6f429SPeter MaydellVCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \ 231e3d6f429SPeter Maydell vd=%vd_dp imm=%vm_sp opc=%vcvt_fix_op 2323111bfc2SPeter Maydell 2333111bfc2SPeter Maydell# VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on size 234*0094e9f4SPeter MaydellVCVT_hp_int ---- 1110 1.11 110 s:1 .... 1001 rz:1 1.0 .... \ 235*0094e9f4SPeter Maydell vd=%vd_sp vm=%vm_sp 2363111bfc2SPeter MaydellVCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ 2373111bfc2SPeter Maydell vd=%vd_sp vm=%vm_sp 2383111bfc2SPeter MaydellVCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ 2393111bfc2SPeter Maydell vd=%vd_sp vm=%vm_dp 240