178e138bcSPeter Maydell# AArch32 VFP instruction descriptions (unconditional insns) 278e138bcSPeter Maydell# 378e138bcSPeter Maydell# Copyright (c) 2019 Linaro, Ltd 478e138bcSPeter Maydell# 578e138bcSPeter Maydell# This library is free software; you can redistribute it and/or 678e138bcSPeter Maydell# modify it under the terms of the GNU Lesser General Public 778e138bcSPeter Maydell# License as published by the Free Software Foundation; either 878e138bcSPeter Maydell# version 2 of the License, or (at your option) any later version. 978e138bcSPeter Maydell# 1078e138bcSPeter Maydell# This library is distributed in the hope that it will be useful, 1178e138bcSPeter Maydell# but WITHOUT ANY WARRANTY; without even the implied warranty of 1278e138bcSPeter Maydell# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1378e138bcSPeter Maydell# Lesser General Public License for more details. 1478e138bcSPeter Maydell# 1578e138bcSPeter Maydell# You should have received a copy of the GNU Lesser General Public 1678e138bcSPeter Maydell# License along with this library; if not, see <http://www.gnu.org/licenses/>. 1778e138bcSPeter Maydell 1878e138bcSPeter Maydell# 1978e138bcSPeter Maydell# This file is processed by scripts/decodetree.py 2078e138bcSPeter Maydell# 2178e138bcSPeter Maydell# Encodings for the unconditional VFP instructions are here: 2278e138bcSPeter Maydell# generally anything matching A32 2378e138bcSPeter Maydell# 1111 1110 .... .... .... 101. ...0 .... 2478e138bcSPeter Maydell# and T32 2578e138bcSPeter Maydell# 1111 110. .... .... .... 101. .... .... 2678e138bcSPeter Maydell# 1111 1110 .... .... .... 101. .... .... 2778e138bcSPeter Maydell# (but those patterns might also cover some Neon instructions, 2878e138bcSPeter Maydell# which do not live in this file.) 29b3ff4b87SPeter Maydell 30b3ff4b87SPeter Maydell# VFP registers have an odd encoding with a four-bit field 31b3ff4b87SPeter Maydell# and a one-bit field which are assembled in different orders 32b3ff4b87SPeter Maydell# depending on whether the register is double or single precision. 33b3ff4b87SPeter Maydell# Each individual instruction function must do the checks for 34b3ff4b87SPeter Maydell# "double register selected but CPU does not have double support" 35b3ff4b87SPeter Maydell# and "double register number has bit 4 set but CPU does not 36b3ff4b87SPeter Maydell# support D16-D31" (which should UNDEF). 37b3ff4b87SPeter Maydell%vm_dp 5:1 0:4 38b3ff4b87SPeter Maydell%vm_sp 0:4 5:1 39b3ff4b87SPeter Maydell%vn_dp 7:1 16:4 40b3ff4b87SPeter Maydell%vn_sp 16:4 7:1 41b3ff4b87SPeter Maydell%vd_dp 22:1 12:4 42b3ff4b87SPeter Maydell%vd_sp 12:4 22:1 43b3ff4b87SPeter Maydell 44b3ff4b87SPeter MaydellVSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \ 45b3ff4b87SPeter Maydell vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0 46b3ff4b87SPeter MaydellVSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ 47b3ff4b87SPeter Maydell vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1 48*f65988a1SPeter Maydell 49*f65988a1SPeter MaydellVMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \ 50*f65988a1SPeter Maydell vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0 51*f65988a1SPeter MaydellVMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \ 52*f65988a1SPeter Maydell vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1 53