1 /* 2 * ARM AdvSIMD / SVE Vector Operations 3 * 4 * Copyright (c) 2018 Linaro 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "tcg/tcg-gvec-desc.h" 24 #include "fpu/softfloat.h" 25 #include "vec_internal.h" 26 27 /* Note that vector data is stored in host-endian 64-bit chunks, 28 so addressing units smaller than that needs a host-endian fixup. */ 29 #ifdef HOST_WORDS_BIGENDIAN 30 #define H1(x) ((x) ^ 7) 31 #define H2(x) ((x) ^ 3) 32 #define H4(x) ((x) ^ 1) 33 #else 34 #define H1(x) (x) 35 #define H2(x) (x) 36 #define H4(x) (x) 37 #endif 38 39 /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ 40 static int16_t do_sqrdmlah_h(int16_t src1, int16_t src2, int16_t src3, 41 bool neg, bool round, uint32_t *sat) 42 { 43 /* 44 * Simplify: 45 * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16 46 * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15 47 */ 48 int32_t ret = (int32_t)src1 * src2; 49 if (neg) { 50 ret = -ret; 51 } 52 ret += ((int32_t)src3 << 15) + (round << 14); 53 ret >>= 15; 54 55 if (ret != (int16_t)ret) { 56 *sat = 1; 57 ret = (ret < 0 ? INT16_MIN : INT16_MAX); 58 } 59 return ret; 60 } 61 62 uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, 63 uint32_t src2, uint32_t src3) 64 { 65 uint32_t *sat = &env->vfp.qc[0]; 66 uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, false, true, sat); 67 uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16, 68 false, true, sat); 69 return deposit32(e1, 16, 16, e2); 70 } 71 72 void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, 73 void *vq, uint32_t desc) 74 { 75 uintptr_t opr_sz = simd_oprsz(desc); 76 int16_t *d = vd; 77 int16_t *n = vn; 78 int16_t *m = vm; 79 uintptr_t i; 80 81 for (i = 0; i < opr_sz / 2; ++i) { 82 d[i] = do_sqrdmlah_h(n[i], m[i], d[i], false, true, vq); 83 } 84 clear_tail(d, opr_sz, simd_maxsz(desc)); 85 } 86 87 uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, 88 uint32_t src2, uint32_t src3) 89 { 90 uint32_t *sat = &env->vfp.qc[0]; 91 uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, true, true, sat); 92 uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16, 93 true, true, sat); 94 return deposit32(e1, 16, 16, e2); 95 } 96 97 void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm, 98 void *vq, uint32_t desc) 99 { 100 uintptr_t opr_sz = simd_oprsz(desc); 101 int16_t *d = vd; 102 int16_t *n = vn; 103 int16_t *m = vm; 104 uintptr_t i; 105 106 for (i = 0; i < opr_sz / 2; ++i) { 107 d[i] = do_sqrdmlah_h(n[i], m[i], d[i], true, true, vq); 108 } 109 clear_tail(d, opr_sz, simd_maxsz(desc)); 110 } 111 112 void HELPER(neon_sqdmulh_h)(void *vd, void *vn, void *vm, 113 void *vq, uint32_t desc) 114 { 115 intptr_t i, opr_sz = simd_oprsz(desc); 116 int16_t *d = vd, *n = vn, *m = vm; 117 118 for (i = 0; i < opr_sz / 2; ++i) { 119 d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, false, vq); 120 } 121 clear_tail(d, opr_sz, simd_maxsz(desc)); 122 } 123 124 void HELPER(neon_sqrdmulh_h)(void *vd, void *vn, void *vm, 125 void *vq, uint32_t desc) 126 { 127 intptr_t i, opr_sz = simd_oprsz(desc); 128 int16_t *d = vd, *n = vn, *m = vm; 129 130 for (i = 0; i < opr_sz / 2; ++i) { 131 d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, true, vq); 132 } 133 clear_tail(d, opr_sz, simd_maxsz(desc)); 134 } 135 136 /* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ 137 static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3, 138 bool neg, bool round, uint32_t *sat) 139 { 140 /* Simplify similarly to int_qrdmlah_s16 above. */ 141 int64_t ret = (int64_t)src1 * src2; 142 if (neg) { 143 ret = -ret; 144 } 145 ret += ((int64_t)src3 << 31) + (round << 30); 146 ret >>= 31; 147 148 if (ret != (int32_t)ret) { 149 *sat = 1; 150 ret = (ret < 0 ? INT32_MIN : INT32_MAX); 151 } 152 return ret; 153 } 154 155 uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, 156 int32_t src2, int32_t src3) 157 { 158 uint32_t *sat = &env->vfp.qc[0]; 159 return do_sqrdmlah_s(src1, src2, src3, false, true, sat); 160 } 161 162 void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm, 163 void *vq, uint32_t desc) 164 { 165 uintptr_t opr_sz = simd_oprsz(desc); 166 int32_t *d = vd; 167 int32_t *n = vn; 168 int32_t *m = vm; 169 uintptr_t i; 170 171 for (i = 0; i < opr_sz / 4; ++i) { 172 d[i] = do_sqrdmlah_s(n[i], m[i], d[i], false, true, vq); 173 } 174 clear_tail(d, opr_sz, simd_maxsz(desc)); 175 } 176 177 uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, 178 int32_t src2, int32_t src3) 179 { 180 uint32_t *sat = &env->vfp.qc[0]; 181 return do_sqrdmlah_s(src1, src2, src3, true, true, sat); 182 } 183 184 void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, 185 void *vq, uint32_t desc) 186 { 187 uintptr_t opr_sz = simd_oprsz(desc); 188 int32_t *d = vd; 189 int32_t *n = vn; 190 int32_t *m = vm; 191 uintptr_t i; 192 193 for (i = 0; i < opr_sz / 4; ++i) { 194 d[i] = do_sqrdmlah_s(n[i], m[i], d[i], true, true, vq); 195 } 196 clear_tail(d, opr_sz, simd_maxsz(desc)); 197 } 198 199 void HELPER(neon_sqdmulh_s)(void *vd, void *vn, void *vm, 200 void *vq, uint32_t desc) 201 { 202 intptr_t i, opr_sz = simd_oprsz(desc); 203 int32_t *d = vd, *n = vn, *m = vm; 204 205 for (i = 0; i < opr_sz / 4; ++i) { 206 d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, false, vq); 207 } 208 clear_tail(d, opr_sz, simd_maxsz(desc)); 209 } 210 211 void HELPER(neon_sqrdmulh_s)(void *vd, void *vn, void *vm, 212 void *vq, uint32_t desc) 213 { 214 intptr_t i, opr_sz = simd_oprsz(desc); 215 int32_t *d = vd, *n = vn, *m = vm; 216 217 for (i = 0; i < opr_sz / 4; ++i) { 218 d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, true, vq); 219 } 220 clear_tail(d, opr_sz, simd_maxsz(desc)); 221 } 222 223 /* Integer 8 and 16-bit dot-product. 224 * 225 * Note that for the loops herein, host endianness does not matter 226 * with respect to the ordering of data within the 64-bit lanes. 227 * All elements are treated equally, no matter where they are. 228 */ 229 230 void HELPER(gvec_sdot_b)(void *vd, void *vn, void *vm, uint32_t desc) 231 { 232 intptr_t i, opr_sz = simd_oprsz(desc); 233 uint32_t *d = vd; 234 int8_t *n = vn, *m = vm; 235 236 for (i = 0; i < opr_sz / 4; ++i) { 237 d[i] += n[i * 4 + 0] * m[i * 4 + 0] 238 + n[i * 4 + 1] * m[i * 4 + 1] 239 + n[i * 4 + 2] * m[i * 4 + 2] 240 + n[i * 4 + 3] * m[i * 4 + 3]; 241 } 242 clear_tail(d, opr_sz, simd_maxsz(desc)); 243 } 244 245 void HELPER(gvec_udot_b)(void *vd, void *vn, void *vm, uint32_t desc) 246 { 247 intptr_t i, opr_sz = simd_oprsz(desc); 248 uint32_t *d = vd; 249 uint8_t *n = vn, *m = vm; 250 251 for (i = 0; i < opr_sz / 4; ++i) { 252 d[i] += n[i * 4 + 0] * m[i * 4 + 0] 253 + n[i * 4 + 1] * m[i * 4 + 1] 254 + n[i * 4 + 2] * m[i * 4 + 2] 255 + n[i * 4 + 3] * m[i * 4 + 3]; 256 } 257 clear_tail(d, opr_sz, simd_maxsz(desc)); 258 } 259 260 void HELPER(gvec_sdot_h)(void *vd, void *vn, void *vm, uint32_t desc) 261 { 262 intptr_t i, opr_sz = simd_oprsz(desc); 263 uint64_t *d = vd; 264 int16_t *n = vn, *m = vm; 265 266 for (i = 0; i < opr_sz / 8; ++i) { 267 d[i] += (int64_t)n[i * 4 + 0] * m[i * 4 + 0] 268 + (int64_t)n[i * 4 + 1] * m[i * 4 + 1] 269 + (int64_t)n[i * 4 + 2] * m[i * 4 + 2] 270 + (int64_t)n[i * 4 + 3] * m[i * 4 + 3]; 271 } 272 clear_tail(d, opr_sz, simd_maxsz(desc)); 273 } 274 275 void HELPER(gvec_udot_h)(void *vd, void *vn, void *vm, uint32_t desc) 276 { 277 intptr_t i, opr_sz = simd_oprsz(desc); 278 uint64_t *d = vd; 279 uint16_t *n = vn, *m = vm; 280 281 for (i = 0; i < opr_sz / 8; ++i) { 282 d[i] += (uint64_t)n[i * 4 + 0] * m[i * 4 + 0] 283 + (uint64_t)n[i * 4 + 1] * m[i * 4 + 1] 284 + (uint64_t)n[i * 4 + 2] * m[i * 4 + 2] 285 + (uint64_t)n[i * 4 + 3] * m[i * 4 + 3]; 286 } 287 clear_tail(d, opr_sz, simd_maxsz(desc)); 288 } 289 290 void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) 291 { 292 intptr_t i, segend, opr_sz = simd_oprsz(desc), opr_sz_4 = opr_sz / 4; 293 intptr_t index = simd_data(desc); 294 uint32_t *d = vd; 295 int8_t *n = vn; 296 int8_t *m_indexed = (int8_t *)vm + index * 4; 297 298 /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. 299 * Otherwise opr_sz is a multiple of 16. 300 */ 301 segend = MIN(4, opr_sz_4); 302 i = 0; 303 do { 304 int8_t m0 = m_indexed[i * 4 + 0]; 305 int8_t m1 = m_indexed[i * 4 + 1]; 306 int8_t m2 = m_indexed[i * 4 + 2]; 307 int8_t m3 = m_indexed[i * 4 + 3]; 308 309 do { 310 d[i] += n[i * 4 + 0] * m0 311 + n[i * 4 + 1] * m1 312 + n[i * 4 + 2] * m2 313 + n[i * 4 + 3] * m3; 314 } while (++i < segend); 315 segend = i + 4; 316 } while (i < opr_sz_4); 317 318 clear_tail(d, opr_sz, simd_maxsz(desc)); 319 } 320 321 void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) 322 { 323 intptr_t i, segend, opr_sz = simd_oprsz(desc), opr_sz_4 = opr_sz / 4; 324 intptr_t index = simd_data(desc); 325 uint32_t *d = vd; 326 uint8_t *n = vn; 327 uint8_t *m_indexed = (uint8_t *)vm + index * 4; 328 329 /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. 330 * Otherwise opr_sz is a multiple of 16. 331 */ 332 segend = MIN(4, opr_sz_4); 333 i = 0; 334 do { 335 uint8_t m0 = m_indexed[i * 4 + 0]; 336 uint8_t m1 = m_indexed[i * 4 + 1]; 337 uint8_t m2 = m_indexed[i * 4 + 2]; 338 uint8_t m3 = m_indexed[i * 4 + 3]; 339 340 do { 341 d[i] += n[i * 4 + 0] * m0 342 + n[i * 4 + 1] * m1 343 + n[i * 4 + 2] * m2 344 + n[i * 4 + 3] * m3; 345 } while (++i < segend); 346 segend = i + 4; 347 } while (i < opr_sz_4); 348 349 clear_tail(d, opr_sz, simd_maxsz(desc)); 350 } 351 352 void HELPER(gvec_sdot_idx_h)(void *vd, void *vn, void *vm, uint32_t desc) 353 { 354 intptr_t i, opr_sz = simd_oprsz(desc), opr_sz_8 = opr_sz / 8; 355 intptr_t index = simd_data(desc); 356 uint64_t *d = vd; 357 int16_t *n = vn; 358 int16_t *m_indexed = (int16_t *)vm + index * 4; 359 360 /* This is supported by SVE only, so opr_sz is always a multiple of 16. 361 * Process the entire segment all at once, writing back the results 362 * only after we've consumed all of the inputs. 363 */ 364 for (i = 0; i < opr_sz_8 ; i += 2) { 365 uint64_t d0, d1; 366 367 d0 = n[i * 4 + 0] * (int64_t)m_indexed[i * 4 + 0]; 368 d0 += n[i * 4 + 1] * (int64_t)m_indexed[i * 4 + 1]; 369 d0 += n[i * 4 + 2] * (int64_t)m_indexed[i * 4 + 2]; 370 d0 += n[i * 4 + 3] * (int64_t)m_indexed[i * 4 + 3]; 371 d1 = n[i * 4 + 4] * (int64_t)m_indexed[i * 4 + 0]; 372 d1 += n[i * 4 + 5] * (int64_t)m_indexed[i * 4 + 1]; 373 d1 += n[i * 4 + 6] * (int64_t)m_indexed[i * 4 + 2]; 374 d1 += n[i * 4 + 7] * (int64_t)m_indexed[i * 4 + 3]; 375 376 d[i + 0] += d0; 377 d[i + 1] += d1; 378 } 379 380 clear_tail(d, opr_sz, simd_maxsz(desc)); 381 } 382 383 void HELPER(gvec_udot_idx_h)(void *vd, void *vn, void *vm, uint32_t desc) 384 { 385 intptr_t i, opr_sz = simd_oprsz(desc), opr_sz_8 = opr_sz / 8; 386 intptr_t index = simd_data(desc); 387 uint64_t *d = vd; 388 uint16_t *n = vn; 389 uint16_t *m_indexed = (uint16_t *)vm + index * 4; 390 391 /* This is supported by SVE only, so opr_sz is always a multiple of 16. 392 * Process the entire segment all at once, writing back the results 393 * only after we've consumed all of the inputs. 394 */ 395 for (i = 0; i < opr_sz_8 ; i += 2) { 396 uint64_t d0, d1; 397 398 d0 = n[i * 4 + 0] * (uint64_t)m_indexed[i * 4 + 0]; 399 d0 += n[i * 4 + 1] * (uint64_t)m_indexed[i * 4 + 1]; 400 d0 += n[i * 4 + 2] * (uint64_t)m_indexed[i * 4 + 2]; 401 d0 += n[i * 4 + 3] * (uint64_t)m_indexed[i * 4 + 3]; 402 d1 = n[i * 4 + 4] * (uint64_t)m_indexed[i * 4 + 0]; 403 d1 += n[i * 4 + 5] * (uint64_t)m_indexed[i * 4 + 1]; 404 d1 += n[i * 4 + 6] * (uint64_t)m_indexed[i * 4 + 2]; 405 d1 += n[i * 4 + 7] * (uint64_t)m_indexed[i * 4 + 3]; 406 407 d[i + 0] += d0; 408 d[i + 1] += d1; 409 } 410 411 clear_tail(d, opr_sz, simd_maxsz(desc)); 412 } 413 414 void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, 415 void *vfpst, uint32_t desc) 416 { 417 uintptr_t opr_sz = simd_oprsz(desc); 418 float16 *d = vd; 419 float16 *n = vn; 420 float16 *m = vm; 421 float_status *fpst = vfpst; 422 uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); 423 uint32_t neg_imag = neg_real ^ 1; 424 uintptr_t i; 425 426 /* Shift boolean to the sign bit so we can xor to negate. */ 427 neg_real <<= 15; 428 neg_imag <<= 15; 429 430 for (i = 0; i < opr_sz / 2; i += 2) { 431 float16 e0 = n[H2(i)]; 432 float16 e1 = m[H2(i + 1)] ^ neg_imag; 433 float16 e2 = n[H2(i + 1)]; 434 float16 e3 = m[H2(i)] ^ neg_real; 435 436 d[H2(i)] = float16_add(e0, e1, fpst); 437 d[H2(i + 1)] = float16_add(e2, e3, fpst); 438 } 439 clear_tail(d, opr_sz, simd_maxsz(desc)); 440 } 441 442 void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, 443 void *vfpst, uint32_t desc) 444 { 445 uintptr_t opr_sz = simd_oprsz(desc); 446 float32 *d = vd; 447 float32 *n = vn; 448 float32 *m = vm; 449 float_status *fpst = vfpst; 450 uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); 451 uint32_t neg_imag = neg_real ^ 1; 452 uintptr_t i; 453 454 /* Shift boolean to the sign bit so we can xor to negate. */ 455 neg_real <<= 31; 456 neg_imag <<= 31; 457 458 for (i = 0; i < opr_sz / 4; i += 2) { 459 float32 e0 = n[H4(i)]; 460 float32 e1 = m[H4(i + 1)] ^ neg_imag; 461 float32 e2 = n[H4(i + 1)]; 462 float32 e3 = m[H4(i)] ^ neg_real; 463 464 d[H4(i)] = float32_add(e0, e1, fpst); 465 d[H4(i + 1)] = float32_add(e2, e3, fpst); 466 } 467 clear_tail(d, opr_sz, simd_maxsz(desc)); 468 } 469 470 void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, 471 void *vfpst, uint32_t desc) 472 { 473 uintptr_t opr_sz = simd_oprsz(desc); 474 float64 *d = vd; 475 float64 *n = vn; 476 float64 *m = vm; 477 float_status *fpst = vfpst; 478 uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1); 479 uint64_t neg_imag = neg_real ^ 1; 480 uintptr_t i; 481 482 /* Shift boolean to the sign bit so we can xor to negate. */ 483 neg_real <<= 63; 484 neg_imag <<= 63; 485 486 for (i = 0; i < opr_sz / 8; i += 2) { 487 float64 e0 = n[i]; 488 float64 e1 = m[i + 1] ^ neg_imag; 489 float64 e2 = n[i + 1]; 490 float64 e3 = m[i] ^ neg_real; 491 492 d[i] = float64_add(e0, e1, fpst); 493 d[i + 1] = float64_add(e2, e3, fpst); 494 } 495 clear_tail(d, opr_sz, simd_maxsz(desc)); 496 } 497 498 void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, 499 void *vfpst, uint32_t desc) 500 { 501 uintptr_t opr_sz = simd_oprsz(desc); 502 float16 *d = vd; 503 float16 *n = vn; 504 float16 *m = vm; 505 float_status *fpst = vfpst; 506 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); 507 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 508 uint32_t neg_real = flip ^ neg_imag; 509 uintptr_t i; 510 511 /* Shift boolean to the sign bit so we can xor to negate. */ 512 neg_real <<= 15; 513 neg_imag <<= 15; 514 515 for (i = 0; i < opr_sz / 2; i += 2) { 516 float16 e2 = n[H2(i + flip)]; 517 float16 e1 = m[H2(i + flip)] ^ neg_real; 518 float16 e4 = e2; 519 float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag; 520 521 d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); 522 d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); 523 } 524 clear_tail(d, opr_sz, simd_maxsz(desc)); 525 } 526 527 void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, 528 void *vfpst, uint32_t desc) 529 { 530 uintptr_t opr_sz = simd_oprsz(desc); 531 float16 *d = vd; 532 float16 *n = vn; 533 float16 *m = vm; 534 float_status *fpst = vfpst; 535 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); 536 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 537 intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2); 538 uint32_t neg_real = flip ^ neg_imag; 539 intptr_t elements = opr_sz / sizeof(float16); 540 intptr_t eltspersegment = 16 / sizeof(float16); 541 intptr_t i, j; 542 543 /* Shift boolean to the sign bit so we can xor to negate. */ 544 neg_real <<= 15; 545 neg_imag <<= 15; 546 547 for (i = 0; i < elements; i += eltspersegment) { 548 float16 mr = m[H2(i + 2 * index + 0)]; 549 float16 mi = m[H2(i + 2 * index + 1)]; 550 float16 e1 = neg_real ^ (flip ? mi : mr); 551 float16 e3 = neg_imag ^ (flip ? mr : mi); 552 553 for (j = i; j < i + eltspersegment; j += 2) { 554 float16 e2 = n[H2(j + flip)]; 555 float16 e4 = e2; 556 557 d[H2(j)] = float16_muladd(e2, e1, d[H2(j)], 0, fpst); 558 d[H2(j + 1)] = float16_muladd(e4, e3, d[H2(j + 1)], 0, fpst); 559 } 560 } 561 clear_tail(d, opr_sz, simd_maxsz(desc)); 562 } 563 564 void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, 565 void *vfpst, uint32_t desc) 566 { 567 uintptr_t opr_sz = simd_oprsz(desc); 568 float32 *d = vd; 569 float32 *n = vn; 570 float32 *m = vm; 571 float_status *fpst = vfpst; 572 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); 573 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 574 uint32_t neg_real = flip ^ neg_imag; 575 uintptr_t i; 576 577 /* Shift boolean to the sign bit so we can xor to negate. */ 578 neg_real <<= 31; 579 neg_imag <<= 31; 580 581 for (i = 0; i < opr_sz / 4; i += 2) { 582 float32 e2 = n[H4(i + flip)]; 583 float32 e1 = m[H4(i + flip)] ^ neg_real; 584 float32 e4 = e2; 585 float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag; 586 587 d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); 588 d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); 589 } 590 clear_tail(d, opr_sz, simd_maxsz(desc)); 591 } 592 593 void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, 594 void *vfpst, uint32_t desc) 595 { 596 uintptr_t opr_sz = simd_oprsz(desc); 597 float32 *d = vd; 598 float32 *n = vn; 599 float32 *m = vm; 600 float_status *fpst = vfpst; 601 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); 602 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 603 intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2); 604 uint32_t neg_real = flip ^ neg_imag; 605 intptr_t elements = opr_sz / sizeof(float32); 606 intptr_t eltspersegment = 16 / sizeof(float32); 607 intptr_t i, j; 608 609 /* Shift boolean to the sign bit so we can xor to negate. */ 610 neg_real <<= 31; 611 neg_imag <<= 31; 612 613 for (i = 0; i < elements; i += eltspersegment) { 614 float32 mr = m[H4(i + 2 * index + 0)]; 615 float32 mi = m[H4(i + 2 * index + 1)]; 616 float32 e1 = neg_real ^ (flip ? mi : mr); 617 float32 e3 = neg_imag ^ (flip ? mr : mi); 618 619 for (j = i; j < i + eltspersegment; j += 2) { 620 float32 e2 = n[H4(j + flip)]; 621 float32 e4 = e2; 622 623 d[H4(j)] = float32_muladd(e2, e1, d[H4(j)], 0, fpst); 624 d[H4(j + 1)] = float32_muladd(e4, e3, d[H4(j + 1)], 0, fpst); 625 } 626 } 627 clear_tail(d, opr_sz, simd_maxsz(desc)); 628 } 629 630 void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, 631 void *vfpst, uint32_t desc) 632 { 633 uintptr_t opr_sz = simd_oprsz(desc); 634 float64 *d = vd; 635 float64 *n = vn; 636 float64 *m = vm; 637 float_status *fpst = vfpst; 638 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); 639 uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 640 uint64_t neg_real = flip ^ neg_imag; 641 uintptr_t i; 642 643 /* Shift boolean to the sign bit so we can xor to negate. */ 644 neg_real <<= 63; 645 neg_imag <<= 63; 646 647 for (i = 0; i < opr_sz / 8; i += 2) { 648 float64 e2 = n[i + flip]; 649 float64 e1 = m[i + flip] ^ neg_real; 650 float64 e4 = e2; 651 float64 e3 = m[i + 1 - flip] ^ neg_imag; 652 653 d[i] = float64_muladd(e2, e1, d[i], 0, fpst); 654 d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst); 655 } 656 clear_tail(d, opr_sz, simd_maxsz(desc)); 657 } 658 659 /* 660 * Floating point comparisons producing an integer result (all 1s or all 0s). 661 * Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do. 662 * Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires. 663 */ 664 static uint16_t float16_ceq(float16 op1, float16 op2, float_status *stat) 665 { 666 return -float16_eq_quiet(op1, op2, stat); 667 } 668 669 static uint32_t float32_ceq(float32 op1, float32 op2, float_status *stat) 670 { 671 return -float32_eq_quiet(op1, op2, stat); 672 } 673 674 static uint16_t float16_cge(float16 op1, float16 op2, float_status *stat) 675 { 676 return -float16_le(op2, op1, stat); 677 } 678 679 static uint32_t float32_cge(float32 op1, float32 op2, float_status *stat) 680 { 681 return -float32_le(op2, op1, stat); 682 } 683 684 static uint16_t float16_cgt(float16 op1, float16 op2, float_status *stat) 685 { 686 return -float16_lt(op2, op1, stat); 687 } 688 689 static uint32_t float32_cgt(float32 op1, float32 op2, float_status *stat) 690 { 691 return -float32_lt(op2, op1, stat); 692 } 693 694 static uint16_t float16_acge(float16 op1, float16 op2, float_status *stat) 695 { 696 return -float16_le(float16_abs(op2), float16_abs(op1), stat); 697 } 698 699 static uint32_t float32_acge(float32 op1, float32 op2, float_status *stat) 700 { 701 return -float32_le(float32_abs(op2), float32_abs(op1), stat); 702 } 703 704 static uint16_t float16_acgt(float16 op1, float16 op2, float_status *stat) 705 { 706 return -float16_lt(float16_abs(op2), float16_abs(op1), stat); 707 } 708 709 static uint32_t float32_acgt(float32 op1, float32 op2, float_status *stat) 710 { 711 return -float32_lt(float32_abs(op2), float32_abs(op1), stat); 712 } 713 714 #define DO_2OP(NAME, FUNC, TYPE) \ 715 void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \ 716 { \ 717 intptr_t i, oprsz = simd_oprsz(desc); \ 718 TYPE *d = vd, *n = vn; \ 719 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 720 d[i] = FUNC(n[i], stat); \ 721 } \ 722 clear_tail(d, oprsz, simd_maxsz(desc)); \ 723 } 724 725 DO_2OP(gvec_frecpe_h, helper_recpe_f16, float16) 726 DO_2OP(gvec_frecpe_s, helper_recpe_f32, float32) 727 DO_2OP(gvec_frecpe_d, helper_recpe_f64, float64) 728 729 DO_2OP(gvec_frsqrte_h, helper_rsqrte_f16, float16) 730 DO_2OP(gvec_frsqrte_s, helper_rsqrte_f32, float32) 731 DO_2OP(gvec_frsqrte_d, helper_rsqrte_f64, float64) 732 733 #undef DO_2OP 734 735 /* Floating-point trigonometric starting value. 736 * See the ARM ARM pseudocode function FPTrigSMul. 737 */ 738 static float16 float16_ftsmul(float16 op1, uint16_t op2, float_status *stat) 739 { 740 float16 result = float16_mul(op1, op1, stat); 741 if (!float16_is_any_nan(result)) { 742 result = float16_set_sign(result, op2 & 1); 743 } 744 return result; 745 } 746 747 static float32 float32_ftsmul(float32 op1, uint32_t op2, float_status *stat) 748 { 749 float32 result = float32_mul(op1, op1, stat); 750 if (!float32_is_any_nan(result)) { 751 result = float32_set_sign(result, op2 & 1); 752 } 753 return result; 754 } 755 756 static float64 float64_ftsmul(float64 op1, uint64_t op2, float_status *stat) 757 { 758 float64 result = float64_mul(op1, op1, stat); 759 if (!float64_is_any_nan(result)) { 760 result = float64_set_sign(result, op2 & 1); 761 } 762 return result; 763 } 764 765 static float16 float16_abd(float16 op1, float16 op2, float_status *stat) 766 { 767 return float16_abs(float16_sub(op1, op2, stat)); 768 } 769 770 static float32 float32_abd(float32 op1, float32 op2, float_status *stat) 771 { 772 return float32_abs(float32_sub(op1, op2, stat)); 773 } 774 775 #define DO_3OP(NAME, FUNC, TYPE) \ 776 void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ 777 { \ 778 intptr_t i, oprsz = simd_oprsz(desc); \ 779 TYPE *d = vd, *n = vn, *m = vm; \ 780 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 781 d[i] = FUNC(n[i], m[i], stat); \ 782 } \ 783 clear_tail(d, oprsz, simd_maxsz(desc)); \ 784 } 785 786 DO_3OP(gvec_fadd_h, float16_add, float16) 787 DO_3OP(gvec_fadd_s, float32_add, float32) 788 DO_3OP(gvec_fadd_d, float64_add, float64) 789 790 DO_3OP(gvec_fsub_h, float16_sub, float16) 791 DO_3OP(gvec_fsub_s, float32_sub, float32) 792 DO_3OP(gvec_fsub_d, float64_sub, float64) 793 794 DO_3OP(gvec_fmul_h, float16_mul, float16) 795 DO_3OP(gvec_fmul_s, float32_mul, float32) 796 DO_3OP(gvec_fmul_d, float64_mul, float64) 797 798 DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16) 799 DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32) 800 DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64) 801 802 DO_3OP(gvec_fabd_h, float16_abd, float16) 803 DO_3OP(gvec_fabd_s, float32_abd, float32) 804 805 DO_3OP(gvec_fceq_h, float16_ceq, float16) 806 DO_3OP(gvec_fceq_s, float32_ceq, float32) 807 808 DO_3OP(gvec_fcge_h, float16_cge, float16) 809 DO_3OP(gvec_fcge_s, float32_cge, float32) 810 811 DO_3OP(gvec_fcgt_h, float16_cgt, float16) 812 DO_3OP(gvec_fcgt_s, float32_cgt, float32) 813 814 DO_3OP(gvec_facge_h, float16_acge, float16) 815 DO_3OP(gvec_facge_s, float32_acge, float32) 816 817 DO_3OP(gvec_facgt_h, float16_acgt, float16) 818 DO_3OP(gvec_facgt_s, float32_acgt, float32) 819 820 DO_3OP(gvec_fmax_h, float16_max, float16) 821 DO_3OP(gvec_fmax_s, float32_max, float32) 822 823 DO_3OP(gvec_fmin_h, float16_min, float16) 824 DO_3OP(gvec_fmin_s, float32_min, float32) 825 826 DO_3OP(gvec_fmaxnum_h, float16_maxnum, float16) 827 DO_3OP(gvec_fmaxnum_s, float32_maxnum, float32) 828 829 DO_3OP(gvec_fminnum_h, float16_minnum, float16) 830 DO_3OP(gvec_fminnum_s, float32_minnum, float32) 831 832 #ifdef TARGET_AARCH64 833 834 DO_3OP(gvec_recps_h, helper_recpsf_f16, float16) 835 DO_3OP(gvec_recps_s, helper_recpsf_f32, float32) 836 DO_3OP(gvec_recps_d, helper_recpsf_f64, float64) 837 838 DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16) 839 DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32) 840 DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64) 841 842 #endif 843 #undef DO_3OP 844 845 /* Non-fused multiply-add (unlike float16_muladd etc, which are fused) */ 846 static float16 float16_muladd_nf(float16 dest, float16 op1, float16 op2, 847 float_status *stat) 848 { 849 return float16_add(dest, float16_mul(op1, op2, stat), stat); 850 } 851 852 static float32 float32_muladd_nf(float32 dest, float32 op1, float32 op2, 853 float_status *stat) 854 { 855 return float32_add(dest, float32_mul(op1, op2, stat), stat); 856 } 857 858 static float16 float16_mulsub_nf(float16 dest, float16 op1, float16 op2, 859 float_status *stat) 860 { 861 return float16_sub(dest, float16_mul(op1, op2, stat), stat); 862 } 863 864 static float32 float32_mulsub_nf(float32 dest, float32 op1, float32 op2, 865 float_status *stat) 866 { 867 return float32_sub(dest, float32_mul(op1, op2, stat), stat); 868 } 869 870 /* Fused versions; these have the semantics Neon VFMA/VFMS want */ 871 static float16 float16_muladd_f(float16 dest, float16 op1, float16 op2, 872 float_status *stat) 873 { 874 return float16_muladd(op1, op2, dest, 0, stat); 875 } 876 877 static float32 float32_muladd_f(float32 dest, float32 op1, float32 op2, 878 float_status *stat) 879 { 880 return float32_muladd(op1, op2, dest, 0, stat); 881 } 882 883 static float16 float16_mulsub_f(float16 dest, float16 op1, float16 op2, 884 float_status *stat) 885 { 886 return float16_muladd(float16_chs(op1), op2, dest, 0, stat); 887 } 888 889 static float32 float32_mulsub_f(float32 dest, float32 op1, float32 op2, 890 float_status *stat) 891 { 892 return float32_muladd(float32_chs(op1), op2, dest, 0, stat); 893 } 894 895 #define DO_MULADD(NAME, FUNC, TYPE) \ 896 void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ 897 { \ 898 intptr_t i, oprsz = simd_oprsz(desc); \ 899 TYPE *d = vd, *n = vn, *m = vm; \ 900 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 901 d[i] = FUNC(d[i], n[i], m[i], stat); \ 902 } \ 903 clear_tail(d, oprsz, simd_maxsz(desc)); \ 904 } 905 906 DO_MULADD(gvec_fmla_h, float16_muladd_nf, float16) 907 DO_MULADD(gvec_fmla_s, float32_muladd_nf, float32) 908 909 DO_MULADD(gvec_fmls_h, float16_mulsub_nf, float16) 910 DO_MULADD(gvec_fmls_s, float32_mulsub_nf, float32) 911 912 DO_MULADD(gvec_vfma_h, float16_muladd_f, float16) 913 DO_MULADD(gvec_vfma_s, float32_muladd_f, float32) 914 915 DO_MULADD(gvec_vfms_h, float16_mulsub_f, float16) 916 DO_MULADD(gvec_vfms_s, float32_mulsub_f, float32) 917 918 /* For the indexed ops, SVE applies the index per 128-bit vector segment. 919 * For AdvSIMD, there is of course only one such vector segment. 920 */ 921 922 #define DO_MUL_IDX(NAME, TYPE, H) \ 923 void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ 924 { \ 925 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \ 926 intptr_t idx = simd_data(desc); \ 927 TYPE *d = vd, *n = vn, *m = vm; \ 928 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \ 929 TYPE mm = m[H(i + idx)]; \ 930 for (j = 0; j < segment; j++) { \ 931 d[i + j] = n[i + j] * mm; \ 932 } \ 933 } \ 934 clear_tail(d, oprsz, simd_maxsz(desc)); \ 935 } 936 937 DO_MUL_IDX(gvec_mul_idx_h, uint16_t, H2) 938 DO_MUL_IDX(gvec_mul_idx_s, uint32_t, H4) 939 DO_MUL_IDX(gvec_mul_idx_d, uint64_t, ) 940 941 #undef DO_MUL_IDX 942 943 #define DO_MLA_IDX(NAME, TYPE, OP, H) \ 944 void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \ 945 { \ 946 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \ 947 intptr_t idx = simd_data(desc); \ 948 TYPE *d = vd, *n = vn, *m = vm, *a = va; \ 949 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \ 950 TYPE mm = m[H(i + idx)]; \ 951 for (j = 0; j < segment; j++) { \ 952 d[i + j] = a[i + j] OP n[i + j] * mm; \ 953 } \ 954 } \ 955 clear_tail(d, oprsz, simd_maxsz(desc)); \ 956 } 957 958 DO_MLA_IDX(gvec_mla_idx_h, uint16_t, +, H2) 959 DO_MLA_IDX(gvec_mla_idx_s, uint32_t, +, H4) 960 DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +, ) 961 962 DO_MLA_IDX(gvec_mls_idx_h, uint16_t, -, H2) 963 DO_MLA_IDX(gvec_mls_idx_s, uint32_t, -, H4) 964 DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, ) 965 966 #undef DO_MLA_IDX 967 968 #define DO_FMUL_IDX(NAME, TYPE, H) \ 969 void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ 970 { \ 971 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \ 972 intptr_t idx = simd_data(desc); \ 973 TYPE *d = vd, *n = vn, *m = vm; \ 974 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \ 975 TYPE mm = m[H(i + idx)]; \ 976 for (j = 0; j < segment; j++) { \ 977 d[i + j] = TYPE##_mul(n[i + j], mm, stat); \ 978 } \ 979 } \ 980 clear_tail(d, oprsz, simd_maxsz(desc)); \ 981 } 982 983 DO_FMUL_IDX(gvec_fmul_idx_h, float16, H2) 984 DO_FMUL_IDX(gvec_fmul_idx_s, float32, H4) 985 DO_FMUL_IDX(gvec_fmul_idx_d, float64, ) 986 987 #undef DO_FMUL_IDX 988 989 #define DO_FMLA_IDX(NAME, TYPE, H) \ 990 void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \ 991 void *stat, uint32_t desc) \ 992 { \ 993 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \ 994 TYPE op1_neg = extract32(desc, SIMD_DATA_SHIFT, 1); \ 995 intptr_t idx = desc >> (SIMD_DATA_SHIFT + 1); \ 996 TYPE *d = vd, *n = vn, *m = vm, *a = va; \ 997 op1_neg <<= (8 * sizeof(TYPE) - 1); \ 998 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \ 999 TYPE mm = m[H(i + idx)]; \ 1000 for (j = 0; j < segment; j++) { \ 1001 d[i + j] = TYPE##_muladd(n[i + j] ^ op1_neg, \ 1002 mm, a[i + j], 0, stat); \ 1003 } \ 1004 } \ 1005 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1006 } 1007 1008 DO_FMLA_IDX(gvec_fmla_idx_h, float16, H2) 1009 DO_FMLA_IDX(gvec_fmla_idx_s, float32, H4) 1010 DO_FMLA_IDX(gvec_fmla_idx_d, float64, ) 1011 1012 #undef DO_FMLA_IDX 1013 1014 #define DO_SAT(NAME, WTYPE, TYPEN, TYPEM, OP, MIN, MAX) \ 1015 void HELPER(NAME)(void *vd, void *vq, void *vn, void *vm, uint32_t desc) \ 1016 { \ 1017 intptr_t i, oprsz = simd_oprsz(desc); \ 1018 TYPEN *d = vd, *n = vn; TYPEM *m = vm; \ 1019 bool q = false; \ 1020 for (i = 0; i < oprsz / sizeof(TYPEN); i++) { \ 1021 WTYPE dd = (WTYPE)n[i] OP m[i]; \ 1022 if (dd < MIN) { \ 1023 dd = MIN; \ 1024 q = true; \ 1025 } else if (dd > MAX) { \ 1026 dd = MAX; \ 1027 q = true; \ 1028 } \ 1029 d[i] = dd; \ 1030 } \ 1031 if (q) { \ 1032 uint32_t *qc = vq; \ 1033 qc[0] = 1; \ 1034 } \ 1035 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1036 } 1037 1038 DO_SAT(gvec_uqadd_b, int, uint8_t, uint8_t, +, 0, UINT8_MAX) 1039 DO_SAT(gvec_uqadd_h, int, uint16_t, uint16_t, +, 0, UINT16_MAX) 1040 DO_SAT(gvec_uqadd_s, int64_t, uint32_t, uint32_t, +, 0, UINT32_MAX) 1041 1042 DO_SAT(gvec_sqadd_b, int, int8_t, int8_t, +, INT8_MIN, INT8_MAX) 1043 DO_SAT(gvec_sqadd_h, int, int16_t, int16_t, +, INT16_MIN, INT16_MAX) 1044 DO_SAT(gvec_sqadd_s, int64_t, int32_t, int32_t, +, INT32_MIN, INT32_MAX) 1045 1046 DO_SAT(gvec_uqsub_b, int, uint8_t, uint8_t, -, 0, UINT8_MAX) 1047 DO_SAT(gvec_uqsub_h, int, uint16_t, uint16_t, -, 0, UINT16_MAX) 1048 DO_SAT(gvec_uqsub_s, int64_t, uint32_t, uint32_t, -, 0, UINT32_MAX) 1049 1050 DO_SAT(gvec_sqsub_b, int, int8_t, int8_t, -, INT8_MIN, INT8_MAX) 1051 DO_SAT(gvec_sqsub_h, int, int16_t, int16_t, -, INT16_MIN, INT16_MAX) 1052 DO_SAT(gvec_sqsub_s, int64_t, int32_t, int32_t, -, INT32_MIN, INT32_MAX) 1053 1054 #undef DO_SAT 1055 1056 void HELPER(gvec_uqadd_d)(void *vd, void *vq, void *vn, 1057 void *vm, uint32_t desc) 1058 { 1059 intptr_t i, oprsz = simd_oprsz(desc); 1060 uint64_t *d = vd, *n = vn, *m = vm; 1061 bool q = false; 1062 1063 for (i = 0; i < oprsz / 8; i++) { 1064 uint64_t nn = n[i], mm = m[i], dd = nn + mm; 1065 if (dd < nn) { 1066 dd = UINT64_MAX; 1067 q = true; 1068 } 1069 d[i] = dd; 1070 } 1071 if (q) { 1072 uint32_t *qc = vq; 1073 qc[0] = 1; 1074 } 1075 clear_tail(d, oprsz, simd_maxsz(desc)); 1076 } 1077 1078 void HELPER(gvec_uqsub_d)(void *vd, void *vq, void *vn, 1079 void *vm, uint32_t desc) 1080 { 1081 intptr_t i, oprsz = simd_oprsz(desc); 1082 uint64_t *d = vd, *n = vn, *m = vm; 1083 bool q = false; 1084 1085 for (i = 0; i < oprsz / 8; i++) { 1086 uint64_t nn = n[i], mm = m[i], dd = nn - mm; 1087 if (nn < mm) { 1088 dd = 0; 1089 q = true; 1090 } 1091 d[i] = dd; 1092 } 1093 if (q) { 1094 uint32_t *qc = vq; 1095 qc[0] = 1; 1096 } 1097 clear_tail(d, oprsz, simd_maxsz(desc)); 1098 } 1099 1100 void HELPER(gvec_sqadd_d)(void *vd, void *vq, void *vn, 1101 void *vm, uint32_t desc) 1102 { 1103 intptr_t i, oprsz = simd_oprsz(desc); 1104 int64_t *d = vd, *n = vn, *m = vm; 1105 bool q = false; 1106 1107 for (i = 0; i < oprsz / 8; i++) { 1108 int64_t nn = n[i], mm = m[i], dd = nn + mm; 1109 if (((dd ^ nn) & ~(nn ^ mm)) & INT64_MIN) { 1110 dd = (nn >> 63) ^ ~INT64_MIN; 1111 q = true; 1112 } 1113 d[i] = dd; 1114 } 1115 if (q) { 1116 uint32_t *qc = vq; 1117 qc[0] = 1; 1118 } 1119 clear_tail(d, oprsz, simd_maxsz(desc)); 1120 } 1121 1122 void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn, 1123 void *vm, uint32_t desc) 1124 { 1125 intptr_t i, oprsz = simd_oprsz(desc); 1126 int64_t *d = vd, *n = vn, *m = vm; 1127 bool q = false; 1128 1129 for (i = 0; i < oprsz / 8; i++) { 1130 int64_t nn = n[i], mm = m[i], dd = nn - mm; 1131 if (((dd ^ nn) & (nn ^ mm)) & INT64_MIN) { 1132 dd = (nn >> 63) ^ ~INT64_MIN; 1133 q = true; 1134 } 1135 d[i] = dd; 1136 } 1137 if (q) { 1138 uint32_t *qc = vq; 1139 qc[0] = 1; 1140 } 1141 clear_tail(d, oprsz, simd_maxsz(desc)); 1142 } 1143 1144 1145 #define DO_SRA(NAME, TYPE) \ 1146 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1147 { \ 1148 intptr_t i, oprsz = simd_oprsz(desc); \ 1149 int shift = simd_data(desc); \ 1150 TYPE *d = vd, *n = vn; \ 1151 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 1152 d[i] += n[i] >> shift; \ 1153 } \ 1154 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1155 } 1156 1157 DO_SRA(gvec_ssra_b, int8_t) 1158 DO_SRA(gvec_ssra_h, int16_t) 1159 DO_SRA(gvec_ssra_s, int32_t) 1160 DO_SRA(gvec_ssra_d, int64_t) 1161 1162 DO_SRA(gvec_usra_b, uint8_t) 1163 DO_SRA(gvec_usra_h, uint16_t) 1164 DO_SRA(gvec_usra_s, uint32_t) 1165 DO_SRA(gvec_usra_d, uint64_t) 1166 1167 #undef DO_SRA 1168 1169 #define DO_RSHR(NAME, TYPE) \ 1170 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1171 { \ 1172 intptr_t i, oprsz = simd_oprsz(desc); \ 1173 int shift = simd_data(desc); \ 1174 TYPE *d = vd, *n = vn; \ 1175 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 1176 TYPE tmp = n[i] >> (shift - 1); \ 1177 d[i] = (tmp >> 1) + (tmp & 1); \ 1178 } \ 1179 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1180 } 1181 1182 DO_RSHR(gvec_srshr_b, int8_t) 1183 DO_RSHR(gvec_srshr_h, int16_t) 1184 DO_RSHR(gvec_srshr_s, int32_t) 1185 DO_RSHR(gvec_srshr_d, int64_t) 1186 1187 DO_RSHR(gvec_urshr_b, uint8_t) 1188 DO_RSHR(gvec_urshr_h, uint16_t) 1189 DO_RSHR(gvec_urshr_s, uint32_t) 1190 DO_RSHR(gvec_urshr_d, uint64_t) 1191 1192 #undef DO_RSHR 1193 1194 #define DO_RSRA(NAME, TYPE) \ 1195 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1196 { \ 1197 intptr_t i, oprsz = simd_oprsz(desc); \ 1198 int shift = simd_data(desc); \ 1199 TYPE *d = vd, *n = vn; \ 1200 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 1201 TYPE tmp = n[i] >> (shift - 1); \ 1202 d[i] += (tmp >> 1) + (tmp & 1); \ 1203 } \ 1204 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1205 } 1206 1207 DO_RSRA(gvec_srsra_b, int8_t) 1208 DO_RSRA(gvec_srsra_h, int16_t) 1209 DO_RSRA(gvec_srsra_s, int32_t) 1210 DO_RSRA(gvec_srsra_d, int64_t) 1211 1212 DO_RSRA(gvec_ursra_b, uint8_t) 1213 DO_RSRA(gvec_ursra_h, uint16_t) 1214 DO_RSRA(gvec_ursra_s, uint32_t) 1215 DO_RSRA(gvec_ursra_d, uint64_t) 1216 1217 #undef DO_RSRA 1218 1219 #define DO_SRI(NAME, TYPE) \ 1220 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1221 { \ 1222 intptr_t i, oprsz = simd_oprsz(desc); \ 1223 int shift = simd_data(desc); \ 1224 TYPE *d = vd, *n = vn; \ 1225 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 1226 d[i] = deposit64(d[i], 0, sizeof(TYPE) * 8 - shift, n[i] >> shift); \ 1227 } \ 1228 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1229 } 1230 1231 DO_SRI(gvec_sri_b, uint8_t) 1232 DO_SRI(gvec_sri_h, uint16_t) 1233 DO_SRI(gvec_sri_s, uint32_t) 1234 DO_SRI(gvec_sri_d, uint64_t) 1235 1236 #undef DO_SRI 1237 1238 #define DO_SLI(NAME, TYPE) \ 1239 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1240 { \ 1241 intptr_t i, oprsz = simd_oprsz(desc); \ 1242 int shift = simd_data(desc); \ 1243 TYPE *d = vd, *n = vn; \ 1244 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 1245 d[i] = deposit64(d[i], shift, sizeof(TYPE) * 8 - shift, n[i]); \ 1246 } \ 1247 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1248 } 1249 1250 DO_SLI(gvec_sli_b, uint8_t) 1251 DO_SLI(gvec_sli_h, uint16_t) 1252 DO_SLI(gvec_sli_s, uint32_t) 1253 DO_SLI(gvec_sli_d, uint64_t) 1254 1255 #undef DO_SLI 1256 1257 /* 1258 * Convert float16 to float32, raising no exceptions and 1259 * preserving exceptional values, including SNaN. 1260 * This is effectively an unpack+repack operation. 1261 */ 1262 static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16) 1263 { 1264 const int f16_bias = 15; 1265 const int f32_bias = 127; 1266 uint32_t sign = extract32(f16, 15, 1); 1267 uint32_t exp = extract32(f16, 10, 5); 1268 uint32_t frac = extract32(f16, 0, 10); 1269 1270 if (exp == 0x1f) { 1271 /* Inf or NaN */ 1272 exp = 0xff; 1273 } else if (exp == 0) { 1274 /* Zero or denormal. */ 1275 if (frac != 0) { 1276 if (fz16) { 1277 frac = 0; 1278 } else { 1279 /* 1280 * Denormal; these are all normal float32. 1281 * Shift the fraction so that the msb is at bit 11, 1282 * then remove bit 11 as the implicit bit of the 1283 * normalized float32. Note that we still go through 1284 * the shift for normal numbers below, to put the 1285 * float32 fraction at the right place. 1286 */ 1287 int shift = clz32(frac) - 21; 1288 frac = (frac << shift) & 0x3ff; 1289 exp = f32_bias - f16_bias - shift + 1; 1290 } 1291 } 1292 } else { 1293 /* Normal number; adjust the bias. */ 1294 exp += f32_bias - f16_bias; 1295 } 1296 sign <<= 31; 1297 exp <<= 23; 1298 frac <<= 23 - 10; 1299 1300 return sign | exp | frac; 1301 } 1302 1303 static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2) 1304 { 1305 /* 1306 * Branchless load of u32[0], u64[0], u32[1], or u64[1]. 1307 * Load the 2nd qword iff is_q & is_2. 1308 * Shift to the 2nd dword iff !is_q & is_2. 1309 * For !is_q & !is_2, the upper bits of the result are garbage. 1310 */ 1311 return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5); 1312 } 1313 1314 /* 1315 * Note that FMLAL requires oprsz == 8 or oprsz == 16, 1316 * as there is not yet SVE versions that might use blocking. 1317 */ 1318 1319 static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst, 1320 uint32_t desc, bool fz16) 1321 { 1322 intptr_t i, oprsz = simd_oprsz(desc); 1323 int is_s = extract32(desc, SIMD_DATA_SHIFT, 1); 1324 int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 1325 int is_q = oprsz == 16; 1326 uint64_t n_4, m_4; 1327 1328 /* Pre-load all of the f16 data, avoiding overlap issues. */ 1329 n_4 = load4_f16(vn, is_q, is_2); 1330 m_4 = load4_f16(vm, is_q, is_2); 1331 1332 /* Negate all inputs for FMLSL at once. */ 1333 if (is_s) { 1334 n_4 ^= 0x8000800080008000ull; 1335 } 1336 1337 for (i = 0; i < oprsz / 4; i++) { 1338 float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16); 1339 float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16); 1340 d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst); 1341 } 1342 clear_tail(d, oprsz, simd_maxsz(desc)); 1343 } 1344 1345 void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm, 1346 void *venv, uint32_t desc) 1347 { 1348 CPUARMState *env = venv; 1349 do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc, 1350 get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); 1351 } 1352 1353 void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm, 1354 void *venv, uint32_t desc) 1355 { 1356 CPUARMState *env = venv; 1357 do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc, 1358 get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); 1359 } 1360 1361 static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst, 1362 uint32_t desc, bool fz16) 1363 { 1364 intptr_t i, oprsz = simd_oprsz(desc); 1365 int is_s = extract32(desc, SIMD_DATA_SHIFT, 1); 1366 int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 1367 int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3); 1368 int is_q = oprsz == 16; 1369 uint64_t n_4; 1370 float32 m_1; 1371 1372 /* Pre-load all of the f16 data, avoiding overlap issues. */ 1373 n_4 = load4_f16(vn, is_q, is_2); 1374 1375 /* Negate all inputs for FMLSL at once. */ 1376 if (is_s) { 1377 n_4 ^= 0x8000800080008000ull; 1378 } 1379 1380 m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16); 1381 1382 for (i = 0; i < oprsz / 4; i++) { 1383 float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16); 1384 d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst); 1385 } 1386 clear_tail(d, oprsz, simd_maxsz(desc)); 1387 } 1388 1389 void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm, 1390 void *venv, uint32_t desc) 1391 { 1392 CPUARMState *env = venv; 1393 do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc, 1394 get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); 1395 } 1396 1397 void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm, 1398 void *venv, uint32_t desc) 1399 { 1400 CPUARMState *env = venv; 1401 do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc, 1402 get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); 1403 } 1404 1405 void HELPER(gvec_sshl_b)(void *vd, void *vn, void *vm, uint32_t desc) 1406 { 1407 intptr_t i, opr_sz = simd_oprsz(desc); 1408 int8_t *d = vd, *n = vn, *m = vm; 1409 1410 for (i = 0; i < opr_sz; ++i) { 1411 int8_t mm = m[i]; 1412 int8_t nn = n[i]; 1413 int8_t res = 0; 1414 if (mm >= 0) { 1415 if (mm < 8) { 1416 res = nn << mm; 1417 } 1418 } else { 1419 res = nn >> (mm > -8 ? -mm : 7); 1420 } 1421 d[i] = res; 1422 } 1423 clear_tail(d, opr_sz, simd_maxsz(desc)); 1424 } 1425 1426 void HELPER(gvec_sshl_h)(void *vd, void *vn, void *vm, uint32_t desc) 1427 { 1428 intptr_t i, opr_sz = simd_oprsz(desc); 1429 int16_t *d = vd, *n = vn, *m = vm; 1430 1431 for (i = 0; i < opr_sz / 2; ++i) { 1432 int8_t mm = m[i]; /* only 8 bits of shift are significant */ 1433 int16_t nn = n[i]; 1434 int16_t res = 0; 1435 if (mm >= 0) { 1436 if (mm < 16) { 1437 res = nn << mm; 1438 } 1439 } else { 1440 res = nn >> (mm > -16 ? -mm : 15); 1441 } 1442 d[i] = res; 1443 } 1444 clear_tail(d, opr_sz, simd_maxsz(desc)); 1445 } 1446 1447 void HELPER(gvec_ushl_b)(void *vd, void *vn, void *vm, uint32_t desc) 1448 { 1449 intptr_t i, opr_sz = simd_oprsz(desc); 1450 uint8_t *d = vd, *n = vn, *m = vm; 1451 1452 for (i = 0; i < opr_sz; ++i) { 1453 int8_t mm = m[i]; 1454 uint8_t nn = n[i]; 1455 uint8_t res = 0; 1456 if (mm >= 0) { 1457 if (mm < 8) { 1458 res = nn << mm; 1459 } 1460 } else { 1461 if (mm > -8) { 1462 res = nn >> -mm; 1463 } 1464 } 1465 d[i] = res; 1466 } 1467 clear_tail(d, opr_sz, simd_maxsz(desc)); 1468 } 1469 1470 void HELPER(gvec_ushl_h)(void *vd, void *vn, void *vm, uint32_t desc) 1471 { 1472 intptr_t i, opr_sz = simd_oprsz(desc); 1473 uint16_t *d = vd, *n = vn, *m = vm; 1474 1475 for (i = 0; i < opr_sz / 2; ++i) { 1476 int8_t mm = m[i]; /* only 8 bits of shift are significant */ 1477 uint16_t nn = n[i]; 1478 uint16_t res = 0; 1479 if (mm >= 0) { 1480 if (mm < 16) { 1481 res = nn << mm; 1482 } 1483 } else { 1484 if (mm > -16) { 1485 res = nn >> -mm; 1486 } 1487 } 1488 d[i] = res; 1489 } 1490 clear_tail(d, opr_sz, simd_maxsz(desc)); 1491 } 1492 1493 /* 1494 * 8x8->8 polynomial multiply. 1495 * 1496 * Polynomial multiplication is like integer multiplication except the 1497 * partial products are XORed, not added. 1498 * 1499 * TODO: expose this as a generic vector operation, as it is a common 1500 * crypto building block. 1501 */ 1502 void HELPER(gvec_pmul_b)(void *vd, void *vn, void *vm, uint32_t desc) 1503 { 1504 intptr_t i, j, opr_sz = simd_oprsz(desc); 1505 uint64_t *d = vd, *n = vn, *m = vm; 1506 1507 for (i = 0; i < opr_sz / 8; ++i) { 1508 uint64_t nn = n[i]; 1509 uint64_t mm = m[i]; 1510 uint64_t rr = 0; 1511 1512 for (j = 0; j < 8; ++j) { 1513 uint64_t mask = (nn & 0x0101010101010101ull) * 0xff; 1514 rr ^= mm & mask; 1515 mm = (mm << 1) & 0xfefefefefefefefeull; 1516 nn >>= 1; 1517 } 1518 d[i] = rr; 1519 } 1520 clear_tail(d, opr_sz, simd_maxsz(desc)); 1521 } 1522 1523 /* 1524 * 64x64->128 polynomial multiply. 1525 * Because of the lanes are not accessed in strict columns, 1526 * this probably cannot be turned into a generic helper. 1527 */ 1528 void HELPER(gvec_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc) 1529 { 1530 intptr_t i, j, opr_sz = simd_oprsz(desc); 1531 intptr_t hi = simd_data(desc); 1532 uint64_t *d = vd, *n = vn, *m = vm; 1533 1534 for (i = 0; i < opr_sz / 8; i += 2) { 1535 uint64_t nn = n[i + hi]; 1536 uint64_t mm = m[i + hi]; 1537 uint64_t rhi = 0; 1538 uint64_t rlo = 0; 1539 1540 /* Bit 0 can only influence the low 64-bit result. */ 1541 if (nn & 1) { 1542 rlo = mm; 1543 } 1544 1545 for (j = 1; j < 64; ++j) { 1546 uint64_t mask = -((nn >> j) & 1); 1547 rlo ^= (mm << j) & mask; 1548 rhi ^= (mm >> (64 - j)) & mask; 1549 } 1550 d[i] = rlo; 1551 d[i + 1] = rhi; 1552 } 1553 clear_tail(d, opr_sz, simd_maxsz(desc)); 1554 } 1555 1556 /* 1557 * 8x8->16 polynomial multiply. 1558 * 1559 * The byte inputs are expanded to (or extracted from) half-words. 1560 * Note that neon and sve2 get the inputs from different positions. 1561 * This allows 4 bytes to be processed in parallel with uint64_t. 1562 */ 1563 1564 static uint64_t expand_byte_to_half(uint64_t x) 1565 { 1566 return (x & 0x000000ff) 1567 | ((x & 0x0000ff00) << 8) 1568 | ((x & 0x00ff0000) << 16) 1569 | ((x & 0xff000000) << 24); 1570 } 1571 1572 static uint64_t pmull_h(uint64_t op1, uint64_t op2) 1573 { 1574 uint64_t result = 0; 1575 int i; 1576 1577 for (i = 0; i < 8; ++i) { 1578 uint64_t mask = (op1 & 0x0001000100010001ull) * 0xffff; 1579 result ^= op2 & mask; 1580 op1 >>= 1; 1581 op2 <<= 1; 1582 } 1583 return result; 1584 } 1585 1586 void HELPER(neon_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) 1587 { 1588 int hi = simd_data(desc); 1589 uint64_t *d = vd, *n = vn, *m = vm; 1590 uint64_t nn = n[hi], mm = m[hi]; 1591 1592 d[0] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm)); 1593 nn >>= 32; 1594 mm >>= 32; 1595 d[1] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm)); 1596 1597 clear_tail(d, 16, simd_maxsz(desc)); 1598 } 1599 1600 #ifdef TARGET_AARCH64 1601 void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) 1602 { 1603 int shift = simd_data(desc) * 8; 1604 intptr_t i, opr_sz = simd_oprsz(desc); 1605 uint64_t *d = vd, *n = vn, *m = vm; 1606 1607 for (i = 0; i < opr_sz / 8; ++i) { 1608 uint64_t nn = (n[i] >> shift) & 0x00ff00ff00ff00ffull; 1609 uint64_t mm = (m[i] >> shift) & 0x00ff00ff00ff00ffull; 1610 1611 d[i] = pmull_h(nn, mm); 1612 } 1613 } 1614 #endif 1615 1616 #define DO_CMP0(NAME, TYPE, OP) \ 1617 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1618 { \ 1619 intptr_t i, opr_sz = simd_oprsz(desc); \ 1620 for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \ 1621 TYPE nn = *(TYPE *)(vn + i); \ 1622 *(TYPE *)(vd + i) = -(nn OP 0); \ 1623 } \ 1624 clear_tail(vd, opr_sz, simd_maxsz(desc)); \ 1625 } 1626 1627 DO_CMP0(gvec_ceq0_b, int8_t, ==) 1628 DO_CMP0(gvec_clt0_b, int8_t, <) 1629 DO_CMP0(gvec_cle0_b, int8_t, <=) 1630 DO_CMP0(gvec_cgt0_b, int8_t, >) 1631 DO_CMP0(gvec_cge0_b, int8_t, >=) 1632 1633 DO_CMP0(gvec_ceq0_h, int16_t, ==) 1634 DO_CMP0(gvec_clt0_h, int16_t, <) 1635 DO_CMP0(gvec_cle0_h, int16_t, <=) 1636 DO_CMP0(gvec_cgt0_h, int16_t, >) 1637 DO_CMP0(gvec_cge0_h, int16_t, >=) 1638 1639 #undef DO_CMP0 1640 1641 #define DO_ABD(NAME, TYPE) \ 1642 void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ 1643 { \ 1644 intptr_t i, opr_sz = simd_oprsz(desc); \ 1645 TYPE *d = vd, *n = vn, *m = vm; \ 1646 \ 1647 for (i = 0; i < opr_sz / sizeof(TYPE); ++i) { \ 1648 d[i] = n[i] < m[i] ? m[i] - n[i] : n[i] - m[i]; \ 1649 } \ 1650 clear_tail(d, opr_sz, simd_maxsz(desc)); \ 1651 } 1652 1653 DO_ABD(gvec_sabd_b, int8_t) 1654 DO_ABD(gvec_sabd_h, int16_t) 1655 DO_ABD(gvec_sabd_s, int32_t) 1656 DO_ABD(gvec_sabd_d, int64_t) 1657 1658 DO_ABD(gvec_uabd_b, uint8_t) 1659 DO_ABD(gvec_uabd_h, uint16_t) 1660 DO_ABD(gvec_uabd_s, uint32_t) 1661 DO_ABD(gvec_uabd_d, uint64_t) 1662 1663 #undef DO_ABD 1664 1665 #define DO_ABA(NAME, TYPE) \ 1666 void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ 1667 { \ 1668 intptr_t i, opr_sz = simd_oprsz(desc); \ 1669 TYPE *d = vd, *n = vn, *m = vm; \ 1670 \ 1671 for (i = 0; i < opr_sz / sizeof(TYPE); ++i) { \ 1672 d[i] += n[i] < m[i] ? m[i] - n[i] : n[i] - m[i]; \ 1673 } \ 1674 clear_tail(d, opr_sz, simd_maxsz(desc)); \ 1675 } 1676 1677 DO_ABA(gvec_saba_b, int8_t) 1678 DO_ABA(gvec_saba_h, int16_t) 1679 DO_ABA(gvec_saba_s, int32_t) 1680 DO_ABA(gvec_saba_d, int64_t) 1681 1682 DO_ABA(gvec_uaba_b, uint8_t) 1683 DO_ABA(gvec_uaba_h, uint16_t) 1684 DO_ABA(gvec_uaba_s, uint32_t) 1685 DO_ABA(gvec_uaba_d, uint64_t) 1686 1687 #undef DO_ABA 1688