1 /* 2 * ARM AdvSIMD / SVE Vector Operations 3 * 4 * Copyright (c) 2018 Linaro 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "tcg/tcg-gvec-desc.h" 24 #include "fpu/softfloat.h" 25 #include "vec_internal.h" 26 27 /* Note that vector data is stored in host-endian 64-bit chunks, 28 so addressing units smaller than that needs a host-endian fixup. */ 29 #ifdef HOST_WORDS_BIGENDIAN 30 #define H1(x) ((x) ^ 7) 31 #define H2(x) ((x) ^ 3) 32 #define H4(x) ((x) ^ 1) 33 #else 34 #define H1(x) (x) 35 #define H2(x) (x) 36 #define H4(x) (x) 37 #endif 38 39 /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ 40 static int16_t do_sqrdmlah_h(int16_t src1, int16_t src2, int16_t src3, 41 bool neg, bool round, uint32_t *sat) 42 { 43 /* 44 * Simplify: 45 * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16 46 * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15 47 */ 48 int32_t ret = (int32_t)src1 * src2; 49 if (neg) { 50 ret = -ret; 51 } 52 ret += ((int32_t)src3 << 15) + (round << 14); 53 ret >>= 15; 54 55 if (ret != (int16_t)ret) { 56 *sat = 1; 57 ret = (ret < 0 ? INT16_MIN : INT16_MAX); 58 } 59 return ret; 60 } 61 62 uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1, 63 uint32_t src2, uint32_t src3) 64 { 65 uint32_t *sat = &env->vfp.qc[0]; 66 uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, false, true, sat); 67 uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16, 68 false, true, sat); 69 return deposit32(e1, 16, 16, e2); 70 } 71 72 void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, 73 void *vq, uint32_t desc) 74 { 75 uintptr_t opr_sz = simd_oprsz(desc); 76 int16_t *d = vd; 77 int16_t *n = vn; 78 int16_t *m = vm; 79 uintptr_t i; 80 81 for (i = 0; i < opr_sz / 2; ++i) { 82 d[i] = do_sqrdmlah_h(n[i], m[i], d[i], false, true, vq); 83 } 84 clear_tail(d, opr_sz, simd_maxsz(desc)); 85 } 86 87 uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1, 88 uint32_t src2, uint32_t src3) 89 { 90 uint32_t *sat = &env->vfp.qc[0]; 91 uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, true, true, sat); 92 uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16, 93 true, true, sat); 94 return deposit32(e1, 16, 16, e2); 95 } 96 97 void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm, 98 void *vq, uint32_t desc) 99 { 100 uintptr_t opr_sz = simd_oprsz(desc); 101 int16_t *d = vd; 102 int16_t *n = vn; 103 int16_t *m = vm; 104 uintptr_t i; 105 106 for (i = 0; i < opr_sz / 2; ++i) { 107 d[i] = do_sqrdmlah_h(n[i], m[i], d[i], true, true, vq); 108 } 109 clear_tail(d, opr_sz, simd_maxsz(desc)); 110 } 111 112 void HELPER(neon_sqdmulh_h)(void *vd, void *vn, void *vm, 113 void *vq, uint32_t desc) 114 { 115 intptr_t i, opr_sz = simd_oprsz(desc); 116 int16_t *d = vd, *n = vn, *m = vm; 117 118 for (i = 0; i < opr_sz / 2; ++i) { 119 d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, false, vq); 120 } 121 clear_tail(d, opr_sz, simd_maxsz(desc)); 122 } 123 124 void HELPER(neon_sqrdmulh_h)(void *vd, void *vn, void *vm, 125 void *vq, uint32_t desc) 126 { 127 intptr_t i, opr_sz = simd_oprsz(desc); 128 int16_t *d = vd, *n = vn, *m = vm; 129 130 for (i = 0; i < opr_sz / 2; ++i) { 131 d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, true, vq); 132 } 133 clear_tail(d, opr_sz, simd_maxsz(desc)); 134 } 135 136 /* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */ 137 static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3, 138 bool neg, bool round, uint32_t *sat) 139 { 140 /* Simplify similarly to int_qrdmlah_s16 above. */ 141 int64_t ret = (int64_t)src1 * src2; 142 if (neg) { 143 ret = -ret; 144 } 145 ret += ((int64_t)src3 << 31) + (round << 30); 146 ret >>= 31; 147 148 if (ret != (int32_t)ret) { 149 *sat = 1; 150 ret = (ret < 0 ? INT32_MIN : INT32_MAX); 151 } 152 return ret; 153 } 154 155 uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1, 156 int32_t src2, int32_t src3) 157 { 158 uint32_t *sat = &env->vfp.qc[0]; 159 return do_sqrdmlah_s(src1, src2, src3, false, true, sat); 160 } 161 162 void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm, 163 void *vq, uint32_t desc) 164 { 165 uintptr_t opr_sz = simd_oprsz(desc); 166 int32_t *d = vd; 167 int32_t *n = vn; 168 int32_t *m = vm; 169 uintptr_t i; 170 171 for (i = 0; i < opr_sz / 4; ++i) { 172 d[i] = do_sqrdmlah_s(n[i], m[i], d[i], false, true, vq); 173 } 174 clear_tail(d, opr_sz, simd_maxsz(desc)); 175 } 176 177 uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1, 178 int32_t src2, int32_t src3) 179 { 180 uint32_t *sat = &env->vfp.qc[0]; 181 return do_sqrdmlah_s(src1, src2, src3, true, true, sat); 182 } 183 184 void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, 185 void *vq, uint32_t desc) 186 { 187 uintptr_t opr_sz = simd_oprsz(desc); 188 int32_t *d = vd; 189 int32_t *n = vn; 190 int32_t *m = vm; 191 uintptr_t i; 192 193 for (i = 0; i < opr_sz / 4; ++i) { 194 d[i] = do_sqrdmlah_s(n[i], m[i], d[i], true, true, vq); 195 } 196 clear_tail(d, opr_sz, simd_maxsz(desc)); 197 } 198 199 void HELPER(neon_sqdmulh_s)(void *vd, void *vn, void *vm, 200 void *vq, uint32_t desc) 201 { 202 intptr_t i, opr_sz = simd_oprsz(desc); 203 int32_t *d = vd, *n = vn, *m = vm; 204 205 for (i = 0; i < opr_sz / 4; ++i) { 206 d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, false, vq); 207 } 208 clear_tail(d, opr_sz, simd_maxsz(desc)); 209 } 210 211 void HELPER(neon_sqrdmulh_s)(void *vd, void *vn, void *vm, 212 void *vq, uint32_t desc) 213 { 214 intptr_t i, opr_sz = simd_oprsz(desc); 215 int32_t *d = vd, *n = vn, *m = vm; 216 217 for (i = 0; i < opr_sz / 4; ++i) { 218 d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, true, vq); 219 } 220 clear_tail(d, opr_sz, simd_maxsz(desc)); 221 } 222 223 /* Integer 8 and 16-bit dot-product. 224 * 225 * Note that for the loops herein, host endianness does not matter 226 * with respect to the ordering of data within the 64-bit lanes. 227 * All elements are treated equally, no matter where they are. 228 */ 229 230 void HELPER(gvec_sdot_b)(void *vd, void *vn, void *vm, uint32_t desc) 231 { 232 intptr_t i, opr_sz = simd_oprsz(desc); 233 uint32_t *d = vd; 234 int8_t *n = vn, *m = vm; 235 236 for (i = 0; i < opr_sz / 4; ++i) { 237 d[i] += n[i * 4 + 0] * m[i * 4 + 0] 238 + n[i * 4 + 1] * m[i * 4 + 1] 239 + n[i * 4 + 2] * m[i * 4 + 2] 240 + n[i * 4 + 3] * m[i * 4 + 3]; 241 } 242 clear_tail(d, opr_sz, simd_maxsz(desc)); 243 } 244 245 void HELPER(gvec_udot_b)(void *vd, void *vn, void *vm, uint32_t desc) 246 { 247 intptr_t i, opr_sz = simd_oprsz(desc); 248 uint32_t *d = vd; 249 uint8_t *n = vn, *m = vm; 250 251 for (i = 0; i < opr_sz / 4; ++i) { 252 d[i] += n[i * 4 + 0] * m[i * 4 + 0] 253 + n[i * 4 + 1] * m[i * 4 + 1] 254 + n[i * 4 + 2] * m[i * 4 + 2] 255 + n[i * 4 + 3] * m[i * 4 + 3]; 256 } 257 clear_tail(d, opr_sz, simd_maxsz(desc)); 258 } 259 260 void HELPER(gvec_sdot_h)(void *vd, void *vn, void *vm, uint32_t desc) 261 { 262 intptr_t i, opr_sz = simd_oprsz(desc); 263 uint64_t *d = vd; 264 int16_t *n = vn, *m = vm; 265 266 for (i = 0; i < opr_sz / 8; ++i) { 267 d[i] += (int64_t)n[i * 4 + 0] * m[i * 4 + 0] 268 + (int64_t)n[i * 4 + 1] * m[i * 4 + 1] 269 + (int64_t)n[i * 4 + 2] * m[i * 4 + 2] 270 + (int64_t)n[i * 4 + 3] * m[i * 4 + 3]; 271 } 272 clear_tail(d, opr_sz, simd_maxsz(desc)); 273 } 274 275 void HELPER(gvec_udot_h)(void *vd, void *vn, void *vm, uint32_t desc) 276 { 277 intptr_t i, opr_sz = simd_oprsz(desc); 278 uint64_t *d = vd; 279 uint16_t *n = vn, *m = vm; 280 281 for (i = 0; i < opr_sz / 8; ++i) { 282 d[i] += (uint64_t)n[i * 4 + 0] * m[i * 4 + 0] 283 + (uint64_t)n[i * 4 + 1] * m[i * 4 + 1] 284 + (uint64_t)n[i * 4 + 2] * m[i * 4 + 2] 285 + (uint64_t)n[i * 4 + 3] * m[i * 4 + 3]; 286 } 287 clear_tail(d, opr_sz, simd_maxsz(desc)); 288 } 289 290 void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) 291 { 292 intptr_t i, segend, opr_sz = simd_oprsz(desc), opr_sz_4 = opr_sz / 4; 293 intptr_t index = simd_data(desc); 294 uint32_t *d = vd; 295 int8_t *n = vn; 296 int8_t *m_indexed = (int8_t *)vm + index * 4; 297 298 /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. 299 * Otherwise opr_sz is a multiple of 16. 300 */ 301 segend = MIN(4, opr_sz_4); 302 i = 0; 303 do { 304 int8_t m0 = m_indexed[i * 4 + 0]; 305 int8_t m1 = m_indexed[i * 4 + 1]; 306 int8_t m2 = m_indexed[i * 4 + 2]; 307 int8_t m3 = m_indexed[i * 4 + 3]; 308 309 do { 310 d[i] += n[i * 4 + 0] * m0 311 + n[i * 4 + 1] * m1 312 + n[i * 4 + 2] * m2 313 + n[i * 4 + 3] * m3; 314 } while (++i < segend); 315 segend = i + 4; 316 } while (i < opr_sz_4); 317 318 clear_tail(d, opr_sz, simd_maxsz(desc)); 319 } 320 321 void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) 322 { 323 intptr_t i, segend, opr_sz = simd_oprsz(desc), opr_sz_4 = opr_sz / 4; 324 intptr_t index = simd_data(desc); 325 uint32_t *d = vd; 326 uint8_t *n = vn; 327 uint8_t *m_indexed = (uint8_t *)vm + index * 4; 328 329 /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. 330 * Otherwise opr_sz is a multiple of 16. 331 */ 332 segend = MIN(4, opr_sz_4); 333 i = 0; 334 do { 335 uint8_t m0 = m_indexed[i * 4 + 0]; 336 uint8_t m1 = m_indexed[i * 4 + 1]; 337 uint8_t m2 = m_indexed[i * 4 + 2]; 338 uint8_t m3 = m_indexed[i * 4 + 3]; 339 340 do { 341 d[i] += n[i * 4 + 0] * m0 342 + n[i * 4 + 1] * m1 343 + n[i * 4 + 2] * m2 344 + n[i * 4 + 3] * m3; 345 } while (++i < segend); 346 segend = i + 4; 347 } while (i < opr_sz_4); 348 349 clear_tail(d, opr_sz, simd_maxsz(desc)); 350 } 351 352 void HELPER(gvec_sdot_idx_h)(void *vd, void *vn, void *vm, uint32_t desc) 353 { 354 intptr_t i, opr_sz = simd_oprsz(desc), opr_sz_8 = opr_sz / 8; 355 intptr_t index = simd_data(desc); 356 uint64_t *d = vd; 357 int16_t *n = vn; 358 int16_t *m_indexed = (int16_t *)vm + index * 4; 359 360 /* This is supported by SVE only, so opr_sz is always a multiple of 16. 361 * Process the entire segment all at once, writing back the results 362 * only after we've consumed all of the inputs. 363 */ 364 for (i = 0; i < opr_sz_8 ; i += 2) { 365 uint64_t d0, d1; 366 367 d0 = n[i * 4 + 0] * (int64_t)m_indexed[i * 4 + 0]; 368 d0 += n[i * 4 + 1] * (int64_t)m_indexed[i * 4 + 1]; 369 d0 += n[i * 4 + 2] * (int64_t)m_indexed[i * 4 + 2]; 370 d0 += n[i * 4 + 3] * (int64_t)m_indexed[i * 4 + 3]; 371 d1 = n[i * 4 + 4] * (int64_t)m_indexed[i * 4 + 0]; 372 d1 += n[i * 4 + 5] * (int64_t)m_indexed[i * 4 + 1]; 373 d1 += n[i * 4 + 6] * (int64_t)m_indexed[i * 4 + 2]; 374 d1 += n[i * 4 + 7] * (int64_t)m_indexed[i * 4 + 3]; 375 376 d[i + 0] += d0; 377 d[i + 1] += d1; 378 } 379 380 clear_tail(d, opr_sz, simd_maxsz(desc)); 381 } 382 383 void HELPER(gvec_udot_idx_h)(void *vd, void *vn, void *vm, uint32_t desc) 384 { 385 intptr_t i, opr_sz = simd_oprsz(desc), opr_sz_8 = opr_sz / 8; 386 intptr_t index = simd_data(desc); 387 uint64_t *d = vd; 388 uint16_t *n = vn; 389 uint16_t *m_indexed = (uint16_t *)vm + index * 4; 390 391 /* This is supported by SVE only, so opr_sz is always a multiple of 16. 392 * Process the entire segment all at once, writing back the results 393 * only after we've consumed all of the inputs. 394 */ 395 for (i = 0; i < opr_sz_8 ; i += 2) { 396 uint64_t d0, d1; 397 398 d0 = n[i * 4 + 0] * (uint64_t)m_indexed[i * 4 + 0]; 399 d0 += n[i * 4 + 1] * (uint64_t)m_indexed[i * 4 + 1]; 400 d0 += n[i * 4 + 2] * (uint64_t)m_indexed[i * 4 + 2]; 401 d0 += n[i * 4 + 3] * (uint64_t)m_indexed[i * 4 + 3]; 402 d1 = n[i * 4 + 4] * (uint64_t)m_indexed[i * 4 + 0]; 403 d1 += n[i * 4 + 5] * (uint64_t)m_indexed[i * 4 + 1]; 404 d1 += n[i * 4 + 6] * (uint64_t)m_indexed[i * 4 + 2]; 405 d1 += n[i * 4 + 7] * (uint64_t)m_indexed[i * 4 + 3]; 406 407 d[i + 0] += d0; 408 d[i + 1] += d1; 409 } 410 411 clear_tail(d, opr_sz, simd_maxsz(desc)); 412 } 413 414 void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, 415 void *vfpst, uint32_t desc) 416 { 417 uintptr_t opr_sz = simd_oprsz(desc); 418 float16 *d = vd; 419 float16 *n = vn; 420 float16 *m = vm; 421 float_status *fpst = vfpst; 422 uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); 423 uint32_t neg_imag = neg_real ^ 1; 424 uintptr_t i; 425 426 /* Shift boolean to the sign bit so we can xor to negate. */ 427 neg_real <<= 15; 428 neg_imag <<= 15; 429 430 for (i = 0; i < opr_sz / 2; i += 2) { 431 float16 e0 = n[H2(i)]; 432 float16 e1 = m[H2(i + 1)] ^ neg_imag; 433 float16 e2 = n[H2(i + 1)]; 434 float16 e3 = m[H2(i)] ^ neg_real; 435 436 d[H2(i)] = float16_add(e0, e1, fpst); 437 d[H2(i + 1)] = float16_add(e2, e3, fpst); 438 } 439 clear_tail(d, opr_sz, simd_maxsz(desc)); 440 } 441 442 void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, 443 void *vfpst, uint32_t desc) 444 { 445 uintptr_t opr_sz = simd_oprsz(desc); 446 float32 *d = vd; 447 float32 *n = vn; 448 float32 *m = vm; 449 float_status *fpst = vfpst; 450 uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); 451 uint32_t neg_imag = neg_real ^ 1; 452 uintptr_t i; 453 454 /* Shift boolean to the sign bit so we can xor to negate. */ 455 neg_real <<= 31; 456 neg_imag <<= 31; 457 458 for (i = 0; i < opr_sz / 4; i += 2) { 459 float32 e0 = n[H4(i)]; 460 float32 e1 = m[H4(i + 1)] ^ neg_imag; 461 float32 e2 = n[H4(i + 1)]; 462 float32 e3 = m[H4(i)] ^ neg_real; 463 464 d[H4(i)] = float32_add(e0, e1, fpst); 465 d[H4(i + 1)] = float32_add(e2, e3, fpst); 466 } 467 clear_tail(d, opr_sz, simd_maxsz(desc)); 468 } 469 470 void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, 471 void *vfpst, uint32_t desc) 472 { 473 uintptr_t opr_sz = simd_oprsz(desc); 474 float64 *d = vd; 475 float64 *n = vn; 476 float64 *m = vm; 477 float_status *fpst = vfpst; 478 uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1); 479 uint64_t neg_imag = neg_real ^ 1; 480 uintptr_t i; 481 482 /* Shift boolean to the sign bit so we can xor to negate. */ 483 neg_real <<= 63; 484 neg_imag <<= 63; 485 486 for (i = 0; i < opr_sz / 8; i += 2) { 487 float64 e0 = n[i]; 488 float64 e1 = m[i + 1] ^ neg_imag; 489 float64 e2 = n[i + 1]; 490 float64 e3 = m[i] ^ neg_real; 491 492 d[i] = float64_add(e0, e1, fpst); 493 d[i + 1] = float64_add(e2, e3, fpst); 494 } 495 clear_tail(d, opr_sz, simd_maxsz(desc)); 496 } 497 498 void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, 499 void *vfpst, uint32_t desc) 500 { 501 uintptr_t opr_sz = simd_oprsz(desc); 502 float16 *d = vd; 503 float16 *n = vn; 504 float16 *m = vm; 505 float_status *fpst = vfpst; 506 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); 507 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 508 uint32_t neg_real = flip ^ neg_imag; 509 uintptr_t i; 510 511 /* Shift boolean to the sign bit so we can xor to negate. */ 512 neg_real <<= 15; 513 neg_imag <<= 15; 514 515 for (i = 0; i < opr_sz / 2; i += 2) { 516 float16 e2 = n[H2(i + flip)]; 517 float16 e1 = m[H2(i + flip)] ^ neg_real; 518 float16 e4 = e2; 519 float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag; 520 521 d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst); 522 d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst); 523 } 524 clear_tail(d, opr_sz, simd_maxsz(desc)); 525 } 526 527 void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, 528 void *vfpst, uint32_t desc) 529 { 530 uintptr_t opr_sz = simd_oprsz(desc); 531 float16 *d = vd; 532 float16 *n = vn; 533 float16 *m = vm; 534 float_status *fpst = vfpst; 535 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); 536 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 537 intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2); 538 uint32_t neg_real = flip ^ neg_imag; 539 intptr_t elements = opr_sz / sizeof(float16); 540 intptr_t eltspersegment = 16 / sizeof(float16); 541 intptr_t i, j; 542 543 /* Shift boolean to the sign bit so we can xor to negate. */ 544 neg_real <<= 15; 545 neg_imag <<= 15; 546 547 for (i = 0; i < elements; i += eltspersegment) { 548 float16 mr = m[H2(i + 2 * index + 0)]; 549 float16 mi = m[H2(i + 2 * index + 1)]; 550 float16 e1 = neg_real ^ (flip ? mi : mr); 551 float16 e3 = neg_imag ^ (flip ? mr : mi); 552 553 for (j = i; j < i + eltspersegment; j += 2) { 554 float16 e2 = n[H2(j + flip)]; 555 float16 e4 = e2; 556 557 d[H2(j)] = float16_muladd(e2, e1, d[H2(j)], 0, fpst); 558 d[H2(j + 1)] = float16_muladd(e4, e3, d[H2(j + 1)], 0, fpst); 559 } 560 } 561 clear_tail(d, opr_sz, simd_maxsz(desc)); 562 } 563 564 void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, 565 void *vfpst, uint32_t desc) 566 { 567 uintptr_t opr_sz = simd_oprsz(desc); 568 float32 *d = vd; 569 float32 *n = vn; 570 float32 *m = vm; 571 float_status *fpst = vfpst; 572 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); 573 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 574 uint32_t neg_real = flip ^ neg_imag; 575 uintptr_t i; 576 577 /* Shift boolean to the sign bit so we can xor to negate. */ 578 neg_real <<= 31; 579 neg_imag <<= 31; 580 581 for (i = 0; i < opr_sz / 4; i += 2) { 582 float32 e2 = n[H4(i + flip)]; 583 float32 e1 = m[H4(i + flip)] ^ neg_real; 584 float32 e4 = e2; 585 float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag; 586 587 d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); 588 d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); 589 } 590 clear_tail(d, opr_sz, simd_maxsz(desc)); 591 } 592 593 void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, 594 void *vfpst, uint32_t desc) 595 { 596 uintptr_t opr_sz = simd_oprsz(desc); 597 float32 *d = vd; 598 float32 *n = vn; 599 float32 *m = vm; 600 float_status *fpst = vfpst; 601 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); 602 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 603 intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2); 604 uint32_t neg_real = flip ^ neg_imag; 605 intptr_t elements = opr_sz / sizeof(float32); 606 intptr_t eltspersegment = 16 / sizeof(float32); 607 intptr_t i, j; 608 609 /* Shift boolean to the sign bit so we can xor to negate. */ 610 neg_real <<= 31; 611 neg_imag <<= 31; 612 613 for (i = 0; i < elements; i += eltspersegment) { 614 float32 mr = m[H4(i + 2 * index + 0)]; 615 float32 mi = m[H4(i + 2 * index + 1)]; 616 float32 e1 = neg_real ^ (flip ? mi : mr); 617 float32 e3 = neg_imag ^ (flip ? mr : mi); 618 619 for (j = i; j < i + eltspersegment; j += 2) { 620 float32 e2 = n[H4(j + flip)]; 621 float32 e4 = e2; 622 623 d[H4(j)] = float32_muladd(e2, e1, d[H4(j)], 0, fpst); 624 d[H4(j + 1)] = float32_muladd(e4, e3, d[H4(j + 1)], 0, fpst); 625 } 626 } 627 clear_tail(d, opr_sz, simd_maxsz(desc)); 628 } 629 630 void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, 631 void *vfpst, uint32_t desc) 632 { 633 uintptr_t opr_sz = simd_oprsz(desc); 634 float64 *d = vd; 635 float64 *n = vn; 636 float64 *m = vm; 637 float_status *fpst = vfpst; 638 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); 639 uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 640 uint64_t neg_real = flip ^ neg_imag; 641 uintptr_t i; 642 643 /* Shift boolean to the sign bit so we can xor to negate. */ 644 neg_real <<= 63; 645 neg_imag <<= 63; 646 647 for (i = 0; i < opr_sz / 8; i += 2) { 648 float64 e2 = n[i + flip]; 649 float64 e1 = m[i + flip] ^ neg_real; 650 float64 e4 = e2; 651 float64 e3 = m[i + 1 - flip] ^ neg_imag; 652 653 d[i] = float64_muladd(e2, e1, d[i], 0, fpst); 654 d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst); 655 } 656 clear_tail(d, opr_sz, simd_maxsz(desc)); 657 } 658 659 /* 660 * Floating point comparisons producing an integer result (all 1s or all 0s). 661 * Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do. 662 * Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires. 663 */ 664 static uint16_t float16_ceq(float16 op1, float16 op2, float_status *stat) 665 { 666 return -float16_eq_quiet(op1, op2, stat); 667 } 668 669 static uint32_t float32_ceq(float32 op1, float32 op2, float_status *stat) 670 { 671 return -float32_eq_quiet(op1, op2, stat); 672 } 673 674 static uint16_t float16_cge(float16 op1, float16 op2, float_status *stat) 675 { 676 return -float16_le(op2, op1, stat); 677 } 678 679 static uint32_t float32_cge(float32 op1, float32 op2, float_status *stat) 680 { 681 return -float32_le(op2, op1, stat); 682 } 683 684 static uint16_t float16_cgt(float16 op1, float16 op2, float_status *stat) 685 { 686 return -float16_lt(op2, op1, stat); 687 } 688 689 static uint32_t float32_cgt(float32 op1, float32 op2, float_status *stat) 690 { 691 return -float32_lt(op2, op1, stat); 692 } 693 694 static uint16_t float16_acge(float16 op1, float16 op2, float_status *stat) 695 { 696 return -float16_le(float16_abs(op2), float16_abs(op1), stat); 697 } 698 699 static uint32_t float32_acge(float32 op1, float32 op2, float_status *stat) 700 { 701 return -float32_le(float32_abs(op2), float32_abs(op1), stat); 702 } 703 704 static uint16_t float16_acgt(float16 op1, float16 op2, float_status *stat) 705 { 706 return -float16_lt(float16_abs(op2), float16_abs(op1), stat); 707 } 708 709 static uint32_t float32_acgt(float32 op1, float32 op2, float_status *stat) 710 { 711 return -float32_lt(float32_abs(op2), float32_abs(op1), stat); 712 } 713 714 #define DO_2OP(NAME, FUNC, TYPE) \ 715 void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \ 716 { \ 717 intptr_t i, oprsz = simd_oprsz(desc); \ 718 TYPE *d = vd, *n = vn; \ 719 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 720 d[i] = FUNC(n[i], stat); \ 721 } \ 722 clear_tail(d, oprsz, simd_maxsz(desc)); \ 723 } 724 725 DO_2OP(gvec_frecpe_h, helper_recpe_f16, float16) 726 DO_2OP(gvec_frecpe_s, helper_recpe_f32, float32) 727 DO_2OP(gvec_frecpe_d, helper_recpe_f64, float64) 728 729 DO_2OP(gvec_frsqrte_h, helper_rsqrte_f16, float16) 730 DO_2OP(gvec_frsqrte_s, helper_rsqrte_f32, float32) 731 DO_2OP(gvec_frsqrte_d, helper_rsqrte_f64, float64) 732 733 #define WRAP_CMP0_FWD(FN, CMPOP, TYPE) \ 734 static TYPE TYPE##_##FN##0(TYPE op, float_status *stat) \ 735 { \ 736 return TYPE##_##CMPOP(op, TYPE##_zero, stat); \ 737 } 738 739 #define WRAP_CMP0_REV(FN, CMPOP, TYPE) \ 740 static TYPE TYPE##_##FN##0(TYPE op, float_status *stat) \ 741 { \ 742 return TYPE##_##CMPOP(TYPE##_zero, op, stat); \ 743 } 744 745 #define DO_2OP_CMP0(FN, CMPOP, DIRN) \ 746 WRAP_CMP0_##DIRN(FN, CMPOP, float16) \ 747 WRAP_CMP0_##DIRN(FN, CMPOP, float32) \ 748 DO_2OP(gvec_f##FN##0_h, float16_##FN##0, float16) \ 749 DO_2OP(gvec_f##FN##0_s, float32_##FN##0, float32) 750 751 DO_2OP_CMP0(cgt, cgt, FWD) 752 DO_2OP_CMP0(cge, cge, FWD) 753 DO_2OP_CMP0(ceq, ceq, FWD) 754 DO_2OP_CMP0(clt, cgt, REV) 755 DO_2OP_CMP0(cle, cge, REV) 756 757 #undef DO_2OP 758 #undef DO_2OP_CMP0 759 760 /* Floating-point trigonometric starting value. 761 * See the ARM ARM pseudocode function FPTrigSMul. 762 */ 763 static float16 float16_ftsmul(float16 op1, uint16_t op2, float_status *stat) 764 { 765 float16 result = float16_mul(op1, op1, stat); 766 if (!float16_is_any_nan(result)) { 767 result = float16_set_sign(result, op2 & 1); 768 } 769 return result; 770 } 771 772 static float32 float32_ftsmul(float32 op1, uint32_t op2, float_status *stat) 773 { 774 float32 result = float32_mul(op1, op1, stat); 775 if (!float32_is_any_nan(result)) { 776 result = float32_set_sign(result, op2 & 1); 777 } 778 return result; 779 } 780 781 static float64 float64_ftsmul(float64 op1, uint64_t op2, float_status *stat) 782 { 783 float64 result = float64_mul(op1, op1, stat); 784 if (!float64_is_any_nan(result)) { 785 result = float64_set_sign(result, op2 & 1); 786 } 787 return result; 788 } 789 790 static float16 float16_abd(float16 op1, float16 op2, float_status *stat) 791 { 792 return float16_abs(float16_sub(op1, op2, stat)); 793 } 794 795 static float32 float32_abd(float32 op1, float32 op2, float_status *stat) 796 { 797 return float32_abs(float32_sub(op1, op2, stat)); 798 } 799 800 /* 801 * Reciprocal step. These are the AArch32 version which uses a 802 * non-fused multiply-and-subtract. 803 */ 804 static float16 float16_recps_nf(float16 op1, float16 op2, float_status *stat) 805 { 806 op1 = float16_squash_input_denormal(op1, stat); 807 op2 = float16_squash_input_denormal(op2, stat); 808 809 if ((float16_is_infinity(op1) && float16_is_zero(op2)) || 810 (float16_is_infinity(op2) && float16_is_zero(op1))) { 811 return float16_two; 812 } 813 return float16_sub(float16_two, float16_mul(op1, op2, stat), stat); 814 } 815 816 static float32 float32_recps_nf(float32 op1, float32 op2, float_status *stat) 817 { 818 op1 = float32_squash_input_denormal(op1, stat); 819 op2 = float32_squash_input_denormal(op2, stat); 820 821 if ((float32_is_infinity(op1) && float32_is_zero(op2)) || 822 (float32_is_infinity(op2) && float32_is_zero(op1))) { 823 return float32_two; 824 } 825 return float32_sub(float32_two, float32_mul(op1, op2, stat), stat); 826 } 827 828 #define DO_3OP(NAME, FUNC, TYPE) \ 829 void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ 830 { \ 831 intptr_t i, oprsz = simd_oprsz(desc); \ 832 TYPE *d = vd, *n = vn, *m = vm; \ 833 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 834 d[i] = FUNC(n[i], m[i], stat); \ 835 } \ 836 clear_tail(d, oprsz, simd_maxsz(desc)); \ 837 } 838 839 DO_3OP(gvec_fadd_h, float16_add, float16) 840 DO_3OP(gvec_fadd_s, float32_add, float32) 841 DO_3OP(gvec_fadd_d, float64_add, float64) 842 843 DO_3OP(gvec_fsub_h, float16_sub, float16) 844 DO_3OP(gvec_fsub_s, float32_sub, float32) 845 DO_3OP(gvec_fsub_d, float64_sub, float64) 846 847 DO_3OP(gvec_fmul_h, float16_mul, float16) 848 DO_3OP(gvec_fmul_s, float32_mul, float32) 849 DO_3OP(gvec_fmul_d, float64_mul, float64) 850 851 DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16) 852 DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32) 853 DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64) 854 855 DO_3OP(gvec_fabd_h, float16_abd, float16) 856 DO_3OP(gvec_fabd_s, float32_abd, float32) 857 858 DO_3OP(gvec_fceq_h, float16_ceq, float16) 859 DO_3OP(gvec_fceq_s, float32_ceq, float32) 860 861 DO_3OP(gvec_fcge_h, float16_cge, float16) 862 DO_3OP(gvec_fcge_s, float32_cge, float32) 863 864 DO_3OP(gvec_fcgt_h, float16_cgt, float16) 865 DO_3OP(gvec_fcgt_s, float32_cgt, float32) 866 867 DO_3OP(gvec_facge_h, float16_acge, float16) 868 DO_3OP(gvec_facge_s, float32_acge, float32) 869 870 DO_3OP(gvec_facgt_h, float16_acgt, float16) 871 DO_3OP(gvec_facgt_s, float32_acgt, float32) 872 873 DO_3OP(gvec_fmax_h, float16_max, float16) 874 DO_3OP(gvec_fmax_s, float32_max, float32) 875 876 DO_3OP(gvec_fmin_h, float16_min, float16) 877 DO_3OP(gvec_fmin_s, float32_min, float32) 878 879 DO_3OP(gvec_fmaxnum_h, float16_maxnum, float16) 880 DO_3OP(gvec_fmaxnum_s, float32_maxnum, float32) 881 882 DO_3OP(gvec_fminnum_h, float16_minnum, float16) 883 DO_3OP(gvec_fminnum_s, float32_minnum, float32) 884 885 DO_3OP(gvec_recps_nf_h, float16_recps_nf, float16) 886 DO_3OP(gvec_recps_nf_s, float32_recps_nf, float32) 887 888 #ifdef TARGET_AARCH64 889 890 DO_3OP(gvec_recps_h, helper_recpsf_f16, float16) 891 DO_3OP(gvec_recps_s, helper_recpsf_f32, float32) 892 DO_3OP(gvec_recps_d, helper_recpsf_f64, float64) 893 894 DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16) 895 DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32) 896 DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64) 897 898 #endif 899 #undef DO_3OP 900 901 /* Non-fused multiply-add (unlike float16_muladd etc, which are fused) */ 902 static float16 float16_muladd_nf(float16 dest, float16 op1, float16 op2, 903 float_status *stat) 904 { 905 return float16_add(dest, float16_mul(op1, op2, stat), stat); 906 } 907 908 static float32 float32_muladd_nf(float32 dest, float32 op1, float32 op2, 909 float_status *stat) 910 { 911 return float32_add(dest, float32_mul(op1, op2, stat), stat); 912 } 913 914 static float16 float16_mulsub_nf(float16 dest, float16 op1, float16 op2, 915 float_status *stat) 916 { 917 return float16_sub(dest, float16_mul(op1, op2, stat), stat); 918 } 919 920 static float32 float32_mulsub_nf(float32 dest, float32 op1, float32 op2, 921 float_status *stat) 922 { 923 return float32_sub(dest, float32_mul(op1, op2, stat), stat); 924 } 925 926 /* Fused versions; these have the semantics Neon VFMA/VFMS want */ 927 static float16 float16_muladd_f(float16 dest, float16 op1, float16 op2, 928 float_status *stat) 929 { 930 return float16_muladd(op1, op2, dest, 0, stat); 931 } 932 933 static float32 float32_muladd_f(float32 dest, float32 op1, float32 op2, 934 float_status *stat) 935 { 936 return float32_muladd(op1, op2, dest, 0, stat); 937 } 938 939 static float16 float16_mulsub_f(float16 dest, float16 op1, float16 op2, 940 float_status *stat) 941 { 942 return float16_muladd(float16_chs(op1), op2, dest, 0, stat); 943 } 944 945 static float32 float32_mulsub_f(float32 dest, float32 op1, float32 op2, 946 float_status *stat) 947 { 948 return float32_muladd(float32_chs(op1), op2, dest, 0, stat); 949 } 950 951 #define DO_MULADD(NAME, FUNC, TYPE) \ 952 void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ 953 { \ 954 intptr_t i, oprsz = simd_oprsz(desc); \ 955 TYPE *d = vd, *n = vn, *m = vm; \ 956 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 957 d[i] = FUNC(d[i], n[i], m[i], stat); \ 958 } \ 959 clear_tail(d, oprsz, simd_maxsz(desc)); \ 960 } 961 962 DO_MULADD(gvec_fmla_h, float16_muladd_nf, float16) 963 DO_MULADD(gvec_fmla_s, float32_muladd_nf, float32) 964 965 DO_MULADD(gvec_fmls_h, float16_mulsub_nf, float16) 966 DO_MULADD(gvec_fmls_s, float32_mulsub_nf, float32) 967 968 DO_MULADD(gvec_vfma_h, float16_muladd_f, float16) 969 DO_MULADD(gvec_vfma_s, float32_muladd_f, float32) 970 971 DO_MULADD(gvec_vfms_h, float16_mulsub_f, float16) 972 DO_MULADD(gvec_vfms_s, float32_mulsub_f, float32) 973 974 /* For the indexed ops, SVE applies the index per 128-bit vector segment. 975 * For AdvSIMD, there is of course only one such vector segment. 976 */ 977 978 #define DO_MUL_IDX(NAME, TYPE, H) \ 979 void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ 980 { \ 981 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \ 982 intptr_t idx = simd_data(desc); \ 983 TYPE *d = vd, *n = vn, *m = vm; \ 984 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \ 985 TYPE mm = m[H(i + idx)]; \ 986 for (j = 0; j < segment; j++) { \ 987 d[i + j] = n[i + j] * mm; \ 988 } \ 989 } \ 990 clear_tail(d, oprsz, simd_maxsz(desc)); \ 991 } 992 993 DO_MUL_IDX(gvec_mul_idx_h, uint16_t, H2) 994 DO_MUL_IDX(gvec_mul_idx_s, uint32_t, H4) 995 DO_MUL_IDX(gvec_mul_idx_d, uint64_t, ) 996 997 #undef DO_MUL_IDX 998 999 #define DO_MLA_IDX(NAME, TYPE, OP, H) \ 1000 void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \ 1001 { \ 1002 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \ 1003 intptr_t idx = simd_data(desc); \ 1004 TYPE *d = vd, *n = vn, *m = vm, *a = va; \ 1005 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \ 1006 TYPE mm = m[H(i + idx)]; \ 1007 for (j = 0; j < segment; j++) { \ 1008 d[i + j] = a[i + j] OP n[i + j] * mm; \ 1009 } \ 1010 } \ 1011 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1012 } 1013 1014 DO_MLA_IDX(gvec_mla_idx_h, uint16_t, +, H2) 1015 DO_MLA_IDX(gvec_mla_idx_s, uint32_t, +, H4) 1016 DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +, ) 1017 1018 DO_MLA_IDX(gvec_mls_idx_h, uint16_t, -, H2) 1019 DO_MLA_IDX(gvec_mls_idx_s, uint32_t, -, H4) 1020 DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, ) 1021 1022 #undef DO_MLA_IDX 1023 1024 #define DO_FMUL_IDX(NAME, TYPE, H) \ 1025 void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ 1026 { \ 1027 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \ 1028 intptr_t idx = simd_data(desc); \ 1029 TYPE *d = vd, *n = vn, *m = vm; \ 1030 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \ 1031 TYPE mm = m[H(i + idx)]; \ 1032 for (j = 0; j < segment; j++) { \ 1033 d[i + j] = TYPE##_mul(n[i + j], mm, stat); \ 1034 } \ 1035 } \ 1036 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1037 } 1038 1039 DO_FMUL_IDX(gvec_fmul_idx_h, float16, H2) 1040 DO_FMUL_IDX(gvec_fmul_idx_s, float32, H4) 1041 DO_FMUL_IDX(gvec_fmul_idx_d, float64, ) 1042 1043 #undef DO_FMUL_IDX 1044 1045 #define DO_FMLA_IDX(NAME, TYPE, H) \ 1046 void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \ 1047 void *stat, uint32_t desc) \ 1048 { \ 1049 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \ 1050 TYPE op1_neg = extract32(desc, SIMD_DATA_SHIFT, 1); \ 1051 intptr_t idx = desc >> (SIMD_DATA_SHIFT + 1); \ 1052 TYPE *d = vd, *n = vn, *m = vm, *a = va; \ 1053 op1_neg <<= (8 * sizeof(TYPE) - 1); \ 1054 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \ 1055 TYPE mm = m[H(i + idx)]; \ 1056 for (j = 0; j < segment; j++) { \ 1057 d[i + j] = TYPE##_muladd(n[i + j] ^ op1_neg, \ 1058 mm, a[i + j], 0, stat); \ 1059 } \ 1060 } \ 1061 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1062 } 1063 1064 DO_FMLA_IDX(gvec_fmla_idx_h, float16, H2) 1065 DO_FMLA_IDX(gvec_fmla_idx_s, float32, H4) 1066 DO_FMLA_IDX(gvec_fmla_idx_d, float64, ) 1067 1068 #undef DO_FMLA_IDX 1069 1070 #define DO_SAT(NAME, WTYPE, TYPEN, TYPEM, OP, MIN, MAX) \ 1071 void HELPER(NAME)(void *vd, void *vq, void *vn, void *vm, uint32_t desc) \ 1072 { \ 1073 intptr_t i, oprsz = simd_oprsz(desc); \ 1074 TYPEN *d = vd, *n = vn; TYPEM *m = vm; \ 1075 bool q = false; \ 1076 for (i = 0; i < oprsz / sizeof(TYPEN); i++) { \ 1077 WTYPE dd = (WTYPE)n[i] OP m[i]; \ 1078 if (dd < MIN) { \ 1079 dd = MIN; \ 1080 q = true; \ 1081 } else if (dd > MAX) { \ 1082 dd = MAX; \ 1083 q = true; \ 1084 } \ 1085 d[i] = dd; \ 1086 } \ 1087 if (q) { \ 1088 uint32_t *qc = vq; \ 1089 qc[0] = 1; \ 1090 } \ 1091 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1092 } 1093 1094 DO_SAT(gvec_uqadd_b, int, uint8_t, uint8_t, +, 0, UINT8_MAX) 1095 DO_SAT(gvec_uqadd_h, int, uint16_t, uint16_t, +, 0, UINT16_MAX) 1096 DO_SAT(gvec_uqadd_s, int64_t, uint32_t, uint32_t, +, 0, UINT32_MAX) 1097 1098 DO_SAT(gvec_sqadd_b, int, int8_t, int8_t, +, INT8_MIN, INT8_MAX) 1099 DO_SAT(gvec_sqadd_h, int, int16_t, int16_t, +, INT16_MIN, INT16_MAX) 1100 DO_SAT(gvec_sqadd_s, int64_t, int32_t, int32_t, +, INT32_MIN, INT32_MAX) 1101 1102 DO_SAT(gvec_uqsub_b, int, uint8_t, uint8_t, -, 0, UINT8_MAX) 1103 DO_SAT(gvec_uqsub_h, int, uint16_t, uint16_t, -, 0, UINT16_MAX) 1104 DO_SAT(gvec_uqsub_s, int64_t, uint32_t, uint32_t, -, 0, UINT32_MAX) 1105 1106 DO_SAT(gvec_sqsub_b, int, int8_t, int8_t, -, INT8_MIN, INT8_MAX) 1107 DO_SAT(gvec_sqsub_h, int, int16_t, int16_t, -, INT16_MIN, INT16_MAX) 1108 DO_SAT(gvec_sqsub_s, int64_t, int32_t, int32_t, -, INT32_MIN, INT32_MAX) 1109 1110 #undef DO_SAT 1111 1112 void HELPER(gvec_uqadd_d)(void *vd, void *vq, void *vn, 1113 void *vm, uint32_t desc) 1114 { 1115 intptr_t i, oprsz = simd_oprsz(desc); 1116 uint64_t *d = vd, *n = vn, *m = vm; 1117 bool q = false; 1118 1119 for (i = 0; i < oprsz / 8; i++) { 1120 uint64_t nn = n[i], mm = m[i], dd = nn + mm; 1121 if (dd < nn) { 1122 dd = UINT64_MAX; 1123 q = true; 1124 } 1125 d[i] = dd; 1126 } 1127 if (q) { 1128 uint32_t *qc = vq; 1129 qc[0] = 1; 1130 } 1131 clear_tail(d, oprsz, simd_maxsz(desc)); 1132 } 1133 1134 void HELPER(gvec_uqsub_d)(void *vd, void *vq, void *vn, 1135 void *vm, uint32_t desc) 1136 { 1137 intptr_t i, oprsz = simd_oprsz(desc); 1138 uint64_t *d = vd, *n = vn, *m = vm; 1139 bool q = false; 1140 1141 for (i = 0; i < oprsz / 8; i++) { 1142 uint64_t nn = n[i], mm = m[i], dd = nn - mm; 1143 if (nn < mm) { 1144 dd = 0; 1145 q = true; 1146 } 1147 d[i] = dd; 1148 } 1149 if (q) { 1150 uint32_t *qc = vq; 1151 qc[0] = 1; 1152 } 1153 clear_tail(d, oprsz, simd_maxsz(desc)); 1154 } 1155 1156 void HELPER(gvec_sqadd_d)(void *vd, void *vq, void *vn, 1157 void *vm, uint32_t desc) 1158 { 1159 intptr_t i, oprsz = simd_oprsz(desc); 1160 int64_t *d = vd, *n = vn, *m = vm; 1161 bool q = false; 1162 1163 for (i = 0; i < oprsz / 8; i++) { 1164 int64_t nn = n[i], mm = m[i], dd = nn + mm; 1165 if (((dd ^ nn) & ~(nn ^ mm)) & INT64_MIN) { 1166 dd = (nn >> 63) ^ ~INT64_MIN; 1167 q = true; 1168 } 1169 d[i] = dd; 1170 } 1171 if (q) { 1172 uint32_t *qc = vq; 1173 qc[0] = 1; 1174 } 1175 clear_tail(d, oprsz, simd_maxsz(desc)); 1176 } 1177 1178 void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn, 1179 void *vm, uint32_t desc) 1180 { 1181 intptr_t i, oprsz = simd_oprsz(desc); 1182 int64_t *d = vd, *n = vn, *m = vm; 1183 bool q = false; 1184 1185 for (i = 0; i < oprsz / 8; i++) { 1186 int64_t nn = n[i], mm = m[i], dd = nn - mm; 1187 if (((dd ^ nn) & (nn ^ mm)) & INT64_MIN) { 1188 dd = (nn >> 63) ^ ~INT64_MIN; 1189 q = true; 1190 } 1191 d[i] = dd; 1192 } 1193 if (q) { 1194 uint32_t *qc = vq; 1195 qc[0] = 1; 1196 } 1197 clear_tail(d, oprsz, simd_maxsz(desc)); 1198 } 1199 1200 1201 #define DO_SRA(NAME, TYPE) \ 1202 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1203 { \ 1204 intptr_t i, oprsz = simd_oprsz(desc); \ 1205 int shift = simd_data(desc); \ 1206 TYPE *d = vd, *n = vn; \ 1207 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 1208 d[i] += n[i] >> shift; \ 1209 } \ 1210 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1211 } 1212 1213 DO_SRA(gvec_ssra_b, int8_t) 1214 DO_SRA(gvec_ssra_h, int16_t) 1215 DO_SRA(gvec_ssra_s, int32_t) 1216 DO_SRA(gvec_ssra_d, int64_t) 1217 1218 DO_SRA(gvec_usra_b, uint8_t) 1219 DO_SRA(gvec_usra_h, uint16_t) 1220 DO_SRA(gvec_usra_s, uint32_t) 1221 DO_SRA(gvec_usra_d, uint64_t) 1222 1223 #undef DO_SRA 1224 1225 #define DO_RSHR(NAME, TYPE) \ 1226 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1227 { \ 1228 intptr_t i, oprsz = simd_oprsz(desc); \ 1229 int shift = simd_data(desc); \ 1230 TYPE *d = vd, *n = vn; \ 1231 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 1232 TYPE tmp = n[i] >> (shift - 1); \ 1233 d[i] = (tmp >> 1) + (tmp & 1); \ 1234 } \ 1235 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1236 } 1237 1238 DO_RSHR(gvec_srshr_b, int8_t) 1239 DO_RSHR(gvec_srshr_h, int16_t) 1240 DO_RSHR(gvec_srshr_s, int32_t) 1241 DO_RSHR(gvec_srshr_d, int64_t) 1242 1243 DO_RSHR(gvec_urshr_b, uint8_t) 1244 DO_RSHR(gvec_urshr_h, uint16_t) 1245 DO_RSHR(gvec_urshr_s, uint32_t) 1246 DO_RSHR(gvec_urshr_d, uint64_t) 1247 1248 #undef DO_RSHR 1249 1250 #define DO_RSRA(NAME, TYPE) \ 1251 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1252 { \ 1253 intptr_t i, oprsz = simd_oprsz(desc); \ 1254 int shift = simd_data(desc); \ 1255 TYPE *d = vd, *n = vn; \ 1256 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 1257 TYPE tmp = n[i] >> (shift - 1); \ 1258 d[i] += (tmp >> 1) + (tmp & 1); \ 1259 } \ 1260 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1261 } 1262 1263 DO_RSRA(gvec_srsra_b, int8_t) 1264 DO_RSRA(gvec_srsra_h, int16_t) 1265 DO_RSRA(gvec_srsra_s, int32_t) 1266 DO_RSRA(gvec_srsra_d, int64_t) 1267 1268 DO_RSRA(gvec_ursra_b, uint8_t) 1269 DO_RSRA(gvec_ursra_h, uint16_t) 1270 DO_RSRA(gvec_ursra_s, uint32_t) 1271 DO_RSRA(gvec_ursra_d, uint64_t) 1272 1273 #undef DO_RSRA 1274 1275 #define DO_SRI(NAME, TYPE) \ 1276 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1277 { \ 1278 intptr_t i, oprsz = simd_oprsz(desc); \ 1279 int shift = simd_data(desc); \ 1280 TYPE *d = vd, *n = vn; \ 1281 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 1282 d[i] = deposit64(d[i], 0, sizeof(TYPE) * 8 - shift, n[i] >> shift); \ 1283 } \ 1284 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1285 } 1286 1287 DO_SRI(gvec_sri_b, uint8_t) 1288 DO_SRI(gvec_sri_h, uint16_t) 1289 DO_SRI(gvec_sri_s, uint32_t) 1290 DO_SRI(gvec_sri_d, uint64_t) 1291 1292 #undef DO_SRI 1293 1294 #define DO_SLI(NAME, TYPE) \ 1295 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1296 { \ 1297 intptr_t i, oprsz = simd_oprsz(desc); \ 1298 int shift = simd_data(desc); \ 1299 TYPE *d = vd, *n = vn; \ 1300 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ 1301 d[i] = deposit64(d[i], shift, sizeof(TYPE) * 8 - shift, n[i]); \ 1302 } \ 1303 clear_tail(d, oprsz, simd_maxsz(desc)); \ 1304 } 1305 1306 DO_SLI(gvec_sli_b, uint8_t) 1307 DO_SLI(gvec_sli_h, uint16_t) 1308 DO_SLI(gvec_sli_s, uint32_t) 1309 DO_SLI(gvec_sli_d, uint64_t) 1310 1311 #undef DO_SLI 1312 1313 /* 1314 * Convert float16 to float32, raising no exceptions and 1315 * preserving exceptional values, including SNaN. 1316 * This is effectively an unpack+repack operation. 1317 */ 1318 static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16) 1319 { 1320 const int f16_bias = 15; 1321 const int f32_bias = 127; 1322 uint32_t sign = extract32(f16, 15, 1); 1323 uint32_t exp = extract32(f16, 10, 5); 1324 uint32_t frac = extract32(f16, 0, 10); 1325 1326 if (exp == 0x1f) { 1327 /* Inf or NaN */ 1328 exp = 0xff; 1329 } else if (exp == 0) { 1330 /* Zero or denormal. */ 1331 if (frac != 0) { 1332 if (fz16) { 1333 frac = 0; 1334 } else { 1335 /* 1336 * Denormal; these are all normal float32. 1337 * Shift the fraction so that the msb is at bit 11, 1338 * then remove bit 11 as the implicit bit of the 1339 * normalized float32. Note that we still go through 1340 * the shift for normal numbers below, to put the 1341 * float32 fraction at the right place. 1342 */ 1343 int shift = clz32(frac) - 21; 1344 frac = (frac << shift) & 0x3ff; 1345 exp = f32_bias - f16_bias - shift + 1; 1346 } 1347 } 1348 } else { 1349 /* Normal number; adjust the bias. */ 1350 exp += f32_bias - f16_bias; 1351 } 1352 sign <<= 31; 1353 exp <<= 23; 1354 frac <<= 23 - 10; 1355 1356 return sign | exp | frac; 1357 } 1358 1359 static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2) 1360 { 1361 /* 1362 * Branchless load of u32[0], u64[0], u32[1], or u64[1]. 1363 * Load the 2nd qword iff is_q & is_2. 1364 * Shift to the 2nd dword iff !is_q & is_2. 1365 * For !is_q & !is_2, the upper bits of the result are garbage. 1366 */ 1367 return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5); 1368 } 1369 1370 /* 1371 * Note that FMLAL requires oprsz == 8 or oprsz == 16, 1372 * as there is not yet SVE versions that might use blocking. 1373 */ 1374 1375 static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst, 1376 uint32_t desc, bool fz16) 1377 { 1378 intptr_t i, oprsz = simd_oprsz(desc); 1379 int is_s = extract32(desc, SIMD_DATA_SHIFT, 1); 1380 int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 1381 int is_q = oprsz == 16; 1382 uint64_t n_4, m_4; 1383 1384 /* Pre-load all of the f16 data, avoiding overlap issues. */ 1385 n_4 = load4_f16(vn, is_q, is_2); 1386 m_4 = load4_f16(vm, is_q, is_2); 1387 1388 /* Negate all inputs for FMLSL at once. */ 1389 if (is_s) { 1390 n_4 ^= 0x8000800080008000ull; 1391 } 1392 1393 for (i = 0; i < oprsz / 4; i++) { 1394 float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16); 1395 float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16); 1396 d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst); 1397 } 1398 clear_tail(d, oprsz, simd_maxsz(desc)); 1399 } 1400 1401 void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm, 1402 void *venv, uint32_t desc) 1403 { 1404 CPUARMState *env = venv; 1405 do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc, 1406 get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); 1407 } 1408 1409 void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm, 1410 void *venv, uint32_t desc) 1411 { 1412 CPUARMState *env = venv; 1413 do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc, 1414 get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); 1415 } 1416 1417 static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst, 1418 uint32_t desc, bool fz16) 1419 { 1420 intptr_t i, oprsz = simd_oprsz(desc); 1421 int is_s = extract32(desc, SIMD_DATA_SHIFT, 1); 1422 int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1); 1423 int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3); 1424 int is_q = oprsz == 16; 1425 uint64_t n_4; 1426 float32 m_1; 1427 1428 /* Pre-load all of the f16 data, avoiding overlap issues. */ 1429 n_4 = load4_f16(vn, is_q, is_2); 1430 1431 /* Negate all inputs for FMLSL at once. */ 1432 if (is_s) { 1433 n_4 ^= 0x8000800080008000ull; 1434 } 1435 1436 m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16); 1437 1438 for (i = 0; i < oprsz / 4; i++) { 1439 float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16); 1440 d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst); 1441 } 1442 clear_tail(d, oprsz, simd_maxsz(desc)); 1443 } 1444 1445 void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm, 1446 void *venv, uint32_t desc) 1447 { 1448 CPUARMState *env = venv; 1449 do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc, 1450 get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); 1451 } 1452 1453 void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm, 1454 void *venv, uint32_t desc) 1455 { 1456 CPUARMState *env = venv; 1457 do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc, 1458 get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); 1459 } 1460 1461 void HELPER(gvec_sshl_b)(void *vd, void *vn, void *vm, uint32_t desc) 1462 { 1463 intptr_t i, opr_sz = simd_oprsz(desc); 1464 int8_t *d = vd, *n = vn, *m = vm; 1465 1466 for (i = 0; i < opr_sz; ++i) { 1467 int8_t mm = m[i]; 1468 int8_t nn = n[i]; 1469 int8_t res = 0; 1470 if (mm >= 0) { 1471 if (mm < 8) { 1472 res = nn << mm; 1473 } 1474 } else { 1475 res = nn >> (mm > -8 ? -mm : 7); 1476 } 1477 d[i] = res; 1478 } 1479 clear_tail(d, opr_sz, simd_maxsz(desc)); 1480 } 1481 1482 void HELPER(gvec_sshl_h)(void *vd, void *vn, void *vm, uint32_t desc) 1483 { 1484 intptr_t i, opr_sz = simd_oprsz(desc); 1485 int16_t *d = vd, *n = vn, *m = vm; 1486 1487 for (i = 0; i < opr_sz / 2; ++i) { 1488 int8_t mm = m[i]; /* only 8 bits of shift are significant */ 1489 int16_t nn = n[i]; 1490 int16_t res = 0; 1491 if (mm >= 0) { 1492 if (mm < 16) { 1493 res = nn << mm; 1494 } 1495 } else { 1496 res = nn >> (mm > -16 ? -mm : 15); 1497 } 1498 d[i] = res; 1499 } 1500 clear_tail(d, opr_sz, simd_maxsz(desc)); 1501 } 1502 1503 void HELPER(gvec_ushl_b)(void *vd, void *vn, void *vm, uint32_t desc) 1504 { 1505 intptr_t i, opr_sz = simd_oprsz(desc); 1506 uint8_t *d = vd, *n = vn, *m = vm; 1507 1508 for (i = 0; i < opr_sz; ++i) { 1509 int8_t mm = m[i]; 1510 uint8_t nn = n[i]; 1511 uint8_t res = 0; 1512 if (mm >= 0) { 1513 if (mm < 8) { 1514 res = nn << mm; 1515 } 1516 } else { 1517 if (mm > -8) { 1518 res = nn >> -mm; 1519 } 1520 } 1521 d[i] = res; 1522 } 1523 clear_tail(d, opr_sz, simd_maxsz(desc)); 1524 } 1525 1526 void HELPER(gvec_ushl_h)(void *vd, void *vn, void *vm, uint32_t desc) 1527 { 1528 intptr_t i, opr_sz = simd_oprsz(desc); 1529 uint16_t *d = vd, *n = vn, *m = vm; 1530 1531 for (i = 0; i < opr_sz / 2; ++i) { 1532 int8_t mm = m[i]; /* only 8 bits of shift are significant */ 1533 uint16_t nn = n[i]; 1534 uint16_t res = 0; 1535 if (mm >= 0) { 1536 if (mm < 16) { 1537 res = nn << mm; 1538 } 1539 } else { 1540 if (mm > -16) { 1541 res = nn >> -mm; 1542 } 1543 } 1544 d[i] = res; 1545 } 1546 clear_tail(d, opr_sz, simd_maxsz(desc)); 1547 } 1548 1549 /* 1550 * 8x8->8 polynomial multiply. 1551 * 1552 * Polynomial multiplication is like integer multiplication except the 1553 * partial products are XORed, not added. 1554 * 1555 * TODO: expose this as a generic vector operation, as it is a common 1556 * crypto building block. 1557 */ 1558 void HELPER(gvec_pmul_b)(void *vd, void *vn, void *vm, uint32_t desc) 1559 { 1560 intptr_t i, j, opr_sz = simd_oprsz(desc); 1561 uint64_t *d = vd, *n = vn, *m = vm; 1562 1563 for (i = 0; i < opr_sz / 8; ++i) { 1564 uint64_t nn = n[i]; 1565 uint64_t mm = m[i]; 1566 uint64_t rr = 0; 1567 1568 for (j = 0; j < 8; ++j) { 1569 uint64_t mask = (nn & 0x0101010101010101ull) * 0xff; 1570 rr ^= mm & mask; 1571 mm = (mm << 1) & 0xfefefefefefefefeull; 1572 nn >>= 1; 1573 } 1574 d[i] = rr; 1575 } 1576 clear_tail(d, opr_sz, simd_maxsz(desc)); 1577 } 1578 1579 /* 1580 * 64x64->128 polynomial multiply. 1581 * Because of the lanes are not accessed in strict columns, 1582 * this probably cannot be turned into a generic helper. 1583 */ 1584 void HELPER(gvec_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc) 1585 { 1586 intptr_t i, j, opr_sz = simd_oprsz(desc); 1587 intptr_t hi = simd_data(desc); 1588 uint64_t *d = vd, *n = vn, *m = vm; 1589 1590 for (i = 0; i < opr_sz / 8; i += 2) { 1591 uint64_t nn = n[i + hi]; 1592 uint64_t mm = m[i + hi]; 1593 uint64_t rhi = 0; 1594 uint64_t rlo = 0; 1595 1596 /* Bit 0 can only influence the low 64-bit result. */ 1597 if (nn & 1) { 1598 rlo = mm; 1599 } 1600 1601 for (j = 1; j < 64; ++j) { 1602 uint64_t mask = -((nn >> j) & 1); 1603 rlo ^= (mm << j) & mask; 1604 rhi ^= (mm >> (64 - j)) & mask; 1605 } 1606 d[i] = rlo; 1607 d[i + 1] = rhi; 1608 } 1609 clear_tail(d, opr_sz, simd_maxsz(desc)); 1610 } 1611 1612 /* 1613 * 8x8->16 polynomial multiply. 1614 * 1615 * The byte inputs are expanded to (or extracted from) half-words. 1616 * Note that neon and sve2 get the inputs from different positions. 1617 * This allows 4 bytes to be processed in parallel with uint64_t. 1618 */ 1619 1620 static uint64_t expand_byte_to_half(uint64_t x) 1621 { 1622 return (x & 0x000000ff) 1623 | ((x & 0x0000ff00) << 8) 1624 | ((x & 0x00ff0000) << 16) 1625 | ((x & 0xff000000) << 24); 1626 } 1627 1628 static uint64_t pmull_h(uint64_t op1, uint64_t op2) 1629 { 1630 uint64_t result = 0; 1631 int i; 1632 1633 for (i = 0; i < 8; ++i) { 1634 uint64_t mask = (op1 & 0x0001000100010001ull) * 0xffff; 1635 result ^= op2 & mask; 1636 op1 >>= 1; 1637 op2 <<= 1; 1638 } 1639 return result; 1640 } 1641 1642 void HELPER(neon_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) 1643 { 1644 int hi = simd_data(desc); 1645 uint64_t *d = vd, *n = vn, *m = vm; 1646 uint64_t nn = n[hi], mm = m[hi]; 1647 1648 d[0] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm)); 1649 nn >>= 32; 1650 mm >>= 32; 1651 d[1] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm)); 1652 1653 clear_tail(d, 16, simd_maxsz(desc)); 1654 } 1655 1656 #ifdef TARGET_AARCH64 1657 void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) 1658 { 1659 int shift = simd_data(desc) * 8; 1660 intptr_t i, opr_sz = simd_oprsz(desc); 1661 uint64_t *d = vd, *n = vn, *m = vm; 1662 1663 for (i = 0; i < opr_sz / 8; ++i) { 1664 uint64_t nn = (n[i] >> shift) & 0x00ff00ff00ff00ffull; 1665 uint64_t mm = (m[i] >> shift) & 0x00ff00ff00ff00ffull; 1666 1667 d[i] = pmull_h(nn, mm); 1668 } 1669 } 1670 #endif 1671 1672 #define DO_CMP0(NAME, TYPE, OP) \ 1673 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ 1674 { \ 1675 intptr_t i, opr_sz = simd_oprsz(desc); \ 1676 for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \ 1677 TYPE nn = *(TYPE *)(vn + i); \ 1678 *(TYPE *)(vd + i) = -(nn OP 0); \ 1679 } \ 1680 clear_tail(vd, opr_sz, simd_maxsz(desc)); \ 1681 } 1682 1683 DO_CMP0(gvec_ceq0_b, int8_t, ==) 1684 DO_CMP0(gvec_clt0_b, int8_t, <) 1685 DO_CMP0(gvec_cle0_b, int8_t, <=) 1686 DO_CMP0(gvec_cgt0_b, int8_t, >) 1687 DO_CMP0(gvec_cge0_b, int8_t, >=) 1688 1689 DO_CMP0(gvec_ceq0_h, int16_t, ==) 1690 DO_CMP0(gvec_clt0_h, int16_t, <) 1691 DO_CMP0(gvec_cle0_h, int16_t, <=) 1692 DO_CMP0(gvec_cgt0_h, int16_t, >) 1693 DO_CMP0(gvec_cge0_h, int16_t, >=) 1694 1695 #undef DO_CMP0 1696 1697 #define DO_ABD(NAME, TYPE) \ 1698 void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ 1699 { \ 1700 intptr_t i, opr_sz = simd_oprsz(desc); \ 1701 TYPE *d = vd, *n = vn, *m = vm; \ 1702 \ 1703 for (i = 0; i < opr_sz / sizeof(TYPE); ++i) { \ 1704 d[i] = n[i] < m[i] ? m[i] - n[i] : n[i] - m[i]; \ 1705 } \ 1706 clear_tail(d, opr_sz, simd_maxsz(desc)); \ 1707 } 1708 1709 DO_ABD(gvec_sabd_b, int8_t) 1710 DO_ABD(gvec_sabd_h, int16_t) 1711 DO_ABD(gvec_sabd_s, int32_t) 1712 DO_ABD(gvec_sabd_d, int64_t) 1713 1714 DO_ABD(gvec_uabd_b, uint8_t) 1715 DO_ABD(gvec_uabd_h, uint16_t) 1716 DO_ABD(gvec_uabd_s, uint32_t) 1717 DO_ABD(gvec_uabd_d, uint64_t) 1718 1719 #undef DO_ABD 1720 1721 #define DO_ABA(NAME, TYPE) \ 1722 void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ 1723 { \ 1724 intptr_t i, opr_sz = simd_oprsz(desc); \ 1725 TYPE *d = vd, *n = vn, *m = vm; \ 1726 \ 1727 for (i = 0; i < opr_sz / sizeof(TYPE); ++i) { \ 1728 d[i] += n[i] < m[i] ? m[i] - n[i] : n[i] - m[i]; \ 1729 } \ 1730 clear_tail(d, opr_sz, simd_maxsz(desc)); \ 1731 } 1732 1733 DO_ABA(gvec_saba_b, int8_t) 1734 DO_ABA(gvec_saba_h, int16_t) 1735 DO_ABA(gvec_saba_s, int32_t) 1736 DO_ABA(gvec_saba_d, int64_t) 1737 1738 DO_ABA(gvec_uaba_b, uint8_t) 1739 DO_ABA(gvec_uaba_h, uint16_t) 1740 DO_ABA(gvec_uaba_s, uint32_t) 1741 DO_ABA(gvec_uaba_d, uint64_t) 1742 1743 #undef DO_ABA 1744