1 #ifndef TARGET_ARM_TRANSLATE_H 2 #define TARGET_ARM_TRANSLATE_H 3 4 #include "cpu.h" 5 #include "tcg/tcg-op.h" 6 #include "tcg/tcg-op-gvec.h" 7 #include "exec/exec-all.h" 8 #include "exec/translator.h" 9 #include "exec/translation-block.h" 10 #include "exec/helper-gen.h" 11 #include "internals.h" 12 #include "cpu-features.h" 13 14 /* internal defines */ 15 16 /* 17 * Save pc_save across a branch, so that we may restore the value from 18 * before the branch at the point the label is emitted. 19 */ 20 typedef struct DisasLabel { 21 TCGLabel *label; 22 target_ulong pc_save; 23 } DisasLabel; 24 25 typedef struct DisasContext { 26 DisasContextBase base; 27 const ARMISARegisters *isar; 28 29 /* The address of the current instruction being translated. */ 30 target_ulong pc_curr; 31 /* 32 * For CF_PCREL, the full value of cpu_pc is not known 33 * (although the page offset is known). For convenience, the 34 * translation loop uses the full virtual address that triggered 35 * the translation, from base.pc_start through pc_curr. 36 * For efficiency, we do not update cpu_pc for every instruction. 37 * Instead, pc_save has the value of pc_curr at the time of the 38 * last update to cpu_pc, which allows us to compute the addend 39 * needed to bring cpu_pc current: pc_curr - pc_save. 40 * If cpu_pc now contains the destination of an indirect branch, 41 * pc_save contains -1 to indicate that relative updates are no 42 * longer possible. 43 */ 44 target_ulong pc_save; 45 target_ulong page_start; 46 uint32_t insn; 47 /* Nonzero if this instruction has been conditionally skipped. */ 48 int condjmp; 49 /* The label that will be jumped to when the instruction is skipped. */ 50 DisasLabel condlabel; 51 /* Thumb-2 conditional execution bits. */ 52 int condexec_mask; 53 int condexec_cond; 54 /* M-profile ECI/ICI exception-continuable instruction state */ 55 int eci; 56 /* 57 * trans_ functions for insns which are continuable should set this true 58 * after decode (ie after any UNDEF checks) 59 */ 60 bool eci_handled; 61 int sctlr_b; 62 MemOp be_data; 63 #if !defined(CONFIG_USER_ONLY) 64 int user; 65 #endif 66 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ 67 uint8_t tbii; /* TBI1|TBI0 for insns */ 68 uint8_t tbid; /* TBI1|TBI0 for data */ 69 uint8_t tcma; /* TCMA1|TCMA0 for MTE */ 70 bool ns; /* Use non-secure CPREG bank on access */ 71 int fp_excp_el; /* FP exception EL or 0 if enabled */ 72 int sve_excp_el; /* SVE exception EL or 0 if enabled */ 73 int sme_excp_el; /* SME exception EL or 0 if enabled */ 74 int vl; /* current vector length in bytes */ 75 int svl; /* current streaming vector length in bytes */ 76 bool vfp_enabled; /* FP enabled via FPSCR.EN */ 77 int vec_len; 78 int vec_stride; 79 bool v7m_handler_mode; 80 bool v8m_secure; /* true if v8M and we're in Secure mode */ 81 bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ 82 bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ 83 bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ 84 bool v7m_lspact; /* FPCCR.LSPACT set */ 85 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI 86 * so that top level loop can generate correct syndrome information. 87 */ 88 uint32_t svc_imm; 89 int current_el; 90 GHashTable *cp_regs; 91 uint64_t features; /* CPU features bits */ 92 bool aarch64; 93 bool thumb; 94 bool lse2; 95 /* Because unallocated encodings generate different exception syndrome 96 * information from traps due to FP being disabled, we can't do a single 97 * "is fp access disabled" check at a high level in the decode tree. 98 * To help in catching bugs where the access check was forgotten in some 99 * code path, we set this flag when the access check is done, and assert 100 * that it is set at the point where we actually touch the FP regs. 101 */ 102 bool fp_access_checked; 103 bool sve_access_checked; 104 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub 105 * single-step support). 106 */ 107 bool ss_active; 108 bool pstate_ss; 109 /* True if the insn just emitted was a load-exclusive instruction 110 * (necessary for syndrome information for single step exceptions), 111 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. 112 */ 113 bool is_ldex; 114 /* True if AccType_UNPRIV should be used for LDTR et al */ 115 bool unpriv; 116 /* True if v8.3-PAuth is active. */ 117 bool pauth_active; 118 /* True if v8.5-MTE access to tags is enabled; index with is_unpriv. */ 119 bool ata[2]; 120 /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */ 121 bool mte_active[2]; 122 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ 123 bool bt; 124 /* True if any CP15 access is trapped by HSTR_EL2 */ 125 bool hstr_active; 126 /* True if memory operations require alignment */ 127 bool align_mem; 128 /* True if PSTATE.IL is set */ 129 bool pstate_il; 130 /* True if PSTATE.SM is set. */ 131 bool pstate_sm; 132 /* True if PSTATE.ZA is set. */ 133 bool pstate_za; 134 /* True if non-streaming insns should raise an SME Streaming exception. */ 135 bool sme_trap_nonstreaming; 136 /* True if the current instruction is non-streaming. */ 137 bool is_nonstreaming; 138 /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ 139 bool mve_no_pred; 140 /* True if fine-grained traps are active */ 141 bool fgt_active; 142 /* True if fine-grained trap on SVC is enabled */ 143 bool fgt_svc; 144 /* True if a trap on ERET is enabled (FGT or NV) */ 145 bool trap_eret; 146 /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */ 147 bool naa; 148 /* True if FEAT_NV HCR_EL2.NV is enabled */ 149 bool nv; 150 /* True if NV enabled and HCR_EL2.NV1 is set */ 151 bool nv1; 152 /* True if NV enabled and HCR_EL2.NV2 is set */ 153 bool nv2; 154 /* True if NV2 enabled and NV2 RAM accesses use EL2&0 translation regime */ 155 bool nv2_mem_e20; 156 /* True if NV2 enabled and NV2 RAM accesses are big-endian */ 157 bool nv2_mem_be; 158 /* 159 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. 160 * < 0, set by the current instruction. 161 */ 162 int8_t btype; 163 /* A copy of cpu->dcz_blocksize. */ 164 uint8_t dcz_blocksize; 165 /* A copy of cpu->gm_blocksize. */ 166 uint8_t gm_blocksize; 167 /* True if the current insn_start has been updated. */ 168 bool insn_start_updated; 169 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ 170 int c15_cpar; 171 /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */ 172 uint32_t nv2_redirect_offset; 173 } DisasContext; 174 175 typedef struct DisasCompare { 176 TCGCond cond; 177 TCGv_i32 value; 178 } DisasCompare; 179 180 /* Share the TCG temporaries common between 32 and 64 bit modes. */ 181 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; 182 extern TCGv_i64 cpu_exclusive_addr; 183 extern TCGv_i64 cpu_exclusive_val; 184 185 /* 186 * Constant expanders for the decoders. 187 */ 188 189 static inline int negate(DisasContext *s, int x) 190 { 191 return -x; 192 } 193 194 static inline int plus_1(DisasContext *s, int x) 195 { 196 return x + 1; 197 } 198 199 static inline int plus_2(DisasContext *s, int x) 200 { 201 return x + 2; 202 } 203 204 static inline int plus_12(DisasContext *s, int x) 205 { 206 return x + 12; 207 } 208 209 static inline int times_2(DisasContext *s, int x) 210 { 211 return x * 2; 212 } 213 214 static inline int times_4(DisasContext *s, int x) 215 { 216 return x * 4; 217 } 218 219 static inline int times_8(DisasContext *s, int x) 220 { 221 return x * 8; 222 } 223 224 static inline int times_2_plus_1(DisasContext *s, int x) 225 { 226 return x * 2 + 1; 227 } 228 229 static inline int rsub_64(DisasContext *s, int x) 230 { 231 return 64 - x; 232 } 233 234 static inline int rsub_32(DisasContext *s, int x) 235 { 236 return 32 - x; 237 } 238 239 static inline int rsub_16(DisasContext *s, int x) 240 { 241 return 16 - x; 242 } 243 244 static inline int rsub_8(DisasContext *s, int x) 245 { 246 return 8 - x; 247 } 248 249 static inline int shl_12(DisasContext *s, int x) 250 { 251 return x << 12; 252 } 253 254 static inline int xor_2(DisasContext *s, int x) 255 { 256 return x ^ 2; 257 } 258 259 static inline int neon_3same_fp_size(DisasContext *s, int x) 260 { 261 /* Convert 0==fp32, 1==fp16 into a MO_* value */ 262 return MO_32 - x; 263 } 264 265 static inline int arm_dc_feature(DisasContext *dc, int feature) 266 { 267 return (dc->features & (1ULL << feature)) != 0; 268 } 269 270 static inline int get_mem_index(DisasContext *s) 271 { 272 return arm_to_core_mmu_idx(s->mmu_idx); 273 } 274 275 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) 276 { 277 /* We don't need to save all of the syndrome so we mask and shift 278 * out unneeded bits to help the sleb128 encoder do a better job. 279 */ 280 syn &= ARM_INSN_START_WORD2_MASK; 281 syn >>= ARM_INSN_START_WORD2_SHIFT; 282 283 /* Check for multiple updates. */ 284 assert(!s->insn_start_updated); 285 s->insn_start_updated = true; 286 tcg_set_insn_start_param(s->base.insn_start, 2, syn); 287 } 288 289 static inline int curr_insn_len(DisasContext *s) 290 { 291 return s->base.pc_next - s->pc_curr; 292 } 293 294 /* is_jmp field values */ 295 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ 296 /* CPU state was modified dynamically; exit to main loop for interrupts. */ 297 #define DISAS_UPDATE_EXIT DISAS_TARGET_1 298 /* These instructions trap after executing, so the A32/T32 decoder must 299 * defer them until after the conditional execution state has been updated. 300 * WFI also needs special handling when single-stepping. 301 */ 302 #define DISAS_WFI DISAS_TARGET_2 303 #define DISAS_SWI DISAS_TARGET_3 304 /* WFE */ 305 #define DISAS_WFE DISAS_TARGET_4 306 #define DISAS_HVC DISAS_TARGET_5 307 #define DISAS_SMC DISAS_TARGET_6 308 #define DISAS_YIELD DISAS_TARGET_7 309 /* M profile branch which might be an exception return (and so needs 310 * custom end-of-TB code) 311 */ 312 #define DISAS_BX_EXCRET DISAS_TARGET_8 313 /* 314 * For instructions which want an immediate exit to the main loop, as opposed 315 * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this 316 * doesn't write the PC on exiting the translation loop so you need to ensure 317 * something (gen_a64_update_pc or runtime helper) has done so before we reach 318 * return from cpu_tb_exec. 319 */ 320 #define DISAS_EXIT DISAS_TARGET_9 321 /* CPU state was modified dynamically; no need to exit, but do not chain. */ 322 #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 323 324 #ifdef TARGET_AARCH64 325 void a64_translate_init(void); 326 void gen_a64_update_pc(DisasContext *s, target_long diff); 327 extern const TranslatorOps aarch64_translator_ops; 328 #else 329 static inline void a64_translate_init(void) 330 { 331 } 332 333 static inline void gen_a64_update_pc(DisasContext *s, target_long diff) 334 { 335 } 336 #endif 337 338 void arm_test_cc(DisasCompare *cmp, int cc); 339 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); 340 void arm_gen_test_cc(int cc, TCGLabel *label); 341 MemOp pow2_align(unsigned i); 342 void unallocated_encoding(DisasContext *s); 343 void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, 344 uint32_t syn, uint32_t target_el); 345 void gen_exception_insn(DisasContext *s, target_long pc_diff, 346 int excp, uint32_t syn); 347 348 /* Return state of Alternate Half-precision flag, caller frees result */ 349 static inline TCGv_i32 get_ahp_flag(void) 350 { 351 TCGv_i32 ret = tcg_temp_new_i32(); 352 353 tcg_gen_ld_i32(ret, tcg_env, offsetoflow32(CPUARMState, vfp.fpcr)); 354 tcg_gen_extract_i32(ret, ret, 26, 1); 355 356 return ret; 357 } 358 359 /* Set bits within PSTATE. */ 360 static inline void set_pstate_bits(uint32_t bits) 361 { 362 TCGv_i32 p = tcg_temp_new_i32(); 363 364 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); 365 366 tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); 367 tcg_gen_ori_i32(p, p, bits); 368 tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); 369 } 370 371 /* Clear bits within PSTATE. */ 372 static inline void clear_pstate_bits(uint32_t bits) 373 { 374 TCGv_i32 p = tcg_temp_new_i32(); 375 376 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); 377 378 tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); 379 tcg_gen_andi_i32(p, p, ~bits); 380 tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); 381 } 382 383 /* If the singlestep state is Active-not-pending, advance to Active-pending. */ 384 static inline void gen_ss_advance(DisasContext *s) 385 { 386 if (s->ss_active) { 387 s->pstate_ss = 0; 388 clear_pstate_bits(PSTATE_SS); 389 } 390 } 391 392 /* Generate an architectural singlestep exception */ 393 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) 394 { 395 /* Fill in the same_el field of the syndrome in the helper. */ 396 uint32_t syn = syn_swstep(false, isv, ex); 397 gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn)); 398 } 399 400 /* 401 * Given a VFP floating point constant encoded into an 8 bit immediate in an 402 * instruction, expand it to the actual constant value of the specified 403 * size, as per the VFPExpandImm() pseudocode in the Arm ARM. 404 */ 405 uint64_t vfp_expand_imm(int size, uint8_t imm8); 406 407 static inline void gen_vfp_absh(TCGv_i32 d, TCGv_i32 s) 408 { 409 tcg_gen_andi_i32(d, s, INT16_MAX); 410 } 411 412 static inline void gen_vfp_abss(TCGv_i32 d, TCGv_i32 s) 413 { 414 tcg_gen_andi_i32(d, s, INT32_MAX); 415 } 416 417 static inline void gen_vfp_absd(TCGv_i64 d, TCGv_i64 s) 418 { 419 tcg_gen_andi_i64(d, s, INT64_MAX); 420 } 421 422 static inline void gen_vfp_negh(TCGv_i32 d, TCGv_i32 s) 423 { 424 tcg_gen_xori_i32(d, s, 1u << 15); 425 } 426 427 static inline void gen_vfp_negs(TCGv_i32 d, TCGv_i32 s) 428 { 429 tcg_gen_xori_i32(d, s, 1u << 31); 430 } 431 432 static inline void gen_vfp_negd(TCGv_i64 d, TCGv_i64 s) 433 { 434 tcg_gen_xori_i64(d, s, 1ull << 63); 435 } 436 437 /* Vector operations shared between ARM and AArch64. */ 438 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 439 uint32_t opr_sz, uint32_t max_sz); 440 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 441 uint32_t opr_sz, uint32_t max_sz); 442 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 443 uint32_t opr_sz, uint32_t max_sz); 444 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 445 uint32_t opr_sz, uint32_t max_sz); 446 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 447 uint32_t opr_sz, uint32_t max_sz); 448 449 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 450 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 451 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 452 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 453 454 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 455 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 456 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 457 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 458 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 459 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 460 void gen_gvec_srshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 461 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 462 void gen_gvec_urshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 463 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 464 void gen_neon_sqshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 465 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 466 void gen_neon_uqshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 467 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 468 void gen_neon_sqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 469 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 470 void gen_neon_uqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 471 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 472 473 void gen_neon_sqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 474 int64_t c, uint32_t opr_sz, uint32_t max_sz); 475 void gen_neon_uqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 476 int64_t c, uint32_t opr_sz, uint32_t max_sz); 477 void gen_neon_sqshlui(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 478 int64_t c, uint32_t opr_sz, uint32_t max_sz); 479 480 void gen_gvec_shadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 481 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 482 void gen_gvec_uhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 483 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 484 void gen_gvec_shsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 485 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 486 void gen_gvec_uhsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 487 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 488 void gen_gvec_srhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 489 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 490 void gen_gvec_urhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 491 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 492 493 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 494 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); 495 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); 496 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 497 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 498 499 void gen_uqadd_bhs(TCGv_i64 res, TCGv_i64 qc, 500 TCGv_i64 a, TCGv_i64 b, MemOp esz); 501 void gen_uqadd_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 502 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 503 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 504 505 void gen_sqadd_bhs(TCGv_i64 res, TCGv_i64 qc, 506 TCGv_i64 a, TCGv_i64 b, MemOp esz); 507 void gen_sqadd_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 508 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 509 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 510 511 void gen_uqsub_bhs(TCGv_i64 res, TCGv_i64 qc, 512 TCGv_i64 a, TCGv_i64 b, MemOp esz); 513 void gen_uqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 514 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 515 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 516 517 void gen_sqsub_bhs(TCGv_i64 res, TCGv_i64 qc, 518 TCGv_i64 a, TCGv_i64 b, MemOp esz); 519 void gen_sqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 520 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 521 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 522 523 void gen_gvec_sshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 524 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 525 void gen_gvec_ushr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 526 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 527 528 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 529 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 530 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 531 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 532 533 void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh); 534 void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh); 535 void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh); 536 void gen_urshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh); 537 538 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 539 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 540 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 541 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 542 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 543 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 544 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 545 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 546 547 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 548 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 549 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 550 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 551 552 void gen_gvec_sqdmulh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 553 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 554 void gen_gvec_sqrdmulh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 555 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 556 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 557 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 558 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 559 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 560 561 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 562 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 563 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 564 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 565 566 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 567 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 568 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 569 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 570 571 void gen_gvec_addp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 572 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 573 void gen_gvec_smaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 574 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 575 void gen_gvec_sminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 576 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 577 void gen_gvec_umaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 578 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 579 void gen_gvec_uminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 580 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 581 582 void gen_gvec_cls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 583 uint32_t opr_sz, uint32_t max_sz); 584 void gen_gvec_clz(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 585 uint32_t opr_sz, uint32_t max_sz); 586 void gen_gvec_cnt(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 587 uint32_t opr_sz, uint32_t max_sz); 588 void gen_gvec_rbit(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 589 uint32_t opr_sz, uint32_t max_sz); 590 void gen_gvec_rev16(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 591 uint32_t opr_sz, uint32_t max_sz); 592 void gen_gvec_rev32(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 593 uint32_t opr_sz, uint32_t max_sz); 594 void gen_gvec_rev64(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 595 uint32_t opr_sz, uint32_t max_sz); 596 597 void gen_gvec_saddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 598 uint32_t opr_sz, uint32_t max_sz); 599 void gen_gvec_sadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 600 uint32_t opr_sz, uint32_t max_sz); 601 void gen_gvec_uaddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 602 uint32_t opr_sz, uint32_t max_sz); 603 void gen_gvec_uadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 604 uint32_t opr_sz, uint32_t max_sz); 605 606 /* These exclusively manipulate the sign bit. */ 607 void gen_gvec_fabs(unsigned vece, uint32_t dofs, uint32_t aofs, 608 uint32_t oprsz, uint32_t maxsz); 609 void gen_gvec_fneg(unsigned vece, uint32_t dofs, uint32_t aofs, 610 uint32_t oprsz, uint32_t maxsz); 611 612 void gen_gvec_urecpe(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 613 uint32_t opr_sz, uint32_t max_sz); 614 void gen_gvec_ursqrte(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 615 uint32_t opr_sz, uint32_t max_sz); 616 617 /* 618 * Forward to the isar_feature_* tests given a DisasContext pointer. 619 */ 620 #define dc_isar_feature(name, ctx) \ 621 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); }) 622 623 /* Note that the gvec expanders operate on offsets + sizes. */ 624 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); 625 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, 626 uint32_t, uint32_t); 627 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, 628 uint32_t, uint32_t, uint32_t); 629 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t, 630 uint32_t, uint32_t, uint32_t); 631 632 /* Function prototype for gen_ functions for calling Neon helpers */ 633 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); 634 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); 635 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); 636 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); 637 typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, 638 TCGv_i32, TCGv_i32); 639 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); 640 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); 641 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); 642 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); 643 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); 644 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr); 645 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); 646 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); 647 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); 648 typedef void NeonGenOne64OpEnvFn(TCGv_i64, TCGv_env, TCGv_i64); 649 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); 650 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 651 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 652 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); 653 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); 654 typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); 655 typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); 656 typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); 657 658 /** 659 * arm_tbflags_from_tb: 660 * @tb: the TranslationBlock 661 * 662 * Extract the flag values from @tb. 663 */ 664 static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) 665 { 666 return (CPUARMTBFlags){ tb->flags, tb->cs_base }; 667 } 668 669 /* 670 * Enum for argument to fpstatus_ptr(). 671 */ 672 typedef enum ARMFPStatusFlavour { 673 FPST_FPCR, 674 FPST_FPCR_F16, 675 FPST_STD, 676 FPST_STD_F16, 677 } ARMFPStatusFlavour; 678 679 /** 680 * fpstatus_ptr: return TCGv_ptr to the specified fp_status field 681 * 682 * We have multiple softfloat float_status fields in the Arm CPU state struct 683 * (see the comment in cpu.h for details). Return a TCGv_ptr which has 684 * been set up to point to the requested field in the CPU state struct. 685 * The options are: 686 * 687 * FPST_FPCR 688 * for non-FP16 operations controlled by the FPCR 689 * FPST_FPCR_F16 690 * for operations controlled by the FPCR where FPCR.FZ16 is to be used 691 * FPST_STD 692 * for A32/T32 Neon operations using the "standard FPSCR value" 693 * FPST_STD_F16 694 * as FPST_STD, but where FPCR.FZ16 is to be used 695 */ 696 static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) 697 { 698 TCGv_ptr statusptr = tcg_temp_new_ptr(); 699 int offset; 700 701 switch (flavour) { 702 case FPST_FPCR: 703 offset = offsetof(CPUARMState, vfp.fp_status); 704 break; 705 case FPST_FPCR_F16: 706 offset = offsetof(CPUARMState, vfp.fp_status_f16); 707 break; 708 case FPST_STD: 709 offset = offsetof(CPUARMState, vfp.standard_fp_status); 710 break; 711 case FPST_STD_F16: 712 offset = offsetof(CPUARMState, vfp.standard_fp_status_f16); 713 break; 714 default: 715 g_assert_not_reached(); 716 } 717 tcg_gen_addi_ptr(statusptr, tcg_env, offset); 718 return statusptr; 719 } 720 721 /** 722 * finalize_memop_atom: 723 * @s: DisasContext 724 * @opc: size+sign+align of the memory operation 725 * @atom: atomicity of the memory operation 726 * 727 * Build the complete MemOp for a memory operation, including alignment, 728 * endianness, and atomicity. 729 * 730 * If (op & MO_AMASK) then the operation already contains the required 731 * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally 732 * unaligned operation, e.g. for AccType_NORMAL. 733 * 734 * In the latter case, there are configuration bits that require alignment, 735 * and this is applied here. Note that there is no way to indicate that 736 * no alignment should ever be enforced; this must be handled manually. 737 */ 738 static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp atom) 739 { 740 if (s->align_mem && !(opc & MO_AMASK)) { 741 opc |= MO_ALIGN; 742 } 743 return opc | atom | s->be_data; 744 } 745 746 /** 747 * finalize_memop: 748 * @s: DisasContext 749 * @opc: size+sign+align of the memory operation 750 * 751 * Like finalize_memop_atom, but with default atomicity. 752 */ 753 static inline MemOp finalize_memop(DisasContext *s, MemOp opc) 754 { 755 MemOp atom = s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN; 756 return finalize_memop_atom(s, opc, atom); 757 } 758 759 /** 760 * finalize_memop_pair: 761 * @s: DisasContext 762 * @opc: size+sign+align of the memory operation 763 * 764 * Like finalize_memop_atom, but with atomicity for a pair. 765 * C.f. Pseudocode for Mem[], operand ispair. 766 */ 767 static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc) 768 { 769 MemOp atom = s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR; 770 return finalize_memop_atom(s, opc, atom); 771 } 772 773 /** 774 * finalize_memop_asimd: 775 * @s: DisasContext 776 * @opc: size+sign+align of the memory operation 777 * 778 * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD. 779 */ 780 static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc) 781 { 782 /* 783 * In the pseudocode for Mem[], with AccessType_ASIMD, size == 16, 784 * if IsAligned(8), the first case provides separate atomicity for 785 * the pair of 64-bit accesses. If !IsAligned(8), the middle cases 786 * do not apply, and we're left with the final case of no atomicity. 787 * Thus MO_ATOM_IFALIGN_PAIR. 788 * 789 * For other sizes, normal LSE2 rules apply. 790 */ 791 if ((opc & MO_SIZE) == MO_128) { 792 return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR); 793 } 794 return finalize_memop(s, opc); 795 } 796 797 /** 798 * asimd_imm_const: Expand an encoded SIMD constant value 799 * 800 * Expand a SIMD constant value. This is essentially the pseudocode 801 * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for 802 * VMVN and VBIC (when cmode < 14 && op == 1). 803 * 804 * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; 805 * callers must catch this; we return the 64-bit constant value defined 806 * for AArch64. 807 * 808 * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but 809 * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; 810 * we produce an immediate constant value of 0 in these cases. 811 */ 812 uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); 813 814 /* 815 * gen_disas_label: 816 * Create a label and cache a copy of pc_save. 817 */ 818 static inline DisasLabel gen_disas_label(DisasContext *s) 819 { 820 return (DisasLabel){ 821 .label = gen_new_label(), 822 .pc_save = s->pc_save, 823 }; 824 } 825 826 /* 827 * set_disas_label: 828 * Emit a label and restore the cached copy of pc_save. 829 */ 830 static inline void set_disas_label(DisasContext *s, DisasLabel l) 831 { 832 gen_set_label(l.label); 833 s->pc_save = l.pc_save; 834 } 835 836 static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key) 837 { 838 TCGv_ptr ret = tcg_temp_new_ptr(); 839 gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key)); 840 return ret; 841 } 842 843 /* 844 * Set and reset rounding mode around another operation. 845 */ 846 static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst) 847 { 848 TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode)); 849 TCGv_i32 old = tcg_temp_new_i32(); 850 851 gen_helper_set_rmode(old, new, fpst); 852 return old; 853 } 854 855 static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst) 856 { 857 gen_helper_set_rmode(old, old, fpst); 858 } 859 860 /* 861 * Helpers for implementing sets of trans_* functions. 862 * Defer the implementation of NAME to FUNC, with optional extra arguments. 863 */ 864 #define TRANS(NAME, FUNC, ...) \ 865 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 866 { return FUNC(s, __VA_ARGS__); } 867 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \ 868 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 869 { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } 870 871 #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ 872 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 873 { \ 874 s->is_nonstreaming = true; \ 875 return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ 876 } 877 878 #endif /* TARGET_ARM_TRANSLATE_H */ 879