1 #ifndef TARGET_ARM_TRANSLATE_H 2 #define TARGET_ARM_TRANSLATE_H 3 4 #include "cpu.h" 5 #include "tcg/tcg-op.h" 6 #include "tcg/tcg-op-gvec.h" 7 #include "exec/exec-all.h" 8 #include "exec/translator.h" 9 #include "exec/translation-block.h" 10 #include "exec/helper-gen.h" 11 #include "internals.h" 12 #include "cpu-features.h" 13 14 /* internal defines */ 15 16 /* 17 * Save pc_save across a branch, so that we may restore the value from 18 * before the branch at the point the label is emitted. 19 */ 20 typedef struct DisasLabel { 21 TCGLabel *label; 22 target_ulong pc_save; 23 } DisasLabel; 24 25 typedef struct DisasContext { 26 DisasContextBase base; 27 const ARMISARegisters *isar; 28 29 /* The address of the current instruction being translated. */ 30 target_ulong pc_curr; 31 /* 32 * For CF_PCREL, the full value of cpu_pc is not known 33 * (although the page offset is known). For convenience, the 34 * translation loop uses the full virtual address that triggered 35 * the translation, from base.pc_start through pc_curr. 36 * For efficiency, we do not update cpu_pc for every instruction. 37 * Instead, pc_save has the value of pc_curr at the time of the 38 * last update to cpu_pc, which allows us to compute the addend 39 * needed to bring cpu_pc current: pc_curr - pc_save. 40 * If cpu_pc now contains the destination of an indirect branch, 41 * pc_save contains -1 to indicate that relative updates are no 42 * longer possible. 43 */ 44 target_ulong pc_save; 45 target_ulong page_start; 46 uint32_t insn; 47 /* Nonzero if this instruction has been conditionally skipped. */ 48 int condjmp; 49 /* The label that will be jumped to when the instruction is skipped. */ 50 DisasLabel condlabel; 51 /* Thumb-2 conditional execution bits. */ 52 int condexec_mask; 53 int condexec_cond; 54 /* M-profile ECI/ICI exception-continuable instruction state */ 55 int eci; 56 /* 57 * trans_ functions for insns which are continuable should set this true 58 * after decode (ie after any UNDEF checks) 59 */ 60 bool eci_handled; 61 int sctlr_b; 62 MemOp be_data; 63 #if !defined(CONFIG_USER_ONLY) 64 int user; 65 #endif 66 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ 67 uint8_t tbii; /* TBI1|TBI0 for insns */ 68 uint8_t tbid; /* TBI1|TBI0 for data */ 69 uint8_t tcma; /* TCMA1|TCMA0 for MTE */ 70 bool ns; /* Use non-secure CPREG bank on access */ 71 int fp_excp_el; /* FP exception EL or 0 if enabled */ 72 int sve_excp_el; /* SVE exception EL or 0 if enabled */ 73 int sme_excp_el; /* SME exception EL or 0 if enabled */ 74 int vl; /* current vector length in bytes */ 75 int svl; /* current streaming vector length in bytes */ 76 bool vfp_enabled; /* FP enabled via FPSCR.EN */ 77 int vec_len; 78 int vec_stride; 79 bool v7m_handler_mode; 80 bool v8m_secure; /* true if v8M and we're in Secure mode */ 81 bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ 82 bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ 83 bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ 84 bool v7m_lspact; /* FPCCR.LSPACT set */ 85 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI 86 * so that top level loop can generate correct syndrome information. 87 */ 88 uint32_t svc_imm; 89 int current_el; 90 GHashTable *cp_regs; 91 uint64_t features; /* CPU features bits */ 92 bool aarch64; 93 bool thumb; 94 bool lse2; 95 /* Because unallocated encodings generate different exception syndrome 96 * information from traps due to FP being disabled, we can't do a single 97 * "is fp access disabled" check at a high level in the decode tree. 98 * To help in catching bugs where the access check was forgotten in some 99 * code path, we set this flag when the access check is done, and assert 100 * that it is set at the point where we actually touch the FP regs. 101 */ 102 bool fp_access_checked; 103 bool sve_access_checked; 104 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub 105 * single-step support). 106 */ 107 bool ss_active; 108 bool pstate_ss; 109 /* True if the insn just emitted was a load-exclusive instruction 110 * (necessary for syndrome information for single step exceptions), 111 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. 112 */ 113 bool is_ldex; 114 /* True if AccType_UNPRIV should be used for LDTR et al */ 115 bool unpriv; 116 /* True if v8.3-PAuth is active. */ 117 bool pauth_active; 118 /* True if v8.5-MTE access to tags is enabled; index with is_unpriv. */ 119 bool ata[2]; 120 /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */ 121 bool mte_active[2]; 122 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ 123 bool bt; 124 /* True if any CP15 access is trapped by HSTR_EL2 */ 125 bool hstr_active; 126 /* True if memory operations require alignment */ 127 bool align_mem; 128 /* True if PSTATE.IL is set */ 129 bool pstate_il; 130 /* True if PSTATE.SM is set. */ 131 bool pstate_sm; 132 /* True if PSTATE.ZA is set. */ 133 bool pstate_za; 134 /* True if non-streaming insns should raise an SME Streaming exception. */ 135 bool sme_trap_nonstreaming; 136 /* True if the current instruction is non-streaming. */ 137 bool is_nonstreaming; 138 /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ 139 bool mve_no_pred; 140 /* True if fine-grained traps are active */ 141 bool fgt_active; 142 /* True if fine-grained trap on SVC is enabled */ 143 bool fgt_svc; 144 /* True if a trap on ERET is enabled (FGT or NV) */ 145 bool trap_eret; 146 /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */ 147 bool naa; 148 /* True if FEAT_NV HCR_EL2.NV is enabled */ 149 bool nv; 150 /* True if NV enabled and HCR_EL2.NV1 is set */ 151 bool nv1; 152 /* True if NV enabled and HCR_EL2.NV2 is set */ 153 bool nv2; 154 /* True if NV2 enabled and NV2 RAM accesses use EL2&0 translation regime */ 155 bool nv2_mem_e20; 156 /* True if NV2 enabled and NV2 RAM accesses are big-endian */ 157 bool nv2_mem_be; 158 /* True if FPCR.AH is 1 (alternate floating point handling) */ 159 bool fpcr_ah; 160 /* True if FPCR.NEP is 1 (FEAT_AFP scalar upper-element result handling) */ 161 bool fpcr_nep; 162 /* 163 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. 164 * < 0, set by the current instruction. 165 */ 166 int8_t btype; 167 /* A copy of cpu->dcz_blocksize. */ 168 uint8_t dcz_blocksize; 169 /* A copy of cpu->gm_blocksize. */ 170 uint8_t gm_blocksize; 171 /* True if the current insn_start has been updated. */ 172 bool insn_start_updated; 173 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ 174 int c15_cpar; 175 /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */ 176 uint32_t nv2_redirect_offset; 177 } DisasContext; 178 179 typedef struct DisasCompare { 180 TCGCond cond; 181 TCGv_i32 value; 182 } DisasCompare; 183 184 /* Share the TCG temporaries common between 32 and 64 bit modes. */ 185 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; 186 extern TCGv_i64 cpu_exclusive_addr; 187 extern TCGv_i64 cpu_exclusive_val; 188 189 /* 190 * Constant expanders for the decoders. 191 */ 192 193 static inline int negate(DisasContext *s, int x) 194 { 195 return -x; 196 } 197 198 static inline int plus_1(DisasContext *s, int x) 199 { 200 return x + 1; 201 } 202 203 static inline int plus_2(DisasContext *s, int x) 204 { 205 return x + 2; 206 } 207 208 static inline int plus_12(DisasContext *s, int x) 209 { 210 return x + 12; 211 } 212 213 static inline int times_2(DisasContext *s, int x) 214 { 215 return x * 2; 216 } 217 218 static inline int times_4(DisasContext *s, int x) 219 { 220 return x * 4; 221 } 222 223 static inline int times_8(DisasContext *s, int x) 224 { 225 return x * 8; 226 } 227 228 static inline int times_2_plus_1(DisasContext *s, int x) 229 { 230 return x * 2 + 1; 231 } 232 233 static inline int rsub_64(DisasContext *s, int x) 234 { 235 return 64 - x; 236 } 237 238 static inline int rsub_32(DisasContext *s, int x) 239 { 240 return 32 - x; 241 } 242 243 static inline int rsub_16(DisasContext *s, int x) 244 { 245 return 16 - x; 246 } 247 248 static inline int rsub_8(DisasContext *s, int x) 249 { 250 return 8 - x; 251 } 252 253 static inline int shl_12(DisasContext *s, int x) 254 { 255 return x << 12; 256 } 257 258 static inline int xor_2(DisasContext *s, int x) 259 { 260 return x ^ 2; 261 } 262 263 static inline int neon_3same_fp_size(DisasContext *s, int x) 264 { 265 /* Convert 0==fp32, 1==fp16 into a MO_* value */ 266 return MO_32 - x; 267 } 268 269 static inline int arm_dc_feature(DisasContext *dc, int feature) 270 { 271 return (dc->features & (1ULL << feature)) != 0; 272 } 273 274 static inline int get_mem_index(DisasContext *s) 275 { 276 return arm_to_core_mmu_idx(s->mmu_idx); 277 } 278 279 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) 280 { 281 /* We don't need to save all of the syndrome so we mask and shift 282 * out unneeded bits to help the sleb128 encoder do a better job. 283 */ 284 syn &= ARM_INSN_START_WORD2_MASK; 285 syn >>= ARM_INSN_START_WORD2_SHIFT; 286 287 /* Check for multiple updates. */ 288 assert(!s->insn_start_updated); 289 s->insn_start_updated = true; 290 tcg_set_insn_start_param(s->base.insn_start, 2, syn); 291 } 292 293 static inline int curr_insn_len(DisasContext *s) 294 { 295 return s->base.pc_next - s->pc_curr; 296 } 297 298 /* is_jmp field values */ 299 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ 300 /* CPU state was modified dynamically; exit to main loop for interrupts. */ 301 #define DISAS_UPDATE_EXIT DISAS_TARGET_1 302 /* These instructions trap after executing, so the A32/T32 decoder must 303 * defer them until after the conditional execution state has been updated. 304 * WFI also needs special handling when single-stepping. 305 */ 306 #define DISAS_WFI DISAS_TARGET_2 307 #define DISAS_SWI DISAS_TARGET_3 308 /* WFE */ 309 #define DISAS_WFE DISAS_TARGET_4 310 #define DISAS_HVC DISAS_TARGET_5 311 #define DISAS_SMC DISAS_TARGET_6 312 #define DISAS_YIELD DISAS_TARGET_7 313 /* M profile branch which might be an exception return (and so needs 314 * custom end-of-TB code) 315 */ 316 #define DISAS_BX_EXCRET DISAS_TARGET_8 317 /* 318 * For instructions which want an immediate exit to the main loop, as opposed 319 * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this 320 * doesn't write the PC on exiting the translation loop so you need to ensure 321 * something (gen_a64_update_pc or runtime helper) has done so before we reach 322 * return from cpu_tb_exec. 323 */ 324 #define DISAS_EXIT DISAS_TARGET_9 325 /* CPU state was modified dynamically; no need to exit, but do not chain. */ 326 #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 327 328 #ifdef TARGET_AARCH64 329 void a64_translate_init(void); 330 void gen_a64_update_pc(DisasContext *s, target_long diff); 331 extern const TranslatorOps aarch64_translator_ops; 332 #else 333 static inline void a64_translate_init(void) 334 { 335 } 336 337 static inline void gen_a64_update_pc(DisasContext *s, target_long diff) 338 { 339 } 340 #endif 341 342 void arm_test_cc(DisasCompare *cmp, int cc); 343 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); 344 void arm_gen_test_cc(int cc, TCGLabel *label); 345 MemOp pow2_align(unsigned i); 346 void unallocated_encoding(DisasContext *s); 347 void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, 348 uint32_t syn, uint32_t target_el); 349 void gen_exception_insn(DisasContext *s, target_long pc_diff, 350 int excp, uint32_t syn); 351 352 /* Return state of Alternate Half-precision flag, caller frees result */ 353 static inline TCGv_i32 get_ahp_flag(void) 354 { 355 TCGv_i32 ret = tcg_temp_new_i32(); 356 357 tcg_gen_ld_i32(ret, tcg_env, offsetoflow32(CPUARMState, vfp.fpcr)); 358 tcg_gen_extract_i32(ret, ret, 26, 1); 359 360 return ret; 361 } 362 363 /* Set bits within PSTATE. */ 364 static inline void set_pstate_bits(uint32_t bits) 365 { 366 TCGv_i32 p = tcg_temp_new_i32(); 367 368 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); 369 370 tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); 371 tcg_gen_ori_i32(p, p, bits); 372 tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); 373 } 374 375 /* Clear bits within PSTATE. */ 376 static inline void clear_pstate_bits(uint32_t bits) 377 { 378 TCGv_i32 p = tcg_temp_new_i32(); 379 380 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); 381 382 tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); 383 tcg_gen_andi_i32(p, p, ~bits); 384 tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); 385 } 386 387 /* If the singlestep state is Active-not-pending, advance to Active-pending. */ 388 static inline void gen_ss_advance(DisasContext *s) 389 { 390 if (s->ss_active) { 391 s->pstate_ss = 0; 392 clear_pstate_bits(PSTATE_SS); 393 } 394 } 395 396 /* Generate an architectural singlestep exception */ 397 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) 398 { 399 /* Fill in the same_el field of the syndrome in the helper. */ 400 uint32_t syn = syn_swstep(false, isv, ex); 401 gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn)); 402 } 403 404 /* 405 * Given a VFP floating point constant encoded into an 8 bit immediate in an 406 * instruction, expand it to the actual constant value of the specified 407 * size, as per the VFPExpandImm() pseudocode in the Arm ARM. 408 */ 409 uint64_t vfp_expand_imm(int size, uint8_t imm8); 410 411 static inline void gen_vfp_absh(TCGv_i32 d, TCGv_i32 s) 412 { 413 tcg_gen_andi_i32(d, s, INT16_MAX); 414 } 415 416 static inline void gen_vfp_abss(TCGv_i32 d, TCGv_i32 s) 417 { 418 tcg_gen_andi_i32(d, s, INT32_MAX); 419 } 420 421 static inline void gen_vfp_absd(TCGv_i64 d, TCGv_i64 s) 422 { 423 tcg_gen_andi_i64(d, s, INT64_MAX); 424 } 425 426 static inline void gen_vfp_negh(TCGv_i32 d, TCGv_i32 s) 427 { 428 tcg_gen_xori_i32(d, s, 1u << 15); 429 } 430 431 static inline void gen_vfp_negs(TCGv_i32 d, TCGv_i32 s) 432 { 433 tcg_gen_xori_i32(d, s, 1u << 31); 434 } 435 436 static inline void gen_vfp_negd(TCGv_i64 d, TCGv_i64 s) 437 { 438 tcg_gen_xori_i64(d, s, 1ull << 63); 439 } 440 441 /* Vector operations shared between ARM and AArch64. */ 442 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 443 uint32_t opr_sz, uint32_t max_sz); 444 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 445 uint32_t opr_sz, uint32_t max_sz); 446 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 447 uint32_t opr_sz, uint32_t max_sz); 448 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 449 uint32_t opr_sz, uint32_t max_sz); 450 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 451 uint32_t opr_sz, uint32_t max_sz); 452 453 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 454 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 455 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 456 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 457 458 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 459 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 460 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 461 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 462 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 463 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 464 void gen_gvec_srshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 465 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 466 void gen_gvec_urshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 467 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 468 void gen_neon_sqshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 469 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 470 void gen_neon_uqshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 471 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 472 void gen_neon_sqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 473 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 474 void gen_neon_uqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 475 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 476 477 void gen_neon_sqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 478 int64_t c, uint32_t opr_sz, uint32_t max_sz); 479 void gen_neon_uqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 480 int64_t c, uint32_t opr_sz, uint32_t max_sz); 481 void gen_neon_sqshlui(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 482 int64_t c, uint32_t opr_sz, uint32_t max_sz); 483 484 void gen_gvec_shadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 485 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 486 void gen_gvec_uhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 487 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 488 void gen_gvec_shsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 489 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 490 void gen_gvec_uhsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 491 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 492 void gen_gvec_srhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 493 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 494 void gen_gvec_urhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 495 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 496 497 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 498 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); 499 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); 500 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 501 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 502 503 void gen_uqadd_bhs(TCGv_i64 res, TCGv_i64 qc, 504 TCGv_i64 a, TCGv_i64 b, MemOp esz); 505 void gen_uqadd_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 506 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 507 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 508 509 void gen_sqadd_bhs(TCGv_i64 res, TCGv_i64 qc, 510 TCGv_i64 a, TCGv_i64 b, MemOp esz); 511 void gen_sqadd_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 512 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 513 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 514 515 void gen_uqsub_bhs(TCGv_i64 res, TCGv_i64 qc, 516 TCGv_i64 a, TCGv_i64 b, MemOp esz); 517 void gen_uqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 518 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 519 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 520 521 void gen_sqsub_bhs(TCGv_i64 res, TCGv_i64 qc, 522 TCGv_i64 a, TCGv_i64 b, MemOp esz); 523 void gen_sqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b); 524 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 525 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 526 527 void gen_gvec_sshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 528 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 529 void gen_gvec_ushr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 530 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 531 532 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 533 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 534 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 535 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 536 537 void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh); 538 void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh); 539 void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh); 540 void gen_urshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh); 541 542 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 543 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 544 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 545 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 546 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 547 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 548 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 549 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 550 551 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 552 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 553 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 554 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 555 556 void gen_gvec_sqdmulh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 557 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 558 void gen_gvec_sqrdmulh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 559 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 560 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 561 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 562 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 563 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 564 565 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 566 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 567 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 568 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 569 570 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 571 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 572 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 573 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 574 575 void gen_gvec_addp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 576 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 577 void gen_gvec_smaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 578 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 579 void gen_gvec_sminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 580 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 581 void gen_gvec_umaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 582 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 583 void gen_gvec_uminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 584 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 585 586 void gen_gvec_cls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 587 uint32_t opr_sz, uint32_t max_sz); 588 void gen_gvec_clz(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 589 uint32_t opr_sz, uint32_t max_sz); 590 void gen_gvec_cnt(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 591 uint32_t opr_sz, uint32_t max_sz); 592 void gen_gvec_rbit(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 593 uint32_t opr_sz, uint32_t max_sz); 594 void gen_gvec_rev16(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 595 uint32_t opr_sz, uint32_t max_sz); 596 void gen_gvec_rev32(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 597 uint32_t opr_sz, uint32_t max_sz); 598 void gen_gvec_rev64(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 599 uint32_t opr_sz, uint32_t max_sz); 600 601 void gen_gvec_saddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 602 uint32_t opr_sz, uint32_t max_sz); 603 void gen_gvec_sadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 604 uint32_t opr_sz, uint32_t max_sz); 605 void gen_gvec_uaddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 606 uint32_t opr_sz, uint32_t max_sz); 607 void gen_gvec_uadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 608 uint32_t opr_sz, uint32_t max_sz); 609 610 /* These exclusively manipulate the sign bit. */ 611 void gen_gvec_fabs(unsigned vece, uint32_t dofs, uint32_t aofs, 612 uint32_t oprsz, uint32_t maxsz); 613 void gen_gvec_fneg(unsigned vece, uint32_t dofs, uint32_t aofs, 614 uint32_t oprsz, uint32_t maxsz); 615 616 void gen_gvec_urecpe(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 617 uint32_t opr_sz, uint32_t max_sz); 618 void gen_gvec_ursqrte(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 619 uint32_t opr_sz, uint32_t max_sz); 620 621 /* 622 * Forward to the isar_feature_* tests given a DisasContext pointer. 623 */ 624 #define dc_isar_feature(name, ctx) \ 625 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); }) 626 627 /* Note that the gvec expanders operate on offsets + sizes. */ 628 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); 629 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, 630 uint32_t, uint32_t); 631 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, 632 uint32_t, uint32_t, uint32_t); 633 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t, 634 uint32_t, uint32_t, uint32_t); 635 636 /* Function prototype for gen_ functions for calling Neon helpers */ 637 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); 638 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); 639 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); 640 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); 641 typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, 642 TCGv_i32, TCGv_i32); 643 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); 644 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); 645 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); 646 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); 647 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); 648 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr); 649 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); 650 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); 651 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); 652 typedef void NeonGenOne64OpEnvFn(TCGv_i64, TCGv_env, TCGv_i64); 653 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); 654 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 655 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 656 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); 657 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); 658 typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); 659 typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); 660 typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); 661 662 /** 663 * arm_tbflags_from_tb: 664 * @tb: the TranslationBlock 665 * 666 * Extract the flag values from @tb. 667 */ 668 static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) 669 { 670 return (CPUARMTBFlags){ tb->flags, tb->cs_base }; 671 } 672 673 /** 674 * fpstatus_ptr: return TCGv_ptr to the specified fp_status field 675 * 676 * We have multiple softfloat float_status fields in the Arm CPU state struct 677 * (see the comment in cpu.h for details). Return a TCGv_ptr which has 678 * been set up to point to the requested field in the CPU state struct. 679 */ 680 static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) 681 { 682 TCGv_ptr statusptr = tcg_temp_new_ptr(); 683 int offset = offsetof(CPUARMState, vfp.fp_status[flavour]); 684 685 tcg_gen_addi_ptr(statusptr, tcg_env, offset); 686 return statusptr; 687 } 688 689 /** 690 * finalize_memop_atom: 691 * @s: DisasContext 692 * @opc: size+sign+align of the memory operation 693 * @atom: atomicity of the memory operation 694 * 695 * Build the complete MemOp for a memory operation, including alignment, 696 * endianness, and atomicity. 697 * 698 * If (op & MO_AMASK) then the operation already contains the required 699 * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally 700 * unaligned operation, e.g. for AccType_NORMAL. 701 * 702 * In the latter case, there are configuration bits that require alignment, 703 * and this is applied here. Note that there is no way to indicate that 704 * no alignment should ever be enforced; this must be handled manually. 705 */ 706 static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp atom) 707 { 708 if (s->align_mem && !(opc & MO_AMASK)) { 709 opc |= MO_ALIGN; 710 } 711 return opc | atom | s->be_data; 712 } 713 714 /** 715 * finalize_memop: 716 * @s: DisasContext 717 * @opc: size+sign+align of the memory operation 718 * 719 * Like finalize_memop_atom, but with default atomicity. 720 */ 721 static inline MemOp finalize_memop(DisasContext *s, MemOp opc) 722 { 723 MemOp atom = s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN; 724 return finalize_memop_atom(s, opc, atom); 725 } 726 727 /** 728 * finalize_memop_pair: 729 * @s: DisasContext 730 * @opc: size+sign+align of the memory operation 731 * 732 * Like finalize_memop_atom, but with atomicity for a pair. 733 * C.f. Pseudocode for Mem[], operand ispair. 734 */ 735 static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc) 736 { 737 MemOp atom = s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR; 738 return finalize_memop_atom(s, opc, atom); 739 } 740 741 /** 742 * finalize_memop_asimd: 743 * @s: DisasContext 744 * @opc: size+sign+align of the memory operation 745 * 746 * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD. 747 */ 748 static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc) 749 { 750 /* 751 * In the pseudocode for Mem[], with AccessType_ASIMD, size == 16, 752 * if IsAligned(8), the first case provides separate atomicity for 753 * the pair of 64-bit accesses. If !IsAligned(8), the middle cases 754 * do not apply, and we're left with the final case of no atomicity. 755 * Thus MO_ATOM_IFALIGN_PAIR. 756 * 757 * For other sizes, normal LSE2 rules apply. 758 */ 759 if ((opc & MO_SIZE) == MO_128) { 760 return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR); 761 } 762 return finalize_memop(s, opc); 763 } 764 765 /** 766 * asimd_imm_const: Expand an encoded SIMD constant value 767 * 768 * Expand a SIMD constant value. This is essentially the pseudocode 769 * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for 770 * VMVN and VBIC (when cmode < 14 && op == 1). 771 * 772 * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; 773 * callers must catch this; we return the 64-bit constant value defined 774 * for AArch64. 775 * 776 * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but 777 * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; 778 * we produce an immediate constant value of 0 in these cases. 779 */ 780 uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); 781 782 /* 783 * gen_disas_label: 784 * Create a label and cache a copy of pc_save. 785 */ 786 static inline DisasLabel gen_disas_label(DisasContext *s) 787 { 788 return (DisasLabel){ 789 .label = gen_new_label(), 790 .pc_save = s->pc_save, 791 }; 792 } 793 794 /* 795 * set_disas_label: 796 * Emit a label and restore the cached copy of pc_save. 797 */ 798 static inline void set_disas_label(DisasContext *s, DisasLabel l) 799 { 800 gen_set_label(l.label); 801 s->pc_save = l.pc_save; 802 } 803 804 static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key) 805 { 806 TCGv_ptr ret = tcg_temp_new_ptr(); 807 gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key)); 808 return ret; 809 } 810 811 /* 812 * Set and reset rounding mode around another operation. 813 */ 814 static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst) 815 { 816 TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode)); 817 TCGv_i32 old = tcg_temp_new_i32(); 818 819 gen_helper_set_rmode(old, new, fpst); 820 return old; 821 } 822 823 static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst) 824 { 825 gen_helper_set_rmode(old, old, fpst); 826 } 827 828 /* 829 * Helpers for implementing sets of trans_* functions. 830 * Defer the implementation of NAME to FUNC, with optional extra arguments. 831 */ 832 #define TRANS(NAME, FUNC, ...) \ 833 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 834 { return FUNC(s, __VA_ARGS__); } 835 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \ 836 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 837 { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } 838 839 #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ 840 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 841 { \ 842 s->is_nonstreaming = true; \ 843 return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ 844 } 845 846 #endif /* TARGET_ARM_TRANSLATE_H */ 847