xref: /qemu/target/arm/tcg/translate-mve.c (revision d3cd965c846bb350637090d2d11bc578b79f87cd)
1 /*
2  *  ARM translation: M-profile MVE instructions
3  *
4  *  Copyright (c) 2021 Linaro, Ltd.
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "tcg/tcg-op.h"
22 #include "tcg/tcg-op-gvec.h"
23 #include "exec/exec-all.h"
24 #include "exec/gen-icount.h"
25 #include "translate.h"
26 #include "translate-a32.h"
27 
28 static inline int vidup_imm(DisasContext *s, int x)
29 {
30     return 1 << x;
31 }
32 
33 /* Include the generated decoder */
34 #include "decode-mve.c.inc"
35 
36 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
37 typedef void MVEGenLdStSGFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
38 typedef void MVEGenLdStIlFn(TCGv_ptr, TCGv_i32, TCGv_i32);
39 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
40 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
41 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
42 typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
43 typedef void MVEGenLongDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
44 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
45 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
46 typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32);
47 typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
48 typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
49 typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
50 typedef void MVEGenVABAVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
51 typedef void MVEGenDualAccOpFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
52 
53 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
54 static inline long mve_qreg_offset(unsigned reg)
55 {
56     return offsetof(CPUARMState, vfp.zregs[reg].d[0]);
57 }
58 
59 static TCGv_ptr mve_qreg_ptr(unsigned reg)
60 {
61     TCGv_ptr ret = tcg_temp_new_ptr();
62     tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg));
63     return ret;
64 }
65 
66 static bool mve_check_qreg_bank(DisasContext *s, int qmask)
67 {
68     /*
69      * Check whether Qregs are in range. For v8.1M only Q0..Q7
70      * are supported, see VFPSmallRegisterBank().
71      */
72     return qmask < 8;
73 }
74 
75 bool mve_eci_check(DisasContext *s)
76 {
77     /*
78      * This is a beatwise insn: check that ECI is valid (not a
79      * reserved value) and note that we are handling it.
80      * Return true if OK, false if we generated an exception.
81      */
82     s->eci_handled = true;
83     switch (s->eci) {
84     case ECI_NONE:
85     case ECI_A0:
86     case ECI_A0A1:
87     case ECI_A0A1A2:
88     case ECI_A0A1A2B0:
89         return true;
90     default:
91         /* Reserved value: INVSTATE UsageFault */
92         gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
93                            default_exception_el(s));
94         return false;
95     }
96 }
97 
98 void mve_update_eci(DisasContext *s)
99 {
100     /*
101      * The helper function will always update the CPUState field,
102      * so we only need to update the DisasContext field.
103      */
104     if (s->eci) {
105         s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE;
106     }
107 }
108 
109 void mve_update_and_store_eci(DisasContext *s)
110 {
111     /*
112      * For insns which don't call a helper function that will call
113      * mve_advance_vpt(), this version updates s->eci and also stores
114      * it out to the CPUState field.
115      */
116     if (s->eci) {
117         mve_update_eci(s);
118         store_cpu_field(tcg_constant_i32(s->eci << 4), condexec_bits);
119     }
120 }
121 
122 static bool mve_skip_first_beat(DisasContext *s)
123 {
124     /* Return true if PSR.ECI says we must skip the first beat of this insn */
125     switch (s->eci) {
126     case ECI_NONE:
127         return false;
128     case ECI_A0:
129     case ECI_A0A1:
130     case ECI_A0A1A2:
131     case ECI_A0A1A2B0:
132         return true;
133     default:
134         g_assert_not_reached();
135     }
136 }
137 
138 static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
139                     unsigned msize)
140 {
141     TCGv_i32 addr;
142     uint32_t offset;
143     TCGv_ptr qreg;
144 
145     if (!dc_isar_feature(aa32_mve, s) ||
146         !mve_check_qreg_bank(s, a->qd) ||
147         !fn) {
148         return false;
149     }
150 
151     /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
152     if (a->rn == 15 || (a->rn == 13 && a->w)) {
153         return false;
154     }
155 
156     if (!mve_eci_check(s) || !vfp_access_check(s)) {
157         return true;
158     }
159 
160     offset = a->imm << msize;
161     if (!a->a) {
162         offset = -offset;
163     }
164     addr = load_reg(s, a->rn);
165     if (a->p) {
166         tcg_gen_addi_i32(addr, addr, offset);
167     }
168 
169     qreg = mve_qreg_ptr(a->qd);
170     fn(cpu_env, qreg, addr);
171     tcg_temp_free_ptr(qreg);
172 
173     /*
174      * Writeback always happens after the last beat of the insn,
175      * regardless of predication
176      */
177     if (a->w) {
178         if (!a->p) {
179             tcg_gen_addi_i32(addr, addr, offset);
180         }
181         store_reg(s, a->rn, addr);
182     } else {
183         tcg_temp_free_i32(addr);
184     }
185     mve_update_eci(s);
186     return true;
187 }
188 
189 static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
190 {
191     static MVEGenLdStFn * const ldstfns[4][2] = {
192         { gen_helper_mve_vstrb, gen_helper_mve_vldrb },
193         { gen_helper_mve_vstrh, gen_helper_mve_vldrh },
194         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
195         { NULL, NULL }
196     };
197     return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
198 }
199 
200 #define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
201     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
202     {                                                           \
203         static MVEGenLdStFn * const ldstfns[2][2] = {           \
204             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
205             { NULL, gen_helper_mve_##ULD },                     \
206         };                                                      \
207         return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
208     }
209 
210 DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
211 DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
212 DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
213 
214 static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a, MVEGenLdStSGFn fn)
215 {
216     TCGv_i32 addr;
217     TCGv_ptr qd, qm;
218 
219     if (!dc_isar_feature(aa32_mve, s) ||
220         !mve_check_qreg_bank(s, a->qd | a->qm) ||
221         !fn || a->rn == 15) {
222         /* Rn case is UNPREDICTABLE */
223         return false;
224     }
225 
226     if (!mve_eci_check(s) || !vfp_access_check(s)) {
227         return true;
228     }
229 
230     addr = load_reg(s, a->rn);
231 
232     qd = mve_qreg_ptr(a->qd);
233     qm = mve_qreg_ptr(a->qm);
234     fn(cpu_env, qd, qm, addr);
235     tcg_temp_free_ptr(qd);
236     tcg_temp_free_ptr(qm);
237     tcg_temp_free_i32(addr);
238     mve_update_eci(s);
239     return true;
240 }
241 
242 /*
243  * The naming scheme here is "vldrb_sg_sh == in-memory byte loads
244  * signextended to halfword elements in register". _os_ indicates that
245  * the offsets in Qm should be scaled by the element size.
246  */
247 /* This macro is just to make the arrays more compact in these functions */
248 #define F(N) gen_helper_mve_##N
249 
250 /* VLDRB/VSTRB (ie msize 1) with OS=1 is UNPREDICTABLE; we UNDEF */
251 static bool trans_VLDR_S_sg(DisasContext *s, arg_vldst_sg *a)
252 {
253     static MVEGenLdStSGFn * const fns[2][4][4] = { {
254             { NULL, F(vldrb_sg_sh), F(vldrb_sg_sw), NULL },
255             { NULL, NULL,           F(vldrh_sg_sw), NULL },
256             { NULL, NULL,           NULL,           NULL },
257             { NULL, NULL,           NULL,           NULL }
258         }, {
259             { NULL, NULL,              NULL,              NULL },
260             { NULL, NULL,              F(vldrh_sg_os_sw), NULL },
261             { NULL, NULL,              NULL,              NULL },
262             { NULL, NULL,              NULL,              NULL }
263         }
264     };
265     if (a->qd == a->qm) {
266         return false; /* UNPREDICTABLE */
267     }
268     return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]);
269 }
270 
271 static bool trans_VLDR_U_sg(DisasContext *s, arg_vldst_sg *a)
272 {
273     static MVEGenLdStSGFn * const fns[2][4][4] = { {
274             { F(vldrb_sg_ub), F(vldrb_sg_uh), F(vldrb_sg_uw), NULL },
275             { NULL,           F(vldrh_sg_uh), F(vldrh_sg_uw), NULL },
276             { NULL,           NULL,           F(vldrw_sg_uw), NULL },
277             { NULL,           NULL,           NULL,           F(vldrd_sg_ud) }
278         }, {
279             { NULL, NULL,              NULL,              NULL },
280             { NULL, F(vldrh_sg_os_uh), F(vldrh_sg_os_uw), NULL },
281             { NULL, NULL,              F(vldrw_sg_os_uw), NULL },
282             { NULL, NULL,              NULL,              F(vldrd_sg_os_ud) }
283         }
284     };
285     if (a->qd == a->qm) {
286         return false; /* UNPREDICTABLE */
287     }
288     return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]);
289 }
290 
291 static bool trans_VSTR_sg(DisasContext *s, arg_vldst_sg *a)
292 {
293     static MVEGenLdStSGFn * const fns[2][4][4] = { {
294             { F(vstrb_sg_ub), F(vstrb_sg_uh), F(vstrb_sg_uw), NULL },
295             { NULL,           F(vstrh_sg_uh), F(vstrh_sg_uw), NULL },
296             { NULL,           NULL,           F(vstrw_sg_uw), NULL },
297             { NULL,           NULL,           NULL,           F(vstrd_sg_ud) }
298         }, {
299             { NULL, NULL,              NULL,              NULL },
300             { NULL, F(vstrh_sg_os_uh), F(vstrh_sg_os_uw), NULL },
301             { NULL, NULL,              F(vstrw_sg_os_uw), NULL },
302             { NULL, NULL,              NULL,              F(vstrd_sg_os_ud) }
303         }
304     };
305     return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]);
306 }
307 
308 #undef F
309 
310 static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_sg_imm *a,
311                            MVEGenLdStSGFn *fn, unsigned msize)
312 {
313     uint32_t offset;
314     TCGv_ptr qd, qm;
315 
316     if (!dc_isar_feature(aa32_mve, s) ||
317         !mve_check_qreg_bank(s, a->qd | a->qm) ||
318         !fn) {
319         return false;
320     }
321 
322     if (!mve_eci_check(s) || !vfp_access_check(s)) {
323         return true;
324     }
325 
326     offset = a->imm << msize;
327     if (!a->a) {
328         offset = -offset;
329     }
330 
331     qd = mve_qreg_ptr(a->qd);
332     qm = mve_qreg_ptr(a->qm);
333     fn(cpu_env, qd, qm, tcg_constant_i32(offset));
334     tcg_temp_free_ptr(qd);
335     tcg_temp_free_ptr(qm);
336     mve_update_eci(s);
337     return true;
338 }
339 
340 static bool trans_VLDRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a)
341 {
342     static MVEGenLdStSGFn * const fns[] = {
343         gen_helper_mve_vldrw_sg_uw,
344         gen_helper_mve_vldrw_sg_wb_uw,
345     };
346     if (a->qd == a->qm) {
347         return false; /* UNPREDICTABLE */
348     }
349     return do_ldst_sg_imm(s, a, fns[a->w], MO_32);
350 }
351 
352 static bool trans_VLDRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a)
353 {
354     static MVEGenLdStSGFn * const fns[] = {
355         gen_helper_mve_vldrd_sg_ud,
356         gen_helper_mve_vldrd_sg_wb_ud,
357     };
358     if (a->qd == a->qm) {
359         return false; /* UNPREDICTABLE */
360     }
361     return do_ldst_sg_imm(s, a, fns[a->w], MO_64);
362 }
363 
364 static bool trans_VSTRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a)
365 {
366     static MVEGenLdStSGFn * const fns[] = {
367         gen_helper_mve_vstrw_sg_uw,
368         gen_helper_mve_vstrw_sg_wb_uw,
369     };
370     return do_ldst_sg_imm(s, a, fns[a->w], MO_32);
371 }
372 
373 static bool trans_VSTRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a)
374 {
375     static MVEGenLdStSGFn * const fns[] = {
376         gen_helper_mve_vstrd_sg_ud,
377         gen_helper_mve_vstrd_sg_wb_ud,
378     };
379     return do_ldst_sg_imm(s, a, fns[a->w], MO_64);
380 }
381 
382 static bool do_vldst_il(DisasContext *s, arg_vldst_il *a, MVEGenLdStIlFn *fn,
383                         int addrinc)
384 {
385     TCGv_i32 rn;
386 
387     if (!dc_isar_feature(aa32_mve, s) ||
388         !mve_check_qreg_bank(s, a->qd) ||
389         !fn || (a->rn == 13 && a->w) || a->rn == 15) {
390         /* Variously UNPREDICTABLE or UNDEF or related-encoding */
391         return false;
392     }
393     if (!mve_eci_check(s) || !vfp_access_check(s)) {
394         return true;
395     }
396 
397     rn = load_reg(s, a->rn);
398     /*
399      * We pass the index of Qd, not a pointer, because the helper must
400      * access multiple Q registers starting at Qd and working up.
401      */
402     fn(cpu_env, tcg_constant_i32(a->qd), rn);
403 
404     if (a->w) {
405         tcg_gen_addi_i32(rn, rn, addrinc);
406         store_reg(s, a->rn, rn);
407     } else {
408         tcg_temp_free_i32(rn);
409     }
410     mve_update_and_store_eci(s);
411     return true;
412 }
413 
414 /* This macro is just to make the arrays more compact in these functions */
415 #define F(N) gen_helper_mve_##N
416 
417 static bool trans_VLD2(DisasContext *s, arg_vldst_il *a)
418 {
419     static MVEGenLdStIlFn * const fns[4][4] = {
420         { F(vld20b), F(vld20h), F(vld20w), NULL, },
421         { F(vld21b), F(vld21h), F(vld21w), NULL, },
422         { NULL, NULL, NULL, NULL },
423         { NULL, NULL, NULL, NULL },
424     };
425     if (a->qd > 6) {
426         return false;
427     }
428     return do_vldst_il(s, a, fns[a->pat][a->size], 32);
429 }
430 
431 static bool trans_VLD4(DisasContext *s, arg_vldst_il *a)
432 {
433     static MVEGenLdStIlFn * const fns[4][4] = {
434         { F(vld40b), F(vld40h), F(vld40w), NULL, },
435         { F(vld41b), F(vld41h), F(vld41w), NULL, },
436         { F(vld42b), F(vld42h), F(vld42w), NULL, },
437         { F(vld43b), F(vld43h), F(vld43w), NULL, },
438     };
439     if (a->qd > 4) {
440         return false;
441     }
442     return do_vldst_il(s, a, fns[a->pat][a->size], 64);
443 }
444 
445 static bool trans_VST2(DisasContext *s, arg_vldst_il *a)
446 {
447     static MVEGenLdStIlFn * const fns[4][4] = {
448         { F(vst20b), F(vst20h), F(vst20w), NULL, },
449         { F(vst21b), F(vst21h), F(vst21w), NULL, },
450         { NULL, NULL, NULL, NULL },
451         { NULL, NULL, NULL, NULL },
452     };
453     if (a->qd > 6) {
454         return false;
455     }
456     return do_vldst_il(s, a, fns[a->pat][a->size], 32);
457 }
458 
459 static bool trans_VST4(DisasContext *s, arg_vldst_il *a)
460 {
461     static MVEGenLdStIlFn * const fns[4][4] = {
462         { F(vst40b), F(vst40h), F(vst40w), NULL, },
463         { F(vst41b), F(vst41h), F(vst41w), NULL, },
464         { F(vst42b), F(vst42h), F(vst42w), NULL, },
465         { F(vst43b), F(vst43h), F(vst43w), NULL, },
466     };
467     if (a->qd > 4) {
468         return false;
469     }
470     return do_vldst_il(s, a, fns[a->pat][a->size], 64);
471 }
472 
473 #undef F
474 
475 static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
476 {
477     TCGv_ptr qd;
478     TCGv_i32 rt;
479 
480     if (!dc_isar_feature(aa32_mve, s) ||
481         !mve_check_qreg_bank(s, a->qd)) {
482         return false;
483     }
484     if (a->rt == 13 || a->rt == 15) {
485         /* UNPREDICTABLE; we choose to UNDEF */
486         return false;
487     }
488     if (!mve_eci_check(s) || !vfp_access_check(s)) {
489         return true;
490     }
491 
492     qd = mve_qreg_ptr(a->qd);
493     rt = load_reg(s, a->rt);
494     tcg_gen_dup_i32(a->size, rt, rt);
495     gen_helper_mve_vdup(cpu_env, qd, rt);
496     tcg_temp_free_ptr(qd);
497     tcg_temp_free_i32(rt);
498     mve_update_eci(s);
499     return true;
500 }
501 
502 static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
503 {
504     TCGv_ptr qd, qm;
505 
506     if (!dc_isar_feature(aa32_mve, s) ||
507         !mve_check_qreg_bank(s, a->qd | a->qm) ||
508         !fn) {
509         return false;
510     }
511 
512     if (!mve_eci_check(s) || !vfp_access_check(s)) {
513         return true;
514     }
515 
516     qd = mve_qreg_ptr(a->qd);
517     qm = mve_qreg_ptr(a->qm);
518     fn(cpu_env, qd, qm);
519     tcg_temp_free_ptr(qd);
520     tcg_temp_free_ptr(qm);
521     mve_update_eci(s);
522     return true;
523 }
524 
525 #define DO_1OP(INSN, FN)                                        \
526     static bool trans_##INSN(DisasContext *s, arg_1op *a)       \
527     {                                                           \
528         static MVEGenOneOpFn * const fns[] = {                  \
529             gen_helper_mve_##FN##b,                             \
530             gen_helper_mve_##FN##h,                             \
531             gen_helper_mve_##FN##w,                             \
532             NULL,                                               \
533         };                                                      \
534         return do_1op(s, a, fns[a->size]);                      \
535     }
536 
537 DO_1OP(VCLZ, vclz)
538 DO_1OP(VCLS, vcls)
539 DO_1OP(VABS, vabs)
540 DO_1OP(VNEG, vneg)
541 DO_1OP(VQABS, vqabs)
542 DO_1OP(VQNEG, vqneg)
543 DO_1OP(VMAXA, vmaxa)
544 DO_1OP(VMINA, vmina)
545 
546 /* Narrowing moves: only size 0 and 1 are valid */
547 #define DO_VMOVN(INSN, FN) \
548     static bool trans_##INSN(DisasContext *s, arg_1op *a)       \
549     {                                                           \
550         static MVEGenOneOpFn * const fns[] = {                  \
551             gen_helper_mve_##FN##b,                             \
552             gen_helper_mve_##FN##h,                             \
553             NULL,                                               \
554             NULL,                                               \
555         };                                                      \
556         return do_1op(s, a, fns[a->size]);                      \
557     }
558 
559 DO_VMOVN(VMOVNB, vmovnb)
560 DO_VMOVN(VMOVNT, vmovnt)
561 DO_VMOVN(VQMOVUNB, vqmovunb)
562 DO_VMOVN(VQMOVUNT, vqmovunt)
563 DO_VMOVN(VQMOVN_BS, vqmovnbs)
564 DO_VMOVN(VQMOVN_TS, vqmovnts)
565 DO_VMOVN(VQMOVN_BU, vqmovnbu)
566 DO_VMOVN(VQMOVN_TU, vqmovntu)
567 
568 static bool trans_VREV16(DisasContext *s, arg_1op *a)
569 {
570     static MVEGenOneOpFn * const fns[] = {
571         gen_helper_mve_vrev16b,
572         NULL,
573         NULL,
574         NULL,
575     };
576     return do_1op(s, a, fns[a->size]);
577 }
578 
579 static bool trans_VREV32(DisasContext *s, arg_1op *a)
580 {
581     static MVEGenOneOpFn * const fns[] = {
582         gen_helper_mve_vrev32b,
583         gen_helper_mve_vrev32h,
584         NULL,
585         NULL,
586     };
587     return do_1op(s, a, fns[a->size]);
588 }
589 
590 static bool trans_VREV64(DisasContext *s, arg_1op *a)
591 {
592     static MVEGenOneOpFn * const fns[] = {
593         gen_helper_mve_vrev64b,
594         gen_helper_mve_vrev64h,
595         gen_helper_mve_vrev64w,
596         NULL,
597     };
598     return do_1op(s, a, fns[a->size]);
599 }
600 
601 static bool trans_VMVN(DisasContext *s, arg_1op *a)
602 {
603     return do_1op(s, a, gen_helper_mve_vmvn);
604 }
605 
606 static bool trans_VABS_fp(DisasContext *s, arg_1op *a)
607 {
608     static MVEGenOneOpFn * const fns[] = {
609         NULL,
610         gen_helper_mve_vfabsh,
611         gen_helper_mve_vfabss,
612         NULL,
613     };
614     if (!dc_isar_feature(aa32_mve_fp, s)) {
615         return false;
616     }
617     return do_1op(s, a, fns[a->size]);
618 }
619 
620 static bool trans_VNEG_fp(DisasContext *s, arg_1op *a)
621 {
622     static MVEGenOneOpFn * const fns[] = {
623         NULL,
624         gen_helper_mve_vfnegh,
625         gen_helper_mve_vfnegs,
626         NULL,
627     };
628     if (!dc_isar_feature(aa32_mve_fp, s)) {
629         return false;
630     }
631     return do_1op(s, a, fns[a->size]);
632 }
633 
634 static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn)
635 {
636     TCGv_ptr qd, qn, qm;
637 
638     if (!dc_isar_feature(aa32_mve, s) ||
639         !mve_check_qreg_bank(s, a->qd | a->qn | a->qm) ||
640         !fn) {
641         return false;
642     }
643     if (!mve_eci_check(s) || !vfp_access_check(s)) {
644         return true;
645     }
646 
647     qd = mve_qreg_ptr(a->qd);
648     qn = mve_qreg_ptr(a->qn);
649     qm = mve_qreg_ptr(a->qm);
650     fn(cpu_env, qd, qn, qm);
651     tcg_temp_free_ptr(qd);
652     tcg_temp_free_ptr(qn);
653     tcg_temp_free_ptr(qm);
654     mve_update_eci(s);
655     return true;
656 }
657 
658 #define DO_LOGIC(INSN, HELPER)                                  \
659     static bool trans_##INSN(DisasContext *s, arg_2op *a)       \
660     {                                                           \
661         return do_2op(s, a, HELPER);                            \
662     }
663 
664 DO_LOGIC(VAND, gen_helper_mve_vand)
665 DO_LOGIC(VBIC, gen_helper_mve_vbic)
666 DO_LOGIC(VORR, gen_helper_mve_vorr)
667 DO_LOGIC(VORN, gen_helper_mve_vorn)
668 DO_LOGIC(VEOR, gen_helper_mve_veor)
669 
670 DO_LOGIC(VPSEL, gen_helper_mve_vpsel)
671 
672 #define DO_2OP(INSN, FN) \
673     static bool trans_##INSN(DisasContext *s, arg_2op *a)       \
674     {                                                           \
675         static MVEGenTwoOpFn * const fns[] = {                  \
676             gen_helper_mve_##FN##b,                             \
677             gen_helper_mve_##FN##h,                             \
678             gen_helper_mve_##FN##w,                             \
679             NULL,                                               \
680         };                                                      \
681         return do_2op(s, a, fns[a->size]);                      \
682     }
683 
684 DO_2OP(VADD, vadd)
685 DO_2OP(VSUB, vsub)
686 DO_2OP(VMUL, vmul)
687 DO_2OP(VMULH_S, vmulhs)
688 DO_2OP(VMULH_U, vmulhu)
689 DO_2OP(VRMULH_S, vrmulhs)
690 DO_2OP(VRMULH_U, vrmulhu)
691 DO_2OP(VMAX_S, vmaxs)
692 DO_2OP(VMAX_U, vmaxu)
693 DO_2OP(VMIN_S, vmins)
694 DO_2OP(VMIN_U, vminu)
695 DO_2OP(VABD_S, vabds)
696 DO_2OP(VABD_U, vabdu)
697 DO_2OP(VHADD_S, vhadds)
698 DO_2OP(VHADD_U, vhaddu)
699 DO_2OP(VHSUB_S, vhsubs)
700 DO_2OP(VHSUB_U, vhsubu)
701 DO_2OP(VMULL_BS, vmullbs)
702 DO_2OP(VMULL_BU, vmullbu)
703 DO_2OP(VMULL_TS, vmullts)
704 DO_2OP(VMULL_TU, vmulltu)
705 DO_2OP(VQDMULH, vqdmulh)
706 DO_2OP(VQRDMULH, vqrdmulh)
707 DO_2OP(VQADD_S, vqadds)
708 DO_2OP(VQADD_U, vqaddu)
709 DO_2OP(VQSUB_S, vqsubs)
710 DO_2OP(VQSUB_U, vqsubu)
711 DO_2OP(VSHL_S, vshls)
712 DO_2OP(VSHL_U, vshlu)
713 DO_2OP(VRSHL_S, vrshls)
714 DO_2OP(VRSHL_U, vrshlu)
715 DO_2OP(VQSHL_S, vqshls)
716 DO_2OP(VQSHL_U, vqshlu)
717 DO_2OP(VQRSHL_S, vqrshls)
718 DO_2OP(VQRSHL_U, vqrshlu)
719 DO_2OP(VQDMLADH, vqdmladh)
720 DO_2OP(VQDMLADHX, vqdmladhx)
721 DO_2OP(VQRDMLADH, vqrdmladh)
722 DO_2OP(VQRDMLADHX, vqrdmladhx)
723 DO_2OP(VQDMLSDH, vqdmlsdh)
724 DO_2OP(VQDMLSDHX, vqdmlsdhx)
725 DO_2OP(VQRDMLSDH, vqrdmlsdh)
726 DO_2OP(VQRDMLSDHX, vqrdmlsdhx)
727 DO_2OP(VRHADD_S, vrhadds)
728 DO_2OP(VRHADD_U, vrhaddu)
729 /*
730  * VCADD Qd == Qm at size MO_32 is UNPREDICTABLE; we choose not to diagnose
731  * so we can reuse the DO_2OP macro. (Our implementation calculates the
732  * "expected" results in this case.) Similarly for VHCADD.
733  */
734 DO_2OP(VCADD90, vcadd90)
735 DO_2OP(VCADD270, vcadd270)
736 DO_2OP(VHCADD90, vhcadd90)
737 DO_2OP(VHCADD270, vhcadd270)
738 
739 static bool trans_VQDMULLB(DisasContext *s, arg_2op *a)
740 {
741     static MVEGenTwoOpFn * const fns[] = {
742         NULL,
743         gen_helper_mve_vqdmullbh,
744         gen_helper_mve_vqdmullbw,
745         NULL,
746     };
747     if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) {
748         /* UNPREDICTABLE; we choose to undef */
749         return false;
750     }
751     return do_2op(s, a, fns[a->size]);
752 }
753 
754 static bool trans_VQDMULLT(DisasContext *s, arg_2op *a)
755 {
756     static MVEGenTwoOpFn * const fns[] = {
757         NULL,
758         gen_helper_mve_vqdmullth,
759         gen_helper_mve_vqdmulltw,
760         NULL,
761     };
762     if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) {
763         /* UNPREDICTABLE; we choose to undef */
764         return false;
765     }
766     return do_2op(s, a, fns[a->size]);
767 }
768 
769 static bool trans_VMULLP_B(DisasContext *s, arg_2op *a)
770 {
771     /*
772      * Note that a->size indicates the output size, ie VMULL.P8
773      * is the 8x8->16 operation and a->size is MO_16; VMULL.P16
774      * is the 16x16->32 operation and a->size is MO_32.
775      */
776     static MVEGenTwoOpFn * const fns[] = {
777         NULL,
778         gen_helper_mve_vmullpbh,
779         gen_helper_mve_vmullpbw,
780         NULL,
781     };
782     return do_2op(s, a, fns[a->size]);
783 }
784 
785 static bool trans_VMULLP_T(DisasContext *s, arg_2op *a)
786 {
787     /* a->size is as for trans_VMULLP_B */
788     static MVEGenTwoOpFn * const fns[] = {
789         NULL,
790         gen_helper_mve_vmullpth,
791         gen_helper_mve_vmullptw,
792         NULL,
793     };
794     return do_2op(s, a, fns[a->size]);
795 }
796 
797 /*
798  * VADC and VSBC: these perform an add-with-carry or subtract-with-carry
799  * of the 32-bit elements in each lane of the input vectors, where the
800  * carry-out of each add is the carry-in of the next.  The initial carry
801  * input is either fixed (0 for VADCI, 1 for VSBCI) or is from FPSCR.C
802  * (for VADC and VSBC); the carry out at the end is written back to FPSCR.C.
803  * These insns are subject to beat-wise execution.  Partial execution
804  * of an I=1 (initial carry input fixed) insn which does not
805  * execute the first beat must start with the current FPSCR.NZCV
806  * value, not the fixed constant input.
807  */
808 static bool trans_VADC(DisasContext *s, arg_2op *a)
809 {
810     return do_2op(s, a, gen_helper_mve_vadc);
811 }
812 
813 static bool trans_VADCI(DisasContext *s, arg_2op *a)
814 {
815     if (mve_skip_first_beat(s)) {
816         return trans_VADC(s, a);
817     }
818     return do_2op(s, a, gen_helper_mve_vadci);
819 }
820 
821 static bool trans_VSBC(DisasContext *s, arg_2op *a)
822 {
823     return do_2op(s, a, gen_helper_mve_vsbc);
824 }
825 
826 static bool trans_VSBCI(DisasContext *s, arg_2op *a)
827 {
828     if (mve_skip_first_beat(s)) {
829         return trans_VSBC(s, a);
830     }
831     return do_2op(s, a, gen_helper_mve_vsbci);
832 }
833 
834 #define DO_2OP_FP(INSN, FN)                                     \
835     static bool trans_##INSN(DisasContext *s, arg_2op *a)       \
836     {                                                           \
837         static MVEGenTwoOpFn * const fns[] = {                  \
838             NULL,                                               \
839             gen_helper_mve_##FN##h,                             \
840             gen_helper_mve_##FN##s,                             \
841             NULL,                                               \
842         };                                                      \
843         if (!dc_isar_feature(aa32_mve_fp, s)) {                 \
844             return false;                                       \
845         }                                                       \
846         return do_2op(s, a, fns[a->size]);                      \
847     }
848 
849 DO_2OP_FP(VADD_fp, vfadd)
850 DO_2OP_FP(VSUB_fp, vfsub)
851 DO_2OP_FP(VMUL_fp, vfmul)
852 DO_2OP_FP(VABD_fp, vfabd)
853 DO_2OP_FP(VMAXNM, vmaxnm)
854 DO_2OP_FP(VMINNM, vminnm)
855 DO_2OP_FP(VCADD90_fp, vfcadd90)
856 DO_2OP_FP(VCADD270_fp, vfcadd270)
857 DO_2OP_FP(VFMA, vfma)
858 DO_2OP_FP(VFMS, vfms)
859 DO_2OP_FP(VCMUL0, vcmul0)
860 DO_2OP_FP(VCMUL90, vcmul90)
861 DO_2OP_FP(VCMUL180, vcmul180)
862 DO_2OP_FP(VCMUL270, vcmul270)
863 DO_2OP_FP(VCMLA0, vcmla0)
864 DO_2OP_FP(VCMLA90, vcmla90)
865 DO_2OP_FP(VCMLA180, vcmla180)
866 DO_2OP_FP(VCMLA270, vcmla270)
867 
868 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
869                           MVEGenTwoOpScalarFn fn)
870 {
871     TCGv_ptr qd, qn;
872     TCGv_i32 rm;
873 
874     if (!dc_isar_feature(aa32_mve, s) ||
875         !mve_check_qreg_bank(s, a->qd | a->qn) ||
876         !fn) {
877         return false;
878     }
879     if (a->rm == 13 || a->rm == 15) {
880         /* UNPREDICTABLE */
881         return false;
882     }
883     if (!mve_eci_check(s) || !vfp_access_check(s)) {
884         return true;
885     }
886 
887     qd = mve_qreg_ptr(a->qd);
888     qn = mve_qreg_ptr(a->qn);
889     rm = load_reg(s, a->rm);
890     fn(cpu_env, qd, qn, rm);
891     tcg_temp_free_i32(rm);
892     tcg_temp_free_ptr(qd);
893     tcg_temp_free_ptr(qn);
894     mve_update_eci(s);
895     return true;
896 }
897 
898 #define DO_2OP_SCALAR(INSN, FN)                                 \
899     static bool trans_##INSN(DisasContext *s, arg_2scalar *a)   \
900     {                                                           \
901         static MVEGenTwoOpScalarFn * const fns[] = {            \
902             gen_helper_mve_##FN##b,                             \
903             gen_helper_mve_##FN##h,                             \
904             gen_helper_mve_##FN##w,                             \
905             NULL,                                               \
906         };                                                      \
907         return do_2op_scalar(s, a, fns[a->size]);               \
908     }
909 
910 DO_2OP_SCALAR(VADD_scalar, vadd_scalar)
911 DO_2OP_SCALAR(VSUB_scalar, vsub_scalar)
912 DO_2OP_SCALAR(VMUL_scalar, vmul_scalar)
913 DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar)
914 DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar)
915 DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar)
916 DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar)
917 DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar)
918 DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar)
919 DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar)
920 DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar)
921 DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar)
922 DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar)
923 DO_2OP_SCALAR(VBRSR, vbrsr)
924 DO_2OP_SCALAR(VMLA, vmla)
925 DO_2OP_SCALAR(VMLAS, vmlas)
926 DO_2OP_SCALAR(VQDMLAH, vqdmlah)
927 DO_2OP_SCALAR(VQRDMLAH, vqrdmlah)
928 DO_2OP_SCALAR(VQDMLASH, vqdmlash)
929 DO_2OP_SCALAR(VQRDMLASH, vqrdmlash)
930 
931 static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a)
932 {
933     static MVEGenTwoOpScalarFn * const fns[] = {
934         NULL,
935         gen_helper_mve_vqdmullb_scalarh,
936         gen_helper_mve_vqdmullb_scalarw,
937         NULL,
938     };
939     if (a->qd == a->qn && a->size == MO_32) {
940         /* UNPREDICTABLE; we choose to undef */
941         return false;
942     }
943     return do_2op_scalar(s, a, fns[a->size]);
944 }
945 
946 static bool trans_VQDMULLT_scalar(DisasContext *s, arg_2scalar *a)
947 {
948     static MVEGenTwoOpScalarFn * const fns[] = {
949         NULL,
950         gen_helper_mve_vqdmullt_scalarh,
951         gen_helper_mve_vqdmullt_scalarw,
952         NULL,
953     };
954     if (a->qd == a->qn && a->size == MO_32) {
955         /* UNPREDICTABLE; we choose to undef */
956         return false;
957     }
958     return do_2op_scalar(s, a, fns[a->size]);
959 }
960 
961 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
962                              MVEGenLongDualAccOpFn *fn)
963 {
964     TCGv_ptr qn, qm;
965     TCGv_i64 rda;
966     TCGv_i32 rdalo, rdahi;
967 
968     if (!dc_isar_feature(aa32_mve, s) ||
969         !mve_check_qreg_bank(s, a->qn | a->qm) ||
970         !fn) {
971         return false;
972     }
973     /*
974      * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
975      * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
976      */
977     if (a->rdahi == 13 || a->rdahi == 15) {
978         return false;
979     }
980     if (!mve_eci_check(s) || !vfp_access_check(s)) {
981         return true;
982     }
983 
984     qn = mve_qreg_ptr(a->qn);
985     qm = mve_qreg_ptr(a->qm);
986 
987     /*
988      * This insn is subject to beat-wise execution. Partial execution
989      * of an A=0 (no-accumulate) insn which does not execute the first
990      * beat must start with the current rda value, not 0.
991      */
992     if (a->a || mve_skip_first_beat(s)) {
993         rda = tcg_temp_new_i64();
994         rdalo = load_reg(s, a->rdalo);
995         rdahi = load_reg(s, a->rdahi);
996         tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
997         tcg_temp_free_i32(rdalo);
998         tcg_temp_free_i32(rdahi);
999     } else {
1000         rda = tcg_const_i64(0);
1001     }
1002 
1003     fn(rda, cpu_env, qn, qm, rda);
1004     tcg_temp_free_ptr(qn);
1005     tcg_temp_free_ptr(qm);
1006 
1007     rdalo = tcg_temp_new_i32();
1008     rdahi = tcg_temp_new_i32();
1009     tcg_gen_extrl_i64_i32(rdalo, rda);
1010     tcg_gen_extrh_i64_i32(rdahi, rda);
1011     store_reg(s, a->rdalo, rdalo);
1012     store_reg(s, a->rdahi, rdahi);
1013     tcg_temp_free_i64(rda);
1014     mve_update_eci(s);
1015     return true;
1016 }
1017 
1018 static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a)
1019 {
1020     static MVEGenLongDualAccOpFn * const fns[4][2] = {
1021         { NULL, NULL },
1022         { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh },
1023         { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw },
1024         { NULL, NULL },
1025     };
1026     return do_long_dual_acc(s, a, fns[a->size][a->x]);
1027 }
1028 
1029 static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a)
1030 {
1031     static MVEGenLongDualAccOpFn * const fns[4][2] = {
1032         { NULL, NULL },
1033         { gen_helper_mve_vmlaldavuh, NULL },
1034         { gen_helper_mve_vmlaldavuw, NULL },
1035         { NULL, NULL },
1036     };
1037     return do_long_dual_acc(s, a, fns[a->size][a->x]);
1038 }
1039 
1040 static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a)
1041 {
1042     static MVEGenLongDualAccOpFn * const fns[4][2] = {
1043         { NULL, NULL },
1044         { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh },
1045         { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw },
1046         { NULL, NULL },
1047     };
1048     return do_long_dual_acc(s, a, fns[a->size][a->x]);
1049 }
1050 
1051 static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a)
1052 {
1053     static MVEGenLongDualAccOpFn * const fns[] = {
1054         gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw,
1055     };
1056     return do_long_dual_acc(s, a, fns[a->x]);
1057 }
1058 
1059 static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a)
1060 {
1061     static MVEGenLongDualAccOpFn * const fns[] = {
1062         gen_helper_mve_vrmlaldavhuw, NULL,
1063     };
1064     return do_long_dual_acc(s, a, fns[a->x]);
1065 }
1066 
1067 static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a)
1068 {
1069     static MVEGenLongDualAccOpFn * const fns[] = {
1070         gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw,
1071     };
1072     return do_long_dual_acc(s, a, fns[a->x]);
1073 }
1074 
1075 static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
1076 {
1077     TCGv_ptr qn, qm;
1078     TCGv_i32 rda;
1079 
1080     if (!dc_isar_feature(aa32_mve, s) ||
1081         !mve_check_qreg_bank(s, a->qn) ||
1082         !fn) {
1083         return false;
1084     }
1085     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1086         return true;
1087     }
1088 
1089     qn = mve_qreg_ptr(a->qn);
1090     qm = mve_qreg_ptr(a->qm);
1091 
1092     /*
1093      * This insn is subject to beat-wise execution. Partial execution
1094      * of an A=0 (no-accumulate) insn which does not execute the first
1095      * beat must start with the current rda value, not 0.
1096      */
1097     if (a->a || mve_skip_first_beat(s)) {
1098         rda = load_reg(s, a->rda);
1099     } else {
1100         rda = tcg_const_i32(0);
1101     }
1102 
1103     fn(rda, cpu_env, qn, qm, rda);
1104     store_reg(s, a->rda, rda);
1105     tcg_temp_free_ptr(qn);
1106     tcg_temp_free_ptr(qm);
1107 
1108     mve_update_eci(s);
1109     return true;
1110 }
1111 
1112 #define DO_DUAL_ACC(INSN, FN)                                           \
1113     static bool trans_##INSN(DisasContext *s, arg_vmladav *a)           \
1114     {                                                                   \
1115         static MVEGenDualAccOpFn * const fns[4][2] = {                  \
1116             { gen_helper_mve_##FN##b, gen_helper_mve_##FN##xb },        \
1117             { gen_helper_mve_##FN##h, gen_helper_mve_##FN##xh },        \
1118             { gen_helper_mve_##FN##w, gen_helper_mve_##FN##xw },        \
1119             { NULL, NULL },                                             \
1120         };                                                              \
1121         return do_dual_acc(s, a, fns[a->size][a->x]);                   \
1122     }
1123 
1124 DO_DUAL_ACC(VMLADAV_S, vmladavs)
1125 DO_DUAL_ACC(VMLSDAV, vmlsdav)
1126 
1127 static bool trans_VMLADAV_U(DisasContext *s, arg_vmladav *a)
1128 {
1129     static MVEGenDualAccOpFn * const fns[4][2] = {
1130         { gen_helper_mve_vmladavub, NULL },
1131         { gen_helper_mve_vmladavuh, NULL },
1132         { gen_helper_mve_vmladavuw, NULL },
1133         { NULL, NULL },
1134     };
1135     return do_dual_acc(s, a, fns[a->size][a->x]);
1136 }
1137 
1138 static void gen_vpst(DisasContext *s, uint32_t mask)
1139 {
1140     /*
1141      * Set the VPR mask fields. We take advantage of MASK01 and MASK23
1142      * being adjacent fields in the register.
1143      *
1144      * Updating the masks is not predicated, but it is subject to beat-wise
1145      * execution, and the mask is updated on the odd-numbered beats.
1146      * So if PSR.ECI says we should skip beat 1, we mustn't update the
1147      * 01 mask field.
1148      */
1149     TCGv_i32 vpr = load_cpu_field(v7m.vpr);
1150     switch (s->eci) {
1151     case ECI_NONE:
1152     case ECI_A0:
1153         /* Update both 01 and 23 fields */
1154         tcg_gen_deposit_i32(vpr, vpr,
1155                             tcg_constant_i32(mask | (mask << 4)),
1156                             R_V7M_VPR_MASK01_SHIFT,
1157                             R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH);
1158         break;
1159     case ECI_A0A1:
1160     case ECI_A0A1A2:
1161     case ECI_A0A1A2B0:
1162         /* Update only the 23 mask field */
1163         tcg_gen_deposit_i32(vpr, vpr,
1164                             tcg_constant_i32(mask),
1165                             R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH);
1166         break;
1167     default:
1168         g_assert_not_reached();
1169     }
1170     store_cpu_field(vpr, v7m.vpr);
1171 }
1172 
1173 static bool trans_VPST(DisasContext *s, arg_VPST *a)
1174 {
1175     /* mask == 0 is a "related encoding" */
1176     if (!dc_isar_feature(aa32_mve, s) || !a->mask) {
1177         return false;
1178     }
1179     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1180         return true;
1181     }
1182     gen_vpst(s, a->mask);
1183     mve_update_and_store_eci(s);
1184     return true;
1185 }
1186 
1187 static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a)
1188 {
1189     /*
1190      * Invert the predicate in VPR.P0. We have call out to
1191      * a helper because this insn itself is beatwise and can
1192      * be predicated.
1193      */
1194     if (!dc_isar_feature(aa32_mve, s)) {
1195         return false;
1196     }
1197     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1198         return true;
1199     }
1200 
1201     gen_helper_mve_vpnot(cpu_env);
1202     mve_update_eci(s);
1203     return true;
1204 }
1205 
1206 static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
1207 {
1208     /* VADDV: vector add across vector */
1209     static MVEGenVADDVFn * const fns[4][2] = {
1210         { gen_helper_mve_vaddvsb, gen_helper_mve_vaddvub },
1211         { gen_helper_mve_vaddvsh, gen_helper_mve_vaddvuh },
1212         { gen_helper_mve_vaddvsw, gen_helper_mve_vaddvuw },
1213         { NULL, NULL }
1214     };
1215     TCGv_ptr qm;
1216     TCGv_i32 rda;
1217 
1218     if (!dc_isar_feature(aa32_mve, s) ||
1219         a->size == 3) {
1220         return false;
1221     }
1222     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1223         return true;
1224     }
1225 
1226     /*
1227      * This insn is subject to beat-wise execution. Partial execution
1228      * of an A=0 (no-accumulate) insn which does not execute the first
1229      * beat must start with the current value of Rda, not zero.
1230      */
1231     if (a->a || mve_skip_first_beat(s)) {
1232         /* Accumulate input from Rda */
1233         rda = load_reg(s, a->rda);
1234     } else {
1235         /* Accumulate starting at zero */
1236         rda = tcg_const_i32(0);
1237     }
1238 
1239     qm = mve_qreg_ptr(a->qm);
1240     fns[a->size][a->u](rda, cpu_env, qm, rda);
1241     store_reg(s, a->rda, rda);
1242     tcg_temp_free_ptr(qm);
1243 
1244     mve_update_eci(s);
1245     return true;
1246 }
1247 
1248 static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
1249 {
1250     /*
1251      * Vector Add Long Across Vector: accumulate the 32-bit
1252      * elements of the vector into a 64-bit result stored in
1253      * a pair of general-purpose registers.
1254      * No need to check Qm's bank: it is only 3 bits in decode.
1255      */
1256     TCGv_ptr qm;
1257     TCGv_i64 rda;
1258     TCGv_i32 rdalo, rdahi;
1259 
1260     if (!dc_isar_feature(aa32_mve, s)) {
1261         return false;
1262     }
1263     /*
1264      * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
1265      * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
1266      */
1267     if (a->rdahi == 13 || a->rdahi == 15) {
1268         return false;
1269     }
1270     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1271         return true;
1272     }
1273 
1274     /*
1275      * This insn is subject to beat-wise execution. Partial execution
1276      * of an A=0 (no-accumulate) insn which does not execute the first
1277      * beat must start with the current value of RdaHi:RdaLo, not zero.
1278      */
1279     if (a->a || mve_skip_first_beat(s)) {
1280         /* Accumulate input from RdaHi:RdaLo */
1281         rda = tcg_temp_new_i64();
1282         rdalo = load_reg(s, a->rdalo);
1283         rdahi = load_reg(s, a->rdahi);
1284         tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
1285         tcg_temp_free_i32(rdalo);
1286         tcg_temp_free_i32(rdahi);
1287     } else {
1288         /* Accumulate starting at zero */
1289         rda = tcg_const_i64(0);
1290     }
1291 
1292     qm = mve_qreg_ptr(a->qm);
1293     if (a->u) {
1294         gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
1295     } else {
1296         gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
1297     }
1298     tcg_temp_free_ptr(qm);
1299 
1300     rdalo = tcg_temp_new_i32();
1301     rdahi = tcg_temp_new_i32();
1302     tcg_gen_extrl_i64_i32(rdalo, rda);
1303     tcg_gen_extrh_i64_i32(rdahi, rda);
1304     store_reg(s, a->rdalo, rdalo);
1305     store_reg(s, a->rdahi, rdahi);
1306     tcg_temp_free_i64(rda);
1307     mve_update_eci(s);
1308     return true;
1309 }
1310 
1311 static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
1312 {
1313     TCGv_ptr qd;
1314     uint64_t imm;
1315 
1316     if (!dc_isar_feature(aa32_mve, s) ||
1317         !mve_check_qreg_bank(s, a->qd) ||
1318         !fn) {
1319         return false;
1320     }
1321     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1322         return true;
1323     }
1324 
1325     imm = asimd_imm_const(a->imm, a->cmode, a->op);
1326 
1327     qd = mve_qreg_ptr(a->qd);
1328     fn(cpu_env, qd, tcg_constant_i64(imm));
1329     tcg_temp_free_ptr(qd);
1330     mve_update_eci(s);
1331     return true;
1332 }
1333 
1334 static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
1335 {
1336     /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
1337     MVEGenOneOpImmFn *fn;
1338 
1339     if ((a->cmode & 1) && a->cmode < 12) {
1340         if (a->op) {
1341             /*
1342              * For op=1, the immediate will be inverted by asimd_imm_const(),
1343              * so the VBIC becomes a logical AND operation.
1344              */
1345             fn = gen_helper_mve_vandi;
1346         } else {
1347             fn = gen_helper_mve_vorri;
1348         }
1349     } else {
1350         /* There is one unallocated cmode/op combination in this space */
1351         if (a->cmode == 15 && a->op == 1) {
1352             return false;
1353         }
1354         /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
1355         fn = gen_helper_mve_vmovi;
1356     }
1357     return do_1imm(s, a, fn);
1358 }
1359 
1360 static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
1361                       bool negateshift)
1362 {
1363     TCGv_ptr qd, qm;
1364     int shift = a->shift;
1365 
1366     if (!dc_isar_feature(aa32_mve, s) ||
1367         !mve_check_qreg_bank(s, a->qd | a->qm) ||
1368         !fn) {
1369         return false;
1370     }
1371     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1372         return true;
1373     }
1374 
1375     /*
1376      * When we handle a right shift insn using a left-shift helper
1377      * which permits a negative shift count to indicate a right-shift,
1378      * we must negate the shift count.
1379      */
1380     if (negateshift) {
1381         shift = -shift;
1382     }
1383 
1384     qd = mve_qreg_ptr(a->qd);
1385     qm = mve_qreg_ptr(a->qm);
1386     fn(cpu_env, qd, qm, tcg_constant_i32(shift));
1387     tcg_temp_free_ptr(qd);
1388     tcg_temp_free_ptr(qm);
1389     mve_update_eci(s);
1390     return true;
1391 }
1392 
1393 #define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
1394     static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
1395     {                                                           \
1396         static MVEGenTwoOpShiftFn * const fns[] = {             \
1397             gen_helper_mve_##FN##b,                             \
1398             gen_helper_mve_##FN##h,                             \
1399             gen_helper_mve_##FN##w,                             \
1400             NULL,                                               \
1401         };                                                      \
1402         return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
1403     }
1404 
1405 DO_2SHIFT(VSHLI, vshli_u, false)
1406 DO_2SHIFT(VQSHLI_S, vqshli_s, false)
1407 DO_2SHIFT(VQSHLI_U, vqshli_u, false)
1408 DO_2SHIFT(VQSHLUI, vqshlui_s, false)
1409 /* These right shifts use a left-shift helper with negated shift count */
1410 DO_2SHIFT(VSHRI_S, vshli_s, true)
1411 DO_2SHIFT(VSHRI_U, vshli_u, true)
1412 DO_2SHIFT(VRSHRI_S, vrshli_s, true)
1413 DO_2SHIFT(VRSHRI_U, vrshli_u, true)
1414 
1415 DO_2SHIFT(VSRI, vsri, false)
1416 DO_2SHIFT(VSLI, vsli, false)
1417 
1418 static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a,
1419                              MVEGenTwoOpShiftFn *fn)
1420 {
1421     TCGv_ptr qda;
1422     TCGv_i32 rm;
1423 
1424     if (!dc_isar_feature(aa32_mve, s) ||
1425         !mve_check_qreg_bank(s, a->qda) ||
1426         a->rm == 13 || a->rm == 15 || !fn) {
1427         /* Rm cases are UNPREDICTABLE */
1428         return false;
1429     }
1430     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1431         return true;
1432     }
1433 
1434     qda = mve_qreg_ptr(a->qda);
1435     rm = load_reg(s, a->rm);
1436     fn(cpu_env, qda, qda, rm);
1437     tcg_temp_free_ptr(qda);
1438     tcg_temp_free_i32(rm);
1439     mve_update_eci(s);
1440     return true;
1441 }
1442 
1443 #define DO_2SHIFT_SCALAR(INSN, FN)                                      \
1444     static bool trans_##INSN(DisasContext *s, arg_shl_scalar *a)        \
1445     {                                                                   \
1446         static MVEGenTwoOpShiftFn * const fns[] = {                     \
1447             gen_helper_mve_##FN##b,                                     \
1448             gen_helper_mve_##FN##h,                                     \
1449             gen_helper_mve_##FN##w,                                     \
1450             NULL,                                                       \
1451         };                                                              \
1452         return do_2shift_scalar(s, a, fns[a->size]);                    \
1453     }
1454 
1455 DO_2SHIFT_SCALAR(VSHL_S_scalar, vshli_s)
1456 DO_2SHIFT_SCALAR(VSHL_U_scalar, vshli_u)
1457 DO_2SHIFT_SCALAR(VRSHL_S_scalar, vrshli_s)
1458 DO_2SHIFT_SCALAR(VRSHL_U_scalar, vrshli_u)
1459 DO_2SHIFT_SCALAR(VQSHL_S_scalar, vqshli_s)
1460 DO_2SHIFT_SCALAR(VQSHL_U_scalar, vqshli_u)
1461 DO_2SHIFT_SCALAR(VQRSHL_S_scalar, vqrshli_s)
1462 DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u)
1463 
1464 #define DO_VSHLL(INSN, FN)                                      \
1465     static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
1466     {                                                           \
1467         static MVEGenTwoOpShiftFn * const fns[] = {             \
1468             gen_helper_mve_##FN##b,                             \
1469             gen_helper_mve_##FN##h,                             \
1470         };                                                      \
1471         return do_2shift(s, a, fns[a->size], false);            \
1472     }
1473 
1474 DO_VSHLL(VSHLL_BS, vshllbs)
1475 DO_VSHLL(VSHLL_BU, vshllbu)
1476 DO_VSHLL(VSHLL_TS, vshllts)
1477 DO_VSHLL(VSHLL_TU, vshlltu)
1478 
1479 #define DO_2SHIFT_N(INSN, FN)                                   \
1480     static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
1481     {                                                           \
1482         static MVEGenTwoOpShiftFn * const fns[] = {             \
1483             gen_helper_mve_##FN##b,                             \
1484             gen_helper_mve_##FN##h,                             \
1485         };                                                      \
1486         return do_2shift(s, a, fns[a->size], false);            \
1487     }
1488 
1489 DO_2SHIFT_N(VSHRNB, vshrnb)
1490 DO_2SHIFT_N(VSHRNT, vshrnt)
1491 DO_2SHIFT_N(VRSHRNB, vrshrnb)
1492 DO_2SHIFT_N(VRSHRNT, vrshrnt)
1493 DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
1494 DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
1495 DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
1496 DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
1497 DO_2SHIFT_N(VQSHRUNB, vqshrunb)
1498 DO_2SHIFT_N(VQSHRUNT, vqshrunt)
1499 DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
1500 DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
1501 DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
1502 DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
1503 DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
1504 DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
1505 
1506 static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
1507 {
1508     /*
1509      * Whole Vector Left Shift with Carry. The carry is taken
1510      * from a general purpose register and written back there.
1511      * An imm of 0 means "shift by 32".
1512      */
1513     TCGv_ptr qd;
1514     TCGv_i32 rdm;
1515 
1516     if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
1517         return false;
1518     }
1519     if (a->rdm == 13 || a->rdm == 15) {
1520         /* CONSTRAINED UNPREDICTABLE: we UNDEF */
1521         return false;
1522     }
1523     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1524         return true;
1525     }
1526 
1527     qd = mve_qreg_ptr(a->qd);
1528     rdm = load_reg(s, a->rdm);
1529     gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
1530     store_reg(s, a->rdm, rdm);
1531     tcg_temp_free_ptr(qd);
1532     mve_update_eci(s);
1533     return true;
1534 }
1535 
1536 static bool do_vidup(DisasContext *s, arg_vidup *a, MVEGenVIDUPFn *fn)
1537 {
1538     TCGv_ptr qd;
1539     TCGv_i32 rn;
1540 
1541     /*
1542      * Vector increment/decrement with wrap and duplicate (VIDUP, VDDUP).
1543      * This fills the vector with elements of successively increasing
1544      * or decreasing values, starting from Rn.
1545      */
1546     if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
1547         return false;
1548     }
1549     if (a->size == MO_64) {
1550         /* size 0b11 is another encoding */
1551         return false;
1552     }
1553     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1554         return true;
1555     }
1556 
1557     qd = mve_qreg_ptr(a->qd);
1558     rn = load_reg(s, a->rn);
1559     fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm));
1560     store_reg(s, a->rn, rn);
1561     tcg_temp_free_ptr(qd);
1562     mve_update_eci(s);
1563     return true;
1564 }
1565 
1566 static bool do_viwdup(DisasContext *s, arg_viwdup *a, MVEGenVIWDUPFn *fn)
1567 {
1568     TCGv_ptr qd;
1569     TCGv_i32 rn, rm;
1570 
1571     /*
1572      * Vector increment/decrement with wrap and duplicate (VIWDUp, VDWDUP)
1573      * This fills the vector with elements of successively increasing
1574      * or decreasing values, starting from Rn. Rm specifies a point where
1575      * the count wraps back around to 0. The updated offset is written back
1576      * to Rn.
1577      */
1578     if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
1579         return false;
1580     }
1581     if (!fn || a->rm == 13 || a->rm == 15) {
1582         /*
1583          * size 0b11 is another encoding; Rm == 13 is UNPREDICTABLE;
1584          * Rm == 13 is VIWDUP, VDWDUP.
1585          */
1586         return false;
1587     }
1588     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1589         return true;
1590     }
1591 
1592     qd = mve_qreg_ptr(a->qd);
1593     rn = load_reg(s, a->rn);
1594     rm = load_reg(s, a->rm);
1595     fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm));
1596     store_reg(s, a->rn, rn);
1597     tcg_temp_free_ptr(qd);
1598     tcg_temp_free_i32(rm);
1599     mve_update_eci(s);
1600     return true;
1601 }
1602 
1603 static bool trans_VIDUP(DisasContext *s, arg_vidup *a)
1604 {
1605     static MVEGenVIDUPFn * const fns[] = {
1606         gen_helper_mve_vidupb,
1607         gen_helper_mve_viduph,
1608         gen_helper_mve_vidupw,
1609         NULL,
1610     };
1611     return do_vidup(s, a, fns[a->size]);
1612 }
1613 
1614 static bool trans_VDDUP(DisasContext *s, arg_vidup *a)
1615 {
1616     static MVEGenVIDUPFn * const fns[] = {
1617         gen_helper_mve_vidupb,
1618         gen_helper_mve_viduph,
1619         gen_helper_mve_vidupw,
1620         NULL,
1621     };
1622     /* VDDUP is just like VIDUP but with a negative immediate */
1623     a->imm = -a->imm;
1624     return do_vidup(s, a, fns[a->size]);
1625 }
1626 
1627 static bool trans_VIWDUP(DisasContext *s, arg_viwdup *a)
1628 {
1629     static MVEGenVIWDUPFn * const fns[] = {
1630         gen_helper_mve_viwdupb,
1631         gen_helper_mve_viwduph,
1632         gen_helper_mve_viwdupw,
1633         NULL,
1634     };
1635     return do_viwdup(s, a, fns[a->size]);
1636 }
1637 
1638 static bool trans_VDWDUP(DisasContext *s, arg_viwdup *a)
1639 {
1640     static MVEGenVIWDUPFn * const fns[] = {
1641         gen_helper_mve_vdwdupb,
1642         gen_helper_mve_vdwduph,
1643         gen_helper_mve_vdwdupw,
1644         NULL,
1645     };
1646     return do_viwdup(s, a, fns[a->size]);
1647 }
1648 
1649 static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn)
1650 {
1651     TCGv_ptr qn, qm;
1652 
1653     if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) ||
1654         !fn) {
1655         return false;
1656     }
1657     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1658         return true;
1659     }
1660 
1661     qn = mve_qreg_ptr(a->qn);
1662     qm = mve_qreg_ptr(a->qm);
1663     fn(cpu_env, qn, qm);
1664     tcg_temp_free_ptr(qn);
1665     tcg_temp_free_ptr(qm);
1666     if (a->mask) {
1667         /* VPT */
1668         gen_vpst(s, a->mask);
1669     }
1670     mve_update_eci(s);
1671     return true;
1672 }
1673 
1674 static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a,
1675                            MVEGenScalarCmpFn *fn)
1676 {
1677     TCGv_ptr qn;
1678     TCGv_i32 rm;
1679 
1680     if (!dc_isar_feature(aa32_mve, s) || !fn || a->rm == 13) {
1681         return false;
1682     }
1683     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1684         return true;
1685     }
1686 
1687     qn = mve_qreg_ptr(a->qn);
1688     if (a->rm == 15) {
1689         /* Encoding Rm=0b1111 means "constant zero" */
1690         rm = tcg_constant_i32(0);
1691     } else {
1692         rm = load_reg(s, a->rm);
1693     }
1694     fn(cpu_env, qn, rm);
1695     tcg_temp_free_ptr(qn);
1696     tcg_temp_free_i32(rm);
1697     if (a->mask) {
1698         /* VPT */
1699         gen_vpst(s, a->mask);
1700     }
1701     mve_update_eci(s);
1702     return true;
1703 }
1704 
1705 #define DO_VCMP(INSN, FN)                                       \
1706     static bool trans_##INSN(DisasContext *s, arg_vcmp *a)      \
1707     {                                                           \
1708         static MVEGenCmpFn * const fns[] = {                    \
1709             gen_helper_mve_##FN##b,                             \
1710             gen_helper_mve_##FN##h,                             \
1711             gen_helper_mve_##FN##w,                             \
1712             NULL,                                               \
1713         };                                                      \
1714         return do_vcmp(s, a, fns[a->size]);                     \
1715     }                                                           \
1716     static bool trans_##INSN##_scalar(DisasContext *s,          \
1717                                       arg_vcmp_scalar *a)       \
1718     {                                                           \
1719         static MVEGenScalarCmpFn * const fns[] = {              \
1720             gen_helper_mve_##FN##_scalarb,                      \
1721             gen_helper_mve_##FN##_scalarh,                      \
1722             gen_helper_mve_##FN##_scalarw,                      \
1723             NULL,                                               \
1724         };                                                      \
1725         return do_vcmp_scalar(s, a, fns[a->size]);              \
1726     }
1727 
1728 DO_VCMP(VCMPEQ, vcmpeq)
1729 DO_VCMP(VCMPNE, vcmpne)
1730 DO_VCMP(VCMPCS, vcmpcs)
1731 DO_VCMP(VCMPHI, vcmphi)
1732 DO_VCMP(VCMPGE, vcmpge)
1733 DO_VCMP(VCMPLT, vcmplt)
1734 DO_VCMP(VCMPGT, vcmpgt)
1735 DO_VCMP(VCMPLE, vcmple)
1736 
1737 static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn)
1738 {
1739     /*
1740      * MIN/MAX operations across a vector: compute the min or
1741      * max of the initial value in a general purpose register
1742      * and all the elements in the vector, and store it back
1743      * into the general purpose register.
1744      */
1745     TCGv_ptr qm;
1746     TCGv_i32 rda;
1747 
1748     if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) ||
1749         !fn || a->rda == 13 || a->rda == 15) {
1750         /* Rda cases are UNPREDICTABLE */
1751         return false;
1752     }
1753     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1754         return true;
1755     }
1756 
1757     qm = mve_qreg_ptr(a->qm);
1758     rda = load_reg(s, a->rda);
1759     fn(rda, cpu_env, qm, rda);
1760     store_reg(s, a->rda, rda);
1761     tcg_temp_free_ptr(qm);
1762     mve_update_eci(s);
1763     return true;
1764 }
1765 
1766 #define DO_VMAXV(INSN, FN)                                      \
1767     static bool trans_##INSN(DisasContext *s, arg_vmaxv *a)     \
1768     {                                                           \
1769         static MVEGenVADDVFn * const fns[] = {                  \
1770             gen_helper_mve_##FN##b,                             \
1771             gen_helper_mve_##FN##h,                             \
1772             gen_helper_mve_##FN##w,                             \
1773             NULL,                                               \
1774         };                                                      \
1775         return do_vmaxv(s, a, fns[a->size]);                    \
1776     }
1777 
1778 DO_VMAXV(VMAXV_S, vmaxvs)
1779 DO_VMAXV(VMAXV_U, vmaxvu)
1780 DO_VMAXV(VMAXAV, vmaxav)
1781 DO_VMAXV(VMINV_S, vminvs)
1782 DO_VMAXV(VMINV_U, vminvu)
1783 DO_VMAXV(VMINAV, vminav)
1784 
1785 static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn)
1786 {
1787     /* Absolute difference accumulated across vector */
1788     TCGv_ptr qn, qm;
1789     TCGv_i32 rda;
1790 
1791     if (!dc_isar_feature(aa32_mve, s) ||
1792         !mve_check_qreg_bank(s, a->qm | a->qn) ||
1793         !fn || a->rda == 13 || a->rda == 15) {
1794         /* Rda cases are UNPREDICTABLE */
1795         return false;
1796     }
1797     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1798         return true;
1799     }
1800 
1801     qm = mve_qreg_ptr(a->qm);
1802     qn = mve_qreg_ptr(a->qn);
1803     rda = load_reg(s, a->rda);
1804     fn(rda, cpu_env, qn, qm, rda);
1805     store_reg(s, a->rda, rda);
1806     tcg_temp_free_ptr(qm);
1807     tcg_temp_free_ptr(qn);
1808     mve_update_eci(s);
1809     return true;
1810 }
1811 
1812 #define DO_VABAV(INSN, FN)                                      \
1813     static bool trans_##INSN(DisasContext *s, arg_vabav *a)     \
1814     {                                                           \
1815         static MVEGenVABAVFn * const fns[] = {                  \
1816             gen_helper_mve_##FN##b,                             \
1817             gen_helper_mve_##FN##h,                             \
1818             gen_helper_mve_##FN##w,                             \
1819             NULL,                                               \
1820         };                                                      \
1821         return do_vabav(s, a, fns[a->size]);                    \
1822     }
1823 
1824 DO_VABAV(VABAV_S, vabavs)
1825 DO_VABAV(VABAV_U, vabavu)
1826 
1827 static bool trans_VMOV_to_2gp(DisasContext *s, arg_VMOV_to_2gp *a)
1828 {
1829     /*
1830      * VMOV two 32-bit vector lanes to two general-purpose registers.
1831      * This insn is not predicated but it is subject to beat-wise
1832      * execution if it is not in an IT block. For us this means
1833      * only that if PSR.ECI says we should not be executing the beat
1834      * corresponding to the lane of the vector register being accessed
1835      * then we should skip perfoming the move, and that we need to do
1836      * the usual check for bad ECI state and advance of ECI state.
1837      * (If PSR.ECI is non-zero then we cannot be in an IT block.)
1838      */
1839     TCGv_i32 tmp;
1840     int vd;
1841 
1842     if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) ||
1843         a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15 ||
1844         a->rt == a->rt2) {
1845         /* Rt/Rt2 cases are UNPREDICTABLE */
1846         return false;
1847     }
1848     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1849         return true;
1850     }
1851 
1852     /* Convert Qreg index to Dreg for read_neon_element32() etc */
1853     vd = a->qd * 2;
1854 
1855     if (!mve_skip_vmov(s, vd, a->idx, MO_32)) {
1856         tmp = tcg_temp_new_i32();
1857         read_neon_element32(tmp, vd, a->idx, MO_32);
1858         store_reg(s, a->rt, tmp);
1859     }
1860     if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) {
1861         tmp = tcg_temp_new_i32();
1862         read_neon_element32(tmp, vd + 1, a->idx, MO_32);
1863         store_reg(s, a->rt2, tmp);
1864     }
1865 
1866     mve_update_and_store_eci(s);
1867     return true;
1868 }
1869 
1870 static bool trans_VMOV_from_2gp(DisasContext *s, arg_VMOV_to_2gp *a)
1871 {
1872     /*
1873      * VMOV two general-purpose registers to two 32-bit vector lanes.
1874      * This insn is not predicated but it is subject to beat-wise
1875      * execution if it is not in an IT block. For us this means
1876      * only that if PSR.ECI says we should not be executing the beat
1877      * corresponding to the lane of the vector register being accessed
1878      * then we should skip perfoming the move, and that we need to do
1879      * the usual check for bad ECI state and advance of ECI state.
1880      * (If PSR.ECI is non-zero then we cannot be in an IT block.)
1881      */
1882     TCGv_i32 tmp;
1883     int vd;
1884 
1885     if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) ||
1886         a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15) {
1887         /* Rt/Rt2 cases are UNPREDICTABLE */
1888         return false;
1889     }
1890     if (!mve_eci_check(s) || !vfp_access_check(s)) {
1891         return true;
1892     }
1893 
1894     /* Convert Qreg idx to Dreg for read_neon_element32() etc */
1895     vd = a->qd * 2;
1896 
1897     if (!mve_skip_vmov(s, vd, a->idx, MO_32)) {
1898         tmp = load_reg(s, a->rt);
1899         write_neon_element32(tmp, vd, a->idx, MO_32);
1900         tcg_temp_free_i32(tmp);
1901     }
1902     if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) {
1903         tmp = load_reg(s, a->rt2);
1904         write_neon_element32(tmp, vd + 1, a->idx, MO_32);
1905         tcg_temp_free_i32(tmp);
1906     }
1907 
1908     mve_update_and_store_eci(s);
1909     return true;
1910 }
1911