1 /* 2 * ARM translation: M-profile MVE instructions 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "tcg/tcg-op.h" 22 #include "tcg/tcg-op-gvec.h" 23 #include "exec/exec-all.h" 24 #include "exec/gen-icount.h" 25 #include "translate.h" 26 #include "translate-a32.h" 27 28 static inline int vidup_imm(DisasContext *s, int x) 29 { 30 return 1 << x; 31 } 32 33 /* Include the generated decoder */ 34 #include "decode-mve.c.inc" 35 36 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 37 typedef void MVEGenLdStSGFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 38 typedef void MVEGenLdStIlFn(TCGv_ptr, TCGv_i32, TCGv_i32); 39 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 40 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); 41 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 42 typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 43 typedef void MVEGenLongDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); 44 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); 45 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); 46 typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32); 47 typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); 48 typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 49 typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 50 typedef void MVEGenVABAVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 51 typedef void MVEGenDualAccOpFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 52 53 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ 54 static inline long mve_qreg_offset(unsigned reg) 55 { 56 return offsetof(CPUARMState, vfp.zregs[reg].d[0]); 57 } 58 59 static TCGv_ptr mve_qreg_ptr(unsigned reg) 60 { 61 TCGv_ptr ret = tcg_temp_new_ptr(); 62 tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg)); 63 return ret; 64 } 65 66 static bool mve_check_qreg_bank(DisasContext *s, int qmask) 67 { 68 /* 69 * Check whether Qregs are in range. For v8.1M only Q0..Q7 70 * are supported, see VFPSmallRegisterBank(). 71 */ 72 return qmask < 8; 73 } 74 75 bool mve_eci_check(DisasContext *s) 76 { 77 /* 78 * This is a beatwise insn: check that ECI is valid (not a 79 * reserved value) and note that we are handling it. 80 * Return true if OK, false if we generated an exception. 81 */ 82 s->eci_handled = true; 83 switch (s->eci) { 84 case ECI_NONE: 85 case ECI_A0: 86 case ECI_A0A1: 87 case ECI_A0A1A2: 88 case ECI_A0A1A2B0: 89 return true; 90 default: 91 /* Reserved value: INVSTATE UsageFault */ 92 gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), 93 default_exception_el(s)); 94 return false; 95 } 96 } 97 98 void mve_update_eci(DisasContext *s) 99 { 100 /* 101 * The helper function will always update the CPUState field, 102 * so we only need to update the DisasContext field. 103 */ 104 if (s->eci) { 105 s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE; 106 } 107 } 108 109 void mve_update_and_store_eci(DisasContext *s) 110 { 111 /* 112 * For insns which don't call a helper function that will call 113 * mve_advance_vpt(), this version updates s->eci and also stores 114 * it out to the CPUState field. 115 */ 116 if (s->eci) { 117 mve_update_eci(s); 118 store_cpu_field(tcg_constant_i32(s->eci << 4), condexec_bits); 119 } 120 } 121 122 static bool mve_skip_first_beat(DisasContext *s) 123 { 124 /* Return true if PSR.ECI says we must skip the first beat of this insn */ 125 switch (s->eci) { 126 case ECI_NONE: 127 return false; 128 case ECI_A0: 129 case ECI_A0A1: 130 case ECI_A0A1A2: 131 case ECI_A0A1A2B0: 132 return true; 133 default: 134 g_assert_not_reached(); 135 } 136 } 137 138 static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, 139 unsigned msize) 140 { 141 TCGv_i32 addr; 142 uint32_t offset; 143 TCGv_ptr qreg; 144 145 if (!dc_isar_feature(aa32_mve, s) || 146 !mve_check_qreg_bank(s, a->qd) || 147 !fn) { 148 return false; 149 } 150 151 /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ 152 if (a->rn == 15 || (a->rn == 13 && a->w)) { 153 return false; 154 } 155 156 if (!mve_eci_check(s) || !vfp_access_check(s)) { 157 return true; 158 } 159 160 offset = a->imm << msize; 161 if (!a->a) { 162 offset = -offset; 163 } 164 addr = load_reg(s, a->rn); 165 if (a->p) { 166 tcg_gen_addi_i32(addr, addr, offset); 167 } 168 169 qreg = mve_qreg_ptr(a->qd); 170 fn(cpu_env, qreg, addr); 171 tcg_temp_free_ptr(qreg); 172 173 /* 174 * Writeback always happens after the last beat of the insn, 175 * regardless of predication 176 */ 177 if (a->w) { 178 if (!a->p) { 179 tcg_gen_addi_i32(addr, addr, offset); 180 } 181 store_reg(s, a->rn, addr); 182 } else { 183 tcg_temp_free_i32(addr); 184 } 185 mve_update_eci(s); 186 return true; 187 } 188 189 static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) 190 { 191 static MVEGenLdStFn * const ldstfns[4][2] = { 192 { gen_helper_mve_vstrb, gen_helper_mve_vldrb }, 193 { gen_helper_mve_vstrh, gen_helper_mve_vldrh }, 194 { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, 195 { NULL, NULL } 196 }; 197 return do_ldst(s, a, ldstfns[a->size][a->l], a->size); 198 } 199 200 #define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \ 201 static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ 202 { \ 203 static MVEGenLdStFn * const ldstfns[2][2] = { \ 204 { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ 205 { NULL, gen_helper_mve_##ULD }, \ 206 }; \ 207 return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \ 208 } 209 210 DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8) 211 DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8) 212 DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16) 213 214 static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a, MVEGenLdStSGFn fn) 215 { 216 TCGv_i32 addr; 217 TCGv_ptr qd, qm; 218 219 if (!dc_isar_feature(aa32_mve, s) || 220 !mve_check_qreg_bank(s, a->qd | a->qm) || 221 !fn || a->rn == 15) { 222 /* Rn case is UNPREDICTABLE */ 223 return false; 224 } 225 226 if (!mve_eci_check(s) || !vfp_access_check(s)) { 227 return true; 228 } 229 230 addr = load_reg(s, a->rn); 231 232 qd = mve_qreg_ptr(a->qd); 233 qm = mve_qreg_ptr(a->qm); 234 fn(cpu_env, qd, qm, addr); 235 tcg_temp_free_ptr(qd); 236 tcg_temp_free_ptr(qm); 237 tcg_temp_free_i32(addr); 238 mve_update_eci(s); 239 return true; 240 } 241 242 /* 243 * The naming scheme here is "vldrb_sg_sh == in-memory byte loads 244 * signextended to halfword elements in register". _os_ indicates that 245 * the offsets in Qm should be scaled by the element size. 246 */ 247 /* This macro is just to make the arrays more compact in these functions */ 248 #define F(N) gen_helper_mve_##N 249 250 /* VLDRB/VSTRB (ie msize 1) with OS=1 is UNPREDICTABLE; we UNDEF */ 251 static bool trans_VLDR_S_sg(DisasContext *s, arg_vldst_sg *a) 252 { 253 static MVEGenLdStSGFn * const fns[2][4][4] = { { 254 { NULL, F(vldrb_sg_sh), F(vldrb_sg_sw), NULL }, 255 { NULL, NULL, F(vldrh_sg_sw), NULL }, 256 { NULL, NULL, NULL, NULL }, 257 { NULL, NULL, NULL, NULL } 258 }, { 259 { NULL, NULL, NULL, NULL }, 260 { NULL, NULL, F(vldrh_sg_os_sw), NULL }, 261 { NULL, NULL, NULL, NULL }, 262 { NULL, NULL, NULL, NULL } 263 } 264 }; 265 if (a->qd == a->qm) { 266 return false; /* UNPREDICTABLE */ 267 } 268 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 269 } 270 271 static bool trans_VLDR_U_sg(DisasContext *s, arg_vldst_sg *a) 272 { 273 static MVEGenLdStSGFn * const fns[2][4][4] = { { 274 { F(vldrb_sg_ub), F(vldrb_sg_uh), F(vldrb_sg_uw), NULL }, 275 { NULL, F(vldrh_sg_uh), F(vldrh_sg_uw), NULL }, 276 { NULL, NULL, F(vldrw_sg_uw), NULL }, 277 { NULL, NULL, NULL, F(vldrd_sg_ud) } 278 }, { 279 { NULL, NULL, NULL, NULL }, 280 { NULL, F(vldrh_sg_os_uh), F(vldrh_sg_os_uw), NULL }, 281 { NULL, NULL, F(vldrw_sg_os_uw), NULL }, 282 { NULL, NULL, NULL, F(vldrd_sg_os_ud) } 283 } 284 }; 285 if (a->qd == a->qm) { 286 return false; /* UNPREDICTABLE */ 287 } 288 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 289 } 290 291 static bool trans_VSTR_sg(DisasContext *s, arg_vldst_sg *a) 292 { 293 static MVEGenLdStSGFn * const fns[2][4][4] = { { 294 { F(vstrb_sg_ub), F(vstrb_sg_uh), F(vstrb_sg_uw), NULL }, 295 { NULL, F(vstrh_sg_uh), F(vstrh_sg_uw), NULL }, 296 { NULL, NULL, F(vstrw_sg_uw), NULL }, 297 { NULL, NULL, NULL, F(vstrd_sg_ud) } 298 }, { 299 { NULL, NULL, NULL, NULL }, 300 { NULL, F(vstrh_sg_os_uh), F(vstrh_sg_os_uw), NULL }, 301 { NULL, NULL, F(vstrw_sg_os_uw), NULL }, 302 { NULL, NULL, NULL, F(vstrd_sg_os_ud) } 303 } 304 }; 305 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 306 } 307 308 #undef F 309 310 static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_sg_imm *a, 311 MVEGenLdStSGFn *fn, unsigned msize) 312 { 313 uint32_t offset; 314 TCGv_ptr qd, qm; 315 316 if (!dc_isar_feature(aa32_mve, s) || 317 !mve_check_qreg_bank(s, a->qd | a->qm) || 318 !fn) { 319 return false; 320 } 321 322 if (!mve_eci_check(s) || !vfp_access_check(s)) { 323 return true; 324 } 325 326 offset = a->imm << msize; 327 if (!a->a) { 328 offset = -offset; 329 } 330 331 qd = mve_qreg_ptr(a->qd); 332 qm = mve_qreg_ptr(a->qm); 333 fn(cpu_env, qd, qm, tcg_constant_i32(offset)); 334 tcg_temp_free_ptr(qd); 335 tcg_temp_free_ptr(qm); 336 mve_update_eci(s); 337 return true; 338 } 339 340 static bool trans_VLDRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 341 { 342 static MVEGenLdStSGFn * const fns[] = { 343 gen_helper_mve_vldrw_sg_uw, 344 gen_helper_mve_vldrw_sg_wb_uw, 345 }; 346 if (a->qd == a->qm) { 347 return false; /* UNPREDICTABLE */ 348 } 349 return do_ldst_sg_imm(s, a, fns[a->w], MO_32); 350 } 351 352 static bool trans_VLDRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 353 { 354 static MVEGenLdStSGFn * const fns[] = { 355 gen_helper_mve_vldrd_sg_ud, 356 gen_helper_mve_vldrd_sg_wb_ud, 357 }; 358 if (a->qd == a->qm) { 359 return false; /* UNPREDICTABLE */ 360 } 361 return do_ldst_sg_imm(s, a, fns[a->w], MO_64); 362 } 363 364 static bool trans_VSTRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 365 { 366 static MVEGenLdStSGFn * const fns[] = { 367 gen_helper_mve_vstrw_sg_uw, 368 gen_helper_mve_vstrw_sg_wb_uw, 369 }; 370 return do_ldst_sg_imm(s, a, fns[a->w], MO_32); 371 } 372 373 static bool trans_VSTRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 374 { 375 static MVEGenLdStSGFn * const fns[] = { 376 gen_helper_mve_vstrd_sg_ud, 377 gen_helper_mve_vstrd_sg_wb_ud, 378 }; 379 return do_ldst_sg_imm(s, a, fns[a->w], MO_64); 380 } 381 382 static bool do_vldst_il(DisasContext *s, arg_vldst_il *a, MVEGenLdStIlFn *fn, 383 int addrinc) 384 { 385 TCGv_i32 rn; 386 387 if (!dc_isar_feature(aa32_mve, s) || 388 !mve_check_qreg_bank(s, a->qd) || 389 !fn || (a->rn == 13 && a->w) || a->rn == 15) { 390 /* Variously UNPREDICTABLE or UNDEF or related-encoding */ 391 return false; 392 } 393 if (!mve_eci_check(s) || !vfp_access_check(s)) { 394 return true; 395 } 396 397 rn = load_reg(s, a->rn); 398 /* 399 * We pass the index of Qd, not a pointer, because the helper must 400 * access multiple Q registers starting at Qd and working up. 401 */ 402 fn(cpu_env, tcg_constant_i32(a->qd), rn); 403 404 if (a->w) { 405 tcg_gen_addi_i32(rn, rn, addrinc); 406 store_reg(s, a->rn, rn); 407 } else { 408 tcg_temp_free_i32(rn); 409 } 410 mve_update_and_store_eci(s); 411 return true; 412 } 413 414 /* This macro is just to make the arrays more compact in these functions */ 415 #define F(N) gen_helper_mve_##N 416 417 static bool trans_VLD2(DisasContext *s, arg_vldst_il *a) 418 { 419 static MVEGenLdStIlFn * const fns[4][4] = { 420 { F(vld20b), F(vld20h), F(vld20w), NULL, }, 421 { F(vld21b), F(vld21h), F(vld21w), NULL, }, 422 { NULL, NULL, NULL, NULL }, 423 { NULL, NULL, NULL, NULL }, 424 }; 425 if (a->qd > 6) { 426 return false; 427 } 428 return do_vldst_il(s, a, fns[a->pat][a->size], 32); 429 } 430 431 static bool trans_VLD4(DisasContext *s, arg_vldst_il *a) 432 { 433 static MVEGenLdStIlFn * const fns[4][4] = { 434 { F(vld40b), F(vld40h), F(vld40w), NULL, }, 435 { F(vld41b), F(vld41h), F(vld41w), NULL, }, 436 { F(vld42b), F(vld42h), F(vld42w), NULL, }, 437 { F(vld43b), F(vld43h), F(vld43w), NULL, }, 438 }; 439 if (a->qd > 4) { 440 return false; 441 } 442 return do_vldst_il(s, a, fns[a->pat][a->size], 64); 443 } 444 445 static bool trans_VST2(DisasContext *s, arg_vldst_il *a) 446 { 447 static MVEGenLdStIlFn * const fns[4][4] = { 448 { F(vst20b), F(vst20h), F(vst20w), NULL, }, 449 { F(vst21b), F(vst21h), F(vst21w), NULL, }, 450 { NULL, NULL, NULL, NULL }, 451 { NULL, NULL, NULL, NULL }, 452 }; 453 if (a->qd > 6) { 454 return false; 455 } 456 return do_vldst_il(s, a, fns[a->pat][a->size], 32); 457 } 458 459 static bool trans_VST4(DisasContext *s, arg_vldst_il *a) 460 { 461 static MVEGenLdStIlFn * const fns[4][4] = { 462 { F(vst40b), F(vst40h), F(vst40w), NULL, }, 463 { F(vst41b), F(vst41h), F(vst41w), NULL, }, 464 { F(vst42b), F(vst42h), F(vst42w), NULL, }, 465 { F(vst43b), F(vst43h), F(vst43w), NULL, }, 466 }; 467 if (a->qd > 4) { 468 return false; 469 } 470 return do_vldst_il(s, a, fns[a->pat][a->size], 64); 471 } 472 473 #undef F 474 475 static bool trans_VDUP(DisasContext *s, arg_VDUP *a) 476 { 477 TCGv_ptr qd; 478 TCGv_i32 rt; 479 480 if (!dc_isar_feature(aa32_mve, s) || 481 !mve_check_qreg_bank(s, a->qd)) { 482 return false; 483 } 484 if (a->rt == 13 || a->rt == 15) { 485 /* UNPREDICTABLE; we choose to UNDEF */ 486 return false; 487 } 488 if (!mve_eci_check(s) || !vfp_access_check(s)) { 489 return true; 490 } 491 492 qd = mve_qreg_ptr(a->qd); 493 rt = load_reg(s, a->rt); 494 tcg_gen_dup_i32(a->size, rt, rt); 495 gen_helper_mve_vdup(cpu_env, qd, rt); 496 tcg_temp_free_ptr(qd); 497 tcg_temp_free_i32(rt); 498 mve_update_eci(s); 499 return true; 500 } 501 502 static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) 503 { 504 TCGv_ptr qd, qm; 505 506 if (!dc_isar_feature(aa32_mve, s) || 507 !mve_check_qreg_bank(s, a->qd | a->qm) || 508 !fn) { 509 return false; 510 } 511 512 if (!mve_eci_check(s) || !vfp_access_check(s)) { 513 return true; 514 } 515 516 qd = mve_qreg_ptr(a->qd); 517 qm = mve_qreg_ptr(a->qm); 518 fn(cpu_env, qd, qm); 519 tcg_temp_free_ptr(qd); 520 tcg_temp_free_ptr(qm); 521 mve_update_eci(s); 522 return true; 523 } 524 525 #define DO_1OP(INSN, FN) \ 526 static bool trans_##INSN(DisasContext *s, arg_1op *a) \ 527 { \ 528 static MVEGenOneOpFn * const fns[] = { \ 529 gen_helper_mve_##FN##b, \ 530 gen_helper_mve_##FN##h, \ 531 gen_helper_mve_##FN##w, \ 532 NULL, \ 533 }; \ 534 return do_1op(s, a, fns[a->size]); \ 535 } 536 537 DO_1OP(VCLZ, vclz) 538 DO_1OP(VCLS, vcls) 539 DO_1OP(VABS, vabs) 540 DO_1OP(VNEG, vneg) 541 DO_1OP(VQABS, vqabs) 542 DO_1OP(VQNEG, vqneg) 543 DO_1OP(VMAXA, vmaxa) 544 DO_1OP(VMINA, vmina) 545 546 /* Narrowing moves: only size 0 and 1 are valid */ 547 #define DO_VMOVN(INSN, FN) \ 548 static bool trans_##INSN(DisasContext *s, arg_1op *a) \ 549 { \ 550 static MVEGenOneOpFn * const fns[] = { \ 551 gen_helper_mve_##FN##b, \ 552 gen_helper_mve_##FN##h, \ 553 NULL, \ 554 NULL, \ 555 }; \ 556 return do_1op(s, a, fns[a->size]); \ 557 } 558 559 DO_VMOVN(VMOVNB, vmovnb) 560 DO_VMOVN(VMOVNT, vmovnt) 561 DO_VMOVN(VQMOVUNB, vqmovunb) 562 DO_VMOVN(VQMOVUNT, vqmovunt) 563 DO_VMOVN(VQMOVN_BS, vqmovnbs) 564 DO_VMOVN(VQMOVN_TS, vqmovnts) 565 DO_VMOVN(VQMOVN_BU, vqmovnbu) 566 DO_VMOVN(VQMOVN_TU, vqmovntu) 567 568 static bool trans_VREV16(DisasContext *s, arg_1op *a) 569 { 570 static MVEGenOneOpFn * const fns[] = { 571 gen_helper_mve_vrev16b, 572 NULL, 573 NULL, 574 NULL, 575 }; 576 return do_1op(s, a, fns[a->size]); 577 } 578 579 static bool trans_VREV32(DisasContext *s, arg_1op *a) 580 { 581 static MVEGenOneOpFn * const fns[] = { 582 gen_helper_mve_vrev32b, 583 gen_helper_mve_vrev32h, 584 NULL, 585 NULL, 586 }; 587 return do_1op(s, a, fns[a->size]); 588 } 589 590 static bool trans_VREV64(DisasContext *s, arg_1op *a) 591 { 592 static MVEGenOneOpFn * const fns[] = { 593 gen_helper_mve_vrev64b, 594 gen_helper_mve_vrev64h, 595 gen_helper_mve_vrev64w, 596 NULL, 597 }; 598 return do_1op(s, a, fns[a->size]); 599 } 600 601 static bool trans_VMVN(DisasContext *s, arg_1op *a) 602 { 603 return do_1op(s, a, gen_helper_mve_vmvn); 604 } 605 606 static bool trans_VABS_fp(DisasContext *s, arg_1op *a) 607 { 608 static MVEGenOneOpFn * const fns[] = { 609 NULL, 610 gen_helper_mve_vfabsh, 611 gen_helper_mve_vfabss, 612 NULL, 613 }; 614 if (!dc_isar_feature(aa32_mve_fp, s)) { 615 return false; 616 } 617 return do_1op(s, a, fns[a->size]); 618 } 619 620 static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) 621 { 622 static MVEGenOneOpFn * const fns[] = { 623 NULL, 624 gen_helper_mve_vfnegh, 625 gen_helper_mve_vfnegs, 626 NULL, 627 }; 628 if (!dc_isar_feature(aa32_mve_fp, s)) { 629 return false; 630 } 631 return do_1op(s, a, fns[a->size]); 632 } 633 634 static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) 635 { 636 TCGv_ptr qd, qn, qm; 637 638 if (!dc_isar_feature(aa32_mve, s) || 639 !mve_check_qreg_bank(s, a->qd | a->qn | a->qm) || 640 !fn) { 641 return false; 642 } 643 if (!mve_eci_check(s) || !vfp_access_check(s)) { 644 return true; 645 } 646 647 qd = mve_qreg_ptr(a->qd); 648 qn = mve_qreg_ptr(a->qn); 649 qm = mve_qreg_ptr(a->qm); 650 fn(cpu_env, qd, qn, qm); 651 tcg_temp_free_ptr(qd); 652 tcg_temp_free_ptr(qn); 653 tcg_temp_free_ptr(qm); 654 mve_update_eci(s); 655 return true; 656 } 657 658 #define DO_LOGIC(INSN, HELPER) \ 659 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 660 { \ 661 return do_2op(s, a, HELPER); \ 662 } 663 664 DO_LOGIC(VAND, gen_helper_mve_vand) 665 DO_LOGIC(VBIC, gen_helper_mve_vbic) 666 DO_LOGIC(VORR, gen_helper_mve_vorr) 667 DO_LOGIC(VORN, gen_helper_mve_vorn) 668 DO_LOGIC(VEOR, gen_helper_mve_veor) 669 670 DO_LOGIC(VPSEL, gen_helper_mve_vpsel) 671 672 #define DO_2OP(INSN, FN) \ 673 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 674 { \ 675 static MVEGenTwoOpFn * const fns[] = { \ 676 gen_helper_mve_##FN##b, \ 677 gen_helper_mve_##FN##h, \ 678 gen_helper_mve_##FN##w, \ 679 NULL, \ 680 }; \ 681 return do_2op(s, a, fns[a->size]); \ 682 } 683 684 DO_2OP(VADD, vadd) 685 DO_2OP(VSUB, vsub) 686 DO_2OP(VMUL, vmul) 687 DO_2OP(VMULH_S, vmulhs) 688 DO_2OP(VMULH_U, vmulhu) 689 DO_2OP(VRMULH_S, vrmulhs) 690 DO_2OP(VRMULH_U, vrmulhu) 691 DO_2OP(VMAX_S, vmaxs) 692 DO_2OP(VMAX_U, vmaxu) 693 DO_2OP(VMIN_S, vmins) 694 DO_2OP(VMIN_U, vminu) 695 DO_2OP(VABD_S, vabds) 696 DO_2OP(VABD_U, vabdu) 697 DO_2OP(VHADD_S, vhadds) 698 DO_2OP(VHADD_U, vhaddu) 699 DO_2OP(VHSUB_S, vhsubs) 700 DO_2OP(VHSUB_U, vhsubu) 701 DO_2OP(VMULL_BS, vmullbs) 702 DO_2OP(VMULL_BU, vmullbu) 703 DO_2OP(VMULL_TS, vmullts) 704 DO_2OP(VMULL_TU, vmulltu) 705 DO_2OP(VQDMULH, vqdmulh) 706 DO_2OP(VQRDMULH, vqrdmulh) 707 DO_2OP(VQADD_S, vqadds) 708 DO_2OP(VQADD_U, vqaddu) 709 DO_2OP(VQSUB_S, vqsubs) 710 DO_2OP(VQSUB_U, vqsubu) 711 DO_2OP(VSHL_S, vshls) 712 DO_2OP(VSHL_U, vshlu) 713 DO_2OP(VRSHL_S, vrshls) 714 DO_2OP(VRSHL_U, vrshlu) 715 DO_2OP(VQSHL_S, vqshls) 716 DO_2OP(VQSHL_U, vqshlu) 717 DO_2OP(VQRSHL_S, vqrshls) 718 DO_2OP(VQRSHL_U, vqrshlu) 719 DO_2OP(VQDMLADH, vqdmladh) 720 DO_2OP(VQDMLADHX, vqdmladhx) 721 DO_2OP(VQRDMLADH, vqrdmladh) 722 DO_2OP(VQRDMLADHX, vqrdmladhx) 723 DO_2OP(VQDMLSDH, vqdmlsdh) 724 DO_2OP(VQDMLSDHX, vqdmlsdhx) 725 DO_2OP(VQRDMLSDH, vqrdmlsdh) 726 DO_2OP(VQRDMLSDHX, vqrdmlsdhx) 727 DO_2OP(VRHADD_S, vrhadds) 728 DO_2OP(VRHADD_U, vrhaddu) 729 /* 730 * VCADD Qd == Qm at size MO_32 is UNPREDICTABLE; we choose not to diagnose 731 * so we can reuse the DO_2OP macro. (Our implementation calculates the 732 * "expected" results in this case.) Similarly for VHCADD. 733 */ 734 DO_2OP(VCADD90, vcadd90) 735 DO_2OP(VCADD270, vcadd270) 736 DO_2OP(VHCADD90, vhcadd90) 737 DO_2OP(VHCADD270, vhcadd270) 738 739 static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) 740 { 741 static MVEGenTwoOpFn * const fns[] = { 742 NULL, 743 gen_helper_mve_vqdmullbh, 744 gen_helper_mve_vqdmullbw, 745 NULL, 746 }; 747 if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) { 748 /* UNPREDICTABLE; we choose to undef */ 749 return false; 750 } 751 return do_2op(s, a, fns[a->size]); 752 } 753 754 static bool trans_VQDMULLT(DisasContext *s, arg_2op *a) 755 { 756 static MVEGenTwoOpFn * const fns[] = { 757 NULL, 758 gen_helper_mve_vqdmullth, 759 gen_helper_mve_vqdmulltw, 760 NULL, 761 }; 762 if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) { 763 /* UNPREDICTABLE; we choose to undef */ 764 return false; 765 } 766 return do_2op(s, a, fns[a->size]); 767 } 768 769 static bool trans_VMULLP_B(DisasContext *s, arg_2op *a) 770 { 771 /* 772 * Note that a->size indicates the output size, ie VMULL.P8 773 * is the 8x8->16 operation and a->size is MO_16; VMULL.P16 774 * is the 16x16->32 operation and a->size is MO_32. 775 */ 776 static MVEGenTwoOpFn * const fns[] = { 777 NULL, 778 gen_helper_mve_vmullpbh, 779 gen_helper_mve_vmullpbw, 780 NULL, 781 }; 782 return do_2op(s, a, fns[a->size]); 783 } 784 785 static bool trans_VMULLP_T(DisasContext *s, arg_2op *a) 786 { 787 /* a->size is as for trans_VMULLP_B */ 788 static MVEGenTwoOpFn * const fns[] = { 789 NULL, 790 gen_helper_mve_vmullpth, 791 gen_helper_mve_vmullptw, 792 NULL, 793 }; 794 return do_2op(s, a, fns[a->size]); 795 } 796 797 /* 798 * VADC and VSBC: these perform an add-with-carry or subtract-with-carry 799 * of the 32-bit elements in each lane of the input vectors, where the 800 * carry-out of each add is the carry-in of the next. The initial carry 801 * input is either fixed (0 for VADCI, 1 for VSBCI) or is from FPSCR.C 802 * (for VADC and VSBC); the carry out at the end is written back to FPSCR.C. 803 * These insns are subject to beat-wise execution. Partial execution 804 * of an I=1 (initial carry input fixed) insn which does not 805 * execute the first beat must start with the current FPSCR.NZCV 806 * value, not the fixed constant input. 807 */ 808 static bool trans_VADC(DisasContext *s, arg_2op *a) 809 { 810 return do_2op(s, a, gen_helper_mve_vadc); 811 } 812 813 static bool trans_VADCI(DisasContext *s, arg_2op *a) 814 { 815 if (mve_skip_first_beat(s)) { 816 return trans_VADC(s, a); 817 } 818 return do_2op(s, a, gen_helper_mve_vadci); 819 } 820 821 static bool trans_VSBC(DisasContext *s, arg_2op *a) 822 { 823 return do_2op(s, a, gen_helper_mve_vsbc); 824 } 825 826 static bool trans_VSBCI(DisasContext *s, arg_2op *a) 827 { 828 if (mve_skip_first_beat(s)) { 829 return trans_VSBC(s, a); 830 } 831 return do_2op(s, a, gen_helper_mve_vsbci); 832 } 833 834 #define DO_2OP_FP(INSN, FN) \ 835 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 836 { \ 837 static MVEGenTwoOpFn * const fns[] = { \ 838 NULL, \ 839 gen_helper_mve_##FN##h, \ 840 gen_helper_mve_##FN##s, \ 841 NULL, \ 842 }; \ 843 if (!dc_isar_feature(aa32_mve_fp, s)) { \ 844 return false; \ 845 } \ 846 return do_2op(s, a, fns[a->size]); \ 847 } 848 849 DO_2OP_FP(VADD_fp, vfadd) 850 DO_2OP_FP(VSUB_fp, vfsub) 851 DO_2OP_FP(VMUL_fp, vfmul) 852 DO_2OP_FP(VABD_fp, vfabd) 853 DO_2OP_FP(VMAXNM, vmaxnm) 854 DO_2OP_FP(VMINNM, vminnm) 855 DO_2OP_FP(VCADD90_fp, vfcadd90) 856 DO_2OP_FP(VCADD270_fp, vfcadd270) 857 DO_2OP_FP(VFMA, vfma) 858 DO_2OP_FP(VFMS, vfms) 859 DO_2OP_FP(VCMUL0, vcmul0) 860 DO_2OP_FP(VCMUL90, vcmul90) 861 DO_2OP_FP(VCMUL180, vcmul180) 862 DO_2OP_FP(VCMUL270, vcmul270) 863 DO_2OP_FP(VCMLA0, vcmla0) 864 DO_2OP_FP(VCMLA90, vcmla90) 865 DO_2OP_FP(VCMLA180, vcmla180) 866 DO_2OP_FP(VCMLA270, vcmla270) 867 DO_2OP_FP(VMAXNMA, vmaxnma) 868 DO_2OP_FP(VMINNMA, vminnma) 869 870 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, 871 MVEGenTwoOpScalarFn fn) 872 { 873 TCGv_ptr qd, qn; 874 TCGv_i32 rm; 875 876 if (!dc_isar_feature(aa32_mve, s) || 877 !mve_check_qreg_bank(s, a->qd | a->qn) || 878 !fn) { 879 return false; 880 } 881 if (a->rm == 13 || a->rm == 15) { 882 /* UNPREDICTABLE */ 883 return false; 884 } 885 if (!mve_eci_check(s) || !vfp_access_check(s)) { 886 return true; 887 } 888 889 qd = mve_qreg_ptr(a->qd); 890 qn = mve_qreg_ptr(a->qn); 891 rm = load_reg(s, a->rm); 892 fn(cpu_env, qd, qn, rm); 893 tcg_temp_free_i32(rm); 894 tcg_temp_free_ptr(qd); 895 tcg_temp_free_ptr(qn); 896 mve_update_eci(s); 897 return true; 898 } 899 900 #define DO_2OP_SCALAR(INSN, FN) \ 901 static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ 902 { \ 903 static MVEGenTwoOpScalarFn * const fns[] = { \ 904 gen_helper_mve_##FN##b, \ 905 gen_helper_mve_##FN##h, \ 906 gen_helper_mve_##FN##w, \ 907 NULL, \ 908 }; \ 909 return do_2op_scalar(s, a, fns[a->size]); \ 910 } 911 912 DO_2OP_SCALAR(VADD_scalar, vadd_scalar) 913 DO_2OP_SCALAR(VSUB_scalar, vsub_scalar) 914 DO_2OP_SCALAR(VMUL_scalar, vmul_scalar) 915 DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) 916 DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) 917 DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) 918 DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) 919 DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar) 920 DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar) 921 DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar) 922 DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) 923 DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) 924 DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) 925 DO_2OP_SCALAR(VBRSR, vbrsr) 926 DO_2OP_SCALAR(VMLA, vmla) 927 DO_2OP_SCALAR(VMLAS, vmlas) 928 DO_2OP_SCALAR(VQDMLAH, vqdmlah) 929 DO_2OP_SCALAR(VQRDMLAH, vqrdmlah) 930 DO_2OP_SCALAR(VQDMLASH, vqdmlash) 931 DO_2OP_SCALAR(VQRDMLASH, vqrdmlash) 932 933 static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a) 934 { 935 static MVEGenTwoOpScalarFn * const fns[] = { 936 NULL, 937 gen_helper_mve_vqdmullb_scalarh, 938 gen_helper_mve_vqdmullb_scalarw, 939 NULL, 940 }; 941 if (a->qd == a->qn && a->size == MO_32) { 942 /* UNPREDICTABLE; we choose to undef */ 943 return false; 944 } 945 return do_2op_scalar(s, a, fns[a->size]); 946 } 947 948 static bool trans_VQDMULLT_scalar(DisasContext *s, arg_2scalar *a) 949 { 950 static MVEGenTwoOpScalarFn * const fns[] = { 951 NULL, 952 gen_helper_mve_vqdmullt_scalarh, 953 gen_helper_mve_vqdmullt_scalarw, 954 NULL, 955 }; 956 if (a->qd == a->qn && a->size == MO_32) { 957 /* UNPREDICTABLE; we choose to undef */ 958 return false; 959 } 960 return do_2op_scalar(s, a, fns[a->size]); 961 } 962 963 964 #define DO_2OP_FP_SCALAR(INSN, FN) \ 965 static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ 966 { \ 967 static MVEGenTwoOpScalarFn * const fns[] = { \ 968 NULL, \ 969 gen_helper_mve_##FN##h, \ 970 gen_helper_mve_##FN##s, \ 971 NULL, \ 972 }; \ 973 if (!dc_isar_feature(aa32_mve_fp, s)) { \ 974 return false; \ 975 } \ 976 return do_2op_scalar(s, a, fns[a->size]); \ 977 } 978 979 DO_2OP_FP_SCALAR(VADD_fp_scalar, vfadd_scalar) 980 DO_2OP_FP_SCALAR(VSUB_fp_scalar, vfsub_scalar) 981 DO_2OP_FP_SCALAR(VMUL_fp_scalar, vfmul_scalar) 982 983 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, 984 MVEGenLongDualAccOpFn *fn) 985 { 986 TCGv_ptr qn, qm; 987 TCGv_i64 rda; 988 TCGv_i32 rdalo, rdahi; 989 990 if (!dc_isar_feature(aa32_mve, s) || 991 !mve_check_qreg_bank(s, a->qn | a->qm) || 992 !fn) { 993 return false; 994 } 995 /* 996 * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related 997 * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. 998 */ 999 if (a->rdahi == 13 || a->rdahi == 15) { 1000 return false; 1001 } 1002 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1003 return true; 1004 } 1005 1006 qn = mve_qreg_ptr(a->qn); 1007 qm = mve_qreg_ptr(a->qm); 1008 1009 /* 1010 * This insn is subject to beat-wise execution. Partial execution 1011 * of an A=0 (no-accumulate) insn which does not execute the first 1012 * beat must start with the current rda value, not 0. 1013 */ 1014 if (a->a || mve_skip_first_beat(s)) { 1015 rda = tcg_temp_new_i64(); 1016 rdalo = load_reg(s, a->rdalo); 1017 rdahi = load_reg(s, a->rdahi); 1018 tcg_gen_concat_i32_i64(rda, rdalo, rdahi); 1019 tcg_temp_free_i32(rdalo); 1020 tcg_temp_free_i32(rdahi); 1021 } else { 1022 rda = tcg_const_i64(0); 1023 } 1024 1025 fn(rda, cpu_env, qn, qm, rda); 1026 tcg_temp_free_ptr(qn); 1027 tcg_temp_free_ptr(qm); 1028 1029 rdalo = tcg_temp_new_i32(); 1030 rdahi = tcg_temp_new_i32(); 1031 tcg_gen_extrl_i64_i32(rdalo, rda); 1032 tcg_gen_extrh_i64_i32(rdahi, rda); 1033 store_reg(s, a->rdalo, rdalo); 1034 store_reg(s, a->rdahi, rdahi); 1035 tcg_temp_free_i64(rda); 1036 mve_update_eci(s); 1037 return true; 1038 } 1039 1040 static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a) 1041 { 1042 static MVEGenLongDualAccOpFn * const fns[4][2] = { 1043 { NULL, NULL }, 1044 { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh }, 1045 { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw }, 1046 { NULL, NULL }, 1047 }; 1048 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1049 } 1050 1051 static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a) 1052 { 1053 static MVEGenLongDualAccOpFn * const fns[4][2] = { 1054 { NULL, NULL }, 1055 { gen_helper_mve_vmlaldavuh, NULL }, 1056 { gen_helper_mve_vmlaldavuw, NULL }, 1057 { NULL, NULL }, 1058 }; 1059 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1060 } 1061 1062 static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) 1063 { 1064 static MVEGenLongDualAccOpFn * const fns[4][2] = { 1065 { NULL, NULL }, 1066 { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh }, 1067 { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw }, 1068 { NULL, NULL }, 1069 }; 1070 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1071 } 1072 1073 static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a) 1074 { 1075 static MVEGenLongDualAccOpFn * const fns[] = { 1076 gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw, 1077 }; 1078 return do_long_dual_acc(s, a, fns[a->x]); 1079 } 1080 1081 static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a) 1082 { 1083 static MVEGenLongDualAccOpFn * const fns[] = { 1084 gen_helper_mve_vrmlaldavhuw, NULL, 1085 }; 1086 return do_long_dual_acc(s, a, fns[a->x]); 1087 } 1088 1089 static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) 1090 { 1091 static MVEGenLongDualAccOpFn * const fns[] = { 1092 gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw, 1093 }; 1094 return do_long_dual_acc(s, a, fns[a->x]); 1095 } 1096 1097 static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn) 1098 { 1099 TCGv_ptr qn, qm; 1100 TCGv_i32 rda; 1101 1102 if (!dc_isar_feature(aa32_mve, s) || 1103 !mve_check_qreg_bank(s, a->qn) || 1104 !fn) { 1105 return false; 1106 } 1107 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1108 return true; 1109 } 1110 1111 qn = mve_qreg_ptr(a->qn); 1112 qm = mve_qreg_ptr(a->qm); 1113 1114 /* 1115 * This insn is subject to beat-wise execution. Partial execution 1116 * of an A=0 (no-accumulate) insn which does not execute the first 1117 * beat must start with the current rda value, not 0. 1118 */ 1119 if (a->a || mve_skip_first_beat(s)) { 1120 rda = load_reg(s, a->rda); 1121 } else { 1122 rda = tcg_const_i32(0); 1123 } 1124 1125 fn(rda, cpu_env, qn, qm, rda); 1126 store_reg(s, a->rda, rda); 1127 tcg_temp_free_ptr(qn); 1128 tcg_temp_free_ptr(qm); 1129 1130 mve_update_eci(s); 1131 return true; 1132 } 1133 1134 #define DO_DUAL_ACC(INSN, FN) \ 1135 static bool trans_##INSN(DisasContext *s, arg_vmladav *a) \ 1136 { \ 1137 static MVEGenDualAccOpFn * const fns[4][2] = { \ 1138 { gen_helper_mve_##FN##b, gen_helper_mve_##FN##xb }, \ 1139 { gen_helper_mve_##FN##h, gen_helper_mve_##FN##xh }, \ 1140 { gen_helper_mve_##FN##w, gen_helper_mve_##FN##xw }, \ 1141 { NULL, NULL }, \ 1142 }; \ 1143 return do_dual_acc(s, a, fns[a->size][a->x]); \ 1144 } 1145 1146 DO_DUAL_ACC(VMLADAV_S, vmladavs) 1147 DO_DUAL_ACC(VMLSDAV, vmlsdav) 1148 1149 static bool trans_VMLADAV_U(DisasContext *s, arg_vmladav *a) 1150 { 1151 static MVEGenDualAccOpFn * const fns[4][2] = { 1152 { gen_helper_mve_vmladavub, NULL }, 1153 { gen_helper_mve_vmladavuh, NULL }, 1154 { gen_helper_mve_vmladavuw, NULL }, 1155 { NULL, NULL }, 1156 }; 1157 return do_dual_acc(s, a, fns[a->size][a->x]); 1158 } 1159 1160 static void gen_vpst(DisasContext *s, uint32_t mask) 1161 { 1162 /* 1163 * Set the VPR mask fields. We take advantage of MASK01 and MASK23 1164 * being adjacent fields in the register. 1165 * 1166 * Updating the masks is not predicated, but it is subject to beat-wise 1167 * execution, and the mask is updated on the odd-numbered beats. 1168 * So if PSR.ECI says we should skip beat 1, we mustn't update the 1169 * 01 mask field. 1170 */ 1171 TCGv_i32 vpr = load_cpu_field(v7m.vpr); 1172 switch (s->eci) { 1173 case ECI_NONE: 1174 case ECI_A0: 1175 /* Update both 01 and 23 fields */ 1176 tcg_gen_deposit_i32(vpr, vpr, 1177 tcg_constant_i32(mask | (mask << 4)), 1178 R_V7M_VPR_MASK01_SHIFT, 1179 R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH); 1180 break; 1181 case ECI_A0A1: 1182 case ECI_A0A1A2: 1183 case ECI_A0A1A2B0: 1184 /* Update only the 23 mask field */ 1185 tcg_gen_deposit_i32(vpr, vpr, 1186 tcg_constant_i32(mask), 1187 R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH); 1188 break; 1189 default: 1190 g_assert_not_reached(); 1191 } 1192 store_cpu_field(vpr, v7m.vpr); 1193 } 1194 1195 static bool trans_VPST(DisasContext *s, arg_VPST *a) 1196 { 1197 /* mask == 0 is a "related encoding" */ 1198 if (!dc_isar_feature(aa32_mve, s) || !a->mask) { 1199 return false; 1200 } 1201 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1202 return true; 1203 } 1204 gen_vpst(s, a->mask); 1205 mve_update_and_store_eci(s); 1206 return true; 1207 } 1208 1209 static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a) 1210 { 1211 /* 1212 * Invert the predicate in VPR.P0. We have call out to 1213 * a helper because this insn itself is beatwise and can 1214 * be predicated. 1215 */ 1216 if (!dc_isar_feature(aa32_mve, s)) { 1217 return false; 1218 } 1219 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1220 return true; 1221 } 1222 1223 gen_helper_mve_vpnot(cpu_env); 1224 mve_update_eci(s); 1225 return true; 1226 } 1227 1228 static bool trans_VADDV(DisasContext *s, arg_VADDV *a) 1229 { 1230 /* VADDV: vector add across vector */ 1231 static MVEGenVADDVFn * const fns[4][2] = { 1232 { gen_helper_mve_vaddvsb, gen_helper_mve_vaddvub }, 1233 { gen_helper_mve_vaddvsh, gen_helper_mve_vaddvuh }, 1234 { gen_helper_mve_vaddvsw, gen_helper_mve_vaddvuw }, 1235 { NULL, NULL } 1236 }; 1237 TCGv_ptr qm; 1238 TCGv_i32 rda; 1239 1240 if (!dc_isar_feature(aa32_mve, s) || 1241 a->size == 3) { 1242 return false; 1243 } 1244 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1245 return true; 1246 } 1247 1248 /* 1249 * This insn is subject to beat-wise execution. Partial execution 1250 * of an A=0 (no-accumulate) insn which does not execute the first 1251 * beat must start with the current value of Rda, not zero. 1252 */ 1253 if (a->a || mve_skip_first_beat(s)) { 1254 /* Accumulate input from Rda */ 1255 rda = load_reg(s, a->rda); 1256 } else { 1257 /* Accumulate starting at zero */ 1258 rda = tcg_const_i32(0); 1259 } 1260 1261 qm = mve_qreg_ptr(a->qm); 1262 fns[a->size][a->u](rda, cpu_env, qm, rda); 1263 store_reg(s, a->rda, rda); 1264 tcg_temp_free_ptr(qm); 1265 1266 mve_update_eci(s); 1267 return true; 1268 } 1269 1270 static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) 1271 { 1272 /* 1273 * Vector Add Long Across Vector: accumulate the 32-bit 1274 * elements of the vector into a 64-bit result stored in 1275 * a pair of general-purpose registers. 1276 * No need to check Qm's bank: it is only 3 bits in decode. 1277 */ 1278 TCGv_ptr qm; 1279 TCGv_i64 rda; 1280 TCGv_i32 rdalo, rdahi; 1281 1282 if (!dc_isar_feature(aa32_mve, s)) { 1283 return false; 1284 } 1285 /* 1286 * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related 1287 * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. 1288 */ 1289 if (a->rdahi == 13 || a->rdahi == 15) { 1290 return false; 1291 } 1292 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1293 return true; 1294 } 1295 1296 /* 1297 * This insn is subject to beat-wise execution. Partial execution 1298 * of an A=0 (no-accumulate) insn which does not execute the first 1299 * beat must start with the current value of RdaHi:RdaLo, not zero. 1300 */ 1301 if (a->a || mve_skip_first_beat(s)) { 1302 /* Accumulate input from RdaHi:RdaLo */ 1303 rda = tcg_temp_new_i64(); 1304 rdalo = load_reg(s, a->rdalo); 1305 rdahi = load_reg(s, a->rdahi); 1306 tcg_gen_concat_i32_i64(rda, rdalo, rdahi); 1307 tcg_temp_free_i32(rdalo); 1308 tcg_temp_free_i32(rdahi); 1309 } else { 1310 /* Accumulate starting at zero */ 1311 rda = tcg_const_i64(0); 1312 } 1313 1314 qm = mve_qreg_ptr(a->qm); 1315 if (a->u) { 1316 gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda); 1317 } else { 1318 gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); 1319 } 1320 tcg_temp_free_ptr(qm); 1321 1322 rdalo = tcg_temp_new_i32(); 1323 rdahi = tcg_temp_new_i32(); 1324 tcg_gen_extrl_i64_i32(rdalo, rda); 1325 tcg_gen_extrh_i64_i32(rdahi, rda); 1326 store_reg(s, a->rdalo, rdalo); 1327 store_reg(s, a->rdahi, rdahi); 1328 tcg_temp_free_i64(rda); 1329 mve_update_eci(s); 1330 return true; 1331 } 1332 1333 static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) 1334 { 1335 TCGv_ptr qd; 1336 uint64_t imm; 1337 1338 if (!dc_isar_feature(aa32_mve, s) || 1339 !mve_check_qreg_bank(s, a->qd) || 1340 !fn) { 1341 return false; 1342 } 1343 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1344 return true; 1345 } 1346 1347 imm = asimd_imm_const(a->imm, a->cmode, a->op); 1348 1349 qd = mve_qreg_ptr(a->qd); 1350 fn(cpu_env, qd, tcg_constant_i64(imm)); 1351 tcg_temp_free_ptr(qd); 1352 mve_update_eci(s); 1353 return true; 1354 } 1355 1356 static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) 1357 { 1358 /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ 1359 MVEGenOneOpImmFn *fn; 1360 1361 if ((a->cmode & 1) && a->cmode < 12) { 1362 if (a->op) { 1363 /* 1364 * For op=1, the immediate will be inverted by asimd_imm_const(), 1365 * so the VBIC becomes a logical AND operation. 1366 */ 1367 fn = gen_helper_mve_vandi; 1368 } else { 1369 fn = gen_helper_mve_vorri; 1370 } 1371 } else { 1372 /* There is one unallocated cmode/op combination in this space */ 1373 if (a->cmode == 15 && a->op == 1) { 1374 return false; 1375 } 1376 /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ 1377 fn = gen_helper_mve_vmovi; 1378 } 1379 return do_1imm(s, a, fn); 1380 } 1381 1382 static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, 1383 bool negateshift) 1384 { 1385 TCGv_ptr qd, qm; 1386 int shift = a->shift; 1387 1388 if (!dc_isar_feature(aa32_mve, s) || 1389 !mve_check_qreg_bank(s, a->qd | a->qm) || 1390 !fn) { 1391 return false; 1392 } 1393 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1394 return true; 1395 } 1396 1397 /* 1398 * When we handle a right shift insn using a left-shift helper 1399 * which permits a negative shift count to indicate a right-shift, 1400 * we must negate the shift count. 1401 */ 1402 if (negateshift) { 1403 shift = -shift; 1404 } 1405 1406 qd = mve_qreg_ptr(a->qd); 1407 qm = mve_qreg_ptr(a->qm); 1408 fn(cpu_env, qd, qm, tcg_constant_i32(shift)); 1409 tcg_temp_free_ptr(qd); 1410 tcg_temp_free_ptr(qm); 1411 mve_update_eci(s); 1412 return true; 1413 } 1414 1415 #define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ 1416 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1417 { \ 1418 static MVEGenTwoOpShiftFn * const fns[] = { \ 1419 gen_helper_mve_##FN##b, \ 1420 gen_helper_mve_##FN##h, \ 1421 gen_helper_mve_##FN##w, \ 1422 NULL, \ 1423 }; \ 1424 return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ 1425 } 1426 1427 DO_2SHIFT(VSHLI, vshli_u, false) 1428 DO_2SHIFT(VQSHLI_S, vqshli_s, false) 1429 DO_2SHIFT(VQSHLI_U, vqshli_u, false) 1430 DO_2SHIFT(VQSHLUI, vqshlui_s, false) 1431 /* These right shifts use a left-shift helper with negated shift count */ 1432 DO_2SHIFT(VSHRI_S, vshli_s, true) 1433 DO_2SHIFT(VSHRI_U, vshli_u, true) 1434 DO_2SHIFT(VRSHRI_S, vrshli_s, true) 1435 DO_2SHIFT(VRSHRI_U, vrshli_u, true) 1436 1437 DO_2SHIFT(VSRI, vsri, false) 1438 DO_2SHIFT(VSLI, vsli, false) 1439 1440 static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a, 1441 MVEGenTwoOpShiftFn *fn) 1442 { 1443 TCGv_ptr qda; 1444 TCGv_i32 rm; 1445 1446 if (!dc_isar_feature(aa32_mve, s) || 1447 !mve_check_qreg_bank(s, a->qda) || 1448 a->rm == 13 || a->rm == 15 || !fn) { 1449 /* Rm cases are UNPREDICTABLE */ 1450 return false; 1451 } 1452 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1453 return true; 1454 } 1455 1456 qda = mve_qreg_ptr(a->qda); 1457 rm = load_reg(s, a->rm); 1458 fn(cpu_env, qda, qda, rm); 1459 tcg_temp_free_ptr(qda); 1460 tcg_temp_free_i32(rm); 1461 mve_update_eci(s); 1462 return true; 1463 } 1464 1465 #define DO_2SHIFT_SCALAR(INSN, FN) \ 1466 static bool trans_##INSN(DisasContext *s, arg_shl_scalar *a) \ 1467 { \ 1468 static MVEGenTwoOpShiftFn * const fns[] = { \ 1469 gen_helper_mve_##FN##b, \ 1470 gen_helper_mve_##FN##h, \ 1471 gen_helper_mve_##FN##w, \ 1472 NULL, \ 1473 }; \ 1474 return do_2shift_scalar(s, a, fns[a->size]); \ 1475 } 1476 1477 DO_2SHIFT_SCALAR(VSHL_S_scalar, vshli_s) 1478 DO_2SHIFT_SCALAR(VSHL_U_scalar, vshli_u) 1479 DO_2SHIFT_SCALAR(VRSHL_S_scalar, vrshli_s) 1480 DO_2SHIFT_SCALAR(VRSHL_U_scalar, vrshli_u) 1481 DO_2SHIFT_SCALAR(VQSHL_S_scalar, vqshli_s) 1482 DO_2SHIFT_SCALAR(VQSHL_U_scalar, vqshli_u) 1483 DO_2SHIFT_SCALAR(VQRSHL_S_scalar, vqrshli_s) 1484 DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u) 1485 1486 #define DO_VSHLL(INSN, FN) \ 1487 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1488 { \ 1489 static MVEGenTwoOpShiftFn * const fns[] = { \ 1490 gen_helper_mve_##FN##b, \ 1491 gen_helper_mve_##FN##h, \ 1492 }; \ 1493 return do_2shift(s, a, fns[a->size], false); \ 1494 } 1495 1496 DO_VSHLL(VSHLL_BS, vshllbs) 1497 DO_VSHLL(VSHLL_BU, vshllbu) 1498 DO_VSHLL(VSHLL_TS, vshllts) 1499 DO_VSHLL(VSHLL_TU, vshlltu) 1500 1501 #define DO_2SHIFT_N(INSN, FN) \ 1502 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1503 { \ 1504 static MVEGenTwoOpShiftFn * const fns[] = { \ 1505 gen_helper_mve_##FN##b, \ 1506 gen_helper_mve_##FN##h, \ 1507 }; \ 1508 return do_2shift(s, a, fns[a->size], false); \ 1509 } 1510 1511 DO_2SHIFT_N(VSHRNB, vshrnb) 1512 DO_2SHIFT_N(VSHRNT, vshrnt) 1513 DO_2SHIFT_N(VRSHRNB, vrshrnb) 1514 DO_2SHIFT_N(VRSHRNT, vrshrnt) 1515 DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s) 1516 DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s) 1517 DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u) 1518 DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u) 1519 DO_2SHIFT_N(VQSHRUNB, vqshrunb) 1520 DO_2SHIFT_N(VQSHRUNT, vqshrunt) 1521 DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s) 1522 DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s) 1523 DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) 1524 DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) 1525 DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) 1526 DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) 1527 1528 static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) 1529 { 1530 /* 1531 * Whole Vector Left Shift with Carry. The carry is taken 1532 * from a general purpose register and written back there. 1533 * An imm of 0 means "shift by 32". 1534 */ 1535 TCGv_ptr qd; 1536 TCGv_i32 rdm; 1537 1538 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1539 return false; 1540 } 1541 if (a->rdm == 13 || a->rdm == 15) { 1542 /* CONSTRAINED UNPREDICTABLE: we UNDEF */ 1543 return false; 1544 } 1545 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1546 return true; 1547 } 1548 1549 qd = mve_qreg_ptr(a->qd); 1550 rdm = load_reg(s, a->rdm); 1551 gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); 1552 store_reg(s, a->rdm, rdm); 1553 tcg_temp_free_ptr(qd); 1554 mve_update_eci(s); 1555 return true; 1556 } 1557 1558 static bool do_vidup(DisasContext *s, arg_vidup *a, MVEGenVIDUPFn *fn) 1559 { 1560 TCGv_ptr qd; 1561 TCGv_i32 rn; 1562 1563 /* 1564 * Vector increment/decrement with wrap and duplicate (VIDUP, VDDUP). 1565 * This fills the vector with elements of successively increasing 1566 * or decreasing values, starting from Rn. 1567 */ 1568 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1569 return false; 1570 } 1571 if (a->size == MO_64) { 1572 /* size 0b11 is another encoding */ 1573 return false; 1574 } 1575 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1576 return true; 1577 } 1578 1579 qd = mve_qreg_ptr(a->qd); 1580 rn = load_reg(s, a->rn); 1581 fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm)); 1582 store_reg(s, a->rn, rn); 1583 tcg_temp_free_ptr(qd); 1584 mve_update_eci(s); 1585 return true; 1586 } 1587 1588 static bool do_viwdup(DisasContext *s, arg_viwdup *a, MVEGenVIWDUPFn *fn) 1589 { 1590 TCGv_ptr qd; 1591 TCGv_i32 rn, rm; 1592 1593 /* 1594 * Vector increment/decrement with wrap and duplicate (VIWDUp, VDWDUP) 1595 * This fills the vector with elements of successively increasing 1596 * or decreasing values, starting from Rn. Rm specifies a point where 1597 * the count wraps back around to 0. The updated offset is written back 1598 * to Rn. 1599 */ 1600 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1601 return false; 1602 } 1603 if (!fn || a->rm == 13 || a->rm == 15) { 1604 /* 1605 * size 0b11 is another encoding; Rm == 13 is UNPREDICTABLE; 1606 * Rm == 13 is VIWDUP, VDWDUP. 1607 */ 1608 return false; 1609 } 1610 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1611 return true; 1612 } 1613 1614 qd = mve_qreg_ptr(a->qd); 1615 rn = load_reg(s, a->rn); 1616 rm = load_reg(s, a->rm); 1617 fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm)); 1618 store_reg(s, a->rn, rn); 1619 tcg_temp_free_ptr(qd); 1620 tcg_temp_free_i32(rm); 1621 mve_update_eci(s); 1622 return true; 1623 } 1624 1625 static bool trans_VIDUP(DisasContext *s, arg_vidup *a) 1626 { 1627 static MVEGenVIDUPFn * const fns[] = { 1628 gen_helper_mve_vidupb, 1629 gen_helper_mve_viduph, 1630 gen_helper_mve_vidupw, 1631 NULL, 1632 }; 1633 return do_vidup(s, a, fns[a->size]); 1634 } 1635 1636 static bool trans_VDDUP(DisasContext *s, arg_vidup *a) 1637 { 1638 static MVEGenVIDUPFn * const fns[] = { 1639 gen_helper_mve_vidupb, 1640 gen_helper_mve_viduph, 1641 gen_helper_mve_vidupw, 1642 NULL, 1643 }; 1644 /* VDDUP is just like VIDUP but with a negative immediate */ 1645 a->imm = -a->imm; 1646 return do_vidup(s, a, fns[a->size]); 1647 } 1648 1649 static bool trans_VIWDUP(DisasContext *s, arg_viwdup *a) 1650 { 1651 static MVEGenVIWDUPFn * const fns[] = { 1652 gen_helper_mve_viwdupb, 1653 gen_helper_mve_viwduph, 1654 gen_helper_mve_viwdupw, 1655 NULL, 1656 }; 1657 return do_viwdup(s, a, fns[a->size]); 1658 } 1659 1660 static bool trans_VDWDUP(DisasContext *s, arg_viwdup *a) 1661 { 1662 static MVEGenVIWDUPFn * const fns[] = { 1663 gen_helper_mve_vdwdupb, 1664 gen_helper_mve_vdwduph, 1665 gen_helper_mve_vdwdupw, 1666 NULL, 1667 }; 1668 return do_viwdup(s, a, fns[a->size]); 1669 } 1670 1671 static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn) 1672 { 1673 TCGv_ptr qn, qm; 1674 1675 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) || 1676 !fn) { 1677 return false; 1678 } 1679 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1680 return true; 1681 } 1682 1683 qn = mve_qreg_ptr(a->qn); 1684 qm = mve_qreg_ptr(a->qm); 1685 fn(cpu_env, qn, qm); 1686 tcg_temp_free_ptr(qn); 1687 tcg_temp_free_ptr(qm); 1688 if (a->mask) { 1689 /* VPT */ 1690 gen_vpst(s, a->mask); 1691 } 1692 mve_update_eci(s); 1693 return true; 1694 } 1695 1696 static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a, 1697 MVEGenScalarCmpFn *fn) 1698 { 1699 TCGv_ptr qn; 1700 TCGv_i32 rm; 1701 1702 if (!dc_isar_feature(aa32_mve, s) || !fn || a->rm == 13) { 1703 return false; 1704 } 1705 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1706 return true; 1707 } 1708 1709 qn = mve_qreg_ptr(a->qn); 1710 if (a->rm == 15) { 1711 /* Encoding Rm=0b1111 means "constant zero" */ 1712 rm = tcg_constant_i32(0); 1713 } else { 1714 rm = load_reg(s, a->rm); 1715 } 1716 fn(cpu_env, qn, rm); 1717 tcg_temp_free_ptr(qn); 1718 tcg_temp_free_i32(rm); 1719 if (a->mask) { 1720 /* VPT */ 1721 gen_vpst(s, a->mask); 1722 } 1723 mve_update_eci(s); 1724 return true; 1725 } 1726 1727 #define DO_VCMP(INSN, FN) \ 1728 static bool trans_##INSN(DisasContext *s, arg_vcmp *a) \ 1729 { \ 1730 static MVEGenCmpFn * const fns[] = { \ 1731 gen_helper_mve_##FN##b, \ 1732 gen_helper_mve_##FN##h, \ 1733 gen_helper_mve_##FN##w, \ 1734 NULL, \ 1735 }; \ 1736 return do_vcmp(s, a, fns[a->size]); \ 1737 } \ 1738 static bool trans_##INSN##_scalar(DisasContext *s, \ 1739 arg_vcmp_scalar *a) \ 1740 { \ 1741 static MVEGenScalarCmpFn * const fns[] = { \ 1742 gen_helper_mve_##FN##_scalarb, \ 1743 gen_helper_mve_##FN##_scalarh, \ 1744 gen_helper_mve_##FN##_scalarw, \ 1745 NULL, \ 1746 }; \ 1747 return do_vcmp_scalar(s, a, fns[a->size]); \ 1748 } 1749 1750 DO_VCMP(VCMPEQ, vcmpeq) 1751 DO_VCMP(VCMPNE, vcmpne) 1752 DO_VCMP(VCMPCS, vcmpcs) 1753 DO_VCMP(VCMPHI, vcmphi) 1754 DO_VCMP(VCMPGE, vcmpge) 1755 DO_VCMP(VCMPLT, vcmplt) 1756 DO_VCMP(VCMPGT, vcmpgt) 1757 DO_VCMP(VCMPLE, vcmple) 1758 1759 static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn) 1760 { 1761 /* 1762 * MIN/MAX operations across a vector: compute the min or 1763 * max of the initial value in a general purpose register 1764 * and all the elements in the vector, and store it back 1765 * into the general purpose register. 1766 */ 1767 TCGv_ptr qm; 1768 TCGv_i32 rda; 1769 1770 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) || 1771 !fn || a->rda == 13 || a->rda == 15) { 1772 /* Rda cases are UNPREDICTABLE */ 1773 return false; 1774 } 1775 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1776 return true; 1777 } 1778 1779 qm = mve_qreg_ptr(a->qm); 1780 rda = load_reg(s, a->rda); 1781 fn(rda, cpu_env, qm, rda); 1782 store_reg(s, a->rda, rda); 1783 tcg_temp_free_ptr(qm); 1784 mve_update_eci(s); 1785 return true; 1786 } 1787 1788 #define DO_VMAXV(INSN, FN) \ 1789 static bool trans_##INSN(DisasContext *s, arg_vmaxv *a) \ 1790 { \ 1791 static MVEGenVADDVFn * const fns[] = { \ 1792 gen_helper_mve_##FN##b, \ 1793 gen_helper_mve_##FN##h, \ 1794 gen_helper_mve_##FN##w, \ 1795 NULL, \ 1796 }; \ 1797 return do_vmaxv(s, a, fns[a->size]); \ 1798 } 1799 1800 DO_VMAXV(VMAXV_S, vmaxvs) 1801 DO_VMAXV(VMAXV_U, vmaxvu) 1802 DO_VMAXV(VMAXAV, vmaxav) 1803 DO_VMAXV(VMINV_S, vminvs) 1804 DO_VMAXV(VMINV_U, vminvu) 1805 DO_VMAXV(VMINAV, vminav) 1806 1807 static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn) 1808 { 1809 /* Absolute difference accumulated across vector */ 1810 TCGv_ptr qn, qm; 1811 TCGv_i32 rda; 1812 1813 if (!dc_isar_feature(aa32_mve, s) || 1814 !mve_check_qreg_bank(s, a->qm | a->qn) || 1815 !fn || a->rda == 13 || a->rda == 15) { 1816 /* Rda cases are UNPREDICTABLE */ 1817 return false; 1818 } 1819 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1820 return true; 1821 } 1822 1823 qm = mve_qreg_ptr(a->qm); 1824 qn = mve_qreg_ptr(a->qn); 1825 rda = load_reg(s, a->rda); 1826 fn(rda, cpu_env, qn, qm, rda); 1827 store_reg(s, a->rda, rda); 1828 tcg_temp_free_ptr(qm); 1829 tcg_temp_free_ptr(qn); 1830 mve_update_eci(s); 1831 return true; 1832 } 1833 1834 #define DO_VABAV(INSN, FN) \ 1835 static bool trans_##INSN(DisasContext *s, arg_vabav *a) \ 1836 { \ 1837 static MVEGenVABAVFn * const fns[] = { \ 1838 gen_helper_mve_##FN##b, \ 1839 gen_helper_mve_##FN##h, \ 1840 gen_helper_mve_##FN##w, \ 1841 NULL, \ 1842 }; \ 1843 return do_vabav(s, a, fns[a->size]); \ 1844 } 1845 1846 DO_VABAV(VABAV_S, vabavs) 1847 DO_VABAV(VABAV_U, vabavu) 1848 1849 static bool trans_VMOV_to_2gp(DisasContext *s, arg_VMOV_to_2gp *a) 1850 { 1851 /* 1852 * VMOV two 32-bit vector lanes to two general-purpose registers. 1853 * This insn is not predicated but it is subject to beat-wise 1854 * execution if it is not in an IT block. For us this means 1855 * only that if PSR.ECI says we should not be executing the beat 1856 * corresponding to the lane of the vector register being accessed 1857 * then we should skip perfoming the move, and that we need to do 1858 * the usual check for bad ECI state and advance of ECI state. 1859 * (If PSR.ECI is non-zero then we cannot be in an IT block.) 1860 */ 1861 TCGv_i32 tmp; 1862 int vd; 1863 1864 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) || 1865 a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15 || 1866 a->rt == a->rt2) { 1867 /* Rt/Rt2 cases are UNPREDICTABLE */ 1868 return false; 1869 } 1870 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1871 return true; 1872 } 1873 1874 /* Convert Qreg index to Dreg for read_neon_element32() etc */ 1875 vd = a->qd * 2; 1876 1877 if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { 1878 tmp = tcg_temp_new_i32(); 1879 read_neon_element32(tmp, vd, a->idx, MO_32); 1880 store_reg(s, a->rt, tmp); 1881 } 1882 if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { 1883 tmp = tcg_temp_new_i32(); 1884 read_neon_element32(tmp, vd + 1, a->idx, MO_32); 1885 store_reg(s, a->rt2, tmp); 1886 } 1887 1888 mve_update_and_store_eci(s); 1889 return true; 1890 } 1891 1892 static bool trans_VMOV_from_2gp(DisasContext *s, arg_VMOV_to_2gp *a) 1893 { 1894 /* 1895 * VMOV two general-purpose registers to two 32-bit vector lanes. 1896 * This insn is not predicated but it is subject to beat-wise 1897 * execution if it is not in an IT block. For us this means 1898 * only that if PSR.ECI says we should not be executing the beat 1899 * corresponding to the lane of the vector register being accessed 1900 * then we should skip perfoming the move, and that we need to do 1901 * the usual check for bad ECI state and advance of ECI state. 1902 * (If PSR.ECI is non-zero then we cannot be in an IT block.) 1903 */ 1904 TCGv_i32 tmp; 1905 int vd; 1906 1907 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) || 1908 a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15) { 1909 /* Rt/Rt2 cases are UNPREDICTABLE */ 1910 return false; 1911 } 1912 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1913 return true; 1914 } 1915 1916 /* Convert Qreg idx to Dreg for read_neon_element32() etc */ 1917 vd = a->qd * 2; 1918 1919 if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { 1920 tmp = load_reg(s, a->rt); 1921 write_neon_element32(tmp, vd, a->idx, MO_32); 1922 tcg_temp_free_i32(tmp); 1923 } 1924 if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { 1925 tmp = load_reg(s, a->rt2); 1926 write_neon_element32(tmp, vd + 1, a->idx, MO_32); 1927 tcg_temp_free_i32(tmp); 1928 } 1929 1930 mve_update_and_store_eci(s); 1931 return true; 1932 } 1933