1 /* 2 * ARM translation: M-profile MVE instructions 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "tcg/tcg-op.h" 22 #include "tcg/tcg-op-gvec.h" 23 #include "exec/exec-all.h" 24 #include "exec/gen-icount.h" 25 #include "translate.h" 26 #include "translate-a32.h" 27 28 static inline int vidup_imm(DisasContext *s, int x) 29 { 30 return 1 << x; 31 } 32 33 /* Include the generated decoder */ 34 #include "decode-mve.c.inc" 35 36 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 37 typedef void MVEGenLdStSGFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 38 typedef void MVEGenLdStIlFn(TCGv_ptr, TCGv_i32, TCGv_i32); 39 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 40 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); 41 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 42 typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 43 typedef void MVEGenLongDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); 44 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); 45 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); 46 typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32); 47 typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); 48 typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 49 typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 50 typedef void MVEGenVABAVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 51 typedef void MVEGenDualAccOpFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 52 53 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ 54 static inline long mve_qreg_offset(unsigned reg) 55 { 56 return offsetof(CPUARMState, vfp.zregs[reg].d[0]); 57 } 58 59 static TCGv_ptr mve_qreg_ptr(unsigned reg) 60 { 61 TCGv_ptr ret = tcg_temp_new_ptr(); 62 tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg)); 63 return ret; 64 } 65 66 static bool mve_check_qreg_bank(DisasContext *s, int qmask) 67 { 68 /* 69 * Check whether Qregs are in range. For v8.1M only Q0..Q7 70 * are supported, see VFPSmallRegisterBank(). 71 */ 72 return qmask < 8; 73 } 74 75 bool mve_eci_check(DisasContext *s) 76 { 77 /* 78 * This is a beatwise insn: check that ECI is valid (not a 79 * reserved value) and note that we are handling it. 80 * Return true if OK, false if we generated an exception. 81 */ 82 s->eci_handled = true; 83 switch (s->eci) { 84 case ECI_NONE: 85 case ECI_A0: 86 case ECI_A0A1: 87 case ECI_A0A1A2: 88 case ECI_A0A1A2B0: 89 return true; 90 default: 91 /* Reserved value: INVSTATE UsageFault */ 92 gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), 93 default_exception_el(s)); 94 return false; 95 } 96 } 97 98 void mve_update_eci(DisasContext *s) 99 { 100 /* 101 * The helper function will always update the CPUState field, 102 * so we only need to update the DisasContext field. 103 */ 104 if (s->eci) { 105 s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE; 106 } 107 } 108 109 void mve_update_and_store_eci(DisasContext *s) 110 { 111 /* 112 * For insns which don't call a helper function that will call 113 * mve_advance_vpt(), this version updates s->eci and also stores 114 * it out to the CPUState field. 115 */ 116 if (s->eci) { 117 mve_update_eci(s); 118 store_cpu_field(tcg_constant_i32(s->eci << 4), condexec_bits); 119 } 120 } 121 122 static bool mve_skip_first_beat(DisasContext *s) 123 { 124 /* Return true if PSR.ECI says we must skip the first beat of this insn */ 125 switch (s->eci) { 126 case ECI_NONE: 127 return false; 128 case ECI_A0: 129 case ECI_A0A1: 130 case ECI_A0A1A2: 131 case ECI_A0A1A2B0: 132 return true; 133 default: 134 g_assert_not_reached(); 135 } 136 } 137 138 static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, 139 unsigned msize) 140 { 141 TCGv_i32 addr; 142 uint32_t offset; 143 TCGv_ptr qreg; 144 145 if (!dc_isar_feature(aa32_mve, s) || 146 !mve_check_qreg_bank(s, a->qd) || 147 !fn) { 148 return false; 149 } 150 151 /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ 152 if (a->rn == 15 || (a->rn == 13 && a->w)) { 153 return false; 154 } 155 156 if (!mve_eci_check(s) || !vfp_access_check(s)) { 157 return true; 158 } 159 160 offset = a->imm << msize; 161 if (!a->a) { 162 offset = -offset; 163 } 164 addr = load_reg(s, a->rn); 165 if (a->p) { 166 tcg_gen_addi_i32(addr, addr, offset); 167 } 168 169 qreg = mve_qreg_ptr(a->qd); 170 fn(cpu_env, qreg, addr); 171 tcg_temp_free_ptr(qreg); 172 173 /* 174 * Writeback always happens after the last beat of the insn, 175 * regardless of predication 176 */ 177 if (a->w) { 178 if (!a->p) { 179 tcg_gen_addi_i32(addr, addr, offset); 180 } 181 store_reg(s, a->rn, addr); 182 } else { 183 tcg_temp_free_i32(addr); 184 } 185 mve_update_eci(s); 186 return true; 187 } 188 189 static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) 190 { 191 static MVEGenLdStFn * const ldstfns[4][2] = { 192 { gen_helper_mve_vstrb, gen_helper_mve_vldrb }, 193 { gen_helper_mve_vstrh, gen_helper_mve_vldrh }, 194 { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, 195 { NULL, NULL } 196 }; 197 return do_ldst(s, a, ldstfns[a->size][a->l], a->size); 198 } 199 200 #define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \ 201 static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ 202 { \ 203 static MVEGenLdStFn * const ldstfns[2][2] = { \ 204 { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ 205 { NULL, gen_helper_mve_##ULD }, \ 206 }; \ 207 return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \ 208 } 209 210 DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8) 211 DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8) 212 DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16) 213 214 static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a, MVEGenLdStSGFn fn) 215 { 216 TCGv_i32 addr; 217 TCGv_ptr qd, qm; 218 219 if (!dc_isar_feature(aa32_mve, s) || 220 !mve_check_qreg_bank(s, a->qd | a->qm) || 221 !fn || a->rn == 15) { 222 /* Rn case is UNPREDICTABLE */ 223 return false; 224 } 225 226 if (!mve_eci_check(s) || !vfp_access_check(s)) { 227 return true; 228 } 229 230 addr = load_reg(s, a->rn); 231 232 qd = mve_qreg_ptr(a->qd); 233 qm = mve_qreg_ptr(a->qm); 234 fn(cpu_env, qd, qm, addr); 235 tcg_temp_free_ptr(qd); 236 tcg_temp_free_ptr(qm); 237 tcg_temp_free_i32(addr); 238 mve_update_eci(s); 239 return true; 240 } 241 242 /* 243 * The naming scheme here is "vldrb_sg_sh == in-memory byte loads 244 * signextended to halfword elements in register". _os_ indicates that 245 * the offsets in Qm should be scaled by the element size. 246 */ 247 /* This macro is just to make the arrays more compact in these functions */ 248 #define F(N) gen_helper_mve_##N 249 250 /* VLDRB/VSTRB (ie msize 1) with OS=1 is UNPREDICTABLE; we UNDEF */ 251 static bool trans_VLDR_S_sg(DisasContext *s, arg_vldst_sg *a) 252 { 253 static MVEGenLdStSGFn * const fns[2][4][4] = { { 254 { NULL, F(vldrb_sg_sh), F(vldrb_sg_sw), NULL }, 255 { NULL, NULL, F(vldrh_sg_sw), NULL }, 256 { NULL, NULL, NULL, NULL }, 257 { NULL, NULL, NULL, NULL } 258 }, { 259 { NULL, NULL, NULL, NULL }, 260 { NULL, NULL, F(vldrh_sg_os_sw), NULL }, 261 { NULL, NULL, NULL, NULL }, 262 { NULL, NULL, NULL, NULL } 263 } 264 }; 265 if (a->qd == a->qm) { 266 return false; /* UNPREDICTABLE */ 267 } 268 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 269 } 270 271 static bool trans_VLDR_U_sg(DisasContext *s, arg_vldst_sg *a) 272 { 273 static MVEGenLdStSGFn * const fns[2][4][4] = { { 274 { F(vldrb_sg_ub), F(vldrb_sg_uh), F(vldrb_sg_uw), NULL }, 275 { NULL, F(vldrh_sg_uh), F(vldrh_sg_uw), NULL }, 276 { NULL, NULL, F(vldrw_sg_uw), NULL }, 277 { NULL, NULL, NULL, F(vldrd_sg_ud) } 278 }, { 279 { NULL, NULL, NULL, NULL }, 280 { NULL, F(vldrh_sg_os_uh), F(vldrh_sg_os_uw), NULL }, 281 { NULL, NULL, F(vldrw_sg_os_uw), NULL }, 282 { NULL, NULL, NULL, F(vldrd_sg_os_ud) } 283 } 284 }; 285 if (a->qd == a->qm) { 286 return false; /* UNPREDICTABLE */ 287 } 288 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 289 } 290 291 static bool trans_VSTR_sg(DisasContext *s, arg_vldst_sg *a) 292 { 293 static MVEGenLdStSGFn * const fns[2][4][4] = { { 294 { F(vstrb_sg_ub), F(vstrb_sg_uh), F(vstrb_sg_uw), NULL }, 295 { NULL, F(vstrh_sg_uh), F(vstrh_sg_uw), NULL }, 296 { NULL, NULL, F(vstrw_sg_uw), NULL }, 297 { NULL, NULL, NULL, F(vstrd_sg_ud) } 298 }, { 299 { NULL, NULL, NULL, NULL }, 300 { NULL, F(vstrh_sg_os_uh), F(vstrh_sg_os_uw), NULL }, 301 { NULL, NULL, F(vstrw_sg_os_uw), NULL }, 302 { NULL, NULL, NULL, F(vstrd_sg_os_ud) } 303 } 304 }; 305 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 306 } 307 308 #undef F 309 310 static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_sg_imm *a, 311 MVEGenLdStSGFn *fn, unsigned msize) 312 { 313 uint32_t offset; 314 TCGv_ptr qd, qm; 315 316 if (!dc_isar_feature(aa32_mve, s) || 317 !mve_check_qreg_bank(s, a->qd | a->qm) || 318 !fn) { 319 return false; 320 } 321 322 if (!mve_eci_check(s) || !vfp_access_check(s)) { 323 return true; 324 } 325 326 offset = a->imm << msize; 327 if (!a->a) { 328 offset = -offset; 329 } 330 331 qd = mve_qreg_ptr(a->qd); 332 qm = mve_qreg_ptr(a->qm); 333 fn(cpu_env, qd, qm, tcg_constant_i32(offset)); 334 tcg_temp_free_ptr(qd); 335 tcg_temp_free_ptr(qm); 336 mve_update_eci(s); 337 return true; 338 } 339 340 static bool trans_VLDRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 341 { 342 static MVEGenLdStSGFn * const fns[] = { 343 gen_helper_mve_vldrw_sg_uw, 344 gen_helper_mve_vldrw_sg_wb_uw, 345 }; 346 if (a->qd == a->qm) { 347 return false; /* UNPREDICTABLE */ 348 } 349 return do_ldst_sg_imm(s, a, fns[a->w], MO_32); 350 } 351 352 static bool trans_VLDRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 353 { 354 static MVEGenLdStSGFn * const fns[] = { 355 gen_helper_mve_vldrd_sg_ud, 356 gen_helper_mve_vldrd_sg_wb_ud, 357 }; 358 if (a->qd == a->qm) { 359 return false; /* UNPREDICTABLE */ 360 } 361 return do_ldst_sg_imm(s, a, fns[a->w], MO_64); 362 } 363 364 static bool trans_VSTRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 365 { 366 static MVEGenLdStSGFn * const fns[] = { 367 gen_helper_mve_vstrw_sg_uw, 368 gen_helper_mve_vstrw_sg_wb_uw, 369 }; 370 return do_ldst_sg_imm(s, a, fns[a->w], MO_32); 371 } 372 373 static bool trans_VSTRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 374 { 375 static MVEGenLdStSGFn * const fns[] = { 376 gen_helper_mve_vstrd_sg_ud, 377 gen_helper_mve_vstrd_sg_wb_ud, 378 }; 379 return do_ldst_sg_imm(s, a, fns[a->w], MO_64); 380 } 381 382 static bool do_vldst_il(DisasContext *s, arg_vldst_il *a, MVEGenLdStIlFn *fn, 383 int addrinc) 384 { 385 TCGv_i32 rn; 386 387 if (!dc_isar_feature(aa32_mve, s) || 388 !mve_check_qreg_bank(s, a->qd) || 389 !fn || (a->rn == 13 && a->w) || a->rn == 15) { 390 /* Variously UNPREDICTABLE or UNDEF or related-encoding */ 391 return false; 392 } 393 if (!mve_eci_check(s) || !vfp_access_check(s)) { 394 return true; 395 } 396 397 rn = load_reg(s, a->rn); 398 /* 399 * We pass the index of Qd, not a pointer, because the helper must 400 * access multiple Q registers starting at Qd and working up. 401 */ 402 fn(cpu_env, tcg_constant_i32(a->qd), rn); 403 404 if (a->w) { 405 tcg_gen_addi_i32(rn, rn, addrinc); 406 store_reg(s, a->rn, rn); 407 } else { 408 tcg_temp_free_i32(rn); 409 } 410 mve_update_and_store_eci(s); 411 return true; 412 } 413 414 /* This macro is just to make the arrays more compact in these functions */ 415 #define F(N) gen_helper_mve_##N 416 417 static bool trans_VLD2(DisasContext *s, arg_vldst_il *a) 418 { 419 static MVEGenLdStIlFn * const fns[4][4] = { 420 { F(vld20b), F(vld20h), F(vld20w), NULL, }, 421 { F(vld21b), F(vld21h), F(vld21w), NULL, }, 422 { NULL, NULL, NULL, NULL }, 423 { NULL, NULL, NULL, NULL }, 424 }; 425 if (a->qd > 6) { 426 return false; 427 } 428 return do_vldst_il(s, a, fns[a->pat][a->size], 32); 429 } 430 431 static bool trans_VLD4(DisasContext *s, arg_vldst_il *a) 432 { 433 static MVEGenLdStIlFn * const fns[4][4] = { 434 { F(vld40b), F(vld40h), F(vld40w), NULL, }, 435 { F(vld41b), F(vld41h), F(vld41w), NULL, }, 436 { F(vld42b), F(vld42h), F(vld42w), NULL, }, 437 { F(vld43b), F(vld43h), F(vld43w), NULL, }, 438 }; 439 if (a->qd > 4) { 440 return false; 441 } 442 return do_vldst_il(s, a, fns[a->pat][a->size], 64); 443 } 444 445 static bool trans_VST2(DisasContext *s, arg_vldst_il *a) 446 { 447 static MVEGenLdStIlFn * const fns[4][4] = { 448 { F(vst20b), F(vst20h), F(vst20w), NULL, }, 449 { F(vst21b), F(vst21h), F(vst21w), NULL, }, 450 { NULL, NULL, NULL, NULL }, 451 { NULL, NULL, NULL, NULL }, 452 }; 453 if (a->qd > 6) { 454 return false; 455 } 456 return do_vldst_il(s, a, fns[a->pat][a->size], 32); 457 } 458 459 static bool trans_VST4(DisasContext *s, arg_vldst_il *a) 460 { 461 static MVEGenLdStIlFn * const fns[4][4] = { 462 { F(vst40b), F(vst40h), F(vst40w), NULL, }, 463 { F(vst41b), F(vst41h), F(vst41w), NULL, }, 464 { F(vst42b), F(vst42h), F(vst42w), NULL, }, 465 { F(vst43b), F(vst43h), F(vst43w), NULL, }, 466 }; 467 if (a->qd > 4) { 468 return false; 469 } 470 return do_vldst_il(s, a, fns[a->pat][a->size], 64); 471 } 472 473 #undef F 474 475 static bool trans_VDUP(DisasContext *s, arg_VDUP *a) 476 { 477 TCGv_ptr qd; 478 TCGv_i32 rt; 479 480 if (!dc_isar_feature(aa32_mve, s) || 481 !mve_check_qreg_bank(s, a->qd)) { 482 return false; 483 } 484 if (a->rt == 13 || a->rt == 15) { 485 /* UNPREDICTABLE; we choose to UNDEF */ 486 return false; 487 } 488 if (!mve_eci_check(s) || !vfp_access_check(s)) { 489 return true; 490 } 491 492 qd = mve_qreg_ptr(a->qd); 493 rt = load_reg(s, a->rt); 494 tcg_gen_dup_i32(a->size, rt, rt); 495 gen_helper_mve_vdup(cpu_env, qd, rt); 496 tcg_temp_free_ptr(qd); 497 tcg_temp_free_i32(rt); 498 mve_update_eci(s); 499 return true; 500 } 501 502 static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) 503 { 504 TCGv_ptr qd, qm; 505 506 if (!dc_isar_feature(aa32_mve, s) || 507 !mve_check_qreg_bank(s, a->qd | a->qm) || 508 !fn) { 509 return false; 510 } 511 512 if (!mve_eci_check(s) || !vfp_access_check(s)) { 513 return true; 514 } 515 516 qd = mve_qreg_ptr(a->qd); 517 qm = mve_qreg_ptr(a->qm); 518 fn(cpu_env, qd, qm); 519 tcg_temp_free_ptr(qd); 520 tcg_temp_free_ptr(qm); 521 mve_update_eci(s); 522 return true; 523 } 524 525 #define DO_1OP(INSN, FN) \ 526 static bool trans_##INSN(DisasContext *s, arg_1op *a) \ 527 { \ 528 static MVEGenOneOpFn * const fns[] = { \ 529 gen_helper_mve_##FN##b, \ 530 gen_helper_mve_##FN##h, \ 531 gen_helper_mve_##FN##w, \ 532 NULL, \ 533 }; \ 534 return do_1op(s, a, fns[a->size]); \ 535 } 536 537 DO_1OP(VCLZ, vclz) 538 DO_1OP(VCLS, vcls) 539 DO_1OP(VABS, vabs) 540 DO_1OP(VNEG, vneg) 541 DO_1OP(VQABS, vqabs) 542 DO_1OP(VQNEG, vqneg) 543 DO_1OP(VMAXA, vmaxa) 544 DO_1OP(VMINA, vmina) 545 546 /* Narrowing moves: only size 0 and 1 are valid */ 547 #define DO_VMOVN(INSN, FN) \ 548 static bool trans_##INSN(DisasContext *s, arg_1op *a) \ 549 { \ 550 static MVEGenOneOpFn * const fns[] = { \ 551 gen_helper_mve_##FN##b, \ 552 gen_helper_mve_##FN##h, \ 553 NULL, \ 554 NULL, \ 555 }; \ 556 return do_1op(s, a, fns[a->size]); \ 557 } 558 559 DO_VMOVN(VMOVNB, vmovnb) 560 DO_VMOVN(VMOVNT, vmovnt) 561 DO_VMOVN(VQMOVUNB, vqmovunb) 562 DO_VMOVN(VQMOVUNT, vqmovunt) 563 DO_VMOVN(VQMOVN_BS, vqmovnbs) 564 DO_VMOVN(VQMOVN_TS, vqmovnts) 565 DO_VMOVN(VQMOVN_BU, vqmovnbu) 566 DO_VMOVN(VQMOVN_TU, vqmovntu) 567 568 static bool trans_VREV16(DisasContext *s, arg_1op *a) 569 { 570 static MVEGenOneOpFn * const fns[] = { 571 gen_helper_mve_vrev16b, 572 NULL, 573 NULL, 574 NULL, 575 }; 576 return do_1op(s, a, fns[a->size]); 577 } 578 579 static bool trans_VREV32(DisasContext *s, arg_1op *a) 580 { 581 static MVEGenOneOpFn * const fns[] = { 582 gen_helper_mve_vrev32b, 583 gen_helper_mve_vrev32h, 584 NULL, 585 NULL, 586 }; 587 return do_1op(s, a, fns[a->size]); 588 } 589 590 static bool trans_VREV64(DisasContext *s, arg_1op *a) 591 { 592 static MVEGenOneOpFn * const fns[] = { 593 gen_helper_mve_vrev64b, 594 gen_helper_mve_vrev64h, 595 gen_helper_mve_vrev64w, 596 NULL, 597 }; 598 return do_1op(s, a, fns[a->size]); 599 } 600 601 static bool trans_VMVN(DisasContext *s, arg_1op *a) 602 { 603 return do_1op(s, a, gen_helper_mve_vmvn); 604 } 605 606 static bool trans_VABS_fp(DisasContext *s, arg_1op *a) 607 { 608 static MVEGenOneOpFn * const fns[] = { 609 NULL, 610 gen_helper_mve_vfabsh, 611 gen_helper_mve_vfabss, 612 NULL, 613 }; 614 if (!dc_isar_feature(aa32_mve_fp, s)) { 615 return false; 616 } 617 return do_1op(s, a, fns[a->size]); 618 } 619 620 static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) 621 { 622 static MVEGenOneOpFn * const fns[] = { 623 NULL, 624 gen_helper_mve_vfnegh, 625 gen_helper_mve_vfnegs, 626 NULL, 627 }; 628 if (!dc_isar_feature(aa32_mve_fp, s)) { 629 return false; 630 } 631 return do_1op(s, a, fns[a->size]); 632 } 633 634 static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) 635 { 636 TCGv_ptr qd, qn, qm; 637 638 if (!dc_isar_feature(aa32_mve, s) || 639 !mve_check_qreg_bank(s, a->qd | a->qn | a->qm) || 640 !fn) { 641 return false; 642 } 643 if (!mve_eci_check(s) || !vfp_access_check(s)) { 644 return true; 645 } 646 647 qd = mve_qreg_ptr(a->qd); 648 qn = mve_qreg_ptr(a->qn); 649 qm = mve_qreg_ptr(a->qm); 650 fn(cpu_env, qd, qn, qm); 651 tcg_temp_free_ptr(qd); 652 tcg_temp_free_ptr(qn); 653 tcg_temp_free_ptr(qm); 654 mve_update_eci(s); 655 return true; 656 } 657 658 #define DO_LOGIC(INSN, HELPER) \ 659 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 660 { \ 661 return do_2op(s, a, HELPER); \ 662 } 663 664 DO_LOGIC(VAND, gen_helper_mve_vand) 665 DO_LOGIC(VBIC, gen_helper_mve_vbic) 666 DO_LOGIC(VORR, gen_helper_mve_vorr) 667 DO_LOGIC(VORN, gen_helper_mve_vorn) 668 DO_LOGIC(VEOR, gen_helper_mve_veor) 669 670 DO_LOGIC(VPSEL, gen_helper_mve_vpsel) 671 672 #define DO_2OP(INSN, FN) \ 673 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 674 { \ 675 static MVEGenTwoOpFn * const fns[] = { \ 676 gen_helper_mve_##FN##b, \ 677 gen_helper_mve_##FN##h, \ 678 gen_helper_mve_##FN##w, \ 679 NULL, \ 680 }; \ 681 return do_2op(s, a, fns[a->size]); \ 682 } 683 684 DO_2OP(VADD, vadd) 685 DO_2OP(VSUB, vsub) 686 DO_2OP(VMUL, vmul) 687 DO_2OP(VMULH_S, vmulhs) 688 DO_2OP(VMULH_U, vmulhu) 689 DO_2OP(VRMULH_S, vrmulhs) 690 DO_2OP(VRMULH_U, vrmulhu) 691 DO_2OP(VMAX_S, vmaxs) 692 DO_2OP(VMAX_U, vmaxu) 693 DO_2OP(VMIN_S, vmins) 694 DO_2OP(VMIN_U, vminu) 695 DO_2OP(VABD_S, vabds) 696 DO_2OP(VABD_U, vabdu) 697 DO_2OP(VHADD_S, vhadds) 698 DO_2OP(VHADD_U, vhaddu) 699 DO_2OP(VHSUB_S, vhsubs) 700 DO_2OP(VHSUB_U, vhsubu) 701 DO_2OP(VMULL_BS, vmullbs) 702 DO_2OP(VMULL_BU, vmullbu) 703 DO_2OP(VMULL_TS, vmullts) 704 DO_2OP(VMULL_TU, vmulltu) 705 DO_2OP(VQDMULH, vqdmulh) 706 DO_2OP(VQRDMULH, vqrdmulh) 707 DO_2OP(VQADD_S, vqadds) 708 DO_2OP(VQADD_U, vqaddu) 709 DO_2OP(VQSUB_S, vqsubs) 710 DO_2OP(VQSUB_U, vqsubu) 711 DO_2OP(VSHL_S, vshls) 712 DO_2OP(VSHL_U, vshlu) 713 DO_2OP(VRSHL_S, vrshls) 714 DO_2OP(VRSHL_U, vrshlu) 715 DO_2OP(VQSHL_S, vqshls) 716 DO_2OP(VQSHL_U, vqshlu) 717 DO_2OP(VQRSHL_S, vqrshls) 718 DO_2OP(VQRSHL_U, vqrshlu) 719 DO_2OP(VQDMLADH, vqdmladh) 720 DO_2OP(VQDMLADHX, vqdmladhx) 721 DO_2OP(VQRDMLADH, vqrdmladh) 722 DO_2OP(VQRDMLADHX, vqrdmladhx) 723 DO_2OP(VQDMLSDH, vqdmlsdh) 724 DO_2OP(VQDMLSDHX, vqdmlsdhx) 725 DO_2OP(VQRDMLSDH, vqrdmlsdh) 726 DO_2OP(VQRDMLSDHX, vqrdmlsdhx) 727 DO_2OP(VRHADD_S, vrhadds) 728 DO_2OP(VRHADD_U, vrhaddu) 729 /* 730 * VCADD Qd == Qm at size MO_32 is UNPREDICTABLE; we choose not to diagnose 731 * so we can reuse the DO_2OP macro. (Our implementation calculates the 732 * "expected" results in this case.) Similarly for VHCADD. 733 */ 734 DO_2OP(VCADD90, vcadd90) 735 DO_2OP(VCADD270, vcadd270) 736 DO_2OP(VHCADD90, vhcadd90) 737 DO_2OP(VHCADD270, vhcadd270) 738 739 static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) 740 { 741 static MVEGenTwoOpFn * const fns[] = { 742 NULL, 743 gen_helper_mve_vqdmullbh, 744 gen_helper_mve_vqdmullbw, 745 NULL, 746 }; 747 if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) { 748 /* UNPREDICTABLE; we choose to undef */ 749 return false; 750 } 751 return do_2op(s, a, fns[a->size]); 752 } 753 754 static bool trans_VQDMULLT(DisasContext *s, arg_2op *a) 755 { 756 static MVEGenTwoOpFn * const fns[] = { 757 NULL, 758 gen_helper_mve_vqdmullth, 759 gen_helper_mve_vqdmulltw, 760 NULL, 761 }; 762 if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) { 763 /* UNPREDICTABLE; we choose to undef */ 764 return false; 765 } 766 return do_2op(s, a, fns[a->size]); 767 } 768 769 static bool trans_VMULLP_B(DisasContext *s, arg_2op *a) 770 { 771 /* 772 * Note that a->size indicates the output size, ie VMULL.P8 773 * is the 8x8->16 operation and a->size is MO_16; VMULL.P16 774 * is the 16x16->32 operation and a->size is MO_32. 775 */ 776 static MVEGenTwoOpFn * const fns[] = { 777 NULL, 778 gen_helper_mve_vmullpbh, 779 gen_helper_mve_vmullpbw, 780 NULL, 781 }; 782 return do_2op(s, a, fns[a->size]); 783 } 784 785 static bool trans_VMULLP_T(DisasContext *s, arg_2op *a) 786 { 787 /* a->size is as for trans_VMULLP_B */ 788 static MVEGenTwoOpFn * const fns[] = { 789 NULL, 790 gen_helper_mve_vmullpth, 791 gen_helper_mve_vmullptw, 792 NULL, 793 }; 794 return do_2op(s, a, fns[a->size]); 795 } 796 797 /* 798 * VADC and VSBC: these perform an add-with-carry or subtract-with-carry 799 * of the 32-bit elements in each lane of the input vectors, where the 800 * carry-out of each add is the carry-in of the next. The initial carry 801 * input is either fixed (0 for VADCI, 1 for VSBCI) or is from FPSCR.C 802 * (for VADC and VSBC); the carry out at the end is written back to FPSCR.C. 803 * These insns are subject to beat-wise execution. Partial execution 804 * of an I=1 (initial carry input fixed) insn which does not 805 * execute the first beat must start with the current FPSCR.NZCV 806 * value, not the fixed constant input. 807 */ 808 static bool trans_VADC(DisasContext *s, arg_2op *a) 809 { 810 return do_2op(s, a, gen_helper_mve_vadc); 811 } 812 813 static bool trans_VADCI(DisasContext *s, arg_2op *a) 814 { 815 if (mve_skip_first_beat(s)) { 816 return trans_VADC(s, a); 817 } 818 return do_2op(s, a, gen_helper_mve_vadci); 819 } 820 821 static bool trans_VSBC(DisasContext *s, arg_2op *a) 822 { 823 return do_2op(s, a, gen_helper_mve_vsbc); 824 } 825 826 static bool trans_VSBCI(DisasContext *s, arg_2op *a) 827 { 828 if (mve_skip_first_beat(s)) { 829 return trans_VSBC(s, a); 830 } 831 return do_2op(s, a, gen_helper_mve_vsbci); 832 } 833 834 #define DO_2OP_FP(INSN, FN) \ 835 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 836 { \ 837 static MVEGenTwoOpFn * const fns[] = { \ 838 NULL, \ 839 gen_helper_mve_##FN##h, \ 840 gen_helper_mve_##FN##s, \ 841 NULL, \ 842 }; \ 843 if (!dc_isar_feature(aa32_mve_fp, s)) { \ 844 return false; \ 845 } \ 846 return do_2op(s, a, fns[a->size]); \ 847 } 848 849 DO_2OP_FP(VADD_fp, vfadd) 850 DO_2OP_FP(VSUB_fp, vfsub) 851 DO_2OP_FP(VMUL_fp, vfmul) 852 DO_2OP_FP(VABD_fp, vfabd) 853 DO_2OP_FP(VMAXNM, vmaxnm) 854 DO_2OP_FP(VMINNM, vminnm) 855 DO_2OP_FP(VCADD90_fp, vfcadd90) 856 DO_2OP_FP(VCADD270_fp, vfcadd270) 857 DO_2OP_FP(VFMA, vfma) 858 DO_2OP_FP(VFMS, vfms) 859 DO_2OP_FP(VCMUL0, vcmul0) 860 DO_2OP_FP(VCMUL90, vcmul90) 861 DO_2OP_FP(VCMUL180, vcmul180) 862 DO_2OP_FP(VCMUL270, vcmul270) 863 DO_2OP_FP(VCMLA0, vcmla0) 864 DO_2OP_FP(VCMLA90, vcmla90) 865 DO_2OP_FP(VCMLA180, vcmla180) 866 DO_2OP_FP(VCMLA270, vcmla270) 867 DO_2OP_FP(VMAXNMA, vmaxnma) 868 DO_2OP_FP(VMINNMA, vminnma) 869 870 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, 871 MVEGenTwoOpScalarFn fn) 872 { 873 TCGv_ptr qd, qn; 874 TCGv_i32 rm; 875 876 if (!dc_isar_feature(aa32_mve, s) || 877 !mve_check_qreg_bank(s, a->qd | a->qn) || 878 !fn) { 879 return false; 880 } 881 if (a->rm == 13 || a->rm == 15) { 882 /* UNPREDICTABLE */ 883 return false; 884 } 885 if (!mve_eci_check(s) || !vfp_access_check(s)) { 886 return true; 887 } 888 889 qd = mve_qreg_ptr(a->qd); 890 qn = mve_qreg_ptr(a->qn); 891 rm = load_reg(s, a->rm); 892 fn(cpu_env, qd, qn, rm); 893 tcg_temp_free_i32(rm); 894 tcg_temp_free_ptr(qd); 895 tcg_temp_free_ptr(qn); 896 mve_update_eci(s); 897 return true; 898 } 899 900 #define DO_2OP_SCALAR(INSN, FN) \ 901 static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ 902 { \ 903 static MVEGenTwoOpScalarFn * const fns[] = { \ 904 gen_helper_mve_##FN##b, \ 905 gen_helper_mve_##FN##h, \ 906 gen_helper_mve_##FN##w, \ 907 NULL, \ 908 }; \ 909 return do_2op_scalar(s, a, fns[a->size]); \ 910 } 911 912 DO_2OP_SCALAR(VADD_scalar, vadd_scalar) 913 DO_2OP_SCALAR(VSUB_scalar, vsub_scalar) 914 DO_2OP_SCALAR(VMUL_scalar, vmul_scalar) 915 DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) 916 DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) 917 DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) 918 DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) 919 DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar) 920 DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar) 921 DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar) 922 DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) 923 DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) 924 DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) 925 DO_2OP_SCALAR(VBRSR, vbrsr) 926 DO_2OP_SCALAR(VMLA, vmla) 927 DO_2OP_SCALAR(VMLAS, vmlas) 928 DO_2OP_SCALAR(VQDMLAH, vqdmlah) 929 DO_2OP_SCALAR(VQRDMLAH, vqrdmlah) 930 DO_2OP_SCALAR(VQDMLASH, vqdmlash) 931 DO_2OP_SCALAR(VQRDMLASH, vqrdmlash) 932 933 static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a) 934 { 935 static MVEGenTwoOpScalarFn * const fns[] = { 936 NULL, 937 gen_helper_mve_vqdmullb_scalarh, 938 gen_helper_mve_vqdmullb_scalarw, 939 NULL, 940 }; 941 if (a->qd == a->qn && a->size == MO_32) { 942 /* UNPREDICTABLE; we choose to undef */ 943 return false; 944 } 945 return do_2op_scalar(s, a, fns[a->size]); 946 } 947 948 static bool trans_VQDMULLT_scalar(DisasContext *s, arg_2scalar *a) 949 { 950 static MVEGenTwoOpScalarFn * const fns[] = { 951 NULL, 952 gen_helper_mve_vqdmullt_scalarh, 953 gen_helper_mve_vqdmullt_scalarw, 954 NULL, 955 }; 956 if (a->qd == a->qn && a->size == MO_32) { 957 /* UNPREDICTABLE; we choose to undef */ 958 return false; 959 } 960 return do_2op_scalar(s, a, fns[a->size]); 961 } 962 963 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, 964 MVEGenLongDualAccOpFn *fn) 965 { 966 TCGv_ptr qn, qm; 967 TCGv_i64 rda; 968 TCGv_i32 rdalo, rdahi; 969 970 if (!dc_isar_feature(aa32_mve, s) || 971 !mve_check_qreg_bank(s, a->qn | a->qm) || 972 !fn) { 973 return false; 974 } 975 /* 976 * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related 977 * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. 978 */ 979 if (a->rdahi == 13 || a->rdahi == 15) { 980 return false; 981 } 982 if (!mve_eci_check(s) || !vfp_access_check(s)) { 983 return true; 984 } 985 986 qn = mve_qreg_ptr(a->qn); 987 qm = mve_qreg_ptr(a->qm); 988 989 /* 990 * This insn is subject to beat-wise execution. Partial execution 991 * of an A=0 (no-accumulate) insn which does not execute the first 992 * beat must start with the current rda value, not 0. 993 */ 994 if (a->a || mve_skip_first_beat(s)) { 995 rda = tcg_temp_new_i64(); 996 rdalo = load_reg(s, a->rdalo); 997 rdahi = load_reg(s, a->rdahi); 998 tcg_gen_concat_i32_i64(rda, rdalo, rdahi); 999 tcg_temp_free_i32(rdalo); 1000 tcg_temp_free_i32(rdahi); 1001 } else { 1002 rda = tcg_const_i64(0); 1003 } 1004 1005 fn(rda, cpu_env, qn, qm, rda); 1006 tcg_temp_free_ptr(qn); 1007 tcg_temp_free_ptr(qm); 1008 1009 rdalo = tcg_temp_new_i32(); 1010 rdahi = tcg_temp_new_i32(); 1011 tcg_gen_extrl_i64_i32(rdalo, rda); 1012 tcg_gen_extrh_i64_i32(rdahi, rda); 1013 store_reg(s, a->rdalo, rdalo); 1014 store_reg(s, a->rdahi, rdahi); 1015 tcg_temp_free_i64(rda); 1016 mve_update_eci(s); 1017 return true; 1018 } 1019 1020 static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a) 1021 { 1022 static MVEGenLongDualAccOpFn * const fns[4][2] = { 1023 { NULL, NULL }, 1024 { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh }, 1025 { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw }, 1026 { NULL, NULL }, 1027 }; 1028 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1029 } 1030 1031 static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a) 1032 { 1033 static MVEGenLongDualAccOpFn * const fns[4][2] = { 1034 { NULL, NULL }, 1035 { gen_helper_mve_vmlaldavuh, NULL }, 1036 { gen_helper_mve_vmlaldavuw, NULL }, 1037 { NULL, NULL }, 1038 }; 1039 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1040 } 1041 1042 static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) 1043 { 1044 static MVEGenLongDualAccOpFn * const fns[4][2] = { 1045 { NULL, NULL }, 1046 { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh }, 1047 { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw }, 1048 { NULL, NULL }, 1049 }; 1050 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1051 } 1052 1053 static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a) 1054 { 1055 static MVEGenLongDualAccOpFn * const fns[] = { 1056 gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw, 1057 }; 1058 return do_long_dual_acc(s, a, fns[a->x]); 1059 } 1060 1061 static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a) 1062 { 1063 static MVEGenLongDualAccOpFn * const fns[] = { 1064 gen_helper_mve_vrmlaldavhuw, NULL, 1065 }; 1066 return do_long_dual_acc(s, a, fns[a->x]); 1067 } 1068 1069 static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) 1070 { 1071 static MVEGenLongDualAccOpFn * const fns[] = { 1072 gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw, 1073 }; 1074 return do_long_dual_acc(s, a, fns[a->x]); 1075 } 1076 1077 static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn) 1078 { 1079 TCGv_ptr qn, qm; 1080 TCGv_i32 rda; 1081 1082 if (!dc_isar_feature(aa32_mve, s) || 1083 !mve_check_qreg_bank(s, a->qn) || 1084 !fn) { 1085 return false; 1086 } 1087 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1088 return true; 1089 } 1090 1091 qn = mve_qreg_ptr(a->qn); 1092 qm = mve_qreg_ptr(a->qm); 1093 1094 /* 1095 * This insn is subject to beat-wise execution. Partial execution 1096 * of an A=0 (no-accumulate) insn which does not execute the first 1097 * beat must start with the current rda value, not 0. 1098 */ 1099 if (a->a || mve_skip_first_beat(s)) { 1100 rda = load_reg(s, a->rda); 1101 } else { 1102 rda = tcg_const_i32(0); 1103 } 1104 1105 fn(rda, cpu_env, qn, qm, rda); 1106 store_reg(s, a->rda, rda); 1107 tcg_temp_free_ptr(qn); 1108 tcg_temp_free_ptr(qm); 1109 1110 mve_update_eci(s); 1111 return true; 1112 } 1113 1114 #define DO_DUAL_ACC(INSN, FN) \ 1115 static bool trans_##INSN(DisasContext *s, arg_vmladav *a) \ 1116 { \ 1117 static MVEGenDualAccOpFn * const fns[4][2] = { \ 1118 { gen_helper_mve_##FN##b, gen_helper_mve_##FN##xb }, \ 1119 { gen_helper_mve_##FN##h, gen_helper_mve_##FN##xh }, \ 1120 { gen_helper_mve_##FN##w, gen_helper_mve_##FN##xw }, \ 1121 { NULL, NULL }, \ 1122 }; \ 1123 return do_dual_acc(s, a, fns[a->size][a->x]); \ 1124 } 1125 1126 DO_DUAL_ACC(VMLADAV_S, vmladavs) 1127 DO_DUAL_ACC(VMLSDAV, vmlsdav) 1128 1129 static bool trans_VMLADAV_U(DisasContext *s, arg_vmladav *a) 1130 { 1131 static MVEGenDualAccOpFn * const fns[4][2] = { 1132 { gen_helper_mve_vmladavub, NULL }, 1133 { gen_helper_mve_vmladavuh, NULL }, 1134 { gen_helper_mve_vmladavuw, NULL }, 1135 { NULL, NULL }, 1136 }; 1137 return do_dual_acc(s, a, fns[a->size][a->x]); 1138 } 1139 1140 static void gen_vpst(DisasContext *s, uint32_t mask) 1141 { 1142 /* 1143 * Set the VPR mask fields. We take advantage of MASK01 and MASK23 1144 * being adjacent fields in the register. 1145 * 1146 * Updating the masks is not predicated, but it is subject to beat-wise 1147 * execution, and the mask is updated on the odd-numbered beats. 1148 * So if PSR.ECI says we should skip beat 1, we mustn't update the 1149 * 01 mask field. 1150 */ 1151 TCGv_i32 vpr = load_cpu_field(v7m.vpr); 1152 switch (s->eci) { 1153 case ECI_NONE: 1154 case ECI_A0: 1155 /* Update both 01 and 23 fields */ 1156 tcg_gen_deposit_i32(vpr, vpr, 1157 tcg_constant_i32(mask | (mask << 4)), 1158 R_V7M_VPR_MASK01_SHIFT, 1159 R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH); 1160 break; 1161 case ECI_A0A1: 1162 case ECI_A0A1A2: 1163 case ECI_A0A1A2B0: 1164 /* Update only the 23 mask field */ 1165 tcg_gen_deposit_i32(vpr, vpr, 1166 tcg_constant_i32(mask), 1167 R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH); 1168 break; 1169 default: 1170 g_assert_not_reached(); 1171 } 1172 store_cpu_field(vpr, v7m.vpr); 1173 } 1174 1175 static bool trans_VPST(DisasContext *s, arg_VPST *a) 1176 { 1177 /* mask == 0 is a "related encoding" */ 1178 if (!dc_isar_feature(aa32_mve, s) || !a->mask) { 1179 return false; 1180 } 1181 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1182 return true; 1183 } 1184 gen_vpst(s, a->mask); 1185 mve_update_and_store_eci(s); 1186 return true; 1187 } 1188 1189 static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a) 1190 { 1191 /* 1192 * Invert the predicate in VPR.P0. We have call out to 1193 * a helper because this insn itself is beatwise and can 1194 * be predicated. 1195 */ 1196 if (!dc_isar_feature(aa32_mve, s)) { 1197 return false; 1198 } 1199 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1200 return true; 1201 } 1202 1203 gen_helper_mve_vpnot(cpu_env); 1204 mve_update_eci(s); 1205 return true; 1206 } 1207 1208 static bool trans_VADDV(DisasContext *s, arg_VADDV *a) 1209 { 1210 /* VADDV: vector add across vector */ 1211 static MVEGenVADDVFn * const fns[4][2] = { 1212 { gen_helper_mve_vaddvsb, gen_helper_mve_vaddvub }, 1213 { gen_helper_mve_vaddvsh, gen_helper_mve_vaddvuh }, 1214 { gen_helper_mve_vaddvsw, gen_helper_mve_vaddvuw }, 1215 { NULL, NULL } 1216 }; 1217 TCGv_ptr qm; 1218 TCGv_i32 rda; 1219 1220 if (!dc_isar_feature(aa32_mve, s) || 1221 a->size == 3) { 1222 return false; 1223 } 1224 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1225 return true; 1226 } 1227 1228 /* 1229 * This insn is subject to beat-wise execution. Partial execution 1230 * of an A=0 (no-accumulate) insn which does not execute the first 1231 * beat must start with the current value of Rda, not zero. 1232 */ 1233 if (a->a || mve_skip_first_beat(s)) { 1234 /* Accumulate input from Rda */ 1235 rda = load_reg(s, a->rda); 1236 } else { 1237 /* Accumulate starting at zero */ 1238 rda = tcg_const_i32(0); 1239 } 1240 1241 qm = mve_qreg_ptr(a->qm); 1242 fns[a->size][a->u](rda, cpu_env, qm, rda); 1243 store_reg(s, a->rda, rda); 1244 tcg_temp_free_ptr(qm); 1245 1246 mve_update_eci(s); 1247 return true; 1248 } 1249 1250 static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) 1251 { 1252 /* 1253 * Vector Add Long Across Vector: accumulate the 32-bit 1254 * elements of the vector into a 64-bit result stored in 1255 * a pair of general-purpose registers. 1256 * No need to check Qm's bank: it is only 3 bits in decode. 1257 */ 1258 TCGv_ptr qm; 1259 TCGv_i64 rda; 1260 TCGv_i32 rdalo, rdahi; 1261 1262 if (!dc_isar_feature(aa32_mve, s)) { 1263 return false; 1264 } 1265 /* 1266 * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related 1267 * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. 1268 */ 1269 if (a->rdahi == 13 || a->rdahi == 15) { 1270 return false; 1271 } 1272 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1273 return true; 1274 } 1275 1276 /* 1277 * This insn is subject to beat-wise execution. Partial execution 1278 * of an A=0 (no-accumulate) insn which does not execute the first 1279 * beat must start with the current value of RdaHi:RdaLo, not zero. 1280 */ 1281 if (a->a || mve_skip_first_beat(s)) { 1282 /* Accumulate input from RdaHi:RdaLo */ 1283 rda = tcg_temp_new_i64(); 1284 rdalo = load_reg(s, a->rdalo); 1285 rdahi = load_reg(s, a->rdahi); 1286 tcg_gen_concat_i32_i64(rda, rdalo, rdahi); 1287 tcg_temp_free_i32(rdalo); 1288 tcg_temp_free_i32(rdahi); 1289 } else { 1290 /* Accumulate starting at zero */ 1291 rda = tcg_const_i64(0); 1292 } 1293 1294 qm = mve_qreg_ptr(a->qm); 1295 if (a->u) { 1296 gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda); 1297 } else { 1298 gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); 1299 } 1300 tcg_temp_free_ptr(qm); 1301 1302 rdalo = tcg_temp_new_i32(); 1303 rdahi = tcg_temp_new_i32(); 1304 tcg_gen_extrl_i64_i32(rdalo, rda); 1305 tcg_gen_extrh_i64_i32(rdahi, rda); 1306 store_reg(s, a->rdalo, rdalo); 1307 store_reg(s, a->rdahi, rdahi); 1308 tcg_temp_free_i64(rda); 1309 mve_update_eci(s); 1310 return true; 1311 } 1312 1313 static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) 1314 { 1315 TCGv_ptr qd; 1316 uint64_t imm; 1317 1318 if (!dc_isar_feature(aa32_mve, s) || 1319 !mve_check_qreg_bank(s, a->qd) || 1320 !fn) { 1321 return false; 1322 } 1323 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1324 return true; 1325 } 1326 1327 imm = asimd_imm_const(a->imm, a->cmode, a->op); 1328 1329 qd = mve_qreg_ptr(a->qd); 1330 fn(cpu_env, qd, tcg_constant_i64(imm)); 1331 tcg_temp_free_ptr(qd); 1332 mve_update_eci(s); 1333 return true; 1334 } 1335 1336 static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) 1337 { 1338 /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ 1339 MVEGenOneOpImmFn *fn; 1340 1341 if ((a->cmode & 1) && a->cmode < 12) { 1342 if (a->op) { 1343 /* 1344 * For op=1, the immediate will be inverted by asimd_imm_const(), 1345 * so the VBIC becomes a logical AND operation. 1346 */ 1347 fn = gen_helper_mve_vandi; 1348 } else { 1349 fn = gen_helper_mve_vorri; 1350 } 1351 } else { 1352 /* There is one unallocated cmode/op combination in this space */ 1353 if (a->cmode == 15 && a->op == 1) { 1354 return false; 1355 } 1356 /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ 1357 fn = gen_helper_mve_vmovi; 1358 } 1359 return do_1imm(s, a, fn); 1360 } 1361 1362 static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, 1363 bool negateshift) 1364 { 1365 TCGv_ptr qd, qm; 1366 int shift = a->shift; 1367 1368 if (!dc_isar_feature(aa32_mve, s) || 1369 !mve_check_qreg_bank(s, a->qd | a->qm) || 1370 !fn) { 1371 return false; 1372 } 1373 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1374 return true; 1375 } 1376 1377 /* 1378 * When we handle a right shift insn using a left-shift helper 1379 * which permits a negative shift count to indicate a right-shift, 1380 * we must negate the shift count. 1381 */ 1382 if (negateshift) { 1383 shift = -shift; 1384 } 1385 1386 qd = mve_qreg_ptr(a->qd); 1387 qm = mve_qreg_ptr(a->qm); 1388 fn(cpu_env, qd, qm, tcg_constant_i32(shift)); 1389 tcg_temp_free_ptr(qd); 1390 tcg_temp_free_ptr(qm); 1391 mve_update_eci(s); 1392 return true; 1393 } 1394 1395 #define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ 1396 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1397 { \ 1398 static MVEGenTwoOpShiftFn * const fns[] = { \ 1399 gen_helper_mve_##FN##b, \ 1400 gen_helper_mve_##FN##h, \ 1401 gen_helper_mve_##FN##w, \ 1402 NULL, \ 1403 }; \ 1404 return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ 1405 } 1406 1407 DO_2SHIFT(VSHLI, vshli_u, false) 1408 DO_2SHIFT(VQSHLI_S, vqshli_s, false) 1409 DO_2SHIFT(VQSHLI_U, vqshli_u, false) 1410 DO_2SHIFT(VQSHLUI, vqshlui_s, false) 1411 /* These right shifts use a left-shift helper with negated shift count */ 1412 DO_2SHIFT(VSHRI_S, vshli_s, true) 1413 DO_2SHIFT(VSHRI_U, vshli_u, true) 1414 DO_2SHIFT(VRSHRI_S, vrshli_s, true) 1415 DO_2SHIFT(VRSHRI_U, vrshli_u, true) 1416 1417 DO_2SHIFT(VSRI, vsri, false) 1418 DO_2SHIFT(VSLI, vsli, false) 1419 1420 static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a, 1421 MVEGenTwoOpShiftFn *fn) 1422 { 1423 TCGv_ptr qda; 1424 TCGv_i32 rm; 1425 1426 if (!dc_isar_feature(aa32_mve, s) || 1427 !mve_check_qreg_bank(s, a->qda) || 1428 a->rm == 13 || a->rm == 15 || !fn) { 1429 /* Rm cases are UNPREDICTABLE */ 1430 return false; 1431 } 1432 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1433 return true; 1434 } 1435 1436 qda = mve_qreg_ptr(a->qda); 1437 rm = load_reg(s, a->rm); 1438 fn(cpu_env, qda, qda, rm); 1439 tcg_temp_free_ptr(qda); 1440 tcg_temp_free_i32(rm); 1441 mve_update_eci(s); 1442 return true; 1443 } 1444 1445 #define DO_2SHIFT_SCALAR(INSN, FN) \ 1446 static bool trans_##INSN(DisasContext *s, arg_shl_scalar *a) \ 1447 { \ 1448 static MVEGenTwoOpShiftFn * const fns[] = { \ 1449 gen_helper_mve_##FN##b, \ 1450 gen_helper_mve_##FN##h, \ 1451 gen_helper_mve_##FN##w, \ 1452 NULL, \ 1453 }; \ 1454 return do_2shift_scalar(s, a, fns[a->size]); \ 1455 } 1456 1457 DO_2SHIFT_SCALAR(VSHL_S_scalar, vshli_s) 1458 DO_2SHIFT_SCALAR(VSHL_U_scalar, vshli_u) 1459 DO_2SHIFT_SCALAR(VRSHL_S_scalar, vrshli_s) 1460 DO_2SHIFT_SCALAR(VRSHL_U_scalar, vrshli_u) 1461 DO_2SHIFT_SCALAR(VQSHL_S_scalar, vqshli_s) 1462 DO_2SHIFT_SCALAR(VQSHL_U_scalar, vqshli_u) 1463 DO_2SHIFT_SCALAR(VQRSHL_S_scalar, vqrshli_s) 1464 DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u) 1465 1466 #define DO_VSHLL(INSN, FN) \ 1467 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1468 { \ 1469 static MVEGenTwoOpShiftFn * const fns[] = { \ 1470 gen_helper_mve_##FN##b, \ 1471 gen_helper_mve_##FN##h, \ 1472 }; \ 1473 return do_2shift(s, a, fns[a->size], false); \ 1474 } 1475 1476 DO_VSHLL(VSHLL_BS, vshllbs) 1477 DO_VSHLL(VSHLL_BU, vshllbu) 1478 DO_VSHLL(VSHLL_TS, vshllts) 1479 DO_VSHLL(VSHLL_TU, vshlltu) 1480 1481 #define DO_2SHIFT_N(INSN, FN) \ 1482 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1483 { \ 1484 static MVEGenTwoOpShiftFn * const fns[] = { \ 1485 gen_helper_mve_##FN##b, \ 1486 gen_helper_mve_##FN##h, \ 1487 }; \ 1488 return do_2shift(s, a, fns[a->size], false); \ 1489 } 1490 1491 DO_2SHIFT_N(VSHRNB, vshrnb) 1492 DO_2SHIFT_N(VSHRNT, vshrnt) 1493 DO_2SHIFT_N(VRSHRNB, vrshrnb) 1494 DO_2SHIFT_N(VRSHRNT, vrshrnt) 1495 DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s) 1496 DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s) 1497 DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u) 1498 DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u) 1499 DO_2SHIFT_N(VQSHRUNB, vqshrunb) 1500 DO_2SHIFT_N(VQSHRUNT, vqshrunt) 1501 DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s) 1502 DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s) 1503 DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) 1504 DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) 1505 DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) 1506 DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) 1507 1508 static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) 1509 { 1510 /* 1511 * Whole Vector Left Shift with Carry. The carry is taken 1512 * from a general purpose register and written back there. 1513 * An imm of 0 means "shift by 32". 1514 */ 1515 TCGv_ptr qd; 1516 TCGv_i32 rdm; 1517 1518 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1519 return false; 1520 } 1521 if (a->rdm == 13 || a->rdm == 15) { 1522 /* CONSTRAINED UNPREDICTABLE: we UNDEF */ 1523 return false; 1524 } 1525 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1526 return true; 1527 } 1528 1529 qd = mve_qreg_ptr(a->qd); 1530 rdm = load_reg(s, a->rdm); 1531 gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); 1532 store_reg(s, a->rdm, rdm); 1533 tcg_temp_free_ptr(qd); 1534 mve_update_eci(s); 1535 return true; 1536 } 1537 1538 static bool do_vidup(DisasContext *s, arg_vidup *a, MVEGenVIDUPFn *fn) 1539 { 1540 TCGv_ptr qd; 1541 TCGv_i32 rn; 1542 1543 /* 1544 * Vector increment/decrement with wrap and duplicate (VIDUP, VDDUP). 1545 * This fills the vector with elements of successively increasing 1546 * or decreasing values, starting from Rn. 1547 */ 1548 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1549 return false; 1550 } 1551 if (a->size == MO_64) { 1552 /* size 0b11 is another encoding */ 1553 return false; 1554 } 1555 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1556 return true; 1557 } 1558 1559 qd = mve_qreg_ptr(a->qd); 1560 rn = load_reg(s, a->rn); 1561 fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm)); 1562 store_reg(s, a->rn, rn); 1563 tcg_temp_free_ptr(qd); 1564 mve_update_eci(s); 1565 return true; 1566 } 1567 1568 static bool do_viwdup(DisasContext *s, arg_viwdup *a, MVEGenVIWDUPFn *fn) 1569 { 1570 TCGv_ptr qd; 1571 TCGv_i32 rn, rm; 1572 1573 /* 1574 * Vector increment/decrement with wrap and duplicate (VIWDUp, VDWDUP) 1575 * This fills the vector with elements of successively increasing 1576 * or decreasing values, starting from Rn. Rm specifies a point where 1577 * the count wraps back around to 0. The updated offset is written back 1578 * to Rn. 1579 */ 1580 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1581 return false; 1582 } 1583 if (!fn || a->rm == 13 || a->rm == 15) { 1584 /* 1585 * size 0b11 is another encoding; Rm == 13 is UNPREDICTABLE; 1586 * Rm == 13 is VIWDUP, VDWDUP. 1587 */ 1588 return false; 1589 } 1590 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1591 return true; 1592 } 1593 1594 qd = mve_qreg_ptr(a->qd); 1595 rn = load_reg(s, a->rn); 1596 rm = load_reg(s, a->rm); 1597 fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm)); 1598 store_reg(s, a->rn, rn); 1599 tcg_temp_free_ptr(qd); 1600 tcg_temp_free_i32(rm); 1601 mve_update_eci(s); 1602 return true; 1603 } 1604 1605 static bool trans_VIDUP(DisasContext *s, arg_vidup *a) 1606 { 1607 static MVEGenVIDUPFn * const fns[] = { 1608 gen_helper_mve_vidupb, 1609 gen_helper_mve_viduph, 1610 gen_helper_mve_vidupw, 1611 NULL, 1612 }; 1613 return do_vidup(s, a, fns[a->size]); 1614 } 1615 1616 static bool trans_VDDUP(DisasContext *s, arg_vidup *a) 1617 { 1618 static MVEGenVIDUPFn * const fns[] = { 1619 gen_helper_mve_vidupb, 1620 gen_helper_mve_viduph, 1621 gen_helper_mve_vidupw, 1622 NULL, 1623 }; 1624 /* VDDUP is just like VIDUP but with a negative immediate */ 1625 a->imm = -a->imm; 1626 return do_vidup(s, a, fns[a->size]); 1627 } 1628 1629 static bool trans_VIWDUP(DisasContext *s, arg_viwdup *a) 1630 { 1631 static MVEGenVIWDUPFn * const fns[] = { 1632 gen_helper_mve_viwdupb, 1633 gen_helper_mve_viwduph, 1634 gen_helper_mve_viwdupw, 1635 NULL, 1636 }; 1637 return do_viwdup(s, a, fns[a->size]); 1638 } 1639 1640 static bool trans_VDWDUP(DisasContext *s, arg_viwdup *a) 1641 { 1642 static MVEGenVIWDUPFn * const fns[] = { 1643 gen_helper_mve_vdwdupb, 1644 gen_helper_mve_vdwduph, 1645 gen_helper_mve_vdwdupw, 1646 NULL, 1647 }; 1648 return do_viwdup(s, a, fns[a->size]); 1649 } 1650 1651 static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn) 1652 { 1653 TCGv_ptr qn, qm; 1654 1655 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) || 1656 !fn) { 1657 return false; 1658 } 1659 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1660 return true; 1661 } 1662 1663 qn = mve_qreg_ptr(a->qn); 1664 qm = mve_qreg_ptr(a->qm); 1665 fn(cpu_env, qn, qm); 1666 tcg_temp_free_ptr(qn); 1667 tcg_temp_free_ptr(qm); 1668 if (a->mask) { 1669 /* VPT */ 1670 gen_vpst(s, a->mask); 1671 } 1672 mve_update_eci(s); 1673 return true; 1674 } 1675 1676 static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a, 1677 MVEGenScalarCmpFn *fn) 1678 { 1679 TCGv_ptr qn; 1680 TCGv_i32 rm; 1681 1682 if (!dc_isar_feature(aa32_mve, s) || !fn || a->rm == 13) { 1683 return false; 1684 } 1685 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1686 return true; 1687 } 1688 1689 qn = mve_qreg_ptr(a->qn); 1690 if (a->rm == 15) { 1691 /* Encoding Rm=0b1111 means "constant zero" */ 1692 rm = tcg_constant_i32(0); 1693 } else { 1694 rm = load_reg(s, a->rm); 1695 } 1696 fn(cpu_env, qn, rm); 1697 tcg_temp_free_ptr(qn); 1698 tcg_temp_free_i32(rm); 1699 if (a->mask) { 1700 /* VPT */ 1701 gen_vpst(s, a->mask); 1702 } 1703 mve_update_eci(s); 1704 return true; 1705 } 1706 1707 #define DO_VCMP(INSN, FN) \ 1708 static bool trans_##INSN(DisasContext *s, arg_vcmp *a) \ 1709 { \ 1710 static MVEGenCmpFn * const fns[] = { \ 1711 gen_helper_mve_##FN##b, \ 1712 gen_helper_mve_##FN##h, \ 1713 gen_helper_mve_##FN##w, \ 1714 NULL, \ 1715 }; \ 1716 return do_vcmp(s, a, fns[a->size]); \ 1717 } \ 1718 static bool trans_##INSN##_scalar(DisasContext *s, \ 1719 arg_vcmp_scalar *a) \ 1720 { \ 1721 static MVEGenScalarCmpFn * const fns[] = { \ 1722 gen_helper_mve_##FN##_scalarb, \ 1723 gen_helper_mve_##FN##_scalarh, \ 1724 gen_helper_mve_##FN##_scalarw, \ 1725 NULL, \ 1726 }; \ 1727 return do_vcmp_scalar(s, a, fns[a->size]); \ 1728 } 1729 1730 DO_VCMP(VCMPEQ, vcmpeq) 1731 DO_VCMP(VCMPNE, vcmpne) 1732 DO_VCMP(VCMPCS, vcmpcs) 1733 DO_VCMP(VCMPHI, vcmphi) 1734 DO_VCMP(VCMPGE, vcmpge) 1735 DO_VCMP(VCMPLT, vcmplt) 1736 DO_VCMP(VCMPGT, vcmpgt) 1737 DO_VCMP(VCMPLE, vcmple) 1738 1739 static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn) 1740 { 1741 /* 1742 * MIN/MAX operations across a vector: compute the min or 1743 * max of the initial value in a general purpose register 1744 * and all the elements in the vector, and store it back 1745 * into the general purpose register. 1746 */ 1747 TCGv_ptr qm; 1748 TCGv_i32 rda; 1749 1750 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) || 1751 !fn || a->rda == 13 || a->rda == 15) { 1752 /* Rda cases are UNPREDICTABLE */ 1753 return false; 1754 } 1755 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1756 return true; 1757 } 1758 1759 qm = mve_qreg_ptr(a->qm); 1760 rda = load_reg(s, a->rda); 1761 fn(rda, cpu_env, qm, rda); 1762 store_reg(s, a->rda, rda); 1763 tcg_temp_free_ptr(qm); 1764 mve_update_eci(s); 1765 return true; 1766 } 1767 1768 #define DO_VMAXV(INSN, FN) \ 1769 static bool trans_##INSN(DisasContext *s, arg_vmaxv *a) \ 1770 { \ 1771 static MVEGenVADDVFn * const fns[] = { \ 1772 gen_helper_mve_##FN##b, \ 1773 gen_helper_mve_##FN##h, \ 1774 gen_helper_mve_##FN##w, \ 1775 NULL, \ 1776 }; \ 1777 return do_vmaxv(s, a, fns[a->size]); \ 1778 } 1779 1780 DO_VMAXV(VMAXV_S, vmaxvs) 1781 DO_VMAXV(VMAXV_U, vmaxvu) 1782 DO_VMAXV(VMAXAV, vmaxav) 1783 DO_VMAXV(VMINV_S, vminvs) 1784 DO_VMAXV(VMINV_U, vminvu) 1785 DO_VMAXV(VMINAV, vminav) 1786 1787 static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn) 1788 { 1789 /* Absolute difference accumulated across vector */ 1790 TCGv_ptr qn, qm; 1791 TCGv_i32 rda; 1792 1793 if (!dc_isar_feature(aa32_mve, s) || 1794 !mve_check_qreg_bank(s, a->qm | a->qn) || 1795 !fn || a->rda == 13 || a->rda == 15) { 1796 /* Rda cases are UNPREDICTABLE */ 1797 return false; 1798 } 1799 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1800 return true; 1801 } 1802 1803 qm = mve_qreg_ptr(a->qm); 1804 qn = mve_qreg_ptr(a->qn); 1805 rda = load_reg(s, a->rda); 1806 fn(rda, cpu_env, qn, qm, rda); 1807 store_reg(s, a->rda, rda); 1808 tcg_temp_free_ptr(qm); 1809 tcg_temp_free_ptr(qn); 1810 mve_update_eci(s); 1811 return true; 1812 } 1813 1814 #define DO_VABAV(INSN, FN) \ 1815 static bool trans_##INSN(DisasContext *s, arg_vabav *a) \ 1816 { \ 1817 static MVEGenVABAVFn * const fns[] = { \ 1818 gen_helper_mve_##FN##b, \ 1819 gen_helper_mve_##FN##h, \ 1820 gen_helper_mve_##FN##w, \ 1821 NULL, \ 1822 }; \ 1823 return do_vabav(s, a, fns[a->size]); \ 1824 } 1825 1826 DO_VABAV(VABAV_S, vabavs) 1827 DO_VABAV(VABAV_U, vabavu) 1828 1829 static bool trans_VMOV_to_2gp(DisasContext *s, arg_VMOV_to_2gp *a) 1830 { 1831 /* 1832 * VMOV two 32-bit vector lanes to two general-purpose registers. 1833 * This insn is not predicated but it is subject to beat-wise 1834 * execution if it is not in an IT block. For us this means 1835 * only that if PSR.ECI says we should not be executing the beat 1836 * corresponding to the lane of the vector register being accessed 1837 * then we should skip perfoming the move, and that we need to do 1838 * the usual check for bad ECI state and advance of ECI state. 1839 * (If PSR.ECI is non-zero then we cannot be in an IT block.) 1840 */ 1841 TCGv_i32 tmp; 1842 int vd; 1843 1844 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) || 1845 a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15 || 1846 a->rt == a->rt2) { 1847 /* Rt/Rt2 cases are UNPREDICTABLE */ 1848 return false; 1849 } 1850 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1851 return true; 1852 } 1853 1854 /* Convert Qreg index to Dreg for read_neon_element32() etc */ 1855 vd = a->qd * 2; 1856 1857 if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { 1858 tmp = tcg_temp_new_i32(); 1859 read_neon_element32(tmp, vd, a->idx, MO_32); 1860 store_reg(s, a->rt, tmp); 1861 } 1862 if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { 1863 tmp = tcg_temp_new_i32(); 1864 read_neon_element32(tmp, vd + 1, a->idx, MO_32); 1865 store_reg(s, a->rt2, tmp); 1866 } 1867 1868 mve_update_and_store_eci(s); 1869 return true; 1870 } 1871 1872 static bool trans_VMOV_from_2gp(DisasContext *s, arg_VMOV_to_2gp *a) 1873 { 1874 /* 1875 * VMOV two general-purpose registers to two 32-bit vector lanes. 1876 * This insn is not predicated but it is subject to beat-wise 1877 * execution if it is not in an IT block. For us this means 1878 * only that if PSR.ECI says we should not be executing the beat 1879 * corresponding to the lane of the vector register being accessed 1880 * then we should skip perfoming the move, and that we need to do 1881 * the usual check for bad ECI state and advance of ECI state. 1882 * (If PSR.ECI is non-zero then we cannot be in an IT block.) 1883 */ 1884 TCGv_i32 tmp; 1885 int vd; 1886 1887 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) || 1888 a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15) { 1889 /* Rt/Rt2 cases are UNPREDICTABLE */ 1890 return false; 1891 } 1892 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1893 return true; 1894 } 1895 1896 /* Convert Qreg idx to Dreg for read_neon_element32() etc */ 1897 vd = a->qd * 2; 1898 1899 if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { 1900 tmp = load_reg(s, a->rt); 1901 write_neon_element32(tmp, vd, a->idx, MO_32); 1902 tcg_temp_free_i32(tmp); 1903 } 1904 if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { 1905 tmp = load_reg(s, a->rt2); 1906 write_neon_element32(tmp, vd + 1, a->idx, MO_32); 1907 tcg_temp_free_i32(tmp); 1908 } 1909 1910 mve_update_and_store_eci(s); 1911 return true; 1912 } 1913