1 /* 2 * ARM translation: M-profile MVE instructions 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "tcg/tcg-op.h" 22 #include "tcg/tcg-op-gvec.h" 23 #include "exec/exec-all.h" 24 #include "exec/gen-icount.h" 25 #include "translate.h" 26 #include "translate-a32.h" 27 28 static inline int vidup_imm(DisasContext *s, int x) 29 { 30 return 1 << x; 31 } 32 33 /* Include the generated decoder */ 34 #include "decode-mve.c.inc" 35 36 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 37 typedef void MVEGenLdStSGFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 38 typedef void MVEGenLdStIlFn(TCGv_ptr, TCGv_i32, TCGv_i32); 39 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 40 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); 41 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 42 typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 43 typedef void MVEGenLongDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); 44 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); 45 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); 46 typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32); 47 typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); 48 typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 49 typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 50 typedef void MVEGenVABAVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 51 typedef void MVEGenDualAccOpFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 52 53 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ 54 static inline long mve_qreg_offset(unsigned reg) 55 { 56 return offsetof(CPUARMState, vfp.zregs[reg].d[0]); 57 } 58 59 static TCGv_ptr mve_qreg_ptr(unsigned reg) 60 { 61 TCGv_ptr ret = tcg_temp_new_ptr(); 62 tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg)); 63 return ret; 64 } 65 66 static bool mve_check_qreg_bank(DisasContext *s, int qmask) 67 { 68 /* 69 * Check whether Qregs are in range. For v8.1M only Q0..Q7 70 * are supported, see VFPSmallRegisterBank(). 71 */ 72 return qmask < 8; 73 } 74 75 bool mve_eci_check(DisasContext *s) 76 { 77 /* 78 * This is a beatwise insn: check that ECI is valid (not a 79 * reserved value) and note that we are handling it. 80 * Return true if OK, false if we generated an exception. 81 */ 82 s->eci_handled = true; 83 switch (s->eci) { 84 case ECI_NONE: 85 case ECI_A0: 86 case ECI_A0A1: 87 case ECI_A0A1A2: 88 case ECI_A0A1A2B0: 89 return true; 90 default: 91 /* Reserved value: INVSTATE UsageFault */ 92 gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), 93 default_exception_el(s)); 94 return false; 95 } 96 } 97 98 void mve_update_eci(DisasContext *s) 99 { 100 /* 101 * The helper function will always update the CPUState field, 102 * so we only need to update the DisasContext field. 103 */ 104 if (s->eci) { 105 s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE; 106 } 107 } 108 109 void mve_update_and_store_eci(DisasContext *s) 110 { 111 /* 112 * For insns which don't call a helper function that will call 113 * mve_advance_vpt(), this version updates s->eci and also stores 114 * it out to the CPUState field. 115 */ 116 if (s->eci) { 117 mve_update_eci(s); 118 store_cpu_field(tcg_constant_i32(s->eci << 4), condexec_bits); 119 } 120 } 121 122 static bool mve_skip_first_beat(DisasContext *s) 123 { 124 /* Return true if PSR.ECI says we must skip the first beat of this insn */ 125 switch (s->eci) { 126 case ECI_NONE: 127 return false; 128 case ECI_A0: 129 case ECI_A0A1: 130 case ECI_A0A1A2: 131 case ECI_A0A1A2B0: 132 return true; 133 default: 134 g_assert_not_reached(); 135 } 136 } 137 138 static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, 139 unsigned msize) 140 { 141 TCGv_i32 addr; 142 uint32_t offset; 143 TCGv_ptr qreg; 144 145 if (!dc_isar_feature(aa32_mve, s) || 146 !mve_check_qreg_bank(s, a->qd) || 147 !fn) { 148 return false; 149 } 150 151 /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ 152 if (a->rn == 15 || (a->rn == 13 && a->w)) { 153 return false; 154 } 155 156 if (!mve_eci_check(s) || !vfp_access_check(s)) { 157 return true; 158 } 159 160 offset = a->imm << msize; 161 if (!a->a) { 162 offset = -offset; 163 } 164 addr = load_reg(s, a->rn); 165 if (a->p) { 166 tcg_gen_addi_i32(addr, addr, offset); 167 } 168 169 qreg = mve_qreg_ptr(a->qd); 170 fn(cpu_env, qreg, addr); 171 tcg_temp_free_ptr(qreg); 172 173 /* 174 * Writeback always happens after the last beat of the insn, 175 * regardless of predication 176 */ 177 if (a->w) { 178 if (!a->p) { 179 tcg_gen_addi_i32(addr, addr, offset); 180 } 181 store_reg(s, a->rn, addr); 182 } else { 183 tcg_temp_free_i32(addr); 184 } 185 mve_update_eci(s); 186 return true; 187 } 188 189 static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) 190 { 191 static MVEGenLdStFn * const ldstfns[4][2] = { 192 { gen_helper_mve_vstrb, gen_helper_mve_vldrb }, 193 { gen_helper_mve_vstrh, gen_helper_mve_vldrh }, 194 { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, 195 { NULL, NULL } 196 }; 197 return do_ldst(s, a, ldstfns[a->size][a->l], a->size); 198 } 199 200 #define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \ 201 static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ 202 { \ 203 static MVEGenLdStFn * const ldstfns[2][2] = { \ 204 { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ 205 { NULL, gen_helper_mve_##ULD }, \ 206 }; \ 207 return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \ 208 } 209 210 DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8) 211 DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8) 212 DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16) 213 214 static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a, MVEGenLdStSGFn fn) 215 { 216 TCGv_i32 addr; 217 TCGv_ptr qd, qm; 218 219 if (!dc_isar_feature(aa32_mve, s) || 220 !mve_check_qreg_bank(s, a->qd | a->qm) || 221 !fn || a->rn == 15) { 222 /* Rn case is UNPREDICTABLE */ 223 return false; 224 } 225 226 if (!mve_eci_check(s) || !vfp_access_check(s)) { 227 return true; 228 } 229 230 addr = load_reg(s, a->rn); 231 232 qd = mve_qreg_ptr(a->qd); 233 qm = mve_qreg_ptr(a->qm); 234 fn(cpu_env, qd, qm, addr); 235 tcg_temp_free_ptr(qd); 236 tcg_temp_free_ptr(qm); 237 tcg_temp_free_i32(addr); 238 mve_update_eci(s); 239 return true; 240 } 241 242 /* 243 * The naming scheme here is "vldrb_sg_sh == in-memory byte loads 244 * signextended to halfword elements in register". _os_ indicates that 245 * the offsets in Qm should be scaled by the element size. 246 */ 247 /* This macro is just to make the arrays more compact in these functions */ 248 #define F(N) gen_helper_mve_##N 249 250 /* VLDRB/VSTRB (ie msize 1) with OS=1 is UNPREDICTABLE; we UNDEF */ 251 static bool trans_VLDR_S_sg(DisasContext *s, arg_vldst_sg *a) 252 { 253 static MVEGenLdStSGFn * const fns[2][4][4] = { { 254 { NULL, F(vldrb_sg_sh), F(vldrb_sg_sw), NULL }, 255 { NULL, NULL, F(vldrh_sg_sw), NULL }, 256 { NULL, NULL, NULL, NULL }, 257 { NULL, NULL, NULL, NULL } 258 }, { 259 { NULL, NULL, NULL, NULL }, 260 { NULL, NULL, F(vldrh_sg_os_sw), NULL }, 261 { NULL, NULL, NULL, NULL }, 262 { NULL, NULL, NULL, NULL } 263 } 264 }; 265 if (a->qd == a->qm) { 266 return false; /* UNPREDICTABLE */ 267 } 268 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 269 } 270 271 static bool trans_VLDR_U_sg(DisasContext *s, arg_vldst_sg *a) 272 { 273 static MVEGenLdStSGFn * const fns[2][4][4] = { { 274 { F(vldrb_sg_ub), F(vldrb_sg_uh), F(vldrb_sg_uw), NULL }, 275 { NULL, F(vldrh_sg_uh), F(vldrh_sg_uw), NULL }, 276 { NULL, NULL, F(vldrw_sg_uw), NULL }, 277 { NULL, NULL, NULL, F(vldrd_sg_ud) } 278 }, { 279 { NULL, NULL, NULL, NULL }, 280 { NULL, F(vldrh_sg_os_uh), F(vldrh_sg_os_uw), NULL }, 281 { NULL, NULL, F(vldrw_sg_os_uw), NULL }, 282 { NULL, NULL, NULL, F(vldrd_sg_os_ud) } 283 } 284 }; 285 if (a->qd == a->qm) { 286 return false; /* UNPREDICTABLE */ 287 } 288 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 289 } 290 291 static bool trans_VSTR_sg(DisasContext *s, arg_vldst_sg *a) 292 { 293 static MVEGenLdStSGFn * const fns[2][4][4] = { { 294 { F(vstrb_sg_ub), F(vstrb_sg_uh), F(vstrb_sg_uw), NULL }, 295 { NULL, F(vstrh_sg_uh), F(vstrh_sg_uw), NULL }, 296 { NULL, NULL, F(vstrw_sg_uw), NULL }, 297 { NULL, NULL, NULL, F(vstrd_sg_ud) } 298 }, { 299 { NULL, NULL, NULL, NULL }, 300 { NULL, F(vstrh_sg_os_uh), F(vstrh_sg_os_uw), NULL }, 301 { NULL, NULL, F(vstrw_sg_os_uw), NULL }, 302 { NULL, NULL, NULL, F(vstrd_sg_os_ud) } 303 } 304 }; 305 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 306 } 307 308 #undef F 309 310 static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_sg_imm *a, 311 MVEGenLdStSGFn *fn, unsigned msize) 312 { 313 uint32_t offset; 314 TCGv_ptr qd, qm; 315 316 if (!dc_isar_feature(aa32_mve, s) || 317 !mve_check_qreg_bank(s, a->qd | a->qm) || 318 !fn) { 319 return false; 320 } 321 322 if (!mve_eci_check(s) || !vfp_access_check(s)) { 323 return true; 324 } 325 326 offset = a->imm << msize; 327 if (!a->a) { 328 offset = -offset; 329 } 330 331 qd = mve_qreg_ptr(a->qd); 332 qm = mve_qreg_ptr(a->qm); 333 fn(cpu_env, qd, qm, tcg_constant_i32(offset)); 334 tcg_temp_free_ptr(qd); 335 tcg_temp_free_ptr(qm); 336 mve_update_eci(s); 337 return true; 338 } 339 340 static bool trans_VLDRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 341 { 342 static MVEGenLdStSGFn * const fns[] = { 343 gen_helper_mve_vldrw_sg_uw, 344 gen_helper_mve_vldrw_sg_wb_uw, 345 }; 346 if (a->qd == a->qm) { 347 return false; /* UNPREDICTABLE */ 348 } 349 return do_ldst_sg_imm(s, a, fns[a->w], MO_32); 350 } 351 352 static bool trans_VLDRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 353 { 354 static MVEGenLdStSGFn * const fns[] = { 355 gen_helper_mve_vldrd_sg_ud, 356 gen_helper_mve_vldrd_sg_wb_ud, 357 }; 358 if (a->qd == a->qm) { 359 return false; /* UNPREDICTABLE */ 360 } 361 return do_ldst_sg_imm(s, a, fns[a->w], MO_64); 362 } 363 364 static bool trans_VSTRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 365 { 366 static MVEGenLdStSGFn * const fns[] = { 367 gen_helper_mve_vstrw_sg_uw, 368 gen_helper_mve_vstrw_sg_wb_uw, 369 }; 370 return do_ldst_sg_imm(s, a, fns[a->w], MO_32); 371 } 372 373 static bool trans_VSTRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 374 { 375 static MVEGenLdStSGFn * const fns[] = { 376 gen_helper_mve_vstrd_sg_ud, 377 gen_helper_mve_vstrd_sg_wb_ud, 378 }; 379 return do_ldst_sg_imm(s, a, fns[a->w], MO_64); 380 } 381 382 static bool do_vldst_il(DisasContext *s, arg_vldst_il *a, MVEGenLdStIlFn *fn, 383 int addrinc) 384 { 385 TCGv_i32 rn; 386 387 if (!dc_isar_feature(aa32_mve, s) || 388 !mve_check_qreg_bank(s, a->qd) || 389 !fn || (a->rn == 13 && a->w) || a->rn == 15) { 390 /* Variously UNPREDICTABLE or UNDEF or related-encoding */ 391 return false; 392 } 393 if (!mve_eci_check(s) || !vfp_access_check(s)) { 394 return true; 395 } 396 397 rn = load_reg(s, a->rn); 398 /* 399 * We pass the index of Qd, not a pointer, because the helper must 400 * access multiple Q registers starting at Qd and working up. 401 */ 402 fn(cpu_env, tcg_constant_i32(a->qd), rn); 403 404 if (a->w) { 405 tcg_gen_addi_i32(rn, rn, addrinc); 406 store_reg(s, a->rn, rn); 407 } else { 408 tcg_temp_free_i32(rn); 409 } 410 mve_update_and_store_eci(s); 411 return true; 412 } 413 414 /* This macro is just to make the arrays more compact in these functions */ 415 #define F(N) gen_helper_mve_##N 416 417 static bool trans_VLD2(DisasContext *s, arg_vldst_il *a) 418 { 419 static MVEGenLdStIlFn * const fns[4][4] = { 420 { F(vld20b), F(vld20h), F(vld20w), NULL, }, 421 { F(vld21b), F(vld21h), F(vld21w), NULL, }, 422 { NULL, NULL, NULL, NULL }, 423 { NULL, NULL, NULL, NULL }, 424 }; 425 if (a->qd > 6) { 426 return false; 427 } 428 return do_vldst_il(s, a, fns[a->pat][a->size], 32); 429 } 430 431 static bool trans_VLD4(DisasContext *s, arg_vldst_il *a) 432 { 433 static MVEGenLdStIlFn * const fns[4][4] = { 434 { F(vld40b), F(vld40h), F(vld40w), NULL, }, 435 { F(vld41b), F(vld41h), F(vld41w), NULL, }, 436 { F(vld42b), F(vld42h), F(vld42w), NULL, }, 437 { F(vld43b), F(vld43h), F(vld43w), NULL, }, 438 }; 439 if (a->qd > 4) { 440 return false; 441 } 442 return do_vldst_il(s, a, fns[a->pat][a->size], 64); 443 } 444 445 static bool trans_VST2(DisasContext *s, arg_vldst_il *a) 446 { 447 static MVEGenLdStIlFn * const fns[4][4] = { 448 { F(vst20b), F(vst20h), F(vst20w), NULL, }, 449 { F(vst21b), F(vst21h), F(vst21w), NULL, }, 450 { NULL, NULL, NULL, NULL }, 451 { NULL, NULL, NULL, NULL }, 452 }; 453 if (a->qd > 6) { 454 return false; 455 } 456 return do_vldst_il(s, a, fns[a->pat][a->size], 32); 457 } 458 459 static bool trans_VST4(DisasContext *s, arg_vldst_il *a) 460 { 461 static MVEGenLdStIlFn * const fns[4][4] = { 462 { F(vst40b), F(vst40h), F(vst40w), NULL, }, 463 { F(vst41b), F(vst41h), F(vst41w), NULL, }, 464 { F(vst42b), F(vst42h), F(vst42w), NULL, }, 465 { F(vst43b), F(vst43h), F(vst43w), NULL, }, 466 }; 467 if (a->qd > 4) { 468 return false; 469 } 470 return do_vldst_il(s, a, fns[a->pat][a->size], 64); 471 } 472 473 #undef F 474 475 static bool trans_VDUP(DisasContext *s, arg_VDUP *a) 476 { 477 TCGv_ptr qd; 478 TCGv_i32 rt; 479 480 if (!dc_isar_feature(aa32_mve, s) || 481 !mve_check_qreg_bank(s, a->qd)) { 482 return false; 483 } 484 if (a->rt == 13 || a->rt == 15) { 485 /* UNPREDICTABLE; we choose to UNDEF */ 486 return false; 487 } 488 if (!mve_eci_check(s) || !vfp_access_check(s)) { 489 return true; 490 } 491 492 qd = mve_qreg_ptr(a->qd); 493 rt = load_reg(s, a->rt); 494 tcg_gen_dup_i32(a->size, rt, rt); 495 gen_helper_mve_vdup(cpu_env, qd, rt); 496 tcg_temp_free_ptr(qd); 497 tcg_temp_free_i32(rt); 498 mve_update_eci(s); 499 return true; 500 } 501 502 static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) 503 { 504 TCGv_ptr qd, qm; 505 506 if (!dc_isar_feature(aa32_mve, s) || 507 !mve_check_qreg_bank(s, a->qd | a->qm) || 508 !fn) { 509 return false; 510 } 511 512 if (!mve_eci_check(s) || !vfp_access_check(s)) { 513 return true; 514 } 515 516 qd = mve_qreg_ptr(a->qd); 517 qm = mve_qreg_ptr(a->qm); 518 fn(cpu_env, qd, qm); 519 tcg_temp_free_ptr(qd); 520 tcg_temp_free_ptr(qm); 521 mve_update_eci(s); 522 return true; 523 } 524 525 #define DO_1OP(INSN, FN) \ 526 static bool trans_##INSN(DisasContext *s, arg_1op *a) \ 527 { \ 528 static MVEGenOneOpFn * const fns[] = { \ 529 gen_helper_mve_##FN##b, \ 530 gen_helper_mve_##FN##h, \ 531 gen_helper_mve_##FN##w, \ 532 NULL, \ 533 }; \ 534 return do_1op(s, a, fns[a->size]); \ 535 } 536 537 DO_1OP(VCLZ, vclz) 538 DO_1OP(VCLS, vcls) 539 DO_1OP(VABS, vabs) 540 DO_1OP(VNEG, vneg) 541 DO_1OP(VQABS, vqabs) 542 DO_1OP(VQNEG, vqneg) 543 DO_1OP(VMAXA, vmaxa) 544 DO_1OP(VMINA, vmina) 545 546 /* Narrowing moves: only size 0 and 1 are valid */ 547 #define DO_VMOVN(INSN, FN) \ 548 static bool trans_##INSN(DisasContext *s, arg_1op *a) \ 549 { \ 550 static MVEGenOneOpFn * const fns[] = { \ 551 gen_helper_mve_##FN##b, \ 552 gen_helper_mve_##FN##h, \ 553 NULL, \ 554 NULL, \ 555 }; \ 556 return do_1op(s, a, fns[a->size]); \ 557 } 558 559 DO_VMOVN(VMOVNB, vmovnb) 560 DO_VMOVN(VMOVNT, vmovnt) 561 DO_VMOVN(VQMOVUNB, vqmovunb) 562 DO_VMOVN(VQMOVUNT, vqmovunt) 563 DO_VMOVN(VQMOVN_BS, vqmovnbs) 564 DO_VMOVN(VQMOVN_TS, vqmovnts) 565 DO_VMOVN(VQMOVN_BU, vqmovnbu) 566 DO_VMOVN(VQMOVN_TU, vqmovntu) 567 568 static bool trans_VREV16(DisasContext *s, arg_1op *a) 569 { 570 static MVEGenOneOpFn * const fns[] = { 571 gen_helper_mve_vrev16b, 572 NULL, 573 NULL, 574 NULL, 575 }; 576 return do_1op(s, a, fns[a->size]); 577 } 578 579 static bool trans_VREV32(DisasContext *s, arg_1op *a) 580 { 581 static MVEGenOneOpFn * const fns[] = { 582 gen_helper_mve_vrev32b, 583 gen_helper_mve_vrev32h, 584 NULL, 585 NULL, 586 }; 587 return do_1op(s, a, fns[a->size]); 588 } 589 590 static bool trans_VREV64(DisasContext *s, arg_1op *a) 591 { 592 static MVEGenOneOpFn * const fns[] = { 593 gen_helper_mve_vrev64b, 594 gen_helper_mve_vrev64h, 595 gen_helper_mve_vrev64w, 596 NULL, 597 }; 598 return do_1op(s, a, fns[a->size]); 599 } 600 601 static bool trans_VMVN(DisasContext *s, arg_1op *a) 602 { 603 return do_1op(s, a, gen_helper_mve_vmvn); 604 } 605 606 static bool trans_VABS_fp(DisasContext *s, arg_1op *a) 607 { 608 static MVEGenOneOpFn * const fns[] = { 609 NULL, 610 gen_helper_mve_vfabsh, 611 gen_helper_mve_vfabss, 612 NULL, 613 }; 614 if (!dc_isar_feature(aa32_mve_fp, s)) { 615 return false; 616 } 617 return do_1op(s, a, fns[a->size]); 618 } 619 620 static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) 621 { 622 static MVEGenOneOpFn * const fns[] = { 623 NULL, 624 gen_helper_mve_vfnegh, 625 gen_helper_mve_vfnegs, 626 NULL, 627 }; 628 if (!dc_isar_feature(aa32_mve_fp, s)) { 629 return false; 630 } 631 return do_1op(s, a, fns[a->size]); 632 } 633 634 static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) 635 { 636 TCGv_ptr qd, qn, qm; 637 638 if (!dc_isar_feature(aa32_mve, s) || 639 !mve_check_qreg_bank(s, a->qd | a->qn | a->qm) || 640 !fn) { 641 return false; 642 } 643 if (!mve_eci_check(s) || !vfp_access_check(s)) { 644 return true; 645 } 646 647 qd = mve_qreg_ptr(a->qd); 648 qn = mve_qreg_ptr(a->qn); 649 qm = mve_qreg_ptr(a->qm); 650 fn(cpu_env, qd, qn, qm); 651 tcg_temp_free_ptr(qd); 652 tcg_temp_free_ptr(qn); 653 tcg_temp_free_ptr(qm); 654 mve_update_eci(s); 655 return true; 656 } 657 658 #define DO_LOGIC(INSN, HELPER) \ 659 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 660 { \ 661 return do_2op(s, a, HELPER); \ 662 } 663 664 DO_LOGIC(VAND, gen_helper_mve_vand) 665 DO_LOGIC(VBIC, gen_helper_mve_vbic) 666 DO_LOGIC(VORR, gen_helper_mve_vorr) 667 DO_LOGIC(VORN, gen_helper_mve_vorn) 668 DO_LOGIC(VEOR, gen_helper_mve_veor) 669 670 DO_LOGIC(VPSEL, gen_helper_mve_vpsel) 671 672 #define DO_2OP(INSN, FN) \ 673 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 674 { \ 675 static MVEGenTwoOpFn * const fns[] = { \ 676 gen_helper_mve_##FN##b, \ 677 gen_helper_mve_##FN##h, \ 678 gen_helper_mve_##FN##w, \ 679 NULL, \ 680 }; \ 681 return do_2op(s, a, fns[a->size]); \ 682 } 683 684 DO_2OP(VADD, vadd) 685 DO_2OP(VSUB, vsub) 686 DO_2OP(VMUL, vmul) 687 DO_2OP(VMULH_S, vmulhs) 688 DO_2OP(VMULH_U, vmulhu) 689 DO_2OP(VRMULH_S, vrmulhs) 690 DO_2OP(VRMULH_U, vrmulhu) 691 DO_2OP(VMAX_S, vmaxs) 692 DO_2OP(VMAX_U, vmaxu) 693 DO_2OP(VMIN_S, vmins) 694 DO_2OP(VMIN_U, vminu) 695 DO_2OP(VABD_S, vabds) 696 DO_2OP(VABD_U, vabdu) 697 DO_2OP(VHADD_S, vhadds) 698 DO_2OP(VHADD_U, vhaddu) 699 DO_2OP(VHSUB_S, vhsubs) 700 DO_2OP(VHSUB_U, vhsubu) 701 DO_2OP(VMULL_BS, vmullbs) 702 DO_2OP(VMULL_BU, vmullbu) 703 DO_2OP(VMULL_TS, vmullts) 704 DO_2OP(VMULL_TU, vmulltu) 705 DO_2OP(VQDMULH, vqdmulh) 706 DO_2OP(VQRDMULH, vqrdmulh) 707 DO_2OP(VQADD_S, vqadds) 708 DO_2OP(VQADD_U, vqaddu) 709 DO_2OP(VQSUB_S, vqsubs) 710 DO_2OP(VQSUB_U, vqsubu) 711 DO_2OP(VSHL_S, vshls) 712 DO_2OP(VSHL_U, vshlu) 713 DO_2OP(VRSHL_S, vrshls) 714 DO_2OP(VRSHL_U, vrshlu) 715 DO_2OP(VQSHL_S, vqshls) 716 DO_2OP(VQSHL_U, vqshlu) 717 DO_2OP(VQRSHL_S, vqrshls) 718 DO_2OP(VQRSHL_U, vqrshlu) 719 DO_2OP(VQDMLADH, vqdmladh) 720 DO_2OP(VQDMLADHX, vqdmladhx) 721 DO_2OP(VQRDMLADH, vqrdmladh) 722 DO_2OP(VQRDMLADHX, vqrdmladhx) 723 DO_2OP(VQDMLSDH, vqdmlsdh) 724 DO_2OP(VQDMLSDHX, vqdmlsdhx) 725 DO_2OP(VQRDMLSDH, vqrdmlsdh) 726 DO_2OP(VQRDMLSDHX, vqrdmlsdhx) 727 DO_2OP(VRHADD_S, vrhadds) 728 DO_2OP(VRHADD_U, vrhaddu) 729 /* 730 * VCADD Qd == Qm at size MO_32 is UNPREDICTABLE; we choose not to diagnose 731 * so we can reuse the DO_2OP macro. (Our implementation calculates the 732 * "expected" results in this case.) Similarly for VHCADD. 733 */ 734 DO_2OP(VCADD90, vcadd90) 735 DO_2OP(VCADD270, vcadd270) 736 DO_2OP(VHCADD90, vhcadd90) 737 DO_2OP(VHCADD270, vhcadd270) 738 739 static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) 740 { 741 static MVEGenTwoOpFn * const fns[] = { 742 NULL, 743 gen_helper_mve_vqdmullbh, 744 gen_helper_mve_vqdmullbw, 745 NULL, 746 }; 747 if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) { 748 /* UNPREDICTABLE; we choose to undef */ 749 return false; 750 } 751 return do_2op(s, a, fns[a->size]); 752 } 753 754 static bool trans_VQDMULLT(DisasContext *s, arg_2op *a) 755 { 756 static MVEGenTwoOpFn * const fns[] = { 757 NULL, 758 gen_helper_mve_vqdmullth, 759 gen_helper_mve_vqdmulltw, 760 NULL, 761 }; 762 if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) { 763 /* UNPREDICTABLE; we choose to undef */ 764 return false; 765 } 766 return do_2op(s, a, fns[a->size]); 767 } 768 769 static bool trans_VMULLP_B(DisasContext *s, arg_2op *a) 770 { 771 /* 772 * Note that a->size indicates the output size, ie VMULL.P8 773 * is the 8x8->16 operation and a->size is MO_16; VMULL.P16 774 * is the 16x16->32 operation and a->size is MO_32. 775 */ 776 static MVEGenTwoOpFn * const fns[] = { 777 NULL, 778 gen_helper_mve_vmullpbh, 779 gen_helper_mve_vmullpbw, 780 NULL, 781 }; 782 return do_2op(s, a, fns[a->size]); 783 } 784 785 static bool trans_VMULLP_T(DisasContext *s, arg_2op *a) 786 { 787 /* a->size is as for trans_VMULLP_B */ 788 static MVEGenTwoOpFn * const fns[] = { 789 NULL, 790 gen_helper_mve_vmullpth, 791 gen_helper_mve_vmullptw, 792 NULL, 793 }; 794 return do_2op(s, a, fns[a->size]); 795 } 796 797 /* 798 * VADC and VSBC: these perform an add-with-carry or subtract-with-carry 799 * of the 32-bit elements in each lane of the input vectors, where the 800 * carry-out of each add is the carry-in of the next. The initial carry 801 * input is either fixed (0 for VADCI, 1 for VSBCI) or is from FPSCR.C 802 * (for VADC and VSBC); the carry out at the end is written back to FPSCR.C. 803 * These insns are subject to beat-wise execution. Partial execution 804 * of an I=1 (initial carry input fixed) insn which does not 805 * execute the first beat must start with the current FPSCR.NZCV 806 * value, not the fixed constant input. 807 */ 808 static bool trans_VADC(DisasContext *s, arg_2op *a) 809 { 810 return do_2op(s, a, gen_helper_mve_vadc); 811 } 812 813 static bool trans_VADCI(DisasContext *s, arg_2op *a) 814 { 815 if (mve_skip_first_beat(s)) { 816 return trans_VADC(s, a); 817 } 818 return do_2op(s, a, gen_helper_mve_vadci); 819 } 820 821 static bool trans_VSBC(DisasContext *s, arg_2op *a) 822 { 823 return do_2op(s, a, gen_helper_mve_vsbc); 824 } 825 826 static bool trans_VSBCI(DisasContext *s, arg_2op *a) 827 { 828 if (mve_skip_first_beat(s)) { 829 return trans_VSBC(s, a); 830 } 831 return do_2op(s, a, gen_helper_mve_vsbci); 832 } 833 834 #define DO_2OP_FP(INSN, FN) \ 835 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 836 { \ 837 static MVEGenTwoOpFn * const fns[] = { \ 838 NULL, \ 839 gen_helper_mve_##FN##h, \ 840 gen_helper_mve_##FN##s, \ 841 NULL, \ 842 }; \ 843 if (!dc_isar_feature(aa32_mve_fp, s)) { \ 844 return false; \ 845 } \ 846 return do_2op(s, a, fns[a->size]); \ 847 } 848 849 DO_2OP_FP(VADD_fp, vfadd) 850 DO_2OP_FP(VSUB_fp, vfsub) 851 DO_2OP_FP(VMUL_fp, vfmul) 852 DO_2OP_FP(VABD_fp, vfabd) 853 DO_2OP_FP(VMAXNM, vmaxnm) 854 DO_2OP_FP(VMINNM, vminnm) 855 DO_2OP_FP(VCADD90_fp, vfcadd90) 856 DO_2OP_FP(VCADD270_fp, vfcadd270) 857 DO_2OP_FP(VFMA, vfma) 858 DO_2OP_FP(VFMS, vfms) 859 860 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, 861 MVEGenTwoOpScalarFn fn) 862 { 863 TCGv_ptr qd, qn; 864 TCGv_i32 rm; 865 866 if (!dc_isar_feature(aa32_mve, s) || 867 !mve_check_qreg_bank(s, a->qd | a->qn) || 868 !fn) { 869 return false; 870 } 871 if (a->rm == 13 || a->rm == 15) { 872 /* UNPREDICTABLE */ 873 return false; 874 } 875 if (!mve_eci_check(s) || !vfp_access_check(s)) { 876 return true; 877 } 878 879 qd = mve_qreg_ptr(a->qd); 880 qn = mve_qreg_ptr(a->qn); 881 rm = load_reg(s, a->rm); 882 fn(cpu_env, qd, qn, rm); 883 tcg_temp_free_i32(rm); 884 tcg_temp_free_ptr(qd); 885 tcg_temp_free_ptr(qn); 886 mve_update_eci(s); 887 return true; 888 } 889 890 #define DO_2OP_SCALAR(INSN, FN) \ 891 static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ 892 { \ 893 static MVEGenTwoOpScalarFn * const fns[] = { \ 894 gen_helper_mve_##FN##b, \ 895 gen_helper_mve_##FN##h, \ 896 gen_helper_mve_##FN##w, \ 897 NULL, \ 898 }; \ 899 return do_2op_scalar(s, a, fns[a->size]); \ 900 } 901 902 DO_2OP_SCALAR(VADD_scalar, vadd_scalar) 903 DO_2OP_SCALAR(VSUB_scalar, vsub_scalar) 904 DO_2OP_SCALAR(VMUL_scalar, vmul_scalar) 905 DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) 906 DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) 907 DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) 908 DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) 909 DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar) 910 DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar) 911 DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar) 912 DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) 913 DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) 914 DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) 915 DO_2OP_SCALAR(VBRSR, vbrsr) 916 DO_2OP_SCALAR(VMLA, vmla) 917 DO_2OP_SCALAR(VMLAS, vmlas) 918 DO_2OP_SCALAR(VQDMLAH, vqdmlah) 919 DO_2OP_SCALAR(VQRDMLAH, vqrdmlah) 920 DO_2OP_SCALAR(VQDMLASH, vqdmlash) 921 DO_2OP_SCALAR(VQRDMLASH, vqrdmlash) 922 923 static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a) 924 { 925 static MVEGenTwoOpScalarFn * const fns[] = { 926 NULL, 927 gen_helper_mve_vqdmullb_scalarh, 928 gen_helper_mve_vqdmullb_scalarw, 929 NULL, 930 }; 931 if (a->qd == a->qn && a->size == MO_32) { 932 /* UNPREDICTABLE; we choose to undef */ 933 return false; 934 } 935 return do_2op_scalar(s, a, fns[a->size]); 936 } 937 938 static bool trans_VQDMULLT_scalar(DisasContext *s, arg_2scalar *a) 939 { 940 static MVEGenTwoOpScalarFn * const fns[] = { 941 NULL, 942 gen_helper_mve_vqdmullt_scalarh, 943 gen_helper_mve_vqdmullt_scalarw, 944 NULL, 945 }; 946 if (a->qd == a->qn && a->size == MO_32) { 947 /* UNPREDICTABLE; we choose to undef */ 948 return false; 949 } 950 return do_2op_scalar(s, a, fns[a->size]); 951 } 952 953 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, 954 MVEGenLongDualAccOpFn *fn) 955 { 956 TCGv_ptr qn, qm; 957 TCGv_i64 rda; 958 TCGv_i32 rdalo, rdahi; 959 960 if (!dc_isar_feature(aa32_mve, s) || 961 !mve_check_qreg_bank(s, a->qn | a->qm) || 962 !fn) { 963 return false; 964 } 965 /* 966 * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related 967 * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. 968 */ 969 if (a->rdahi == 13 || a->rdahi == 15) { 970 return false; 971 } 972 if (!mve_eci_check(s) || !vfp_access_check(s)) { 973 return true; 974 } 975 976 qn = mve_qreg_ptr(a->qn); 977 qm = mve_qreg_ptr(a->qm); 978 979 /* 980 * This insn is subject to beat-wise execution. Partial execution 981 * of an A=0 (no-accumulate) insn which does not execute the first 982 * beat must start with the current rda value, not 0. 983 */ 984 if (a->a || mve_skip_first_beat(s)) { 985 rda = tcg_temp_new_i64(); 986 rdalo = load_reg(s, a->rdalo); 987 rdahi = load_reg(s, a->rdahi); 988 tcg_gen_concat_i32_i64(rda, rdalo, rdahi); 989 tcg_temp_free_i32(rdalo); 990 tcg_temp_free_i32(rdahi); 991 } else { 992 rda = tcg_const_i64(0); 993 } 994 995 fn(rda, cpu_env, qn, qm, rda); 996 tcg_temp_free_ptr(qn); 997 tcg_temp_free_ptr(qm); 998 999 rdalo = tcg_temp_new_i32(); 1000 rdahi = tcg_temp_new_i32(); 1001 tcg_gen_extrl_i64_i32(rdalo, rda); 1002 tcg_gen_extrh_i64_i32(rdahi, rda); 1003 store_reg(s, a->rdalo, rdalo); 1004 store_reg(s, a->rdahi, rdahi); 1005 tcg_temp_free_i64(rda); 1006 mve_update_eci(s); 1007 return true; 1008 } 1009 1010 static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a) 1011 { 1012 static MVEGenLongDualAccOpFn * const fns[4][2] = { 1013 { NULL, NULL }, 1014 { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh }, 1015 { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw }, 1016 { NULL, NULL }, 1017 }; 1018 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1019 } 1020 1021 static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a) 1022 { 1023 static MVEGenLongDualAccOpFn * const fns[4][2] = { 1024 { NULL, NULL }, 1025 { gen_helper_mve_vmlaldavuh, NULL }, 1026 { gen_helper_mve_vmlaldavuw, NULL }, 1027 { NULL, NULL }, 1028 }; 1029 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1030 } 1031 1032 static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) 1033 { 1034 static MVEGenLongDualAccOpFn * const fns[4][2] = { 1035 { NULL, NULL }, 1036 { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh }, 1037 { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw }, 1038 { NULL, NULL }, 1039 }; 1040 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1041 } 1042 1043 static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a) 1044 { 1045 static MVEGenLongDualAccOpFn * const fns[] = { 1046 gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw, 1047 }; 1048 return do_long_dual_acc(s, a, fns[a->x]); 1049 } 1050 1051 static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a) 1052 { 1053 static MVEGenLongDualAccOpFn * const fns[] = { 1054 gen_helper_mve_vrmlaldavhuw, NULL, 1055 }; 1056 return do_long_dual_acc(s, a, fns[a->x]); 1057 } 1058 1059 static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) 1060 { 1061 static MVEGenLongDualAccOpFn * const fns[] = { 1062 gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw, 1063 }; 1064 return do_long_dual_acc(s, a, fns[a->x]); 1065 } 1066 1067 static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn) 1068 { 1069 TCGv_ptr qn, qm; 1070 TCGv_i32 rda; 1071 1072 if (!dc_isar_feature(aa32_mve, s) || 1073 !mve_check_qreg_bank(s, a->qn) || 1074 !fn) { 1075 return false; 1076 } 1077 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1078 return true; 1079 } 1080 1081 qn = mve_qreg_ptr(a->qn); 1082 qm = mve_qreg_ptr(a->qm); 1083 1084 /* 1085 * This insn is subject to beat-wise execution. Partial execution 1086 * of an A=0 (no-accumulate) insn which does not execute the first 1087 * beat must start with the current rda value, not 0. 1088 */ 1089 if (a->a || mve_skip_first_beat(s)) { 1090 rda = load_reg(s, a->rda); 1091 } else { 1092 rda = tcg_const_i32(0); 1093 } 1094 1095 fn(rda, cpu_env, qn, qm, rda); 1096 store_reg(s, a->rda, rda); 1097 tcg_temp_free_ptr(qn); 1098 tcg_temp_free_ptr(qm); 1099 1100 mve_update_eci(s); 1101 return true; 1102 } 1103 1104 #define DO_DUAL_ACC(INSN, FN) \ 1105 static bool trans_##INSN(DisasContext *s, arg_vmladav *a) \ 1106 { \ 1107 static MVEGenDualAccOpFn * const fns[4][2] = { \ 1108 { gen_helper_mve_##FN##b, gen_helper_mve_##FN##xb }, \ 1109 { gen_helper_mve_##FN##h, gen_helper_mve_##FN##xh }, \ 1110 { gen_helper_mve_##FN##w, gen_helper_mve_##FN##xw }, \ 1111 { NULL, NULL }, \ 1112 }; \ 1113 return do_dual_acc(s, a, fns[a->size][a->x]); \ 1114 } 1115 1116 DO_DUAL_ACC(VMLADAV_S, vmladavs) 1117 DO_DUAL_ACC(VMLSDAV, vmlsdav) 1118 1119 static bool trans_VMLADAV_U(DisasContext *s, arg_vmladav *a) 1120 { 1121 static MVEGenDualAccOpFn * const fns[4][2] = { 1122 { gen_helper_mve_vmladavub, NULL }, 1123 { gen_helper_mve_vmladavuh, NULL }, 1124 { gen_helper_mve_vmladavuw, NULL }, 1125 { NULL, NULL }, 1126 }; 1127 return do_dual_acc(s, a, fns[a->size][a->x]); 1128 } 1129 1130 static void gen_vpst(DisasContext *s, uint32_t mask) 1131 { 1132 /* 1133 * Set the VPR mask fields. We take advantage of MASK01 and MASK23 1134 * being adjacent fields in the register. 1135 * 1136 * Updating the masks is not predicated, but it is subject to beat-wise 1137 * execution, and the mask is updated on the odd-numbered beats. 1138 * So if PSR.ECI says we should skip beat 1, we mustn't update the 1139 * 01 mask field. 1140 */ 1141 TCGv_i32 vpr = load_cpu_field(v7m.vpr); 1142 switch (s->eci) { 1143 case ECI_NONE: 1144 case ECI_A0: 1145 /* Update both 01 and 23 fields */ 1146 tcg_gen_deposit_i32(vpr, vpr, 1147 tcg_constant_i32(mask | (mask << 4)), 1148 R_V7M_VPR_MASK01_SHIFT, 1149 R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH); 1150 break; 1151 case ECI_A0A1: 1152 case ECI_A0A1A2: 1153 case ECI_A0A1A2B0: 1154 /* Update only the 23 mask field */ 1155 tcg_gen_deposit_i32(vpr, vpr, 1156 tcg_constant_i32(mask), 1157 R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH); 1158 break; 1159 default: 1160 g_assert_not_reached(); 1161 } 1162 store_cpu_field(vpr, v7m.vpr); 1163 } 1164 1165 static bool trans_VPST(DisasContext *s, arg_VPST *a) 1166 { 1167 /* mask == 0 is a "related encoding" */ 1168 if (!dc_isar_feature(aa32_mve, s) || !a->mask) { 1169 return false; 1170 } 1171 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1172 return true; 1173 } 1174 gen_vpst(s, a->mask); 1175 mve_update_and_store_eci(s); 1176 return true; 1177 } 1178 1179 static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a) 1180 { 1181 /* 1182 * Invert the predicate in VPR.P0. We have call out to 1183 * a helper because this insn itself is beatwise and can 1184 * be predicated. 1185 */ 1186 if (!dc_isar_feature(aa32_mve, s)) { 1187 return false; 1188 } 1189 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1190 return true; 1191 } 1192 1193 gen_helper_mve_vpnot(cpu_env); 1194 mve_update_eci(s); 1195 return true; 1196 } 1197 1198 static bool trans_VADDV(DisasContext *s, arg_VADDV *a) 1199 { 1200 /* VADDV: vector add across vector */ 1201 static MVEGenVADDVFn * const fns[4][2] = { 1202 { gen_helper_mve_vaddvsb, gen_helper_mve_vaddvub }, 1203 { gen_helper_mve_vaddvsh, gen_helper_mve_vaddvuh }, 1204 { gen_helper_mve_vaddvsw, gen_helper_mve_vaddvuw }, 1205 { NULL, NULL } 1206 }; 1207 TCGv_ptr qm; 1208 TCGv_i32 rda; 1209 1210 if (!dc_isar_feature(aa32_mve, s) || 1211 a->size == 3) { 1212 return false; 1213 } 1214 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1215 return true; 1216 } 1217 1218 /* 1219 * This insn is subject to beat-wise execution. Partial execution 1220 * of an A=0 (no-accumulate) insn which does not execute the first 1221 * beat must start with the current value of Rda, not zero. 1222 */ 1223 if (a->a || mve_skip_first_beat(s)) { 1224 /* Accumulate input from Rda */ 1225 rda = load_reg(s, a->rda); 1226 } else { 1227 /* Accumulate starting at zero */ 1228 rda = tcg_const_i32(0); 1229 } 1230 1231 qm = mve_qreg_ptr(a->qm); 1232 fns[a->size][a->u](rda, cpu_env, qm, rda); 1233 store_reg(s, a->rda, rda); 1234 tcg_temp_free_ptr(qm); 1235 1236 mve_update_eci(s); 1237 return true; 1238 } 1239 1240 static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) 1241 { 1242 /* 1243 * Vector Add Long Across Vector: accumulate the 32-bit 1244 * elements of the vector into a 64-bit result stored in 1245 * a pair of general-purpose registers. 1246 * No need to check Qm's bank: it is only 3 bits in decode. 1247 */ 1248 TCGv_ptr qm; 1249 TCGv_i64 rda; 1250 TCGv_i32 rdalo, rdahi; 1251 1252 if (!dc_isar_feature(aa32_mve, s)) { 1253 return false; 1254 } 1255 /* 1256 * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related 1257 * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. 1258 */ 1259 if (a->rdahi == 13 || a->rdahi == 15) { 1260 return false; 1261 } 1262 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1263 return true; 1264 } 1265 1266 /* 1267 * This insn is subject to beat-wise execution. Partial execution 1268 * of an A=0 (no-accumulate) insn which does not execute the first 1269 * beat must start with the current value of RdaHi:RdaLo, not zero. 1270 */ 1271 if (a->a || mve_skip_first_beat(s)) { 1272 /* Accumulate input from RdaHi:RdaLo */ 1273 rda = tcg_temp_new_i64(); 1274 rdalo = load_reg(s, a->rdalo); 1275 rdahi = load_reg(s, a->rdahi); 1276 tcg_gen_concat_i32_i64(rda, rdalo, rdahi); 1277 tcg_temp_free_i32(rdalo); 1278 tcg_temp_free_i32(rdahi); 1279 } else { 1280 /* Accumulate starting at zero */ 1281 rda = tcg_const_i64(0); 1282 } 1283 1284 qm = mve_qreg_ptr(a->qm); 1285 if (a->u) { 1286 gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda); 1287 } else { 1288 gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); 1289 } 1290 tcg_temp_free_ptr(qm); 1291 1292 rdalo = tcg_temp_new_i32(); 1293 rdahi = tcg_temp_new_i32(); 1294 tcg_gen_extrl_i64_i32(rdalo, rda); 1295 tcg_gen_extrh_i64_i32(rdahi, rda); 1296 store_reg(s, a->rdalo, rdalo); 1297 store_reg(s, a->rdahi, rdahi); 1298 tcg_temp_free_i64(rda); 1299 mve_update_eci(s); 1300 return true; 1301 } 1302 1303 static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) 1304 { 1305 TCGv_ptr qd; 1306 uint64_t imm; 1307 1308 if (!dc_isar_feature(aa32_mve, s) || 1309 !mve_check_qreg_bank(s, a->qd) || 1310 !fn) { 1311 return false; 1312 } 1313 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1314 return true; 1315 } 1316 1317 imm = asimd_imm_const(a->imm, a->cmode, a->op); 1318 1319 qd = mve_qreg_ptr(a->qd); 1320 fn(cpu_env, qd, tcg_constant_i64(imm)); 1321 tcg_temp_free_ptr(qd); 1322 mve_update_eci(s); 1323 return true; 1324 } 1325 1326 static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) 1327 { 1328 /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ 1329 MVEGenOneOpImmFn *fn; 1330 1331 if ((a->cmode & 1) && a->cmode < 12) { 1332 if (a->op) { 1333 /* 1334 * For op=1, the immediate will be inverted by asimd_imm_const(), 1335 * so the VBIC becomes a logical AND operation. 1336 */ 1337 fn = gen_helper_mve_vandi; 1338 } else { 1339 fn = gen_helper_mve_vorri; 1340 } 1341 } else { 1342 /* There is one unallocated cmode/op combination in this space */ 1343 if (a->cmode == 15 && a->op == 1) { 1344 return false; 1345 } 1346 /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ 1347 fn = gen_helper_mve_vmovi; 1348 } 1349 return do_1imm(s, a, fn); 1350 } 1351 1352 static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, 1353 bool negateshift) 1354 { 1355 TCGv_ptr qd, qm; 1356 int shift = a->shift; 1357 1358 if (!dc_isar_feature(aa32_mve, s) || 1359 !mve_check_qreg_bank(s, a->qd | a->qm) || 1360 !fn) { 1361 return false; 1362 } 1363 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1364 return true; 1365 } 1366 1367 /* 1368 * When we handle a right shift insn using a left-shift helper 1369 * which permits a negative shift count to indicate a right-shift, 1370 * we must negate the shift count. 1371 */ 1372 if (negateshift) { 1373 shift = -shift; 1374 } 1375 1376 qd = mve_qreg_ptr(a->qd); 1377 qm = mve_qreg_ptr(a->qm); 1378 fn(cpu_env, qd, qm, tcg_constant_i32(shift)); 1379 tcg_temp_free_ptr(qd); 1380 tcg_temp_free_ptr(qm); 1381 mve_update_eci(s); 1382 return true; 1383 } 1384 1385 #define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ 1386 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1387 { \ 1388 static MVEGenTwoOpShiftFn * const fns[] = { \ 1389 gen_helper_mve_##FN##b, \ 1390 gen_helper_mve_##FN##h, \ 1391 gen_helper_mve_##FN##w, \ 1392 NULL, \ 1393 }; \ 1394 return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ 1395 } 1396 1397 DO_2SHIFT(VSHLI, vshli_u, false) 1398 DO_2SHIFT(VQSHLI_S, vqshli_s, false) 1399 DO_2SHIFT(VQSHLI_U, vqshli_u, false) 1400 DO_2SHIFT(VQSHLUI, vqshlui_s, false) 1401 /* These right shifts use a left-shift helper with negated shift count */ 1402 DO_2SHIFT(VSHRI_S, vshli_s, true) 1403 DO_2SHIFT(VSHRI_U, vshli_u, true) 1404 DO_2SHIFT(VRSHRI_S, vrshli_s, true) 1405 DO_2SHIFT(VRSHRI_U, vrshli_u, true) 1406 1407 DO_2SHIFT(VSRI, vsri, false) 1408 DO_2SHIFT(VSLI, vsli, false) 1409 1410 static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a, 1411 MVEGenTwoOpShiftFn *fn) 1412 { 1413 TCGv_ptr qda; 1414 TCGv_i32 rm; 1415 1416 if (!dc_isar_feature(aa32_mve, s) || 1417 !mve_check_qreg_bank(s, a->qda) || 1418 a->rm == 13 || a->rm == 15 || !fn) { 1419 /* Rm cases are UNPREDICTABLE */ 1420 return false; 1421 } 1422 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1423 return true; 1424 } 1425 1426 qda = mve_qreg_ptr(a->qda); 1427 rm = load_reg(s, a->rm); 1428 fn(cpu_env, qda, qda, rm); 1429 tcg_temp_free_ptr(qda); 1430 tcg_temp_free_i32(rm); 1431 mve_update_eci(s); 1432 return true; 1433 } 1434 1435 #define DO_2SHIFT_SCALAR(INSN, FN) \ 1436 static bool trans_##INSN(DisasContext *s, arg_shl_scalar *a) \ 1437 { \ 1438 static MVEGenTwoOpShiftFn * const fns[] = { \ 1439 gen_helper_mve_##FN##b, \ 1440 gen_helper_mve_##FN##h, \ 1441 gen_helper_mve_##FN##w, \ 1442 NULL, \ 1443 }; \ 1444 return do_2shift_scalar(s, a, fns[a->size]); \ 1445 } 1446 1447 DO_2SHIFT_SCALAR(VSHL_S_scalar, vshli_s) 1448 DO_2SHIFT_SCALAR(VSHL_U_scalar, vshli_u) 1449 DO_2SHIFT_SCALAR(VRSHL_S_scalar, vrshli_s) 1450 DO_2SHIFT_SCALAR(VRSHL_U_scalar, vrshli_u) 1451 DO_2SHIFT_SCALAR(VQSHL_S_scalar, vqshli_s) 1452 DO_2SHIFT_SCALAR(VQSHL_U_scalar, vqshli_u) 1453 DO_2SHIFT_SCALAR(VQRSHL_S_scalar, vqrshli_s) 1454 DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u) 1455 1456 #define DO_VSHLL(INSN, FN) \ 1457 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1458 { \ 1459 static MVEGenTwoOpShiftFn * const fns[] = { \ 1460 gen_helper_mve_##FN##b, \ 1461 gen_helper_mve_##FN##h, \ 1462 }; \ 1463 return do_2shift(s, a, fns[a->size], false); \ 1464 } 1465 1466 DO_VSHLL(VSHLL_BS, vshllbs) 1467 DO_VSHLL(VSHLL_BU, vshllbu) 1468 DO_VSHLL(VSHLL_TS, vshllts) 1469 DO_VSHLL(VSHLL_TU, vshlltu) 1470 1471 #define DO_2SHIFT_N(INSN, FN) \ 1472 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1473 { \ 1474 static MVEGenTwoOpShiftFn * const fns[] = { \ 1475 gen_helper_mve_##FN##b, \ 1476 gen_helper_mve_##FN##h, \ 1477 }; \ 1478 return do_2shift(s, a, fns[a->size], false); \ 1479 } 1480 1481 DO_2SHIFT_N(VSHRNB, vshrnb) 1482 DO_2SHIFT_N(VSHRNT, vshrnt) 1483 DO_2SHIFT_N(VRSHRNB, vrshrnb) 1484 DO_2SHIFT_N(VRSHRNT, vrshrnt) 1485 DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s) 1486 DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s) 1487 DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u) 1488 DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u) 1489 DO_2SHIFT_N(VQSHRUNB, vqshrunb) 1490 DO_2SHIFT_N(VQSHRUNT, vqshrunt) 1491 DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s) 1492 DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s) 1493 DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) 1494 DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) 1495 DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) 1496 DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) 1497 1498 static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) 1499 { 1500 /* 1501 * Whole Vector Left Shift with Carry. The carry is taken 1502 * from a general purpose register and written back there. 1503 * An imm of 0 means "shift by 32". 1504 */ 1505 TCGv_ptr qd; 1506 TCGv_i32 rdm; 1507 1508 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1509 return false; 1510 } 1511 if (a->rdm == 13 || a->rdm == 15) { 1512 /* CONSTRAINED UNPREDICTABLE: we UNDEF */ 1513 return false; 1514 } 1515 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1516 return true; 1517 } 1518 1519 qd = mve_qreg_ptr(a->qd); 1520 rdm = load_reg(s, a->rdm); 1521 gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); 1522 store_reg(s, a->rdm, rdm); 1523 tcg_temp_free_ptr(qd); 1524 mve_update_eci(s); 1525 return true; 1526 } 1527 1528 static bool do_vidup(DisasContext *s, arg_vidup *a, MVEGenVIDUPFn *fn) 1529 { 1530 TCGv_ptr qd; 1531 TCGv_i32 rn; 1532 1533 /* 1534 * Vector increment/decrement with wrap and duplicate (VIDUP, VDDUP). 1535 * This fills the vector with elements of successively increasing 1536 * or decreasing values, starting from Rn. 1537 */ 1538 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1539 return false; 1540 } 1541 if (a->size == MO_64) { 1542 /* size 0b11 is another encoding */ 1543 return false; 1544 } 1545 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1546 return true; 1547 } 1548 1549 qd = mve_qreg_ptr(a->qd); 1550 rn = load_reg(s, a->rn); 1551 fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm)); 1552 store_reg(s, a->rn, rn); 1553 tcg_temp_free_ptr(qd); 1554 mve_update_eci(s); 1555 return true; 1556 } 1557 1558 static bool do_viwdup(DisasContext *s, arg_viwdup *a, MVEGenVIWDUPFn *fn) 1559 { 1560 TCGv_ptr qd; 1561 TCGv_i32 rn, rm; 1562 1563 /* 1564 * Vector increment/decrement with wrap and duplicate (VIWDUp, VDWDUP) 1565 * This fills the vector with elements of successively increasing 1566 * or decreasing values, starting from Rn. Rm specifies a point where 1567 * the count wraps back around to 0. The updated offset is written back 1568 * to Rn. 1569 */ 1570 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1571 return false; 1572 } 1573 if (!fn || a->rm == 13 || a->rm == 15) { 1574 /* 1575 * size 0b11 is another encoding; Rm == 13 is UNPREDICTABLE; 1576 * Rm == 13 is VIWDUP, VDWDUP. 1577 */ 1578 return false; 1579 } 1580 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1581 return true; 1582 } 1583 1584 qd = mve_qreg_ptr(a->qd); 1585 rn = load_reg(s, a->rn); 1586 rm = load_reg(s, a->rm); 1587 fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm)); 1588 store_reg(s, a->rn, rn); 1589 tcg_temp_free_ptr(qd); 1590 tcg_temp_free_i32(rm); 1591 mve_update_eci(s); 1592 return true; 1593 } 1594 1595 static bool trans_VIDUP(DisasContext *s, arg_vidup *a) 1596 { 1597 static MVEGenVIDUPFn * const fns[] = { 1598 gen_helper_mve_vidupb, 1599 gen_helper_mve_viduph, 1600 gen_helper_mve_vidupw, 1601 NULL, 1602 }; 1603 return do_vidup(s, a, fns[a->size]); 1604 } 1605 1606 static bool trans_VDDUP(DisasContext *s, arg_vidup *a) 1607 { 1608 static MVEGenVIDUPFn * const fns[] = { 1609 gen_helper_mve_vidupb, 1610 gen_helper_mve_viduph, 1611 gen_helper_mve_vidupw, 1612 NULL, 1613 }; 1614 /* VDDUP is just like VIDUP but with a negative immediate */ 1615 a->imm = -a->imm; 1616 return do_vidup(s, a, fns[a->size]); 1617 } 1618 1619 static bool trans_VIWDUP(DisasContext *s, arg_viwdup *a) 1620 { 1621 static MVEGenVIWDUPFn * const fns[] = { 1622 gen_helper_mve_viwdupb, 1623 gen_helper_mve_viwduph, 1624 gen_helper_mve_viwdupw, 1625 NULL, 1626 }; 1627 return do_viwdup(s, a, fns[a->size]); 1628 } 1629 1630 static bool trans_VDWDUP(DisasContext *s, arg_viwdup *a) 1631 { 1632 static MVEGenVIWDUPFn * const fns[] = { 1633 gen_helper_mve_vdwdupb, 1634 gen_helper_mve_vdwduph, 1635 gen_helper_mve_vdwdupw, 1636 NULL, 1637 }; 1638 return do_viwdup(s, a, fns[a->size]); 1639 } 1640 1641 static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn) 1642 { 1643 TCGv_ptr qn, qm; 1644 1645 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) || 1646 !fn) { 1647 return false; 1648 } 1649 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1650 return true; 1651 } 1652 1653 qn = mve_qreg_ptr(a->qn); 1654 qm = mve_qreg_ptr(a->qm); 1655 fn(cpu_env, qn, qm); 1656 tcg_temp_free_ptr(qn); 1657 tcg_temp_free_ptr(qm); 1658 if (a->mask) { 1659 /* VPT */ 1660 gen_vpst(s, a->mask); 1661 } 1662 mve_update_eci(s); 1663 return true; 1664 } 1665 1666 static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a, 1667 MVEGenScalarCmpFn *fn) 1668 { 1669 TCGv_ptr qn; 1670 TCGv_i32 rm; 1671 1672 if (!dc_isar_feature(aa32_mve, s) || !fn || a->rm == 13) { 1673 return false; 1674 } 1675 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1676 return true; 1677 } 1678 1679 qn = mve_qreg_ptr(a->qn); 1680 if (a->rm == 15) { 1681 /* Encoding Rm=0b1111 means "constant zero" */ 1682 rm = tcg_constant_i32(0); 1683 } else { 1684 rm = load_reg(s, a->rm); 1685 } 1686 fn(cpu_env, qn, rm); 1687 tcg_temp_free_ptr(qn); 1688 tcg_temp_free_i32(rm); 1689 if (a->mask) { 1690 /* VPT */ 1691 gen_vpst(s, a->mask); 1692 } 1693 mve_update_eci(s); 1694 return true; 1695 } 1696 1697 #define DO_VCMP(INSN, FN) \ 1698 static bool trans_##INSN(DisasContext *s, arg_vcmp *a) \ 1699 { \ 1700 static MVEGenCmpFn * const fns[] = { \ 1701 gen_helper_mve_##FN##b, \ 1702 gen_helper_mve_##FN##h, \ 1703 gen_helper_mve_##FN##w, \ 1704 NULL, \ 1705 }; \ 1706 return do_vcmp(s, a, fns[a->size]); \ 1707 } \ 1708 static bool trans_##INSN##_scalar(DisasContext *s, \ 1709 arg_vcmp_scalar *a) \ 1710 { \ 1711 static MVEGenScalarCmpFn * const fns[] = { \ 1712 gen_helper_mve_##FN##_scalarb, \ 1713 gen_helper_mve_##FN##_scalarh, \ 1714 gen_helper_mve_##FN##_scalarw, \ 1715 NULL, \ 1716 }; \ 1717 return do_vcmp_scalar(s, a, fns[a->size]); \ 1718 } 1719 1720 DO_VCMP(VCMPEQ, vcmpeq) 1721 DO_VCMP(VCMPNE, vcmpne) 1722 DO_VCMP(VCMPCS, vcmpcs) 1723 DO_VCMP(VCMPHI, vcmphi) 1724 DO_VCMP(VCMPGE, vcmpge) 1725 DO_VCMP(VCMPLT, vcmplt) 1726 DO_VCMP(VCMPGT, vcmpgt) 1727 DO_VCMP(VCMPLE, vcmple) 1728 1729 static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn) 1730 { 1731 /* 1732 * MIN/MAX operations across a vector: compute the min or 1733 * max of the initial value in a general purpose register 1734 * and all the elements in the vector, and store it back 1735 * into the general purpose register. 1736 */ 1737 TCGv_ptr qm; 1738 TCGv_i32 rda; 1739 1740 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) || 1741 !fn || a->rda == 13 || a->rda == 15) { 1742 /* Rda cases are UNPREDICTABLE */ 1743 return false; 1744 } 1745 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1746 return true; 1747 } 1748 1749 qm = mve_qreg_ptr(a->qm); 1750 rda = load_reg(s, a->rda); 1751 fn(rda, cpu_env, qm, rda); 1752 store_reg(s, a->rda, rda); 1753 tcg_temp_free_ptr(qm); 1754 mve_update_eci(s); 1755 return true; 1756 } 1757 1758 #define DO_VMAXV(INSN, FN) \ 1759 static bool trans_##INSN(DisasContext *s, arg_vmaxv *a) \ 1760 { \ 1761 static MVEGenVADDVFn * const fns[] = { \ 1762 gen_helper_mve_##FN##b, \ 1763 gen_helper_mve_##FN##h, \ 1764 gen_helper_mve_##FN##w, \ 1765 NULL, \ 1766 }; \ 1767 return do_vmaxv(s, a, fns[a->size]); \ 1768 } 1769 1770 DO_VMAXV(VMAXV_S, vmaxvs) 1771 DO_VMAXV(VMAXV_U, vmaxvu) 1772 DO_VMAXV(VMAXAV, vmaxav) 1773 DO_VMAXV(VMINV_S, vminvs) 1774 DO_VMAXV(VMINV_U, vminvu) 1775 DO_VMAXV(VMINAV, vminav) 1776 1777 static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn) 1778 { 1779 /* Absolute difference accumulated across vector */ 1780 TCGv_ptr qn, qm; 1781 TCGv_i32 rda; 1782 1783 if (!dc_isar_feature(aa32_mve, s) || 1784 !mve_check_qreg_bank(s, a->qm | a->qn) || 1785 !fn || a->rda == 13 || a->rda == 15) { 1786 /* Rda cases are UNPREDICTABLE */ 1787 return false; 1788 } 1789 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1790 return true; 1791 } 1792 1793 qm = mve_qreg_ptr(a->qm); 1794 qn = mve_qreg_ptr(a->qn); 1795 rda = load_reg(s, a->rda); 1796 fn(rda, cpu_env, qn, qm, rda); 1797 store_reg(s, a->rda, rda); 1798 tcg_temp_free_ptr(qm); 1799 tcg_temp_free_ptr(qn); 1800 mve_update_eci(s); 1801 return true; 1802 } 1803 1804 #define DO_VABAV(INSN, FN) \ 1805 static bool trans_##INSN(DisasContext *s, arg_vabav *a) \ 1806 { \ 1807 static MVEGenVABAVFn * const fns[] = { \ 1808 gen_helper_mve_##FN##b, \ 1809 gen_helper_mve_##FN##h, \ 1810 gen_helper_mve_##FN##w, \ 1811 NULL, \ 1812 }; \ 1813 return do_vabav(s, a, fns[a->size]); \ 1814 } 1815 1816 DO_VABAV(VABAV_S, vabavs) 1817 DO_VABAV(VABAV_U, vabavu) 1818 1819 static bool trans_VMOV_to_2gp(DisasContext *s, arg_VMOV_to_2gp *a) 1820 { 1821 /* 1822 * VMOV two 32-bit vector lanes to two general-purpose registers. 1823 * This insn is not predicated but it is subject to beat-wise 1824 * execution if it is not in an IT block. For us this means 1825 * only that if PSR.ECI says we should not be executing the beat 1826 * corresponding to the lane of the vector register being accessed 1827 * then we should skip perfoming the move, and that we need to do 1828 * the usual check for bad ECI state and advance of ECI state. 1829 * (If PSR.ECI is non-zero then we cannot be in an IT block.) 1830 */ 1831 TCGv_i32 tmp; 1832 int vd; 1833 1834 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) || 1835 a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15 || 1836 a->rt == a->rt2) { 1837 /* Rt/Rt2 cases are UNPREDICTABLE */ 1838 return false; 1839 } 1840 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1841 return true; 1842 } 1843 1844 /* Convert Qreg index to Dreg for read_neon_element32() etc */ 1845 vd = a->qd * 2; 1846 1847 if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { 1848 tmp = tcg_temp_new_i32(); 1849 read_neon_element32(tmp, vd, a->idx, MO_32); 1850 store_reg(s, a->rt, tmp); 1851 } 1852 if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { 1853 tmp = tcg_temp_new_i32(); 1854 read_neon_element32(tmp, vd + 1, a->idx, MO_32); 1855 store_reg(s, a->rt2, tmp); 1856 } 1857 1858 mve_update_and_store_eci(s); 1859 return true; 1860 } 1861 1862 static bool trans_VMOV_from_2gp(DisasContext *s, arg_VMOV_to_2gp *a) 1863 { 1864 /* 1865 * VMOV two general-purpose registers to two 32-bit vector lanes. 1866 * This insn is not predicated but it is subject to beat-wise 1867 * execution if it is not in an IT block. For us this means 1868 * only that if PSR.ECI says we should not be executing the beat 1869 * corresponding to the lane of the vector register being accessed 1870 * then we should skip perfoming the move, and that we need to do 1871 * the usual check for bad ECI state and advance of ECI state. 1872 * (If PSR.ECI is non-zero then we cannot be in an IT block.) 1873 */ 1874 TCGv_i32 tmp; 1875 int vd; 1876 1877 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) || 1878 a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15) { 1879 /* Rt/Rt2 cases are UNPREDICTABLE */ 1880 return false; 1881 } 1882 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1883 return true; 1884 } 1885 1886 /* Convert Qreg idx to Dreg for read_neon_element32() etc */ 1887 vd = a->qd * 2; 1888 1889 if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { 1890 tmp = load_reg(s, a->rt); 1891 write_neon_element32(tmp, vd, a->idx, MO_32); 1892 tcg_temp_free_i32(tmp); 1893 } 1894 if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { 1895 tmp = load_reg(s, a->rt2); 1896 write_neon_element32(tmp, vd + 1, a->idx, MO_32); 1897 tcg_temp_free_i32(tmp); 1898 } 1899 1900 mve_update_and_store_eci(s); 1901 return true; 1902 } 1903