1 /* 2 * ARM translation: M-profile MVE instructions 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "tcg/tcg-op.h" 22 #include "tcg/tcg-op-gvec.h" 23 #include "exec/exec-all.h" 24 #include "exec/gen-icount.h" 25 #include "translate.h" 26 #include "translate-a32.h" 27 28 static inline int vidup_imm(DisasContext *s, int x) 29 { 30 return 1 << x; 31 } 32 33 /* Include the generated decoder */ 34 #include "decode-mve.c.inc" 35 36 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 37 typedef void MVEGenLdStSGFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 38 typedef void MVEGenLdStIlFn(TCGv_ptr, TCGv_i32, TCGv_i32); 39 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 40 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); 41 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 42 typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 43 typedef void MVEGenLongDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); 44 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); 45 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); 46 typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32); 47 typedef void MVEGenVIWDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); 48 typedef void MVEGenCmpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 49 typedef void MVEGenScalarCmpFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 50 typedef void MVEGenVABAVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 51 typedef void MVEGenDualAccOpFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); 52 53 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ 54 static inline long mve_qreg_offset(unsigned reg) 55 { 56 return offsetof(CPUARMState, vfp.zregs[reg].d[0]); 57 } 58 59 static TCGv_ptr mve_qreg_ptr(unsigned reg) 60 { 61 TCGv_ptr ret = tcg_temp_new_ptr(); 62 tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg)); 63 return ret; 64 } 65 66 static bool mve_check_qreg_bank(DisasContext *s, int qmask) 67 { 68 /* 69 * Check whether Qregs are in range. For v8.1M only Q0..Q7 70 * are supported, see VFPSmallRegisterBank(). 71 */ 72 return qmask < 8; 73 } 74 75 bool mve_eci_check(DisasContext *s) 76 { 77 /* 78 * This is a beatwise insn: check that ECI is valid (not a 79 * reserved value) and note that we are handling it. 80 * Return true if OK, false if we generated an exception. 81 */ 82 s->eci_handled = true; 83 switch (s->eci) { 84 case ECI_NONE: 85 case ECI_A0: 86 case ECI_A0A1: 87 case ECI_A0A1A2: 88 case ECI_A0A1A2B0: 89 return true; 90 default: 91 /* Reserved value: INVSTATE UsageFault */ 92 gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), 93 default_exception_el(s)); 94 return false; 95 } 96 } 97 98 void mve_update_eci(DisasContext *s) 99 { 100 /* 101 * The helper function will always update the CPUState field, 102 * so we only need to update the DisasContext field. 103 */ 104 if (s->eci) { 105 s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE; 106 } 107 } 108 109 void mve_update_and_store_eci(DisasContext *s) 110 { 111 /* 112 * For insns which don't call a helper function that will call 113 * mve_advance_vpt(), this version updates s->eci and also stores 114 * it out to the CPUState field. 115 */ 116 if (s->eci) { 117 mve_update_eci(s); 118 store_cpu_field(tcg_constant_i32(s->eci << 4), condexec_bits); 119 } 120 } 121 122 static bool mve_skip_first_beat(DisasContext *s) 123 { 124 /* Return true if PSR.ECI says we must skip the first beat of this insn */ 125 switch (s->eci) { 126 case ECI_NONE: 127 return false; 128 case ECI_A0: 129 case ECI_A0A1: 130 case ECI_A0A1A2: 131 case ECI_A0A1A2B0: 132 return true; 133 default: 134 g_assert_not_reached(); 135 } 136 } 137 138 static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, 139 unsigned msize) 140 { 141 TCGv_i32 addr; 142 uint32_t offset; 143 TCGv_ptr qreg; 144 145 if (!dc_isar_feature(aa32_mve, s) || 146 !mve_check_qreg_bank(s, a->qd) || 147 !fn) { 148 return false; 149 } 150 151 /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ 152 if (a->rn == 15 || (a->rn == 13 && a->w)) { 153 return false; 154 } 155 156 if (!mve_eci_check(s) || !vfp_access_check(s)) { 157 return true; 158 } 159 160 offset = a->imm << msize; 161 if (!a->a) { 162 offset = -offset; 163 } 164 addr = load_reg(s, a->rn); 165 if (a->p) { 166 tcg_gen_addi_i32(addr, addr, offset); 167 } 168 169 qreg = mve_qreg_ptr(a->qd); 170 fn(cpu_env, qreg, addr); 171 tcg_temp_free_ptr(qreg); 172 173 /* 174 * Writeback always happens after the last beat of the insn, 175 * regardless of predication 176 */ 177 if (a->w) { 178 if (!a->p) { 179 tcg_gen_addi_i32(addr, addr, offset); 180 } 181 store_reg(s, a->rn, addr); 182 } else { 183 tcg_temp_free_i32(addr); 184 } 185 mve_update_eci(s); 186 return true; 187 } 188 189 static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) 190 { 191 static MVEGenLdStFn * const ldstfns[4][2] = { 192 { gen_helper_mve_vstrb, gen_helper_mve_vldrb }, 193 { gen_helper_mve_vstrh, gen_helper_mve_vldrh }, 194 { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, 195 { NULL, NULL } 196 }; 197 return do_ldst(s, a, ldstfns[a->size][a->l], a->size); 198 } 199 200 #define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \ 201 static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ 202 { \ 203 static MVEGenLdStFn * const ldstfns[2][2] = { \ 204 { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ 205 { NULL, gen_helper_mve_##ULD }, \ 206 }; \ 207 return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \ 208 } 209 210 DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8) 211 DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8) 212 DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16) 213 214 static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a, MVEGenLdStSGFn fn) 215 { 216 TCGv_i32 addr; 217 TCGv_ptr qd, qm; 218 219 if (!dc_isar_feature(aa32_mve, s) || 220 !mve_check_qreg_bank(s, a->qd | a->qm) || 221 !fn || a->rn == 15) { 222 /* Rn case is UNPREDICTABLE */ 223 return false; 224 } 225 226 if (!mve_eci_check(s) || !vfp_access_check(s)) { 227 return true; 228 } 229 230 addr = load_reg(s, a->rn); 231 232 qd = mve_qreg_ptr(a->qd); 233 qm = mve_qreg_ptr(a->qm); 234 fn(cpu_env, qd, qm, addr); 235 tcg_temp_free_ptr(qd); 236 tcg_temp_free_ptr(qm); 237 tcg_temp_free_i32(addr); 238 mve_update_eci(s); 239 return true; 240 } 241 242 /* 243 * The naming scheme here is "vldrb_sg_sh == in-memory byte loads 244 * signextended to halfword elements in register". _os_ indicates that 245 * the offsets in Qm should be scaled by the element size. 246 */ 247 /* This macro is just to make the arrays more compact in these functions */ 248 #define F(N) gen_helper_mve_##N 249 250 /* VLDRB/VSTRB (ie msize 1) with OS=1 is UNPREDICTABLE; we UNDEF */ 251 static bool trans_VLDR_S_sg(DisasContext *s, arg_vldst_sg *a) 252 { 253 static MVEGenLdStSGFn * const fns[2][4][4] = { { 254 { NULL, F(vldrb_sg_sh), F(vldrb_sg_sw), NULL }, 255 { NULL, NULL, F(vldrh_sg_sw), NULL }, 256 { NULL, NULL, NULL, NULL }, 257 { NULL, NULL, NULL, NULL } 258 }, { 259 { NULL, NULL, NULL, NULL }, 260 { NULL, NULL, F(vldrh_sg_os_sw), NULL }, 261 { NULL, NULL, NULL, NULL }, 262 { NULL, NULL, NULL, NULL } 263 } 264 }; 265 if (a->qd == a->qm) { 266 return false; /* UNPREDICTABLE */ 267 } 268 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 269 } 270 271 static bool trans_VLDR_U_sg(DisasContext *s, arg_vldst_sg *a) 272 { 273 static MVEGenLdStSGFn * const fns[2][4][4] = { { 274 { F(vldrb_sg_ub), F(vldrb_sg_uh), F(vldrb_sg_uw), NULL }, 275 { NULL, F(vldrh_sg_uh), F(vldrh_sg_uw), NULL }, 276 { NULL, NULL, F(vldrw_sg_uw), NULL }, 277 { NULL, NULL, NULL, F(vldrd_sg_ud) } 278 }, { 279 { NULL, NULL, NULL, NULL }, 280 { NULL, F(vldrh_sg_os_uh), F(vldrh_sg_os_uw), NULL }, 281 { NULL, NULL, F(vldrw_sg_os_uw), NULL }, 282 { NULL, NULL, NULL, F(vldrd_sg_os_ud) } 283 } 284 }; 285 if (a->qd == a->qm) { 286 return false; /* UNPREDICTABLE */ 287 } 288 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 289 } 290 291 static bool trans_VSTR_sg(DisasContext *s, arg_vldst_sg *a) 292 { 293 static MVEGenLdStSGFn * const fns[2][4][4] = { { 294 { F(vstrb_sg_ub), F(vstrb_sg_uh), F(vstrb_sg_uw), NULL }, 295 { NULL, F(vstrh_sg_uh), F(vstrh_sg_uw), NULL }, 296 { NULL, NULL, F(vstrw_sg_uw), NULL }, 297 { NULL, NULL, NULL, F(vstrd_sg_ud) } 298 }, { 299 { NULL, NULL, NULL, NULL }, 300 { NULL, F(vstrh_sg_os_uh), F(vstrh_sg_os_uw), NULL }, 301 { NULL, NULL, F(vstrw_sg_os_uw), NULL }, 302 { NULL, NULL, NULL, F(vstrd_sg_os_ud) } 303 } 304 }; 305 return do_ldst_sg(s, a, fns[a->os][a->msize][a->size]); 306 } 307 308 #undef F 309 310 static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_sg_imm *a, 311 MVEGenLdStSGFn *fn, unsigned msize) 312 { 313 uint32_t offset; 314 TCGv_ptr qd, qm; 315 316 if (!dc_isar_feature(aa32_mve, s) || 317 !mve_check_qreg_bank(s, a->qd | a->qm) || 318 !fn) { 319 return false; 320 } 321 322 if (!mve_eci_check(s) || !vfp_access_check(s)) { 323 return true; 324 } 325 326 offset = a->imm << msize; 327 if (!a->a) { 328 offset = -offset; 329 } 330 331 qd = mve_qreg_ptr(a->qd); 332 qm = mve_qreg_ptr(a->qm); 333 fn(cpu_env, qd, qm, tcg_constant_i32(offset)); 334 tcg_temp_free_ptr(qd); 335 tcg_temp_free_ptr(qm); 336 mve_update_eci(s); 337 return true; 338 } 339 340 static bool trans_VLDRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 341 { 342 static MVEGenLdStSGFn * const fns[] = { 343 gen_helper_mve_vldrw_sg_uw, 344 gen_helper_mve_vldrw_sg_wb_uw, 345 }; 346 if (a->qd == a->qm) { 347 return false; /* UNPREDICTABLE */ 348 } 349 return do_ldst_sg_imm(s, a, fns[a->w], MO_32); 350 } 351 352 static bool trans_VLDRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 353 { 354 static MVEGenLdStSGFn * const fns[] = { 355 gen_helper_mve_vldrd_sg_ud, 356 gen_helper_mve_vldrd_sg_wb_ud, 357 }; 358 if (a->qd == a->qm) { 359 return false; /* UNPREDICTABLE */ 360 } 361 return do_ldst_sg_imm(s, a, fns[a->w], MO_64); 362 } 363 364 static bool trans_VSTRW_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 365 { 366 static MVEGenLdStSGFn * const fns[] = { 367 gen_helper_mve_vstrw_sg_uw, 368 gen_helper_mve_vstrw_sg_wb_uw, 369 }; 370 return do_ldst_sg_imm(s, a, fns[a->w], MO_32); 371 } 372 373 static bool trans_VSTRD_sg_imm(DisasContext *s, arg_vldst_sg_imm *a) 374 { 375 static MVEGenLdStSGFn * const fns[] = { 376 gen_helper_mve_vstrd_sg_ud, 377 gen_helper_mve_vstrd_sg_wb_ud, 378 }; 379 return do_ldst_sg_imm(s, a, fns[a->w], MO_64); 380 } 381 382 static bool do_vldst_il(DisasContext *s, arg_vldst_il *a, MVEGenLdStIlFn *fn, 383 int addrinc) 384 { 385 TCGv_i32 rn; 386 387 if (!dc_isar_feature(aa32_mve, s) || 388 !mve_check_qreg_bank(s, a->qd) || 389 !fn || (a->rn == 13 && a->w) || a->rn == 15) { 390 /* Variously UNPREDICTABLE or UNDEF or related-encoding */ 391 return false; 392 } 393 if (!mve_eci_check(s) || !vfp_access_check(s)) { 394 return true; 395 } 396 397 rn = load_reg(s, a->rn); 398 /* 399 * We pass the index of Qd, not a pointer, because the helper must 400 * access multiple Q registers starting at Qd and working up. 401 */ 402 fn(cpu_env, tcg_constant_i32(a->qd), rn); 403 404 if (a->w) { 405 tcg_gen_addi_i32(rn, rn, addrinc); 406 store_reg(s, a->rn, rn); 407 } else { 408 tcg_temp_free_i32(rn); 409 } 410 mve_update_and_store_eci(s); 411 return true; 412 } 413 414 /* This macro is just to make the arrays more compact in these functions */ 415 #define F(N) gen_helper_mve_##N 416 417 static bool trans_VLD2(DisasContext *s, arg_vldst_il *a) 418 { 419 static MVEGenLdStIlFn * const fns[4][4] = { 420 { F(vld20b), F(vld20h), F(vld20w), NULL, }, 421 { F(vld21b), F(vld21h), F(vld21w), NULL, }, 422 { NULL, NULL, NULL, NULL }, 423 { NULL, NULL, NULL, NULL }, 424 }; 425 if (a->qd > 6) { 426 return false; 427 } 428 return do_vldst_il(s, a, fns[a->pat][a->size], 32); 429 } 430 431 static bool trans_VLD4(DisasContext *s, arg_vldst_il *a) 432 { 433 static MVEGenLdStIlFn * const fns[4][4] = { 434 { F(vld40b), F(vld40h), F(vld40w), NULL, }, 435 { F(vld41b), F(vld41h), F(vld41w), NULL, }, 436 { F(vld42b), F(vld42h), F(vld42w), NULL, }, 437 { F(vld43b), F(vld43h), F(vld43w), NULL, }, 438 }; 439 if (a->qd > 4) { 440 return false; 441 } 442 return do_vldst_il(s, a, fns[a->pat][a->size], 64); 443 } 444 445 static bool trans_VST2(DisasContext *s, arg_vldst_il *a) 446 { 447 static MVEGenLdStIlFn * const fns[4][4] = { 448 { F(vst20b), F(vst20h), F(vst20w), NULL, }, 449 { F(vst21b), F(vst21h), F(vst21w), NULL, }, 450 { NULL, NULL, NULL, NULL }, 451 { NULL, NULL, NULL, NULL }, 452 }; 453 if (a->qd > 6) { 454 return false; 455 } 456 return do_vldst_il(s, a, fns[a->pat][a->size], 32); 457 } 458 459 static bool trans_VST4(DisasContext *s, arg_vldst_il *a) 460 { 461 static MVEGenLdStIlFn * const fns[4][4] = { 462 { F(vst40b), F(vst40h), F(vst40w), NULL, }, 463 { F(vst41b), F(vst41h), F(vst41w), NULL, }, 464 { F(vst42b), F(vst42h), F(vst42w), NULL, }, 465 { F(vst43b), F(vst43h), F(vst43w), NULL, }, 466 }; 467 if (a->qd > 4) { 468 return false; 469 } 470 return do_vldst_il(s, a, fns[a->pat][a->size], 64); 471 } 472 473 #undef F 474 475 static bool trans_VDUP(DisasContext *s, arg_VDUP *a) 476 { 477 TCGv_ptr qd; 478 TCGv_i32 rt; 479 480 if (!dc_isar_feature(aa32_mve, s) || 481 !mve_check_qreg_bank(s, a->qd)) { 482 return false; 483 } 484 if (a->rt == 13 || a->rt == 15) { 485 /* UNPREDICTABLE; we choose to UNDEF */ 486 return false; 487 } 488 if (!mve_eci_check(s) || !vfp_access_check(s)) { 489 return true; 490 } 491 492 qd = mve_qreg_ptr(a->qd); 493 rt = load_reg(s, a->rt); 494 tcg_gen_dup_i32(a->size, rt, rt); 495 gen_helper_mve_vdup(cpu_env, qd, rt); 496 tcg_temp_free_ptr(qd); 497 tcg_temp_free_i32(rt); 498 mve_update_eci(s); 499 return true; 500 } 501 502 static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) 503 { 504 TCGv_ptr qd, qm; 505 506 if (!dc_isar_feature(aa32_mve, s) || 507 !mve_check_qreg_bank(s, a->qd | a->qm) || 508 !fn) { 509 return false; 510 } 511 512 if (!mve_eci_check(s) || !vfp_access_check(s)) { 513 return true; 514 } 515 516 qd = mve_qreg_ptr(a->qd); 517 qm = mve_qreg_ptr(a->qm); 518 fn(cpu_env, qd, qm); 519 tcg_temp_free_ptr(qd); 520 tcg_temp_free_ptr(qm); 521 mve_update_eci(s); 522 return true; 523 } 524 525 #define DO_1OP(INSN, FN) \ 526 static bool trans_##INSN(DisasContext *s, arg_1op *a) \ 527 { \ 528 static MVEGenOneOpFn * const fns[] = { \ 529 gen_helper_mve_##FN##b, \ 530 gen_helper_mve_##FN##h, \ 531 gen_helper_mve_##FN##w, \ 532 NULL, \ 533 }; \ 534 return do_1op(s, a, fns[a->size]); \ 535 } 536 537 DO_1OP(VCLZ, vclz) 538 DO_1OP(VCLS, vcls) 539 DO_1OP(VABS, vabs) 540 DO_1OP(VNEG, vneg) 541 DO_1OP(VQABS, vqabs) 542 DO_1OP(VQNEG, vqneg) 543 DO_1OP(VMAXA, vmaxa) 544 DO_1OP(VMINA, vmina) 545 546 /* Narrowing moves: only size 0 and 1 are valid */ 547 #define DO_VMOVN(INSN, FN) \ 548 static bool trans_##INSN(DisasContext *s, arg_1op *a) \ 549 { \ 550 static MVEGenOneOpFn * const fns[] = { \ 551 gen_helper_mve_##FN##b, \ 552 gen_helper_mve_##FN##h, \ 553 NULL, \ 554 NULL, \ 555 }; \ 556 return do_1op(s, a, fns[a->size]); \ 557 } 558 559 DO_VMOVN(VMOVNB, vmovnb) 560 DO_VMOVN(VMOVNT, vmovnt) 561 DO_VMOVN(VQMOVUNB, vqmovunb) 562 DO_VMOVN(VQMOVUNT, vqmovunt) 563 DO_VMOVN(VQMOVN_BS, vqmovnbs) 564 DO_VMOVN(VQMOVN_TS, vqmovnts) 565 DO_VMOVN(VQMOVN_BU, vqmovnbu) 566 DO_VMOVN(VQMOVN_TU, vqmovntu) 567 568 static bool trans_VREV16(DisasContext *s, arg_1op *a) 569 { 570 static MVEGenOneOpFn * const fns[] = { 571 gen_helper_mve_vrev16b, 572 NULL, 573 NULL, 574 NULL, 575 }; 576 return do_1op(s, a, fns[a->size]); 577 } 578 579 static bool trans_VREV32(DisasContext *s, arg_1op *a) 580 { 581 static MVEGenOneOpFn * const fns[] = { 582 gen_helper_mve_vrev32b, 583 gen_helper_mve_vrev32h, 584 NULL, 585 NULL, 586 }; 587 return do_1op(s, a, fns[a->size]); 588 } 589 590 static bool trans_VREV64(DisasContext *s, arg_1op *a) 591 { 592 static MVEGenOneOpFn * const fns[] = { 593 gen_helper_mve_vrev64b, 594 gen_helper_mve_vrev64h, 595 gen_helper_mve_vrev64w, 596 NULL, 597 }; 598 return do_1op(s, a, fns[a->size]); 599 } 600 601 static bool trans_VMVN(DisasContext *s, arg_1op *a) 602 { 603 return do_1op(s, a, gen_helper_mve_vmvn); 604 } 605 606 static bool trans_VABS_fp(DisasContext *s, arg_1op *a) 607 { 608 static MVEGenOneOpFn * const fns[] = { 609 NULL, 610 gen_helper_mve_vfabsh, 611 gen_helper_mve_vfabss, 612 NULL, 613 }; 614 if (!dc_isar_feature(aa32_mve_fp, s)) { 615 return false; 616 } 617 return do_1op(s, a, fns[a->size]); 618 } 619 620 static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) 621 { 622 static MVEGenOneOpFn * const fns[] = { 623 NULL, 624 gen_helper_mve_vfnegh, 625 gen_helper_mve_vfnegs, 626 NULL, 627 }; 628 if (!dc_isar_feature(aa32_mve_fp, s)) { 629 return false; 630 } 631 return do_1op(s, a, fns[a->size]); 632 } 633 634 static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) 635 { 636 TCGv_ptr qd, qn, qm; 637 638 if (!dc_isar_feature(aa32_mve, s) || 639 !mve_check_qreg_bank(s, a->qd | a->qn | a->qm) || 640 !fn) { 641 return false; 642 } 643 if (!mve_eci_check(s) || !vfp_access_check(s)) { 644 return true; 645 } 646 647 qd = mve_qreg_ptr(a->qd); 648 qn = mve_qreg_ptr(a->qn); 649 qm = mve_qreg_ptr(a->qm); 650 fn(cpu_env, qd, qn, qm); 651 tcg_temp_free_ptr(qd); 652 tcg_temp_free_ptr(qn); 653 tcg_temp_free_ptr(qm); 654 mve_update_eci(s); 655 return true; 656 } 657 658 #define DO_LOGIC(INSN, HELPER) \ 659 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 660 { \ 661 return do_2op(s, a, HELPER); \ 662 } 663 664 DO_LOGIC(VAND, gen_helper_mve_vand) 665 DO_LOGIC(VBIC, gen_helper_mve_vbic) 666 DO_LOGIC(VORR, gen_helper_mve_vorr) 667 DO_LOGIC(VORN, gen_helper_mve_vorn) 668 DO_LOGIC(VEOR, gen_helper_mve_veor) 669 670 DO_LOGIC(VPSEL, gen_helper_mve_vpsel) 671 672 #define DO_2OP(INSN, FN) \ 673 static bool trans_##INSN(DisasContext *s, arg_2op *a) \ 674 { \ 675 static MVEGenTwoOpFn * const fns[] = { \ 676 gen_helper_mve_##FN##b, \ 677 gen_helper_mve_##FN##h, \ 678 gen_helper_mve_##FN##w, \ 679 NULL, \ 680 }; \ 681 return do_2op(s, a, fns[a->size]); \ 682 } 683 684 DO_2OP(VADD, vadd) 685 DO_2OP(VSUB, vsub) 686 DO_2OP(VMUL, vmul) 687 DO_2OP(VMULH_S, vmulhs) 688 DO_2OP(VMULH_U, vmulhu) 689 DO_2OP(VRMULH_S, vrmulhs) 690 DO_2OP(VRMULH_U, vrmulhu) 691 DO_2OP(VMAX_S, vmaxs) 692 DO_2OP(VMAX_U, vmaxu) 693 DO_2OP(VMIN_S, vmins) 694 DO_2OP(VMIN_U, vminu) 695 DO_2OP(VABD_S, vabds) 696 DO_2OP(VABD_U, vabdu) 697 DO_2OP(VHADD_S, vhadds) 698 DO_2OP(VHADD_U, vhaddu) 699 DO_2OP(VHSUB_S, vhsubs) 700 DO_2OP(VHSUB_U, vhsubu) 701 DO_2OP(VMULL_BS, vmullbs) 702 DO_2OP(VMULL_BU, vmullbu) 703 DO_2OP(VMULL_TS, vmullts) 704 DO_2OP(VMULL_TU, vmulltu) 705 DO_2OP(VQDMULH, vqdmulh) 706 DO_2OP(VQRDMULH, vqrdmulh) 707 DO_2OP(VQADD_S, vqadds) 708 DO_2OP(VQADD_U, vqaddu) 709 DO_2OP(VQSUB_S, vqsubs) 710 DO_2OP(VQSUB_U, vqsubu) 711 DO_2OP(VSHL_S, vshls) 712 DO_2OP(VSHL_U, vshlu) 713 DO_2OP(VRSHL_S, vrshls) 714 DO_2OP(VRSHL_U, vrshlu) 715 DO_2OP(VQSHL_S, vqshls) 716 DO_2OP(VQSHL_U, vqshlu) 717 DO_2OP(VQRSHL_S, vqrshls) 718 DO_2OP(VQRSHL_U, vqrshlu) 719 DO_2OP(VQDMLADH, vqdmladh) 720 DO_2OP(VQDMLADHX, vqdmladhx) 721 DO_2OP(VQRDMLADH, vqrdmladh) 722 DO_2OP(VQRDMLADHX, vqrdmladhx) 723 DO_2OP(VQDMLSDH, vqdmlsdh) 724 DO_2OP(VQDMLSDHX, vqdmlsdhx) 725 DO_2OP(VQRDMLSDH, vqrdmlsdh) 726 DO_2OP(VQRDMLSDHX, vqrdmlsdhx) 727 DO_2OP(VRHADD_S, vrhadds) 728 DO_2OP(VRHADD_U, vrhaddu) 729 /* 730 * VCADD Qd == Qm at size MO_32 is UNPREDICTABLE; we choose not to diagnose 731 * so we can reuse the DO_2OP macro. (Our implementation calculates the 732 * "expected" results in this case.) Similarly for VHCADD. 733 */ 734 DO_2OP(VCADD90, vcadd90) 735 DO_2OP(VCADD270, vcadd270) 736 DO_2OP(VHCADD90, vhcadd90) 737 DO_2OP(VHCADD270, vhcadd270) 738 739 static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) 740 { 741 static MVEGenTwoOpFn * const fns[] = { 742 NULL, 743 gen_helper_mve_vqdmullbh, 744 gen_helper_mve_vqdmullbw, 745 NULL, 746 }; 747 if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) { 748 /* UNPREDICTABLE; we choose to undef */ 749 return false; 750 } 751 return do_2op(s, a, fns[a->size]); 752 } 753 754 static bool trans_VQDMULLT(DisasContext *s, arg_2op *a) 755 { 756 static MVEGenTwoOpFn * const fns[] = { 757 NULL, 758 gen_helper_mve_vqdmullth, 759 gen_helper_mve_vqdmulltw, 760 NULL, 761 }; 762 if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) { 763 /* UNPREDICTABLE; we choose to undef */ 764 return false; 765 } 766 return do_2op(s, a, fns[a->size]); 767 } 768 769 static bool trans_VMULLP_B(DisasContext *s, arg_2op *a) 770 { 771 /* 772 * Note that a->size indicates the output size, ie VMULL.P8 773 * is the 8x8->16 operation and a->size is MO_16; VMULL.P16 774 * is the 16x16->32 operation and a->size is MO_32. 775 */ 776 static MVEGenTwoOpFn * const fns[] = { 777 NULL, 778 gen_helper_mve_vmullpbh, 779 gen_helper_mve_vmullpbw, 780 NULL, 781 }; 782 return do_2op(s, a, fns[a->size]); 783 } 784 785 static bool trans_VMULLP_T(DisasContext *s, arg_2op *a) 786 { 787 /* a->size is as for trans_VMULLP_B */ 788 static MVEGenTwoOpFn * const fns[] = { 789 NULL, 790 gen_helper_mve_vmullpth, 791 gen_helper_mve_vmullptw, 792 NULL, 793 }; 794 return do_2op(s, a, fns[a->size]); 795 } 796 797 /* 798 * VADC and VSBC: these perform an add-with-carry or subtract-with-carry 799 * of the 32-bit elements in each lane of the input vectors, where the 800 * carry-out of each add is the carry-in of the next. The initial carry 801 * input is either fixed (0 for VADCI, 1 for VSBCI) or is from FPSCR.C 802 * (for VADC and VSBC); the carry out at the end is written back to FPSCR.C. 803 * These insns are subject to beat-wise execution. Partial execution 804 * of an I=1 (initial carry input fixed) insn which does not 805 * execute the first beat must start with the current FPSCR.NZCV 806 * value, not the fixed constant input. 807 */ 808 static bool trans_VADC(DisasContext *s, arg_2op *a) 809 { 810 return do_2op(s, a, gen_helper_mve_vadc); 811 } 812 813 static bool trans_VADCI(DisasContext *s, arg_2op *a) 814 { 815 if (mve_skip_first_beat(s)) { 816 return trans_VADC(s, a); 817 } 818 return do_2op(s, a, gen_helper_mve_vadci); 819 } 820 821 static bool trans_VSBC(DisasContext *s, arg_2op *a) 822 { 823 return do_2op(s, a, gen_helper_mve_vsbc); 824 } 825 826 static bool trans_VSBCI(DisasContext *s, arg_2op *a) 827 { 828 if (mve_skip_first_beat(s)) { 829 return trans_VSBC(s, a); 830 } 831 return do_2op(s, a, gen_helper_mve_vsbci); 832 } 833 834 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, 835 MVEGenTwoOpScalarFn fn) 836 { 837 TCGv_ptr qd, qn; 838 TCGv_i32 rm; 839 840 if (!dc_isar_feature(aa32_mve, s) || 841 !mve_check_qreg_bank(s, a->qd | a->qn) || 842 !fn) { 843 return false; 844 } 845 if (a->rm == 13 || a->rm == 15) { 846 /* UNPREDICTABLE */ 847 return false; 848 } 849 if (!mve_eci_check(s) || !vfp_access_check(s)) { 850 return true; 851 } 852 853 qd = mve_qreg_ptr(a->qd); 854 qn = mve_qreg_ptr(a->qn); 855 rm = load_reg(s, a->rm); 856 fn(cpu_env, qd, qn, rm); 857 tcg_temp_free_i32(rm); 858 tcg_temp_free_ptr(qd); 859 tcg_temp_free_ptr(qn); 860 mve_update_eci(s); 861 return true; 862 } 863 864 #define DO_2OP_SCALAR(INSN, FN) \ 865 static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ 866 { \ 867 static MVEGenTwoOpScalarFn * const fns[] = { \ 868 gen_helper_mve_##FN##b, \ 869 gen_helper_mve_##FN##h, \ 870 gen_helper_mve_##FN##w, \ 871 NULL, \ 872 }; \ 873 return do_2op_scalar(s, a, fns[a->size]); \ 874 } 875 876 DO_2OP_SCALAR(VADD_scalar, vadd_scalar) 877 DO_2OP_SCALAR(VSUB_scalar, vsub_scalar) 878 DO_2OP_SCALAR(VMUL_scalar, vmul_scalar) 879 DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) 880 DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) 881 DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) 882 DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) 883 DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar) 884 DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar) 885 DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar) 886 DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) 887 DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) 888 DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) 889 DO_2OP_SCALAR(VBRSR, vbrsr) 890 DO_2OP_SCALAR(VMLA, vmla) 891 DO_2OP_SCALAR(VMLAS, vmlas) 892 DO_2OP_SCALAR(VQDMLAH, vqdmlah) 893 DO_2OP_SCALAR(VQRDMLAH, vqrdmlah) 894 DO_2OP_SCALAR(VQDMLASH, vqdmlash) 895 DO_2OP_SCALAR(VQRDMLASH, vqrdmlash) 896 897 static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a) 898 { 899 static MVEGenTwoOpScalarFn * const fns[] = { 900 NULL, 901 gen_helper_mve_vqdmullb_scalarh, 902 gen_helper_mve_vqdmullb_scalarw, 903 NULL, 904 }; 905 if (a->qd == a->qn && a->size == MO_32) { 906 /* UNPREDICTABLE; we choose to undef */ 907 return false; 908 } 909 return do_2op_scalar(s, a, fns[a->size]); 910 } 911 912 static bool trans_VQDMULLT_scalar(DisasContext *s, arg_2scalar *a) 913 { 914 static MVEGenTwoOpScalarFn * const fns[] = { 915 NULL, 916 gen_helper_mve_vqdmullt_scalarh, 917 gen_helper_mve_vqdmullt_scalarw, 918 NULL, 919 }; 920 if (a->qd == a->qn && a->size == MO_32) { 921 /* UNPREDICTABLE; we choose to undef */ 922 return false; 923 } 924 return do_2op_scalar(s, a, fns[a->size]); 925 } 926 927 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, 928 MVEGenLongDualAccOpFn *fn) 929 { 930 TCGv_ptr qn, qm; 931 TCGv_i64 rda; 932 TCGv_i32 rdalo, rdahi; 933 934 if (!dc_isar_feature(aa32_mve, s) || 935 !mve_check_qreg_bank(s, a->qn | a->qm) || 936 !fn) { 937 return false; 938 } 939 /* 940 * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related 941 * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. 942 */ 943 if (a->rdahi == 13 || a->rdahi == 15) { 944 return false; 945 } 946 if (!mve_eci_check(s) || !vfp_access_check(s)) { 947 return true; 948 } 949 950 qn = mve_qreg_ptr(a->qn); 951 qm = mve_qreg_ptr(a->qm); 952 953 /* 954 * This insn is subject to beat-wise execution. Partial execution 955 * of an A=0 (no-accumulate) insn which does not execute the first 956 * beat must start with the current rda value, not 0. 957 */ 958 if (a->a || mve_skip_first_beat(s)) { 959 rda = tcg_temp_new_i64(); 960 rdalo = load_reg(s, a->rdalo); 961 rdahi = load_reg(s, a->rdahi); 962 tcg_gen_concat_i32_i64(rda, rdalo, rdahi); 963 tcg_temp_free_i32(rdalo); 964 tcg_temp_free_i32(rdahi); 965 } else { 966 rda = tcg_const_i64(0); 967 } 968 969 fn(rda, cpu_env, qn, qm, rda); 970 tcg_temp_free_ptr(qn); 971 tcg_temp_free_ptr(qm); 972 973 rdalo = tcg_temp_new_i32(); 974 rdahi = tcg_temp_new_i32(); 975 tcg_gen_extrl_i64_i32(rdalo, rda); 976 tcg_gen_extrh_i64_i32(rdahi, rda); 977 store_reg(s, a->rdalo, rdalo); 978 store_reg(s, a->rdahi, rdahi); 979 tcg_temp_free_i64(rda); 980 mve_update_eci(s); 981 return true; 982 } 983 984 static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a) 985 { 986 static MVEGenLongDualAccOpFn * const fns[4][2] = { 987 { NULL, NULL }, 988 { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh }, 989 { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw }, 990 { NULL, NULL }, 991 }; 992 return do_long_dual_acc(s, a, fns[a->size][a->x]); 993 } 994 995 static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a) 996 { 997 static MVEGenLongDualAccOpFn * const fns[4][2] = { 998 { NULL, NULL }, 999 { gen_helper_mve_vmlaldavuh, NULL }, 1000 { gen_helper_mve_vmlaldavuw, NULL }, 1001 { NULL, NULL }, 1002 }; 1003 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1004 } 1005 1006 static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) 1007 { 1008 static MVEGenLongDualAccOpFn * const fns[4][2] = { 1009 { NULL, NULL }, 1010 { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh }, 1011 { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw }, 1012 { NULL, NULL }, 1013 }; 1014 return do_long_dual_acc(s, a, fns[a->size][a->x]); 1015 } 1016 1017 static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a) 1018 { 1019 static MVEGenLongDualAccOpFn * const fns[] = { 1020 gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw, 1021 }; 1022 return do_long_dual_acc(s, a, fns[a->x]); 1023 } 1024 1025 static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a) 1026 { 1027 static MVEGenLongDualAccOpFn * const fns[] = { 1028 gen_helper_mve_vrmlaldavhuw, NULL, 1029 }; 1030 return do_long_dual_acc(s, a, fns[a->x]); 1031 } 1032 1033 static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) 1034 { 1035 static MVEGenLongDualAccOpFn * const fns[] = { 1036 gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw, 1037 }; 1038 return do_long_dual_acc(s, a, fns[a->x]); 1039 } 1040 1041 static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn) 1042 { 1043 TCGv_ptr qn, qm; 1044 TCGv_i32 rda; 1045 1046 if (!dc_isar_feature(aa32_mve, s) || 1047 !mve_check_qreg_bank(s, a->qn) || 1048 !fn) { 1049 return false; 1050 } 1051 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1052 return true; 1053 } 1054 1055 qn = mve_qreg_ptr(a->qn); 1056 qm = mve_qreg_ptr(a->qm); 1057 1058 /* 1059 * This insn is subject to beat-wise execution. Partial execution 1060 * of an A=0 (no-accumulate) insn which does not execute the first 1061 * beat must start with the current rda value, not 0. 1062 */ 1063 if (a->a || mve_skip_first_beat(s)) { 1064 rda = load_reg(s, a->rda); 1065 } else { 1066 rda = tcg_const_i32(0); 1067 } 1068 1069 fn(rda, cpu_env, qn, qm, rda); 1070 store_reg(s, a->rda, rda); 1071 tcg_temp_free_ptr(qn); 1072 tcg_temp_free_ptr(qm); 1073 1074 mve_update_eci(s); 1075 return true; 1076 } 1077 1078 #define DO_DUAL_ACC(INSN, FN) \ 1079 static bool trans_##INSN(DisasContext *s, arg_vmladav *a) \ 1080 { \ 1081 static MVEGenDualAccOpFn * const fns[4][2] = { \ 1082 { gen_helper_mve_##FN##b, gen_helper_mve_##FN##xb }, \ 1083 { gen_helper_mve_##FN##h, gen_helper_mve_##FN##xh }, \ 1084 { gen_helper_mve_##FN##w, gen_helper_mve_##FN##xw }, \ 1085 { NULL, NULL }, \ 1086 }; \ 1087 return do_dual_acc(s, a, fns[a->size][a->x]); \ 1088 } 1089 1090 DO_DUAL_ACC(VMLADAV_S, vmladavs) 1091 DO_DUAL_ACC(VMLSDAV, vmlsdav) 1092 1093 static bool trans_VMLADAV_U(DisasContext *s, arg_vmladav *a) 1094 { 1095 static MVEGenDualAccOpFn * const fns[4][2] = { 1096 { gen_helper_mve_vmladavub, NULL }, 1097 { gen_helper_mve_vmladavuh, NULL }, 1098 { gen_helper_mve_vmladavuw, NULL }, 1099 { NULL, NULL }, 1100 }; 1101 return do_dual_acc(s, a, fns[a->size][a->x]); 1102 } 1103 1104 static void gen_vpst(DisasContext *s, uint32_t mask) 1105 { 1106 /* 1107 * Set the VPR mask fields. We take advantage of MASK01 and MASK23 1108 * being adjacent fields in the register. 1109 * 1110 * Updating the masks is not predicated, but it is subject to beat-wise 1111 * execution, and the mask is updated on the odd-numbered beats. 1112 * So if PSR.ECI says we should skip beat 1, we mustn't update the 1113 * 01 mask field. 1114 */ 1115 TCGv_i32 vpr = load_cpu_field(v7m.vpr); 1116 switch (s->eci) { 1117 case ECI_NONE: 1118 case ECI_A0: 1119 /* Update both 01 and 23 fields */ 1120 tcg_gen_deposit_i32(vpr, vpr, 1121 tcg_constant_i32(mask | (mask << 4)), 1122 R_V7M_VPR_MASK01_SHIFT, 1123 R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH); 1124 break; 1125 case ECI_A0A1: 1126 case ECI_A0A1A2: 1127 case ECI_A0A1A2B0: 1128 /* Update only the 23 mask field */ 1129 tcg_gen_deposit_i32(vpr, vpr, 1130 tcg_constant_i32(mask), 1131 R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH); 1132 break; 1133 default: 1134 g_assert_not_reached(); 1135 } 1136 store_cpu_field(vpr, v7m.vpr); 1137 } 1138 1139 static bool trans_VPST(DisasContext *s, arg_VPST *a) 1140 { 1141 /* mask == 0 is a "related encoding" */ 1142 if (!dc_isar_feature(aa32_mve, s) || !a->mask) { 1143 return false; 1144 } 1145 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1146 return true; 1147 } 1148 gen_vpst(s, a->mask); 1149 mve_update_and_store_eci(s); 1150 return true; 1151 } 1152 1153 static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a) 1154 { 1155 /* 1156 * Invert the predicate in VPR.P0. We have call out to 1157 * a helper because this insn itself is beatwise and can 1158 * be predicated. 1159 */ 1160 if (!dc_isar_feature(aa32_mve, s)) { 1161 return false; 1162 } 1163 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1164 return true; 1165 } 1166 1167 gen_helper_mve_vpnot(cpu_env); 1168 mve_update_eci(s); 1169 return true; 1170 } 1171 1172 static bool trans_VADDV(DisasContext *s, arg_VADDV *a) 1173 { 1174 /* VADDV: vector add across vector */ 1175 static MVEGenVADDVFn * const fns[4][2] = { 1176 { gen_helper_mve_vaddvsb, gen_helper_mve_vaddvub }, 1177 { gen_helper_mve_vaddvsh, gen_helper_mve_vaddvuh }, 1178 { gen_helper_mve_vaddvsw, gen_helper_mve_vaddvuw }, 1179 { NULL, NULL } 1180 }; 1181 TCGv_ptr qm; 1182 TCGv_i32 rda; 1183 1184 if (!dc_isar_feature(aa32_mve, s) || 1185 a->size == 3) { 1186 return false; 1187 } 1188 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1189 return true; 1190 } 1191 1192 /* 1193 * This insn is subject to beat-wise execution. Partial execution 1194 * of an A=0 (no-accumulate) insn which does not execute the first 1195 * beat must start with the current value of Rda, not zero. 1196 */ 1197 if (a->a || mve_skip_first_beat(s)) { 1198 /* Accumulate input from Rda */ 1199 rda = load_reg(s, a->rda); 1200 } else { 1201 /* Accumulate starting at zero */ 1202 rda = tcg_const_i32(0); 1203 } 1204 1205 qm = mve_qreg_ptr(a->qm); 1206 fns[a->size][a->u](rda, cpu_env, qm, rda); 1207 store_reg(s, a->rda, rda); 1208 tcg_temp_free_ptr(qm); 1209 1210 mve_update_eci(s); 1211 return true; 1212 } 1213 1214 static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) 1215 { 1216 /* 1217 * Vector Add Long Across Vector: accumulate the 32-bit 1218 * elements of the vector into a 64-bit result stored in 1219 * a pair of general-purpose registers. 1220 * No need to check Qm's bank: it is only 3 bits in decode. 1221 */ 1222 TCGv_ptr qm; 1223 TCGv_i64 rda; 1224 TCGv_i32 rdalo, rdahi; 1225 1226 if (!dc_isar_feature(aa32_mve, s)) { 1227 return false; 1228 } 1229 /* 1230 * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related 1231 * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. 1232 */ 1233 if (a->rdahi == 13 || a->rdahi == 15) { 1234 return false; 1235 } 1236 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1237 return true; 1238 } 1239 1240 /* 1241 * This insn is subject to beat-wise execution. Partial execution 1242 * of an A=0 (no-accumulate) insn which does not execute the first 1243 * beat must start with the current value of RdaHi:RdaLo, not zero. 1244 */ 1245 if (a->a || mve_skip_first_beat(s)) { 1246 /* Accumulate input from RdaHi:RdaLo */ 1247 rda = tcg_temp_new_i64(); 1248 rdalo = load_reg(s, a->rdalo); 1249 rdahi = load_reg(s, a->rdahi); 1250 tcg_gen_concat_i32_i64(rda, rdalo, rdahi); 1251 tcg_temp_free_i32(rdalo); 1252 tcg_temp_free_i32(rdahi); 1253 } else { 1254 /* Accumulate starting at zero */ 1255 rda = tcg_const_i64(0); 1256 } 1257 1258 qm = mve_qreg_ptr(a->qm); 1259 if (a->u) { 1260 gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda); 1261 } else { 1262 gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); 1263 } 1264 tcg_temp_free_ptr(qm); 1265 1266 rdalo = tcg_temp_new_i32(); 1267 rdahi = tcg_temp_new_i32(); 1268 tcg_gen_extrl_i64_i32(rdalo, rda); 1269 tcg_gen_extrh_i64_i32(rdahi, rda); 1270 store_reg(s, a->rdalo, rdalo); 1271 store_reg(s, a->rdahi, rdahi); 1272 tcg_temp_free_i64(rda); 1273 mve_update_eci(s); 1274 return true; 1275 } 1276 1277 static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) 1278 { 1279 TCGv_ptr qd; 1280 uint64_t imm; 1281 1282 if (!dc_isar_feature(aa32_mve, s) || 1283 !mve_check_qreg_bank(s, a->qd) || 1284 !fn) { 1285 return false; 1286 } 1287 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1288 return true; 1289 } 1290 1291 imm = asimd_imm_const(a->imm, a->cmode, a->op); 1292 1293 qd = mve_qreg_ptr(a->qd); 1294 fn(cpu_env, qd, tcg_constant_i64(imm)); 1295 tcg_temp_free_ptr(qd); 1296 mve_update_eci(s); 1297 return true; 1298 } 1299 1300 static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) 1301 { 1302 /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ 1303 MVEGenOneOpImmFn *fn; 1304 1305 if ((a->cmode & 1) && a->cmode < 12) { 1306 if (a->op) { 1307 /* 1308 * For op=1, the immediate will be inverted by asimd_imm_const(), 1309 * so the VBIC becomes a logical AND operation. 1310 */ 1311 fn = gen_helper_mve_vandi; 1312 } else { 1313 fn = gen_helper_mve_vorri; 1314 } 1315 } else { 1316 /* There is one unallocated cmode/op combination in this space */ 1317 if (a->cmode == 15 && a->op == 1) { 1318 return false; 1319 } 1320 /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ 1321 fn = gen_helper_mve_vmovi; 1322 } 1323 return do_1imm(s, a, fn); 1324 } 1325 1326 static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, 1327 bool negateshift) 1328 { 1329 TCGv_ptr qd, qm; 1330 int shift = a->shift; 1331 1332 if (!dc_isar_feature(aa32_mve, s) || 1333 !mve_check_qreg_bank(s, a->qd | a->qm) || 1334 !fn) { 1335 return false; 1336 } 1337 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1338 return true; 1339 } 1340 1341 /* 1342 * When we handle a right shift insn using a left-shift helper 1343 * which permits a negative shift count to indicate a right-shift, 1344 * we must negate the shift count. 1345 */ 1346 if (negateshift) { 1347 shift = -shift; 1348 } 1349 1350 qd = mve_qreg_ptr(a->qd); 1351 qm = mve_qreg_ptr(a->qm); 1352 fn(cpu_env, qd, qm, tcg_constant_i32(shift)); 1353 tcg_temp_free_ptr(qd); 1354 tcg_temp_free_ptr(qm); 1355 mve_update_eci(s); 1356 return true; 1357 } 1358 1359 #define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ 1360 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1361 { \ 1362 static MVEGenTwoOpShiftFn * const fns[] = { \ 1363 gen_helper_mve_##FN##b, \ 1364 gen_helper_mve_##FN##h, \ 1365 gen_helper_mve_##FN##w, \ 1366 NULL, \ 1367 }; \ 1368 return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ 1369 } 1370 1371 DO_2SHIFT(VSHLI, vshli_u, false) 1372 DO_2SHIFT(VQSHLI_S, vqshli_s, false) 1373 DO_2SHIFT(VQSHLI_U, vqshli_u, false) 1374 DO_2SHIFT(VQSHLUI, vqshlui_s, false) 1375 /* These right shifts use a left-shift helper with negated shift count */ 1376 DO_2SHIFT(VSHRI_S, vshli_s, true) 1377 DO_2SHIFT(VSHRI_U, vshli_u, true) 1378 DO_2SHIFT(VRSHRI_S, vrshli_s, true) 1379 DO_2SHIFT(VRSHRI_U, vrshli_u, true) 1380 1381 DO_2SHIFT(VSRI, vsri, false) 1382 DO_2SHIFT(VSLI, vsli, false) 1383 1384 static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a, 1385 MVEGenTwoOpShiftFn *fn) 1386 { 1387 TCGv_ptr qda; 1388 TCGv_i32 rm; 1389 1390 if (!dc_isar_feature(aa32_mve, s) || 1391 !mve_check_qreg_bank(s, a->qda) || 1392 a->rm == 13 || a->rm == 15 || !fn) { 1393 /* Rm cases are UNPREDICTABLE */ 1394 return false; 1395 } 1396 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1397 return true; 1398 } 1399 1400 qda = mve_qreg_ptr(a->qda); 1401 rm = load_reg(s, a->rm); 1402 fn(cpu_env, qda, qda, rm); 1403 tcg_temp_free_ptr(qda); 1404 tcg_temp_free_i32(rm); 1405 mve_update_eci(s); 1406 return true; 1407 } 1408 1409 #define DO_2SHIFT_SCALAR(INSN, FN) \ 1410 static bool trans_##INSN(DisasContext *s, arg_shl_scalar *a) \ 1411 { \ 1412 static MVEGenTwoOpShiftFn * const fns[] = { \ 1413 gen_helper_mve_##FN##b, \ 1414 gen_helper_mve_##FN##h, \ 1415 gen_helper_mve_##FN##w, \ 1416 NULL, \ 1417 }; \ 1418 return do_2shift_scalar(s, a, fns[a->size]); \ 1419 } 1420 1421 DO_2SHIFT_SCALAR(VSHL_S_scalar, vshli_s) 1422 DO_2SHIFT_SCALAR(VSHL_U_scalar, vshli_u) 1423 DO_2SHIFT_SCALAR(VRSHL_S_scalar, vrshli_s) 1424 DO_2SHIFT_SCALAR(VRSHL_U_scalar, vrshli_u) 1425 DO_2SHIFT_SCALAR(VQSHL_S_scalar, vqshli_s) 1426 DO_2SHIFT_SCALAR(VQSHL_U_scalar, vqshli_u) 1427 DO_2SHIFT_SCALAR(VQRSHL_S_scalar, vqrshli_s) 1428 DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u) 1429 1430 #define DO_VSHLL(INSN, FN) \ 1431 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1432 { \ 1433 static MVEGenTwoOpShiftFn * const fns[] = { \ 1434 gen_helper_mve_##FN##b, \ 1435 gen_helper_mve_##FN##h, \ 1436 }; \ 1437 return do_2shift(s, a, fns[a->size], false); \ 1438 } 1439 1440 DO_VSHLL(VSHLL_BS, vshllbs) 1441 DO_VSHLL(VSHLL_BU, vshllbu) 1442 DO_VSHLL(VSHLL_TS, vshllts) 1443 DO_VSHLL(VSHLL_TU, vshlltu) 1444 1445 #define DO_2SHIFT_N(INSN, FN) \ 1446 static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ 1447 { \ 1448 static MVEGenTwoOpShiftFn * const fns[] = { \ 1449 gen_helper_mve_##FN##b, \ 1450 gen_helper_mve_##FN##h, \ 1451 }; \ 1452 return do_2shift(s, a, fns[a->size], false); \ 1453 } 1454 1455 DO_2SHIFT_N(VSHRNB, vshrnb) 1456 DO_2SHIFT_N(VSHRNT, vshrnt) 1457 DO_2SHIFT_N(VRSHRNB, vrshrnb) 1458 DO_2SHIFT_N(VRSHRNT, vrshrnt) 1459 DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s) 1460 DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s) 1461 DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u) 1462 DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u) 1463 DO_2SHIFT_N(VQSHRUNB, vqshrunb) 1464 DO_2SHIFT_N(VQSHRUNT, vqshrunt) 1465 DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s) 1466 DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s) 1467 DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) 1468 DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) 1469 DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) 1470 DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) 1471 1472 static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) 1473 { 1474 /* 1475 * Whole Vector Left Shift with Carry. The carry is taken 1476 * from a general purpose register and written back there. 1477 * An imm of 0 means "shift by 32". 1478 */ 1479 TCGv_ptr qd; 1480 TCGv_i32 rdm; 1481 1482 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1483 return false; 1484 } 1485 if (a->rdm == 13 || a->rdm == 15) { 1486 /* CONSTRAINED UNPREDICTABLE: we UNDEF */ 1487 return false; 1488 } 1489 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1490 return true; 1491 } 1492 1493 qd = mve_qreg_ptr(a->qd); 1494 rdm = load_reg(s, a->rdm); 1495 gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); 1496 store_reg(s, a->rdm, rdm); 1497 tcg_temp_free_ptr(qd); 1498 mve_update_eci(s); 1499 return true; 1500 } 1501 1502 static bool do_vidup(DisasContext *s, arg_vidup *a, MVEGenVIDUPFn *fn) 1503 { 1504 TCGv_ptr qd; 1505 TCGv_i32 rn; 1506 1507 /* 1508 * Vector increment/decrement with wrap and duplicate (VIDUP, VDDUP). 1509 * This fills the vector with elements of successively increasing 1510 * or decreasing values, starting from Rn. 1511 */ 1512 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1513 return false; 1514 } 1515 if (a->size == MO_64) { 1516 /* size 0b11 is another encoding */ 1517 return false; 1518 } 1519 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1520 return true; 1521 } 1522 1523 qd = mve_qreg_ptr(a->qd); 1524 rn = load_reg(s, a->rn); 1525 fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm)); 1526 store_reg(s, a->rn, rn); 1527 tcg_temp_free_ptr(qd); 1528 mve_update_eci(s); 1529 return true; 1530 } 1531 1532 static bool do_viwdup(DisasContext *s, arg_viwdup *a, MVEGenVIWDUPFn *fn) 1533 { 1534 TCGv_ptr qd; 1535 TCGv_i32 rn, rm; 1536 1537 /* 1538 * Vector increment/decrement with wrap and duplicate (VIWDUp, VDWDUP) 1539 * This fills the vector with elements of successively increasing 1540 * or decreasing values, starting from Rn. Rm specifies a point where 1541 * the count wraps back around to 0. The updated offset is written back 1542 * to Rn. 1543 */ 1544 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { 1545 return false; 1546 } 1547 if (!fn || a->rm == 13 || a->rm == 15) { 1548 /* 1549 * size 0b11 is another encoding; Rm == 13 is UNPREDICTABLE; 1550 * Rm == 13 is VIWDUP, VDWDUP. 1551 */ 1552 return false; 1553 } 1554 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1555 return true; 1556 } 1557 1558 qd = mve_qreg_ptr(a->qd); 1559 rn = load_reg(s, a->rn); 1560 rm = load_reg(s, a->rm); 1561 fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm)); 1562 store_reg(s, a->rn, rn); 1563 tcg_temp_free_ptr(qd); 1564 tcg_temp_free_i32(rm); 1565 mve_update_eci(s); 1566 return true; 1567 } 1568 1569 static bool trans_VIDUP(DisasContext *s, arg_vidup *a) 1570 { 1571 static MVEGenVIDUPFn * const fns[] = { 1572 gen_helper_mve_vidupb, 1573 gen_helper_mve_viduph, 1574 gen_helper_mve_vidupw, 1575 NULL, 1576 }; 1577 return do_vidup(s, a, fns[a->size]); 1578 } 1579 1580 static bool trans_VDDUP(DisasContext *s, arg_vidup *a) 1581 { 1582 static MVEGenVIDUPFn * const fns[] = { 1583 gen_helper_mve_vidupb, 1584 gen_helper_mve_viduph, 1585 gen_helper_mve_vidupw, 1586 NULL, 1587 }; 1588 /* VDDUP is just like VIDUP but with a negative immediate */ 1589 a->imm = -a->imm; 1590 return do_vidup(s, a, fns[a->size]); 1591 } 1592 1593 static bool trans_VIWDUP(DisasContext *s, arg_viwdup *a) 1594 { 1595 static MVEGenVIWDUPFn * const fns[] = { 1596 gen_helper_mve_viwdupb, 1597 gen_helper_mve_viwduph, 1598 gen_helper_mve_viwdupw, 1599 NULL, 1600 }; 1601 return do_viwdup(s, a, fns[a->size]); 1602 } 1603 1604 static bool trans_VDWDUP(DisasContext *s, arg_viwdup *a) 1605 { 1606 static MVEGenVIWDUPFn * const fns[] = { 1607 gen_helper_mve_vdwdupb, 1608 gen_helper_mve_vdwduph, 1609 gen_helper_mve_vdwdupw, 1610 NULL, 1611 }; 1612 return do_viwdup(s, a, fns[a->size]); 1613 } 1614 1615 static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn) 1616 { 1617 TCGv_ptr qn, qm; 1618 1619 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) || 1620 !fn) { 1621 return false; 1622 } 1623 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1624 return true; 1625 } 1626 1627 qn = mve_qreg_ptr(a->qn); 1628 qm = mve_qreg_ptr(a->qm); 1629 fn(cpu_env, qn, qm); 1630 tcg_temp_free_ptr(qn); 1631 tcg_temp_free_ptr(qm); 1632 if (a->mask) { 1633 /* VPT */ 1634 gen_vpst(s, a->mask); 1635 } 1636 mve_update_eci(s); 1637 return true; 1638 } 1639 1640 static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a, 1641 MVEGenScalarCmpFn *fn) 1642 { 1643 TCGv_ptr qn; 1644 TCGv_i32 rm; 1645 1646 if (!dc_isar_feature(aa32_mve, s) || !fn || a->rm == 13) { 1647 return false; 1648 } 1649 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1650 return true; 1651 } 1652 1653 qn = mve_qreg_ptr(a->qn); 1654 if (a->rm == 15) { 1655 /* Encoding Rm=0b1111 means "constant zero" */ 1656 rm = tcg_constant_i32(0); 1657 } else { 1658 rm = load_reg(s, a->rm); 1659 } 1660 fn(cpu_env, qn, rm); 1661 tcg_temp_free_ptr(qn); 1662 tcg_temp_free_i32(rm); 1663 if (a->mask) { 1664 /* VPT */ 1665 gen_vpst(s, a->mask); 1666 } 1667 mve_update_eci(s); 1668 return true; 1669 } 1670 1671 #define DO_VCMP(INSN, FN) \ 1672 static bool trans_##INSN(DisasContext *s, arg_vcmp *a) \ 1673 { \ 1674 static MVEGenCmpFn * const fns[] = { \ 1675 gen_helper_mve_##FN##b, \ 1676 gen_helper_mve_##FN##h, \ 1677 gen_helper_mve_##FN##w, \ 1678 NULL, \ 1679 }; \ 1680 return do_vcmp(s, a, fns[a->size]); \ 1681 } \ 1682 static bool trans_##INSN##_scalar(DisasContext *s, \ 1683 arg_vcmp_scalar *a) \ 1684 { \ 1685 static MVEGenScalarCmpFn * const fns[] = { \ 1686 gen_helper_mve_##FN##_scalarb, \ 1687 gen_helper_mve_##FN##_scalarh, \ 1688 gen_helper_mve_##FN##_scalarw, \ 1689 NULL, \ 1690 }; \ 1691 return do_vcmp_scalar(s, a, fns[a->size]); \ 1692 } 1693 1694 DO_VCMP(VCMPEQ, vcmpeq) 1695 DO_VCMP(VCMPNE, vcmpne) 1696 DO_VCMP(VCMPCS, vcmpcs) 1697 DO_VCMP(VCMPHI, vcmphi) 1698 DO_VCMP(VCMPGE, vcmpge) 1699 DO_VCMP(VCMPLT, vcmplt) 1700 DO_VCMP(VCMPGT, vcmpgt) 1701 DO_VCMP(VCMPLE, vcmple) 1702 1703 static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn) 1704 { 1705 /* 1706 * MIN/MAX operations across a vector: compute the min or 1707 * max of the initial value in a general purpose register 1708 * and all the elements in the vector, and store it back 1709 * into the general purpose register. 1710 */ 1711 TCGv_ptr qm; 1712 TCGv_i32 rda; 1713 1714 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qm) || 1715 !fn || a->rda == 13 || a->rda == 15) { 1716 /* Rda cases are UNPREDICTABLE */ 1717 return false; 1718 } 1719 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1720 return true; 1721 } 1722 1723 qm = mve_qreg_ptr(a->qm); 1724 rda = load_reg(s, a->rda); 1725 fn(rda, cpu_env, qm, rda); 1726 store_reg(s, a->rda, rda); 1727 tcg_temp_free_ptr(qm); 1728 mve_update_eci(s); 1729 return true; 1730 } 1731 1732 #define DO_VMAXV(INSN, FN) \ 1733 static bool trans_##INSN(DisasContext *s, arg_vmaxv *a) \ 1734 { \ 1735 static MVEGenVADDVFn * const fns[] = { \ 1736 gen_helper_mve_##FN##b, \ 1737 gen_helper_mve_##FN##h, \ 1738 gen_helper_mve_##FN##w, \ 1739 NULL, \ 1740 }; \ 1741 return do_vmaxv(s, a, fns[a->size]); \ 1742 } 1743 1744 DO_VMAXV(VMAXV_S, vmaxvs) 1745 DO_VMAXV(VMAXV_U, vmaxvu) 1746 DO_VMAXV(VMAXAV, vmaxav) 1747 DO_VMAXV(VMINV_S, vminvs) 1748 DO_VMAXV(VMINV_U, vminvu) 1749 DO_VMAXV(VMINAV, vminav) 1750 1751 static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn) 1752 { 1753 /* Absolute difference accumulated across vector */ 1754 TCGv_ptr qn, qm; 1755 TCGv_i32 rda; 1756 1757 if (!dc_isar_feature(aa32_mve, s) || 1758 !mve_check_qreg_bank(s, a->qm | a->qn) || 1759 !fn || a->rda == 13 || a->rda == 15) { 1760 /* Rda cases are UNPREDICTABLE */ 1761 return false; 1762 } 1763 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1764 return true; 1765 } 1766 1767 qm = mve_qreg_ptr(a->qm); 1768 qn = mve_qreg_ptr(a->qn); 1769 rda = load_reg(s, a->rda); 1770 fn(rda, cpu_env, qn, qm, rda); 1771 store_reg(s, a->rda, rda); 1772 tcg_temp_free_ptr(qm); 1773 tcg_temp_free_ptr(qn); 1774 mve_update_eci(s); 1775 return true; 1776 } 1777 1778 #define DO_VABAV(INSN, FN) \ 1779 static bool trans_##INSN(DisasContext *s, arg_vabav *a) \ 1780 { \ 1781 static MVEGenVABAVFn * const fns[] = { \ 1782 gen_helper_mve_##FN##b, \ 1783 gen_helper_mve_##FN##h, \ 1784 gen_helper_mve_##FN##w, \ 1785 NULL, \ 1786 }; \ 1787 return do_vabav(s, a, fns[a->size]); \ 1788 } 1789 1790 DO_VABAV(VABAV_S, vabavs) 1791 DO_VABAV(VABAV_U, vabavu) 1792 1793 static bool trans_VMOV_to_2gp(DisasContext *s, arg_VMOV_to_2gp *a) 1794 { 1795 /* 1796 * VMOV two 32-bit vector lanes to two general-purpose registers. 1797 * This insn is not predicated but it is subject to beat-wise 1798 * execution if it is not in an IT block. For us this means 1799 * only that if PSR.ECI says we should not be executing the beat 1800 * corresponding to the lane of the vector register being accessed 1801 * then we should skip perfoming the move, and that we need to do 1802 * the usual check for bad ECI state and advance of ECI state. 1803 * (If PSR.ECI is non-zero then we cannot be in an IT block.) 1804 */ 1805 TCGv_i32 tmp; 1806 int vd; 1807 1808 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) || 1809 a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15 || 1810 a->rt == a->rt2) { 1811 /* Rt/Rt2 cases are UNPREDICTABLE */ 1812 return false; 1813 } 1814 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1815 return true; 1816 } 1817 1818 /* Convert Qreg index to Dreg for read_neon_element32() etc */ 1819 vd = a->qd * 2; 1820 1821 if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { 1822 tmp = tcg_temp_new_i32(); 1823 read_neon_element32(tmp, vd, a->idx, MO_32); 1824 store_reg(s, a->rt, tmp); 1825 } 1826 if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { 1827 tmp = tcg_temp_new_i32(); 1828 read_neon_element32(tmp, vd + 1, a->idx, MO_32); 1829 store_reg(s, a->rt2, tmp); 1830 } 1831 1832 mve_update_and_store_eci(s); 1833 return true; 1834 } 1835 1836 static bool trans_VMOV_from_2gp(DisasContext *s, arg_VMOV_to_2gp *a) 1837 { 1838 /* 1839 * VMOV two general-purpose registers to two 32-bit vector lanes. 1840 * This insn is not predicated but it is subject to beat-wise 1841 * execution if it is not in an IT block. For us this means 1842 * only that if PSR.ECI says we should not be executing the beat 1843 * corresponding to the lane of the vector register being accessed 1844 * then we should skip perfoming the move, and that we need to do 1845 * the usual check for bad ECI state and advance of ECI state. 1846 * (If PSR.ECI is non-zero then we cannot be in an IT block.) 1847 */ 1848 TCGv_i32 tmp; 1849 int vd; 1850 1851 if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd) || 1852 a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15) { 1853 /* Rt/Rt2 cases are UNPREDICTABLE */ 1854 return false; 1855 } 1856 if (!mve_eci_check(s) || !vfp_access_check(s)) { 1857 return true; 1858 } 1859 1860 /* Convert Qreg idx to Dreg for read_neon_element32() etc */ 1861 vd = a->qd * 2; 1862 1863 if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { 1864 tmp = load_reg(s, a->rt); 1865 write_neon_element32(tmp, vd, a->idx, MO_32); 1866 tcg_temp_free_i32(tmp); 1867 } 1868 if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { 1869 tmp = load_reg(s, a->rt2); 1870 write_neon_element32(tmp, vd + 1, a->idx, MO_32); 1871 tcg_temp_free_i32(tmp); 1872 } 1873 1874 mve_update_and_store_eci(s); 1875 return true; 1876 } 1877