15ce389f2SPeter Maydell /* 25ce389f2SPeter Maydell * AArch32 translation, common definitions. 35ce389f2SPeter Maydell * 45ce389f2SPeter Maydell * Copyright (c) 2021 Linaro, Ltd. 55ce389f2SPeter Maydell * 65ce389f2SPeter Maydell * This library is free software; you can redistribute it and/or 75ce389f2SPeter Maydell * modify it under the terms of the GNU Lesser General Public 85ce389f2SPeter Maydell * License as published by the Free Software Foundation; either 95ce389f2SPeter Maydell * version 2.1 of the License, or (at your option) any later version. 105ce389f2SPeter Maydell * 115ce389f2SPeter Maydell * This library is distributed in the hope that it will be useful, 125ce389f2SPeter Maydell * but WITHOUT ANY WARRANTY; without even the implied warranty of 135ce389f2SPeter Maydell * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 145ce389f2SPeter Maydell * Lesser General Public License for more details. 155ce389f2SPeter Maydell * 165ce389f2SPeter Maydell * You should have received a copy of the GNU Lesser General Public 175ce389f2SPeter Maydell * License along with this library; if not, see <http://www.gnu.org/licenses/>. 185ce389f2SPeter Maydell */ 195ce389f2SPeter Maydell 205ce389f2SPeter Maydell #ifndef TARGET_ARM_TRANSLATE_A64_H 215ce389f2SPeter Maydell #define TARGET_ARM_TRANSLATE_A64_H 225ce389f2SPeter Maydell 235ce389f2SPeter Maydell void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); 245ce389f2SPeter Maydell void arm_gen_condlabel(DisasContext *s); 255ce389f2SPeter Maydell bool vfp_access_check(DisasContext *s); 265ce389f2SPeter Maydell void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); 275ce389f2SPeter Maydell void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); 285ce389f2SPeter Maydell void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); 295ce389f2SPeter Maydell void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); 305ce389f2SPeter Maydell 315ce389f2SPeter Maydell static inline TCGv_i32 load_cpu_offset(int offset) 325ce389f2SPeter Maydell { 335ce389f2SPeter Maydell TCGv_i32 tmp = tcg_temp_new_i32(); 345ce389f2SPeter Maydell tcg_gen_ld_i32(tmp, cpu_env, offset); 355ce389f2SPeter Maydell return tmp; 365ce389f2SPeter Maydell } 375ce389f2SPeter Maydell 385ce389f2SPeter Maydell #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) 395ce389f2SPeter Maydell 405ce389f2SPeter Maydell static inline void store_cpu_offset(TCGv_i32 var, int offset) 415ce389f2SPeter Maydell { 425ce389f2SPeter Maydell tcg_gen_st_i32(var, cpu_env, offset); 435ce389f2SPeter Maydell tcg_temp_free_i32(var); 445ce389f2SPeter Maydell } 455ce389f2SPeter Maydell 465ce389f2SPeter Maydell #define store_cpu_field(var, name) \ 475ce389f2SPeter Maydell store_cpu_offset(var, offsetof(CPUARMState, name)) 485ce389f2SPeter Maydell 495ce389f2SPeter Maydell /* Create a new temporary and set it to the value of a CPU register. */ 505ce389f2SPeter Maydell static inline TCGv_i32 load_reg(DisasContext *s, int reg) 515ce389f2SPeter Maydell { 525ce389f2SPeter Maydell TCGv_i32 tmp = tcg_temp_new_i32(); 535ce389f2SPeter Maydell load_reg_var(s, tmp, reg); 545ce389f2SPeter Maydell return tmp; 555ce389f2SPeter Maydell } 565ce389f2SPeter Maydell 575ce389f2SPeter Maydell #endif 58